阅读说明：本技术 基于spi的双全工通信方法、主机、从机及存储介质 (SPI-based dual-full-duplex communication method, host, slave and storage medium ) 是由 陈维洲 左绍舟 陈利君 李强 于 2020-10-26 设计创作，主要内容包括：本申请公开了一种基于SPI的双全工通信方法、主机、从机及存储介质,能够主从设备之间的双全工通信方式。该方法包括：从机若需要向所述主机发送第一通信数据,则发出中断信号,以使信号线的电平由第一电平变为第二电平；主机若检测到所述信号线的电平由第一电平变为第二电平,则向从机发送时钟信号；从机接收到所述时钟信号后,发送第一通信数据至所述主机；主机接收所述从机发送的所述第一通信数据,并实时检测所述信号线的电平；从机若发送完所述第一通信数据,则清除所述中断信号,以使所述信号线的电平由所述第二电平变为所述第一电平；主机若检测到所述信号线的电平由所述第二电平变为所述第一电平,则终止向所述从机发送所述时钟信号。(The application discloses a double-full-duplex communication method based on SPI, a host, a slave and a storage medium, which can realize a double-full-duplex communication mode between the host and the slave. The method comprises the following steps: if the slave computer needs to send first communication data to the host computer, sending an interrupt signal so as to change the level of the signal line from a first level to a second level; if the host detects that the level of the signal line is changed from a first level to a second level, the host sends a clock signal to the slave; after receiving the clock signal, the slave machine sends first communication data to the host machine; the master machine receives the first communication data sent by the slave machine and detects the level of the signal line in real time; if the slave machine finishes sending the first communication data, clearing the interrupt signal so as to change the level of the signal wire from the second level to the first level; and if the master machine detects that the level of the signal line is changed from the second level to the first level, the master machine stops sending the clock signal to the slave machine.)

1. A double-full-duplex communication method based on SPI is applied to a double-full-duplex communication system, the double-full-duplex communication system comprises a host and a slave, the host and the slave are in communication connection through the SPI, a clock line is connected between the host and the slave, and the double-full-duplex communication method is characterized in that a signal line is further connected between the host and the slave, and the method comprises the following steps:

if the slave computer needs to send first communication data to the host computer, sending an interrupt signal to change the level of the signal line from a first level to a second level;

if the master machine detects that the level of the signal line is changed from a first level to a second level, the master machine sends a clock signal to the slave machine;

after receiving the clock signal, the slave machine sends first communication data to the host machine;

the master machine receives the first communication data sent by the slave machine and detects the level of the signal line in real time;

if the slave machine finishes sending the first communication data, clearing the interrupt signal so as to change the level of the signal wire from the second level to the first level;

and if the master machine detects that the level of the signal line is changed from the second level to the first level, the master machine stops sending the clock signal to the slave machine.

2. A double-full-duplex communication method based on SPI is applied to a host, the host is in communication connection with a slave through the SPI, a clock line is connected between the host and the slave, the double-full-duplex communication method is characterized in that a signal line is further connected between the host and the slave, and the method comprises the following steps:

if the level of the signal line is detected to be changed from a first level to a second level, sending a clock signal to a slave machine to indicate the slave machine to send first communication data based on the clock signal; the level of the signal line is changed from a first level to a second level, the slave machine sends out an interrupt signal to control the level, and the slave machine sends out the interrupt signal when the first communication data needs to be sent to the host machine;

receiving the first communication data sent by the slave machine, and detecting the level of the signal line in real time;

if the level of the signal line is detected to be changed from the second level to the first level, the clock signal is stopped being sent to the slave; wherein the level of the signal line is changed from the second level to the first level and is controlled by the slave machine clearing the interrupt signal, and the slave machine clears the interrupt signal after sending the first communication data.

3. The method of claim 2, wherein before said sending a clock signal to a slave if it is detected that the level of said signal line changes from a first level to a second level, further comprising:

initializing a first SPI controller of the host and a first working state of the signal line at the host end.

4. The method according to claim 2 or 3, further comprising, after said receiving said first communication data sent from said slave and detecting the level of said signal line in real time:

and if detecting that second communication data are to be sent, circularly sending the second communication data until the sending is finished.

5. A double-full-duplex communication method based on SPI is applied to a slave computer, the slave computer is in communication connection with a host computer through the SPI, a clock line is connected between the slave computer and the host computer, the double-full-duplex communication method is characterized in that a signal line is further connected between the slave computer and the host computer, and the method comprises the following steps:

if first communication data need to be sent to the host, sending an interrupt signal to change the level of the signal line from a first level to a second level;

receiving a clock signal sent by the host, and sending first communication data based on the clock signal; the clock signal is a signal sent to the slave after the master detects that the level of the signal line is changed from the first level to the second level;

and if the first communication data is sent, clearing the interrupt signal so as to change the level of the signal line from the second level to the first level to indicate the host to stop sending the clock signal.

6. The method of claim 5, wherein before the slave sends the first communication data to the master if necessary, further comprising:

and initializing a second SPI controller of the slave and a second working state of the signal line at the slave end.

7. The method of claim 5 or 6, wherein after clearing the interrupt signal if the first communication data is sent, further comprising:

and receiving second communication data sent by the host, and filtering invalid data from the second communication data according to a preset data verification rule.

8. A host, comprising: memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the method according to any of claims 2 to 4 when executing the computer program.

9. A slave, comprising: memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the method according to any of claims 5 to 7 when executing the computer program.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method of any one of claims 2 to 4, or which, when being executed by a processor, carries out the method of any one of claims 5 to 7.

Technical Field

The application belongs to the technical field of communication, and particularly relates to a double-full-duplex communication method based on SPI, a host, a slave and a storage medium.

Background

The stable and efficient data interaction between the master device and the slave device requires that both the master device and the slave device can actively initiate a request, that is, the master device and the slave device can realize full-duplex communication, and the size of data interaction between the master device and the slave device is not limited. At present, full-duplex communication between a master device and a slave device can be realized based on RS232 or RS485 communication, but the communication rate cannot meet the requirement of high efficiency, and the bit error rate is increased and the communication stability is low due to too high baud rate configuration; the communication rate of the standard SPI communication can reach the high-efficiency requirement, but the standard SPI communication cannot meet the full-duplex communication, and the slave machine cannot determine the size of the interactive data.

Therefore, the problem that stable and efficient data interaction between the master device and the slave device cannot be carried out exists in the prior art.

Disclosure of Invention

The application provides a double-full-duplex communication method, a double-full-duplex communication system, double-full-duplex communication equipment and a storage medium based on SPI (serial peripheral interface), which can solve the problem that stable and efficient data interaction cannot be carried out between master equipment and slave equipment in the prior art.

In a first aspect, the present application provides an SPI-based duplex communication method, applied to a duplex communication system, where the duplex communication system includes a master and a slave, the master and the slave are connected through an SPI communication, and a clock line is connected between the master and the slave, and the method is characterized in that a signal line is further connected between the master and the slave, and the method includes:

if the slave computer needs to send first communication data to the host computer, sending an interrupt signal to change the level of the signal line from a first level to a second level;

if the master machine detects that the level of the signal line is changed from a first level to a second level, the master machine sends a clock signal to the slave machine;

after receiving the clock signal, the slave machine sends first communication data to the host machine;

the master machine receives the first communication data sent by the slave machine and detects the level of the signal line in real time;

if the slave machine finishes sending the first communication data, clearing the interrupt signal so as to change the level of the signal wire from the second level to the first level;

and if the master machine detects that the level of the signal line is changed from the second level to the first level, the master machine stops sending the clock signal to the slave machine.

In a second aspect, the present application provides an SPI-based duplex communication method, which is applied to a master, the master and a slave are connected through an SPI, a clock line is connected between the master and the slave, and a signal line is further connected between the master and the slave, the method including:

if the level of the signal line is detected to be changed from a first level to a second level, sending a clock signal to a slave machine to indicate the slave machine to send first communication data based on the clock signal; the level of the signal line is changed from a first level to a second level, the slave machine sends out an interrupt signal to control the level, and the slave machine sends out the interrupt signal when the first communication data needs to be sent to the host machine;

receiving the first communication data sent by the slave machine, and detecting the level of the signal line in real time;

if the level of the signal line is detected to be changed from the second level to the first level, the clock signal is stopped being sent to the slave; wherein the level of the signal line is changed from the second level to the first level and is controlled by the slave machine clearing the interrupt signal, and the slave machine clears the interrupt signal after sending the first communication data.

In an optional implementation manner, before the sending a clock signal to a slave if it is detected that the level of the signal line changes from the first level to the second level, the method further includes:

initializing a first SPI controller of the host and a first working state of the signal line at the host end.

In an optional implementation manner, after the receiving the first communication data sent by the slave and detecting the level of the signal line in real time, the method further includes:

and if detecting that second communication data are to be sent, circularly sending the second communication data until the sending is finished.

The third aspect of the present application provides a dual-full-duplex communication method based on an SPI, which is applied to a slave, wherein the slave is in communication connection with a host through the SPI, a clock line is connected between the slave and the host, and a signal line is further connected between the slave and the host, and the method includes:

if the slave computer needs to send first communication data to the host computer, sending an interrupt signal so as to change the level of the signal line from a first level to a second level;

receiving a clock signal sent by the host, and sending first communication data based on the clock signal; the clock signal is a signal sent to the slave after the master detects that the level of the signal line is changed from the first level to the second level;

and if the first communication data is sent, clearing the interrupt signal so as to change the level of the signal line from the second level to the first level to indicate the host to stop sending the clock signal.

In an optional implementation manner, before the slave sends the first communication data to the master if necessary, the method further includes:

and initializing a second SPI controller of the slave and a second working state of the signal line at the slave end.

In an optional implementation manner, after clearing the interrupt signal if the first communication data is sent, the method further includes:

and receiving second communication data sent by the host, and filtering invalid data from the second communication data according to a preset data verification rule.

The application in a fourth aspect provides a double-full-duplex communication system based on SPI, which comprises a host and a slave, wherein the host and the slave are in communication connection through SPI, and a clock line is connected between the host and the slave;

the slave is used for sending an interrupt signal when first communication data need to be sent to the host, sending the first communication data to the host after a clock signal sent by the host is received, and clearing the interrupt signal after the first communication data is sent; wherein the slave device transmits the interrupt signal to change the level of the signal line from the second level to the first level; the slave machine clears the interrupt signal so as to change the level of the signal line from a first level to a second level;

the master is used for sending a clock signal to the slave when detecting that the level of the signal line is changed from a first level to a second level, receiving the first communication data sent by the slave, detecting the level of the signal line in real time, and stopping sending the clock signal to the slave when detecting that the level of the signal line is changed from the second level to the first level.

This application fifth aspect provides a host computer, pass through SPI communication connection between host computer and the slave computer, just the host computer with be connected with the clock line between the slave computer, the host computer with still be connected with the signal line between the slave computer, the host computer includes:

the first sending module is used for sending a clock signal to a slave machine to indicate the slave machine to send first communication data based on the clock signal if the level of the signal line is detected to be changed from a first level to a second level; the level of the signal line is changed from a first level to a second level, the slave machine sends out an interrupt signal to control the level, and the slave machine sends out the interrupt signal when the first communication data needs to be sent to the host machine;

the detection module is used for receiving the first communication data sent by the slave machine and detecting the level of the signal line in real time;

a termination module, configured to terminate sending the clock signal to the slave if it is detected that the level of the signal line changes from the second level to the first level; wherein the level of the signal line is changed from the second level to the first level and is controlled by the slave machine clearing the interrupt signal, and the slave machine clears the interrupt signal after sending the first communication data.

In an optional implementation manner, the method further includes:

the first initialization module is used for initializing a first SPI controller of the host and a first working state of the signal line at the host end.

In an optional implementation manner, the method further includes:

and the second sending module is used for circularly sending the second communication data until the second communication data is sent if the second communication data to be sent is detected.

The sixth aspect of the present application provides a slave machine, through SPI communication connection between slave machine and the host machine, just be connected with the clock line between the slave machine and the host machine, still be connected with the signal line between the slave machine and the host machine, the slave machine includes:

the sending module is used for sending an interrupt signal if first communication data needs to be sent to the host computer so as to change the level of the signal line from a first level to a second level;

the third sending module is used for receiving the clock signal sent by the host and sending first communication data based on the clock signal; the clock signal is a signal sent to the slave after the master detects that the level of the signal line is changed from the first level to the second level;

and the clearing module is used for clearing the interrupt signal if the first communication data is sent out, so that the level of the signal line is changed from the second level to the first level, and the host is instructed to stop sending the clock signal.

In an optional implementation manner, the method further includes:

and the second initialization module is used for initializing a second SPI controller of the slave and a second working state of the signal line at the slave end.

In an optional implementation manner, the method further includes:

and the filtering module is used for receiving the second communication data sent by the host and filtering invalid data from the second communication data according to a preset data verification rule. A seventh aspect of the present application provides a host comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to the second aspect when executing the computer program.

An eighth aspect of the present application provides a slave, which includes a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to the second aspect when executing the computer program.

A ninth aspect of the present application provides a computer readable storage medium having stored thereon a computer program for, when executed by a processor, performing the steps of the method according to the second aspect or for, when executed by a processor, performing the steps of the method according to the third aspect.

In a tenth aspect, the present application provides a computer program product comprising a computer program that when executed by one or more processors performs the steps of the method according to the first aspect described above, or a computer program that when executed by one or more processors performs the steps of the method according to the second aspect described above.

According to the SPI-based duplex full-duplex communication method of the first aspect, the signal line is connected between the master and the slave, so that when the slave needs to send communication data to the master or finishes sending communication data, the level change of the signal line can be controlled by the slave through the interrupt signal, so that the master can send a clock signal to the slave or terminate sending the clock signal according to the level change of the signal line, thereby realizing that the slave sends communication data to the master or terminates sending the communication data based on the clock signal, further realizing a duplex full-duplex communication mode between the master and the slave, and enabling stable and efficient data interaction between the master and the slave.

It is to be understood that the beneficial effects of the second to tenth aspects can be seen from the description of the first aspect, and are not repeated herein.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic diagram of a duplex communication system provided in a first embodiment of the present application;

fig. 2 is a flowchart of an implementation of an SPI-based dual-full-duplex communication method according to a second embodiment of the present application;

fig. 3 is a flowchart of an implementation of a SPI-based dual-full-duplex communication method according to a third embodiment of the present application;

fig. 4 is a flowchart of an implementation of a SPI-based dual-full-duplex communication method according to a fourth embodiment of the present application;

fig. 5 is an interaction flowchart of a slave and a master according to a fifth embodiment of the present application;

fig. 6 is a schematic structural diagram of a host according to a sixth embodiment of the present application;

fig. 7 is a schematic structural diagram of a slave according to a seventh embodiment of the present application;

fig. 8 is a schematic structural diagram of a host according to an eighth embodiment of the present application;

fig. 9 is a schematic structural diagram of a slave according to a ninth embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

The event recommendation method provided by the present application is exemplarily described below with reference to specific embodiments. First, fig. 1 is a schematic diagram of a duplex communication system according to a first embodiment of the present application. As shown in fig. 1, a duplex communication system 100 includes a master 101 and a slave 102. The host 101 is a device which plays a main role between two communication devices and is used for issuing commands; the slave 102 is a device for receiving a command between two communication devices. In some embodiments of the present application, the master 101 and the slave 102 are communicatively connected through a Serial Peripheral Interface (SPI) 103, a clock line 104 is connected between the master 101 and the slave 102, and a signal line 105 is also connected between the master 101 and the slave 102.

At present, data/signaling interaction between communication devices needs to be carried out through a serial peripheral interface, and the requirements of full duplex, high efficiency and stable communication need to be met. And when the RS232 is used for communication, the communication speed cannot meet the requirement, the speed configuration is too high, and the stability cannot be ensured. When the common serial peripheral interface based on the standard SPI is used for communication, full-duplex communication cannot be achieved, a request must be initiated by one end of a host, a slave system cannot actively initiate the request, data with any size cannot be sent, and the data can be sent only according to the data length requested by the host. Based on the above problems, in the embodiment of the application, a signal line is extended on the basis of a standard SPI serial peripheral interface to realize full-duplex communication of the SPI serial peripheral interface, and the requirement that a data request can be initiated between a master device and a slave device at the same time and the data length is not limited is met.

Illustratively, the slave 102 is configured to send an interrupt signal when first communication data needs to be sent to the host, send the first communication data to the host 101 after receiving a clock signal sent by the host 101, and clear the interrupt signal after sending the first communication data; the slave 102 sends the interrupt signal to change the level of the signal line 105 from the second level to the first level; the slave 102 clears the interrupt signal to change the level of the signal line 105 from the first level to the second level.

The master 101 is configured to send a clock signal to the slave 102 when detecting that the level of the signal line 105 changes from a first level to a second level, receive the first communication data sent by the slave 102, detect the level of the signal line 105 in real time, and terminate sending the clock signal to the slave 102 when detecting that the level of the signal line 105 changes from the second level to the first level.

As can be seen from the above analysis, in the duplex communication system provided by the present application, the signal line 105 is connected between the master 101 and the slave 102, and is used for sending the notification signal when the slave 102 needs to send the communication data, and in the present application, the notification signal is an interrupt signal, so that the level of the signal line 105 is changed from the first level to the second level, and the master 101 is notified of sending the clock signal, so that the slave 102 can send the communication data according to the clock signal until the communication data is sent completely.

Illustratively, the first level is an initial level of the signal line 105, for example, the initial level of the signal line 105 is a high level, and the initial state of the signal line 105 is a high signal line.

Optionally, in some embodiments of the present application, the configuration of the signal line 105 at the slave 102 end is output, and is set to a high level by default. The configuration of the signal line 105 at the host side is input. Illustratively, the signal line 105 serves as an interrupt source, configured as a double-edge trigger at the host end. That is, when data needs to be transmitted through the signal line 105, the slave 102 pulls down the level of the signal line 105 first, and pulls up the level of the signal line 105 after the data transmission is completed.

The SPI-based duplex communication method provided by the present application is exemplarily described below by specific embodiments.

As shown in fig. 2, fig. 2 is a flowchart of an implementation of an SPI-based duplex communication method according to a second embodiment of the present application. This implementation may be performed by the host computer shown in fig. 1. The details are as follows:

s201, if the level of the signal line is detected to be changed from a first level to a second level, a clock signal is sent to a slave machine so as to instruct the slave machine to send first communication data based on the clock signal; the level of the signal line is changed from a first level to a second level, the slave machine sends out an interrupt signal to control the level, and the slave machine sends out the interrupt signal when the first communication data needs to be sent to the host machine.

In an embodiment of the present application, the first level is an initial level of the signal line, when the signal line is at the initial level, an interrupt source of the master is not triggered, and the master does not send a clock signal to the slave. For example, the first level is a level greater than the second level, and exemplarily, the first level is a high level, and the second level is a low level after the first level is pulled down.

And the slave machine sends first communication data to the host machine after receiving the clock signal sent by the host machine. The first communication data may be any data that the slave needs to actively send to the master.

It can be understood that, before the step of sending a clock signal to a slave if it is detected that the level of the signal line changes from the first level to the second level, the method further includes:

initializing a first SPI controller of the host and a first working state of the signal line at the host end.

Illustratively, a first SPI controller that initializes the host is master mode and configures SPI clock polarity and clock phase CPOL to be 0 and CPHA to be 1. And configuring the port of a large signal line at the host end as an input state, configuring the trigger condition of the GPIO as double-edge trigger, registering GPIO interruption, and realizing an interruption trigger function. Further, in some embodiments of the present application, it is also necessary to initialize the input/output buffer, for example, allocate a memory space with a suitable size for storing data that needs to be sent and received by the SPI. The sending buffer is used to determine whether the SPI needs to switch the working mode, for example, switching between a read mode and a write mode.

S202, receiving the first communication data sent by the slave machine, and detecting the level of the signal line in real time.

It should be noted that, in the process of receiving the first communication data sent by the slave, the host detects the level of the signal line in real time, when the level of the signal line changes, the interrupt source is triggered, the host defaults to receiving a signal interrupt, which indicates that the level state of the signal line changes, at this time, the host reads the current state of the signal line, and if the level of the signal line changes from the first level (low level) to the second level (high level), which indicates that the data sending from the slave is completed, the host leaves the read mode and enters the write mode.

S203, if it is detected that the level of the signal line changes from the second level to the first level, terminating the transmission of the clock signal to the slave; wherein the level of the signal line is changed from the second level to the first level and is controlled by the slave machine clearing the interrupt signal, and the slave machine clears the interrupt signal after sending the first communication data. As can be seen from the above analysis, according to the SPI-based duplex communication method provided in the embodiment of the present application, the signal line is connected between the master device and the slave device, so that when the slave device needs to send communication data to the master device or finishes sending communication data, the level change of the signal line can be controlled by the interrupt signal, so that the master device can send a clock signal to the slave device or terminate sending the clock signal according to the level change of the signal line, thereby implementing sending of communication data to the master device or terminating sending of the communication data by the slave device based on the clock signal, further implementing a duplex communication mode between the master device and the slave device, and enabling stable and efficient data interaction between the master device and the slave device.

In some optional implementations of the present application, after the receiving the first communication data sent by the slave and detecting the level of the signal line in real time, the method may further include: and if detecting that second communication data are to be sent, circularly sending the second communication data until the sending is finished. Exemplarily, as shown in fig. 3, fig. 3 is a flowchart of an implementation of the SPI-based duplex communication method according to the third embodiment of the present application. As can be seen from fig. 3, in this embodiment, compared with the embodiment shown in fig. 2, the specific implementation processes of S301 to S302 are the same as those of S201 to S202 and those of S304 and S203, except that S303 is further included after S302, it should be noted that the bits of S303 and S304 are in parallel execution relationship. The details are as follows:

s301, if the level of the signal line is detected to be changed from a first level to a second level, a clock signal is sent to a slave machine to indicate the slave machine to send first communication data based on the clock signal; the level of the signal line is changed from a first level to a second level, the slave machine sends out an interrupt signal to control the level, and the slave machine sends out the interrupt signal when the first communication data needs to be sent to the host machine.

S302, receiving the first communication data sent by the slave machine, and detecting the level of the signal line in real time.

And S303, if detecting that second communication data are to be sent, circularly sending the second communication data until the sending is finished.

S304, if it is detected that the level of the signal line changes from the second level to the first level, terminating the transmission of the clock signal to the slave; wherein the level of the signal line is changed from the second level to the first level and is controlled by the slave machine clearing the interrupt signal, and the slave machine clears the interrupt signal after sending the first communication data.

It can be understood that after the interrupt source of the SPI serial peripheral interface is triggered, the first communication data sent by the slave can be normally received and written into the receiving cache; if the data to be sent is cached in the SPI serial peripheral interface, the data are sent circularly until the sending is finished; when the SPI serial peripheral interface sends no data in the cache, the host detects whether the SPI serial peripheral interface is in a reading mode, if the SPI serial peripheral interface sends no data in the cache, the host sends 0xFF, detects whether the sending cache has data to be sent again, and the process is carried out in a circulating mode until the SPI serial peripheral interface leaves the reading mode.

As shown in fig. 4, fig. 4 is a flowchart of an implementation of the SPI-based dual-duplex communication method according to the fourth embodiment of the present application. This embodiment may be performed by the slave in fig. 1. The details are as follows:

s401, if first communication data need to be sent to the host, an interrupt signal is sent out, so that the level of the signal line is changed from a first level to a second level.

S402, receiving a clock signal sent by the host, and sending first communication data based on the clock signal; the clock signal is a signal sent to the slave after the master detects that the level of the signal line is changed from the first level to the second level.

S403, if the first communication data is sent, clearing the interrupt signal to change the level of the signal line from the second level to the first level, so as to instruct the host to terminate sending the clock signal.

It can be understood that, before the slave sends the first communication data to the master as required, the method further includes: and initializing a second SPI controller of the slave and a second working state of the signal line at the slave end.

Illustratively, initializing the second SPI controller of the slave includes configuring the second SPI controller of the slave in slave mode and configuring the second SPI clock polarity and clock phase of the slave to CPOL ═ 0 and CPHA ═ 1, respectively. Initializing a second working state of the signal line at the slave end comprises initializing a port of the signal line at the slave end as an output state and when the slave is configured to need to send data, pulling down the level of the signal line, and after the sending is finished, pulling up the level of the signal line.

Optionally, in some embodiments of the present application, a memory space with a suitable size may also be allocated for storing data that needs to be sent and received by the SPI.

It can be understood that, since the slave needs to actively send data, when the master generates a clock and sends a clock signal to the slave, the slave receives an equal amount of invalid data (invalid data generated by the clock signal sent by the master), which requires the slave to perform data verification on the received second communication data sent by the master, for example, the invalid characters may be filtered through a start character and a data verification rule to obtain valid data. Illustratively, after clearing the interrupt signal if the first communication data is sent, the method further includes:

and receiving second communication data sent by the host, and filtering invalid data from the second communication data according to a preset data verification rule.

Optionally, the preset data check rule may include analyzing the second communication data, determining whether each data packet included in the second communication data satisfies a preset data packet format, and if there is a data packet included in the second communication data that does not satisfy the preset data packet format, determining that the data packet is invalid data, and filtering out the invalid data.

As can be seen from the above analysis, in the SPI-based duplex communication method provided in the embodiment of the present application, the signal line is connected between the master device and the slave device, so that when the slave device needs to send communication data to the master device or finishes sending communication data, the level change of the signal line can be controlled by the interrupt signal, so that the master device can send a clock signal to the slave device or terminate sending the clock signal according to the level change of the signal line, thereby implementing sending of communication data to the master device or terminating sending of the communication data by the slave device based on the clock signal, further implementing a duplex communication mode between the master device and the slave device, and enabling stable and efficient data interaction between the master device and the slave device.

As shown in fig. 5, fig. 5 is a flowchart of interaction between a slave and a master according to a fifth embodiment of the present application. The details are as follows:

s501, if the slave machine needs to send first communication data to the host machine, sending an interrupt signal to enable the level of the signal line to be changed from a first level to a second level;

and S502, if the master machine detects that the level of the signal line is changed from the first level to the second level, the master machine sends a clock signal to the slave machine.

And S503, after receiving the clock signal, the slave machine sends first communication data to the host machine.

S504, the host receives the first communication data sent by the slave and detects the level of the signal line in real time.

And S505, if the slave machine finishes sending the first communication data, clearing the interrupt signal so as to change the level of the signal wire from the second level to the first level.

S506, if the master detects that the level of the signal line changes from the second level to the first level, the master terminates sending the clock signal to the slave.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

Corresponding to the SPI-based duplex communication method described in the foregoing embodiment, fig. 6 and fig. 7 respectively show structural block diagrams of the master and the slave provided in the embodiment of the present application, and for convenience of description, only parts related to the embodiment of the present application are shown.

As shown in fig. 6, fig. 6 is a schematic structural diagram of a host according to a sixth embodiment of the present application. As can be seen from fig. 6, the master 101 and the slave 102 are connected by SPI communication, a clock line is connected between the master 101 and the slave 102, a signal line is further connected between the master 101 and the slave 102, and the master 101 includes:

a first sending module 601, configured to send a clock signal to a slave to instruct the slave to send first communication data based on the clock signal if it is detected that the level of the signal line changes from a first level to a second level; the level of the signal line is changed from a first level to a second level, the slave machine sends out an interrupt signal to control the level, and the slave machine sends out the interrupt signal when the first communication data needs to be sent to the host machine.

The detecting module 602 is configured to receive the first communication data sent by the slave, and detect the level of the signal line in real time.

A termination module 603, configured to terminate sending the clock signal to the slave if it is detected that the level of the signal line changes from the second level to the first level; wherein the level of the signal line is changed from the second level to the first level and is controlled by the slave machine clearing the interrupt signal, and the slave machine clears the interrupt signal after sending the first communication data.

In an optional implementation manner, the method further includes:

the first initialization module is used for initializing a first SPI controller of the host and a first working state of the signal line at the host end.

In an optional implementation manner, the method further includes:

and the second sending module is used for circularly sending the second communication data until the second communication data is sent if the second communication data to be sent is detected.

It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

As shown in fig. 7, fig. 7 is a schematic structural diagram of a slave according to a seventh embodiment of the present application. The slave 102 is connected with the master 101 through SPI communication, a clock line is connected between the slave 102 and the master 101, a signal line is further connected between the slave 102 and the master 101, and the slave 102 includes:

an issuing module 701, configured to issue an interrupt signal if first communication data needs to be sent to the host, so that the level of the signal line changes from a first level to a second level.

A third sending module 702, configured to receive a clock signal sent by the host, and send first communication data based on the clock signal; the clock signal is a signal sent to the slave after the master detects that the level of the signal line is changed from the first level to the second level.

A clearing module 703, configured to clear the interrupt signal if the first communication data is sent, so that the level of the signal line is changed from the second level to the first level, so as to instruct the host to terminate sending the clock signal.

In an optional implementation manner, the method further includes:

and the second initialization module is used for initializing a second SPI controller of the slave and a second working state of the signal line at the slave end.

In an optional implementation manner, the method further includes:

and the filtering module is used for receiving the second communication data sent by the host and filtering invalid data from the second communication data according to a preset data verification rule.

Fig. 8 is a schematic structural diagram of a host according to an eighth embodiment of the present application. As shown in fig. 8, the host 101 of this embodiment includes: at least one processor 80 (only one shown in fig. 8), a memory 81, and a computer program 82 stored in the memory 81 and executable on the at least one processor 80, the processor 80 implementing the steps in the method embodiment described above in fig. 2 when executing the computer program 82.

The host 101 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The host 101 may include, but is not limited to, a processor 80, a memory 81. Those skilled in the art will appreciate that fig. 8 is merely an example of the host 101 and does not constitute a limitation on the host 101, and may include more or less components than those shown, or combine certain components, or different components, such as input output devices, network access devices, etc.

The Processor 80 may be a Central Processing Unit (CPU), and the Processor 80 may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 81 may in some embodiments be an internal storage unit of the host 8, such as a hard disk or a memory of the host 8. The memory 81 may also be an external storage device of the host 8 in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the host 8. Further, the memory 81 may also include both an internal storage unit of the host 8 and an external storage device. The memory 81 is used for storing an operating system, an application program, a BootLoader (BootLoader), data, and other programs, such as program codes of the computer program. The memory 81 may also be used to temporarily store data that has been output or is to be output.

Fig. 9 is a schematic structural diagram of a slave according to a ninth embodiment of the present application. As shown in fig. 9, the slave 102 of this embodiment includes: at least one processor 90 (only one shown in fig. 9), a memory 91, and a computer program 92 stored in the memory 91 and executable on the at least one processor 90, the processor 90 implementing the steps in the method embodiment described above in fig. 4 when executing the computer program 92.

The slave 102 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The slave 102 may include, but is not limited to, a processor 90, a memory 91. Those skilled in the art will appreciate that fig. 9 is only an example of the slave 102, and does not constitute a limitation to the slave 102, and may include more or less components than those shown, or combine some components, or different components, for example, may further include an input/output device, a network access device, and the like.

The Processor 90 may be a Central Processing Unit (CPU), and the Processor 90 may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 91 may in some embodiments be an internal storage unit of the slave 9, such as a hard disk or a memory of the slave 9. In other embodiments, the memory 91 may also be an external storage device of the slave 9, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), or the like, provided on the slave 9. Further, the memory 91 may also include both an internal storage unit and an external storage device of the slave 9. The memory 91 is used for storing an operating system, an application program, a BootLoader (BootLoader), data, and other programs, such as program codes of the computer program. The memory 91 may also be used to temporarily store data that has been output or is to be output.

An embodiment of the present application further provides a network device, where the network device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, the processor implementing the steps of any of the various method embodiments described above when executing the computer program.

The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the above-mentioned method embodiments.

The embodiments of the present application provide a computer program product, which when running on a mobile terminal, enables the mobile terminal to implement the steps in the above method embodiments when executed.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/electronic device, a recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other ways. For example, the above-described apparatus/network device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.