阅读说明：本技术 用于等离子体加工设备的电压波形发生器 (Voltage waveform generator for plasma processing apparatus ) 是由 安东尼厄斯·威廉默斯·亨德里克斯·约翰尼斯·德里森 于 2020-04-21 设计创作，主要内容包括：一种在输出端(14)生成电压波形的方法和装置,包括提供具有第一幅值(V-(1))的第一DC电压、具有第二幅值的第二DC电流(I-(2))、具有第三幅值(V-(3))的第三DC电压和具有第四幅值(V-(4))的第四DC电压,其中,该第一幅值(V-(1))高于该第三幅值(V-(3))和该第四幅值(V-(4))。将该第四DC电压耦合到该输出端(14),然后将该第一DC电压耦合到该输出端,以使该输出端(14)的输出电压(V-(P))达到高水平。将该第一DC电压与该输出端(14)解耦,然后将该第三DC电压耦合到该输出端,以获得该输出电压(V-(P))的下降。在耦合该第三DC电压之后,将接地电位(V-(0))耦合到该输出端(14),并且在耦合该接地电位之后,将该第二DC电流(I-(2))耦合到该输出端(14),其中,该第二DC电流使该输出电压(V-(P))斜降。(A method and apparatus for generating a voltage waveform at an output (14) includes providing a voltage waveform having a first amplitude (V) 1 ) A second DC current (I) having a second magnitude 2 ) Having a third amplitude (V) 3 ) And has a fourth amplitude (V) 4 ) Wherein the first amplitude (V) is 1 ) Above the third amplitude value (V) 3 ) And the fourth amplitude (V) 4 ). Coupling the fourth DC voltage to the output terminal (14) and then coupling the first DC voltage to the output terminal to electrically output the output terminal (14)Pressure (V) P ) Reaching a high level. Decoupling the first DC voltage from the output (14) and then coupling the third DC voltage to the output to obtain the output voltage (V) P ) Is reduced. After coupling the third DC voltage, the ground potential (V) is set 0 ) Is coupled to the output (14) and, after coupling the ground potential, the second DC current (I) 2 ) Coupled to the output terminal (14), wherein the second DC current causes the output voltage (V) P ) And (5) obliquely descending.)

1. A method of generating a voltage waveform at an output (14), the method comprising:

providing a first amplitude (V)₁) A second DC current (I) having a second magnitude₂) Having a third amplitude (V)₃) And has a fourth amplitude (V)₄) Wherein the first amplitude (V) is₁) Above the third amplitude value (V)₃) And the fourth amplitude (V)₄)，

Coupling the fourth DC voltage to the output terminal (14) and then coupling the first DC voltage to the output terminal such that the output voltage (V) of the output terminal (14)_P) The high level is reached and the voltage level is,

decoupling the first DC voltage from the output (14) and then coupling the third DC voltage to the output to obtain the output voltage (V)_P) The decrease in the amount of the nitrogen component,

after coupling the third DC voltage, the ground potential (V) is set₀) Is coupled to the output (14), an

After coupling the ground potential, the second DC current (I)₂) Coupled to the output terminal (14), wherein the second DC current causes the output voltage (V)_P) And (5) obliquely descending.

2. The method of claim 1, wherein the first amplitude (V) is during coupling of the respective DC voltage to the output terminal (14)₁) The third amplitude (V)₃) And the fourth amplitude (V)₄) Is constant.

3. The method of claim 1 or 2, wherein the third amplitude (V)₃) And the fourth amplitude (V)₄) One or both of which are higher than the ground potential (V)₀)。

4. The method of any one of the preceding claims, wherein the method comprisesThird amplitude (V)₃) And the fourth amplitude (V)₄) Is different.

5. The method of any of claims 1 to 4, comprising: the output (14) is coupled to a process platform (105) that supports a substrate (101) for plasma processing, wherein the voltage waveform induces a positive voltage peak followed by a negative voltage on an exposed surface of the substrate.

6. The method of claim 5, comprising selectively coupling the fourth DC voltage between the step of coupling the fourth DC voltage and the step of coupling the first DC voltage and/or coupling the third DC voltage and coupling the ground potential (V)₀) Is measured by the commutation time (T) between steps (a) and (b)_Reversing) To be respectively coupled at the time (T) of the first DC voltage_SW1) And coupling the ground potential (V)₀) To obtain zero current between the output (14) and the processing platform (105).

7. The method of claim 5 or 6, comprising coupling the fourth DC voltage between the step of coupling the fourth DC voltage and the step of coupling the first DC voltage and/or the step of coupling the third DC voltage with the ground potential (V ™)₀) Is measured by the commutation time (T) between steps (a) and (b)_Reversing) Is selected to represent 0.5/f₀Wherein f is₀Is the natural frequency of the electrical system of the plasma processing system (100) as seen at the output (14).

8. The method of any of claims 5 to 7, comprising: measuring a current between the output (14) and the processing platform (105) and adjusting one or more of:

a commutation time (T) between the step of coupling the fourth DC voltage and the step of coupling the first DC voltage_Reversing)，

Coupling the third DC voltage to the ground potential (V)₀) The time of the commutation between the steps of (a),

the third amplitude (V)₃) And an

The fourth amplitude (V)₄)。

9. The method of any one of the preceding claims, comprising dividing the fourth amplitude (V)₄) Chosen as an average representing:

at the moment (T) of coupling the fourth DC voltage to the output (14)₀) Output voltage (V)_P) And an

At the moment (T) when the first DC voltage is coupled to the output terminal₁) Output voltage (V)_P) (ii) a And/or applying the third amplitude (V)₃) Chosen as an average representing:

at the moment (T) of coupling the third DC voltage to the output (14)₃) Output voltage (V)_P) And an

At the ground potential (V)₀) Time instant (T) coupled to the output terminal₄) Output voltage (V)_P)。

10. The method of any one of the preceding claims, comprising decoupling the fourth DC voltage after coupling the first DC voltage, and/or decoupling the third DC voltage after coupling the second DC current.

11. A voltage waveform generator (10) for a plasma processing apparatus (100), the voltage waveform generator comprising a power stage (11, 110) and a controller (16), wherein the power stage comprises:

an output node (14),

through the first Switch (SW)₁) A first DC power source (21) coupled to the output node (14), wherein the first DC power source is configured to output a first amplitude (V)₁) The voltage of (a) is set to be,

a second DC power supply (51) coupled to the output node (14) and configured to provide a current (I) of a second magnitude₂) And an

Through the second Switch (SW)₂，SW₅) A ground terminal (13) coupled to the output node (14),

characterized in that the power stage (11, 110) further comprises:

through the third Switch (SW)₃) A third DC power source (31) coupled to the output node (14), wherein the third DC power source is configured to output a third amplitude (V)₃) Voltage of, and

through the fourth Switch (SW)₄) A fourth DC power source (41) coupled to the output node (14), wherein the fourth DC power source is configured to output a fourth magnitude (Vg)₄) The voltage of (a) is set to be,

wherein the first DC power source (21), the third DC power source (31) and the fourth DC power source (41) are coupled in parallel to the output node (14),

wherein the first amplitude (V)₁) Greater than the third amplitude (V)₃) And the fourth amplitude (V)₄)，

Wherein the controller (16) is configured to control the first Switch (SW)₁) The second Switch (SW)₂，SW₅) The third Switch (SW)₃) And the fourth Switch (SW)₄) To obtain a predetermined voltage waveform at the output node (14).

12. The voltage waveform generator of claim 11, wherein the controller (16) is configured to sequentially close the fourth Switch (SW) in succession₄) The first Switch (SW)₁) The third Switch (SW)₃) And the second Switch (SW)₂，SW₅) To obtain a voltage pulse at the output node (14).

13. The voltage waveform generator of claim 12, wherein the controller (16) is configured to close the third Switch (SW)₃) Before the first Switch (SW) is opened₁)。

14. The voltage waveform generator of any of claims 11 to 13, wherein the second DC power source (51) is configured to draw a current (I) having a positive second magnitude from the output node (14)₂)。

15. The voltage waveform generator according to any of the claims 11 to 14, wherein the second DC power source (51) is passed through a fifth Switch (SW)₂，SW₅) Coupled to the output node, the controller (16) is configured to operate the fifth switch.

16. The voltage waveform generator of claim 15, wherein the controller (16) is configured to close the fifth switch after closing the second switch.

17. The voltage waveform generator of claim 15 or 16, comprising a bypass Switch (SW) connected in series between the ground terminal (13) and the output node (14)₅) And a process Switch (SW)₂) Wherein the second DC power source (51) is coupled to a node (15) between the bypass switch and the process switch, wherein the controller (16) is configured to operate the bypass switch and the process switch such that when the bypass Switch (SW) is turned on₅) When closed, the process Switch (SW)₂) The second switch is formed and when the bypass Switch (SW)₅) When disconnected, the process Switch (SW)₂) The fifth switch is formed.

18. The voltage waveform generator of any one of claims 11 to 17, comprising a current control loop (164) coupled to the controller (16), wherein the current control loop comprises a current measurement sensor (165) operable to measure a current at the output node (14), and wherein the controller (16) is configured to adjust, based on a value determined by the current measurement sensor (165), one or more of:

the first Switch (SW)₁) The second Switch (SW)₂，SW₅) The third Switch (SW)₃) And the fourth Switch (SW)₄) A switching time of one or more of, and

the third amplitude (V)₃) And the fourth amplitude (V)₄) Set point of one or more of.

19. The voltage waveform generator according to any of the claims 11 to 18, comprising a switch coupled to the third Switch (SW)₃) And the output node (14) and/or the fourth Switch (SW)₄) A commutation inductor (L) between the output node (14)₃，L₄)。

20. An apparatus (100) for plasma processing, comprising:

means (102, 107) for generating a plasma (103),

a process platform (105) for supporting a substrate (101) to be processed by the plasma, and

the voltage waveform generator (10, 110) of any of claims 11 to 19, wherein the output node (14) is electrically connected to the processing platform (105).

21. The voltage waveform generator (10) of any one of claims 11 to 19, or the device of claim 20, wherein the controller (16) is configured to implement the method of any one of claims 1 to 10.

Technical Field

The present invention relates to a voltage waveform generator for a plasma processing apparatus and an associated method of generating a voltage waveform for plasma processing, particularly for generating a voltage waveform for voltage biasing on a substrate to be plasma processed. The voltage bias is advantageously used to control ion energy in plasma assisted etching, plasma assisted layer deposition, or reactive ion etching (REI).

Background

In plasma-assisted etching and plasma-assisted layer deposition, a Radio Frequency (RF) generator is used to generate a bias voltage to control ion energy. To improve process control, it is important to accurately control the bias voltage and the resulting Ion Energy Distribution (IED). Generating this bias voltage is done by a limited efficiency (broadband) linear amplifier or a limited flexibility (narrow band) switched amplifier or a dedicated pulse generating amplifier. Most amplifiers only indirectly control the output voltage waveform (e.g., control the output power or rely on calibration) resulting in limited performance (the generated waveform is less close to the ideal output voltage waveform), resulting in less than ideal ion energy distribution and limited reproducibility (wafer-to-wafer variations and system-to-system variations).

US 9208992 describes a plasma processing apparatus comprising a switched mode power supply for forming a periodic voltage function at an exposed surface of a substrate to be processed. The periodic voltage function achieves a desired ion energy intensity profile to perform etching of the substrate or plasma deposition on the substrate.

The above-described switched mode power supply may generate a waveform with a specific shape of the DC current to compensate for the ion current (see fig. 14 of US 9208992). To this end, the switched mode power supply comprises two switching components coupled in a half bridge manner and controlled based on a drive signal generated by a controller as shown in fig. 3 of US 9208992. For such waveforms, the reactor capacitance and stray inductance may experience commutation, resulting in losses. The relationship between the system parameters and the commutation (or switching) loss P can be expressed as:

P_{reactor reversal}∝C_{Reactor with a reactor shell}·V_Reversing ²·f_Reversing

Typical ranges for these parameters are:

-C_{reactor with a reactor shell}: from 500pF to 10nF of the air,

-V_reversing: the voltage of the power supply is 10V to 2kV,

-f_reversing: 20kHz to 1 MHz.

Depending on the process conditions and reactor design, this may result in losses in excess of 500W.

In current plasma processes, there is a trend toward higher commutating voltage levels, larger reactor sizes, higher capacitance C_{Reactor with a reactor shell}. Therefore, using the prior art waveform generator would introduce higher losses, which is unacceptable.

Furthermore, the plasma reactor has an inherent reactor capacitance and the interconnection between the reactor and the bias voltage generator has stray inductances, which form an LC circuit with inherent resonance characteristics. Due to resonances in the system, slow switching speeds (finite dV/dt at the switching node) or damping resistances (or buffers) are mandatory to prevent excitation of resonances that can lead to unwanted substrate voltage ringing. Such ringing can produce undesirable voltages on the substrate that negatively impact the required IED. This slow switching speed results in a longer discharge period, effectively reducing the machining/discharge ratio, which in turn results in longer time to machine the substrate. Too long a discharge time can also have a negative effect on the formation of the sheath or on the preservation of the sheath. However, the damping resistor (or snubber) may cause additional undesirable losses.

Disclosure of Invention

The object of the present invention is to overcome the above drawbacks. It is an object of the present invention to provide a voltage waveform generator for plasma processing and an associated method of generating a voltage waveform, such that higher efficiencies can be achieved. It is an object of the present invention to provide such a generator and method which allows for an increase in process throughput with no or limited loss of efficiency.

It is an object of the present invention to provide a plasma processing apparatus and associated method that allows for improved process control. In particular, it is an object of the present invention to provide such a device and method which are able to more accurately approximate an ideal or desired voltage waveform and/or which allow faster convergence to such an ideal waveform.

According to a first aspect of the present invention there is provided a method of generating a voltage waveform for plasma processing as set out in the accompanying claims. The voltage waveform is advantageously a periodic bias voltage that is applied to an exposed surface of a substrate undergoing plasma processing, such as plasma assisted etching, plasma assisted layer deposition, or reactive ion etching (REI).

According to a second aspect of the present invention there is provided a voltage waveform generator for a plasma processing apparatus as set forth in the appended claims. The voltage waveform generator is advantageously configured to generate a periodic bias voltage to be applied to a substrate undergoing plasma processing. The voltage waveform generator is advantageously configured to implement the method according to the first aspect.

According to a third aspect of the present invention there is provided a plasma processing apparatus comprising the voltage waveform generator of the second aspect.

The voltage waveform generator according to the present invention comprises a power stage topology that allows for the generation of a periodic bias voltage, for example for use in a plasma processing apparatus. The power stage topology includes different voltage levels (voltage levels) that may be successively coupled to the output to obtain the periodic bias voltage. The number of voltage levels is such that resonant commutation can be obtained during voltage level variations of the waveform, thereby enabling fast and lossless commutation. Furthermore, advantageously, by suitably controlling the timing of the application of the switches of different voltage levels, and by suitably selecting the voltage levels, the following results can be obtained: at the end of the commutation (discharge) period, the desired substrate voltage level is reached, which advantageously is substantially equal to the generator output voltage, and the current through the stray inductances of the interconnections between the generator and the substrate is approximately 0A. Thus, there is no ringing in the system, and no damping or slow commutation need be implemented. Lossless commutation allows the bias voltage to be generated in an efficient manner. The fast commutation reduces the disturbance of the sheath (sheath) during the discharge period. This results in better process control. Fast commutation enables a further reduction of the IED range. Narrow IEDs are critical to process control.

According to another aspect, a method for controlling or operating a plasma processing apparatus is described herein.

Drawings

Aspects of the present invention will now be described in more detail, with reference to the appended drawings, wherein like reference numerals represent like features, and wherein:

fig. 1 shows an example of a voltage waveform generator according to aspects of the present invention, which is used as a bias generator for an ICP (inductively coupled plasma) reactor;

FIG. 2 shows a simplified reactor plasma model and a voltage waveform generator according to the present invention coupled thereto;

FIG. 3 shows (not to scale) a (periodic) voltage waveform that may be applied to the node shown in FIG. 2;

fig. 4 shows a voltage waveform generator according to a first embodiment of the invention;

FIG. 5 shows the voltage waveform generator of FIG. 4 with a simplified model of a load coupled to a power stage of the voltage waveform generator;

FIG. 6 shows a possible switching embodiment of the voltage waveform generator of FIG. 4 with an N-channel MOSFET;

FIG. 7 illustrates the voltage waveform generator of FIG. 4, wherein the DC current source is implemented with a DC voltage source and coupled inductor, and an optional Transient Voltage Suppressor (TVS);

FIG. 8 shows a graph illustrating the relationship between the power stage voltage level and the switch control signal of the voltage waveform generator of FIG. 4;

FIG. 9 schematically illustrates a closed-loop control embodiment of the voltage waveform generator of FIG. 4;

fig. 10 shows the voltage waveform generator of fig. 4 with the addition of a commutation inductor;

fig. 11 shows graphs illustrating voltage levels and current levels during commutation with switching slew rates in accordance with aspects of the present invention;

FIG. 12 shows a graph illustrating voltage levels and current levels during non-optimal commutation with switching slew rate;

FIG. 13 shows a voltage waveform generator as in FIG. 4, including an overvoltage protection circuit;

fig. 14 shows a first embodiment example of the overvoltage protection circuit of fig. 13;

fig. 15 shows a second embodiment example of the overvoltage protection circuit of fig. 13;

fig. 16 shows a voltage waveform generator according to a second embodiment of the invention, with a continuous current source;

fig. 17 shows a possible switching implementation of the voltage waveform generator of fig. 16 with N-channel MOSFETs.

Detailed Description

Fig. 1 illustrates one of the typical uses of a bias voltage waveform generator (BVG)10 in an Inductively Coupled Plasma (ICP) apparatus 100, wherein BVG 10 controls the voltage of a substrate 101 (typically a wafer) by controlling the substrate stage voltage. In the plasma reactor 102, a plasma 103 is generated by introducing a plasma-forming gas 104 into a dielectric tube 108 surrounded by an induction coil 107. This arrangement forms a plasma torch that directs a plasma 103 towards a platform 105 (substrate table) on which a substrate 101 is placed. Alternatively, the precursor 109 may be introduced into the plasma reactor 102. An RF voltage is applied to the induction coil 107 by an RF power supply 120 and a matching network 121 as known in the art. The RF power supplies 120 and BVG 10 may be controlled by a system host controller 130. Plasma processes suitable for the present invention are so-called low pressure or reduced pressure plasmas, i.e. operating at pressures significantly below atmospheric pressure, for example between 1mTorr and 10 Torr. For this purpose, the plasma reactor 102 is advantageously gas-tight, and the required pressure in the plasma reactor 102 is obtained by means of a vacuum pump 106.

BVG 10 can also be used in other configurations, such as Capacitively Coupled Plasma (CCP) reactors, or direct interconnections (not via the system host) of control signals between source power generators (RF power supplies) and BVG. Different sources can be used to generate the plasma (e.g., capacitively coupled plasma, electron cyclotron resonance, magnetron, DC voltage, etc.).

Fig. 2 shows a (highly) simplified electrical model of a plasma reactor, showing the reactor and the load formed by the plasma pair BVG 10to explain the operation of BVG 10. BVG 10 includes a power stage 11 that passes through an optional physical capacitor C₁Output terminal 12 coupled to BVG 10to prevent a DC current from a voltage induced on the surface of substrate 101 or from a voltage of the electronic chuck from flowing through power stage 11. The power stage 11 is configured to generate a bias voltage applied on the output terminal 12. Due to C₁The DC component of the bias voltage is self-biased, e.g., the voltage is set due to differences in ion and electron mobility in the sheath. The plasma reactor may be modeled as shown in fig. 2, but more or less complex models may also be used. L is₁Is the lumped inductance representing the inductance caused by the BVG output power interconnect and return path. C₂Is a lumped capacitor representing the capacitance from the substrate stage 105 and substrate stage power interconnect to ground. This capacitance is typically dominated by the capacitance from the substrate table to the dark shield, i.e., the metal shield adjacent to the stage 105 that prevents plasma from propagating beyond the stage (e.g., into the pump 106). C₃Is the combined capacitance of the dielectric substrate and/or the under-table platen of dielectric material (e.g., due to an electrostatic chuck support on/in the substrate platen). R_PRepresenting the sheath impedance caused by the limited ion mobility in the sheath during the process period. D_PIndicating a high electron mobility in the sheath during the discharge period. V_PLIs the plasma potential at the sheath over the substrate.

The DC (bias) voltage on the sheath ideally results in a narrow IED, while the level of the DC voltage controls the level of the (average) ion energy. Charge accumulation occurs on the dielectric substrate and/or the sub-table stage of the dielectric material (e.g., electrostatic chuck support) due to positively charged ions collected on the surface. This charge build-up on the substrate and/or substrate stage needs to be compensated for in order to keep the voltage potential (and hence the ion energy) on the sheath constant. It is desirable to limit the charge build-up and hence the potential on the substrate and/or substrate table to prevent damage to the substrate and/or substrate table. Such compensation may be provided by providing for successive process periods T_PDischarge period T in between_DDuring which a periodic discharge of the substrate and/or substrate table is effected, as shown in fig. 3. Fig. 3 shows an ideal periodic voltage waveform V to be generated by BVG_PSo as to obtain a desired voltage waveform V on the exposed surface of the substrate_S. In fig. 2, node V is shown where the waveform is evaluated_P、V_T、V_SWherein V is_PRepresenting the voltage, V, output by the power stage 11_TRepresents a voltage at the substrate stage (stage) 105, and V_SRepresenting the substrate voltage, i.e., the voltage on the exposed surface of the substrate 101. Discharge period T_DMay be about 500 ns. Machining period T_PMay be about 10 mus.

In accordance with the present invention, the prior art disadvantages associated with excessive commutation losses and uncontrolled resonant ringing are remedied by implementing specific commutation, referred to as resonant commutation, in power stage 11 at BVG 10. Referring to fig. 4, in order to enable resonant commutation, the power stage 11 comprises a first DC power supply implemented to output a first amplitude V₁Voltage source 21 of a DC voltage. DC voltage source 21 passes through a first switch SW₁To the output node 14 of the power stage 11. The power stage 11 further comprises a second DC power supply and providesA ground terminal 13 at ground potential, the power supply being embodied to output a DC current I of a second magnitude₂And a current source 51. In the present embodiment, the DC current source 51 passes through the second switch SW₂Connected to the output node 14. The ground terminal 13 passes through the bypass switch SW₅Is connected to the current source 51 and the second switch SW₂Intermediate nodes 15 in between.

Closing switch SW₂And SW₅Both connecting ground terminal 13 to output node 14. The output node is connected to output terminal 12 of BVG 10, which in turn may be coupled to substrate table 105. DC blocking capacitor C₁May optionally be coupled between output node 14 and output terminal 12.

Furthermore, the power stage 11 comprises a third DC supply and a fourth DC supply, which are respectively embodied as voltage sources 31, 41 and are configured to respectively output a third amplitude V₃And a fourth amplitude V₄The DC voltage of (1). The DC voltage sources 31 and 41 are connected via respective third switches SW₃And a fourth switch SW₄Connected to the output node 14. The interconnection lines between the voltage sources 31 and 41 and the output node 14 may advantageously each comprise a diode D₃And D₄So as to allow current in only one direction. All voltage sources 21 to 41 are connected in parallel to the output node 14.

A simplified model of the load seen from the output node 14 is shown in figure 5. FIG. 6 shows a switch SW using N-channel MOSFETs₁To SW₅Possible embodiments of (1).

Referring to fig. 7, the DC current source 51 may alternatively be implemented using a DC voltage source 52 in series with an inductor 53, which typically has a large inductance, e.g., 0.5mH or more. The transient voltage suppressor 54 is advantageously placed in SW₅To provide a continuous current path for inductor 53 and limit SW₅The voltage of (c). Other alternative embodiments use power amplifiers that generate variable DC currents, for example to compensate for dielectric constant changes caused by voltage bias. Likewise, alternative embodiments of the voltage sources 21, 31 and 41 are possible, for example based on electricity with a capacitor connected between the current source output and groundA flow source. Alternatively, the low voltage side of voltage source 41 (connected to ground in fig. 7) may be connected to the low voltage side of voltage source 52. This allows the use of only a voltage source that provides a positive voltage.

The additional DC voltage sources 31 and 41 allow to reduce or eliminate commutation losses and resonant ringing during or after commutation when obtaining the required bias voltage waveform according to the invention. Referring to fig. 8, the switches SW may be paired in the order shown using control signals₁To SW₅And (5) carrying out operation. In order to obtain a desired periodic voltage waveform V at the substrate 101_SBVG 10 will require an output voltage waveform V at the output node 14_PDepending on the modeled load (see, e.g., fig. 2). V_PA positive voltage peak may be included to obtain a substrate discharge followed by a voltage drop and ramp down during the processing time of the substrate.

Advantageously, the waveform V_PAt least three different voltage levels may be included: amplitude of V₁Advantageously supplied by the voltage source 21; amplitude of V₅By ramping down the voltage when the current source 51 is connected to the load; and a ground potential V₀. The voltage waveform generator 10 according to the present invention advantageously allows such a waveform to be obtained by: using additional voltage sources 31 and 41 at waveform V_PMiddle supply of intermediate voltage level V₃And V₄So as to realize the voltage V on the one hand₁Rise and, on the other hand, effect a voltage drop to ground potential V₀Or even down to V₅. These additional (intermediate) voltage levels allow avoiding undesired voltage oscillations after a commutation event by using appropriate switching timings between the different voltage levels.

For example, still referring to FIG. 8, from time T₀At the beginning, the substrate discharge period T_DStarting, wherein the substrate voltage V_SBecomes a positive value. For this purpose, a switch SW₄At T₀Closed, and other switches SW₁、SW₂And SW₃(except for the bypass switch SW₅Which can be closed so as to be a current I₂Providing a current path) remains open. Closed SW₄Result in V_PUp to the amplitude V of the voltage source 41₄. Next, at T₁，SW₁Closure, resulting in V_PRises to level V₁。SW₄Advantageously slightly at T₁Then disconnected because of V₄Below V₁And due to the diode D₄Is present. Advantageously, the amplitude V is adjusted₁Is selected such that the substrate voltage V_SIs positive.

For a substrate discharge period T_DAfter that, a new machining period T is started_PAgain let V_SIs negative. For this purpose, the switch SW is advantageously opened₁And also SW₄(e.g., at time T₂) And later on, at T₃Switch SW₃Is closed, resulting in a voltage V_PDown to the amplitude V of the voltage source 31₃Up to switch SW₂At time T₄Closed to connect the output node to ground potential (resulting in a (further) drop of Vp) because of the switch SW₅Remains closed until a later time T₅. This marks the machining period T_PTo begin. Amplitude V₃、V₄And V₁Advantageously, the amplitude is kept constant during the closing of the respective switch, and the amplitude may be kept constant throughout the entire operation.

At T₅，SW₅Is disconnected and SW₂And remain closed. This results in the output node 14 being connected to the current source 51 and the current I₂Will influence V_PThereby advantageously allowing the substrate voltage V to be compensated for charge build-up on the substrate and/or substrate table_SMaintained at a constant level. Just before starting a new discharge period, the bypass switch SW₅At time T₇Closed (advantageously slightly at time T)₆Disconnect switch SW₂Thereafter).

Due to the diode D₃Switch SW₃Can exceed T₄And may even exceed T₅Is turned off at a certain time. Note that SW₄And SW₁Due to diode D₄) And SW₃And SW₂Due to diode D₃) Advantageously no dead time is required. Dead time T₃-T₂Is to prevent V₁And V₃Short circuit is required.

The power stage 11 as described herein allows to be operated in such a way (by being the switch SW)₁To SW₅Generate appropriate switch control signals) to minimize oscillations on the output and prevent parasitic resonances in the system. For this purpose, the power stage is advantageously operated such that at the end of the commutation period L is passed₁Becomes 0A. In the waveform of fig. 8, there are basically two commutation periods. The first commutation is during the voltage rise phase, in particular starting at T₀I.e. SW₄And ends at T₁I.e. SW₁Closing of (3). The second commutation is during the voltage reduction phase. The commutation period starts at T₃I.e. SW₃And ends at T₄I.e. SW₂Closing of (3).

To ensure at the end of the commutation period (in particular at T)₄And advantageously also at T₁) Through L₁Can become 0A, advantageously suitably selected to respectively close the switches SW₁And SW₂Time T of₁And T₄(or, equivalently, the switch interval T)₁-T₀And T₄-T₃). If Switch (SW)₁Or SW₂) Closing too late, due to the capacitance on the output node 14 and the voltage on this capacitance not being equal to C₄L is caused by the fact that the voltage₁And the voltage V on the output node 14_PIn the middle of the oscillation. If Switch (SW)₁Or SW₂) Closure too early, then L₁Is not 0A, and this will result in L₁And C₄Ringing occurs in between. The criticality of selecting the appropriate switching time is shown in fig. 11 and 12. In FIGS. 11 and 12, T₀And T₁Indicating application of a control signal to the switch SW₄And SW₁To close the moment of the corresponding switch. In practice, the switch will have a limited switching speed, as in the output section of fig. 11 and 12Voltage V at point 14_PIs shown by the finite dV/dt. As a result, the switch SW₄Will be at T₀Begins to close and will be at time T_SW4The closed state is achieved. Similarly, switch SW₁At T₁Begins to close and will be at time T_SW1The closed state is achieved.

As can be seen from FIG. 11, at time T_SW1Implementing the switch SW₁At the moment, by L₁Current of (I)_L1Has dropped to zero and prevents the voltage V at the substrate stage_TOr the voltage V at the substrate_SIs oscillated. This is not the case in FIG. 12, where in I_L1At T_SW1Time instant of non-zero to realize SW₁Closed state (T)_SW1)。

In addition to the above, by appropriate selection of the voltage level (respectively V) applied during the commutation period₃And V₄) To advantageously prevent oscillation. The voltage level advantageously falls at the start of commutation (time T, respectively)₀And T₃) Voltage level of time and end of commutation (time T, respectively)₁And T₄) Between voltage levels of time. It can be seen that V₃And V₄Is equal to (V)_{End of commutation}+V_{Start of commutation})/2. In other words, V₃Is of optimum amplitude V_PAt T₀And T₁Average value of (a). V₄Is of optimum amplitude V_PAt T₃And T₄Average value of (a).

The load of BVG 10 as seen at output node 14 can be modeled as having a reactor inductance L₁And total capacitance C₄In the series LC circuit of (1), as shown in FIG. 5, are each equal to T₁-T₀And T₄-T₃Optimum commutation time T_ReversingCan be arranged asWherein C is₄Representing the equivalent capacitance seen from the output node 14, e.g. C in the model of FIG. 2₁、C₂And C₃The sum of (a) and (b). More generallyIn one word, it can be said that the optimum commutation time T of the ideal conditions is assumed_ReversingCorresponding to the fundamental natural frequency f of the load₀Half of the period corresponding to (resonant frequency), or T_Reversing＝0.5/f₀。

It was assumed above that all components (e.g. switches, diodes and lumped models of plasma reactors) are ideal and lossless. Since this is not in accordance with the actual situation, the commutation parameters can be further adjusted to take into account the non-ideal situation. Operation may be started based on the values of the commutation parameters (commutation time, commutation voltage) determined above. During operation, one or more of these commutation parameters are advantageously adjusted by implementing appropriate process controls, for example by a closed loop control algorithm, for example based on current feedback. Referring to fig. 9, BVG 10 includes a controller 16 configured to control the operation of power stage 11. In particular, the controller 16 is configured to output a switch control signal 161 to control the switch SW₁To SW₅The operation of (2). The controller 16 may be configured to output a voltage setpoint 162 to set the magnitude of one or more of the DC voltage sources 21, 31, 41 and possibly 52. The controller 16 may be further configured to output a current setpoint 163 to set the DC current I output by the current source 51₂The level of (c). Alternatively, one or more of the DC voltage sources 21, 31, 41 and 52 and/or the current source 51 may have a voltage output or a current output of fixed magnitude.

The controller 16 advantageously includes a feedback control loop, advantageously a current feedback control loop 164. Current control loop 164 includes a current sensor 165 configured to measure the current output by power stage 11. The current sensor 165 may be arranged at the output node 14. The controller 16 may include a first input 167 coupled to the current control loop 164, which is configured to feed the value of the output current measured by the current sensor 165 to the controller 16. Through the second input 166, the controller 16 may be configured to receive setpoints for one or more of the switch control signal 161, the voltage setpoint 162, and the current setpoint 163. These set points may be received from a system host controller or user interface, which may be configured to determine the set points based on a model of the load of BVG 10 (e.g., as determined in the preceding paragraph). The controller 16 may be configured to adjust the set point, in particular the switch control signal 161 and/or the voltage set point 162, based on an input 167 fed back from the current sensor 165.

Referring to FIG. 10, in order to have a high self-resonant frequency (e.g., low C)₄And/or low L₁) In the case of reactors of (2) and of (SW)₁Or SW₂Is less sensitive to the closing moment of the reversing switch SW₃And SW₄Series-connected mode adding commutation inductor L₃And L₄. Alternatively or additionally, the output blocking capacitor C may be connected to₁An inductor (not shown) is added in series.

The diagram of fig. 10 additionally includes an overvoltage protection circuit, which is connected via a diode D_FWAnd a bidirectional transient voltage suppressor TVS_FWTo allow protection of the SW₄And L₄In between.

Referring to fig. 13, an overvoltage protection circuit 17 may be provided at the output of the power stage 11 or BVG 10 and configured to protect the power stage 11 by clamping the output voltage. A possible embodiment of the overvoltage protection circuit is shown in fig. 14 and 15. The overvoltage protection circuit may comprise a diode D between the output node 14 and the voltage source 21₁. Between the output node 14 and ground potential, a diode D₂And a unidirectional transient voltage suppressor TVS₁Coupled in the opposite current direction. When the current measuring sensor 171, 172 or 173 detects a current through the clamping diode and/or TVS, the power stage 11 may be turned off to reduce losses.

Referring to fig. 16 and 17, in an alternative embodiment of power stage 110 of BVG 10, a current source 51 is coupled between output node 14 and output terminal 12, advantageously between output node 14 and output blocking capacitor C₁In the meantime. This allows to have a continuous compensation current I₂Although the voltage across current source 51 will be higher than the voltage across power stage 11. In the power stage 110, a bypass switch SW₅Can be omitted even if the switch SW₂Should have bi-directional voltage blocking and current conducting capabilities.