阅读说明：本技术 用于快速瞬态响应的开关电力调节器中的自适应电流控制 (Adaptive current control in switching power regulators for fast transient response ) 是由 申蔚 于 2020-03-24 设计创作，主要内容包括：本公开描述了用于快速瞬态响应的开关电力调节器中自适应电流控制的各个方面。在一些方面,响应于检测到瞬态负载(702),防止开关电力调节器(134)的时钟(326)影响电流应用到调节器的电感器。第一开关设备(302)应用电流到调节器的电感器(310),直到电感器电流达到最大电流水平(712)为止。然后,第二开关设备(304)基于开关电力调节器的输出电压(312)使电流能够流过电感器,直到电感器电流达到电流控制信号(716)为止。在一些方面,偏移(706)也被应用到电流控制信号以进一步增加平均电感器电流。这些操作可以在不中断时钟的情况下重复进行,以快速增加电感器电流,因此响应于瞬态负载电流被提供给调节器输出。(The present disclosure describes various aspects of adaptive current control in switching power regulators for fast transient response. In some aspects, in response to detecting a transient load (702), a clock (326) of a switching power regulator (134) is prevented from affecting the application of current to an inductor of the regulator. The first switching device (302) applies current to an inductor (310) of the regulator until the inductor current reaches a maximum current level (712). The second switching device (304) then enables current to flow through the inductor based on the output voltage (312) of the switching power regulator until the inductor current reaches the current control signal (716). In some aspects, an offset (706) is also applied to the current control signal to further increase the average inductor current. These operations may be repeated without interrupting the clock to rapidly increase the inductor current, and thus be provided to the regulator output in response to the transient load current.)

1. A method implemented by a switching power regulator to increase output current in response to an increase in a load on the switching power regulator, the method comprising:

detecting the increase in the load at an output of the switching power regulator;

in response to the increase in the load, initiating an adaptive current control mode of the switching power regulator in which a clock-influencing current of the switching power regulator is prevented from being applied to an inductor of the switching power regulator;

implementing a first phase of the adaptive current control mode in which the current is applied to the inductor of the switching power regulator via a first switching device and from an input of the switching power regulator until an inductor current reaches a predefined level of maximum current;

implementing a second phase of the adaptive current control mode in which the current is enabled to flow through the inductor via a second switching device and from a potential below the input of the switching power regulator until the inductor current reaches a current control signal based on an output voltage of the switching power regulator;

detecting a decrease in the load at the output when the switching power regulator is operating in the adaptive current control mode; and

in response to the reduction of the load at the output, switching the switching power regulator to operate in a steady-state mode in which the clock of the switching power regulator affects the application of the current to the inductor of the switching power regulator.

2. The method of claim 1, wherein operating the switching power regulator in the adaptive current control mode further comprises applying a predefined offset to the current control signal effective to increase an average amount of the inductor current flowing through the inductor.

3. The method of claim 1 or 2, wherein operating the switching power regulator in the adaptive current control mode further comprises comparing a current-based derivative of the current control signal to a predefined ramp signal to detect the reduction of the load at the output.

4. The method of any of the preceding claims, wherein operating the switching power regulator in the adaptive current control mode further comprises masking a slope compensation signal applied to the current control signal during the steady state mode operation to prevent the slope compensation signal from affecting current application to the inductor.

5. The method of any one of the preceding claims, wherein:

the first phase of implementing the adaptive current control mode comprises:

sensing, at a first node operably coupled to the first switching device, an amount of the current applied to the inductor of the switching power regulator to provide a first indication of the inductor current; and

deactivating the first switching device in response to the first indication of inductor current flow meeting a predefined threshold for the maximum current level; or the second stage of implementing the adaptive current control mode comprises:

sensing, at a second node operably coupled to the second switching device, an amount of the current flowing through the inductor of the switching power regulator to provide a second indication of the inductor current; and

comparing the second indication of the inductor current to the control signal based on the output voltage of the switching power regulator when the second switching device is activated.

6. The method of any of the preceding claims, further comprising detecting the increase in the load at the output of the switching power regulator based on at least one of:

the switching power regulator switching from a Pulse Frequency Modulation (PFM) mode to a Pulse Width Modulation (PWM) mode;

an output voltage dip at the output of the switching power regulator;

a rising edge of an output voltage provided by an error amplifier operably coupled to the output of the switching power regulator providing the current control signal; or

A current-based output provided by the error amplifier operatively coupled to the output of the switching power regulator.

7. A circuit for regulating power, comprising:

a first switching device coupled to an input of the circuit;

an inductor having a first end coupled to the first switching device and a second end coupled to an output of the circuit;

a second switch coupled between the first end of the inductor and a potential below the input of the circuit;

first and second sensing electronic circuits configured to provide first and second indications of current flowing through the first and second switching devices, respectively;

a clock operably coupled to the drive electronics of the first switching device and the second switching device;

a current comparator having an output operably coupled to the drive electronics and a first input operably coupled to the second sense electronics;

an error amplifier having an input operably coupled to the output of the circuit and an output coupled to a second input of the current comparator; and

an adaptive current controller configured to:

detecting an increase in a load at the output of the circuit;

in response to the increase in the load, causing the circuit to operate in an adaptive current control mode in which the clock-influencing current of the circuit is prevented from being applied to the inductor of the circuit;

implementing a first phase of the adaptive current control mode in which the current is applied to the inductor via the first switching device until the first indication of current flowing through the inductor reaches a predefined level of maximum inductor current;

implementing a second phase of the adaptive current control mode in which the current is enabled to flow through the inductor via the second switching device until the current comparator determines that the second indication of current flowing through the inductor reaches a current control signal provided via the output of the error amplifier;

detecting a decrease in the load at the output when the circuit is operating in the adaptive current control mode; and

in response to the reduction in the load at the output, transitioning the circuit from the adaptive current control mode to operating in a steady-state mode in which the clock of the circuit affects the application of the current to the inductor of the circuit.

8. The circuit of claim 7, further comprising an electronic circuit configured to apply an offset to the output signal of the error amplifier effective to increase an average amount of the current flowing into the inductor for at least a portion of the time the circuit is operating in the adaptive current control mode.

9. The circuit of claim 8, wherein the electronic circuit further comprises:

at least one logic gate configured to generate the offset in response to detecting a transient load at the output of the circuit; and

a comparator configured to:

comparing a current-based indication of a voltage at the output of the circuit to a predefined ramp signal to transition the circuit to the steady-state mode or to cease generating the offset; and

in response to the current-based indication no longer exceeding the predefined ramp signal, transitioning the circuit to the steady-state mode; or

Ceasing to generate the offset in response to the current-based indication no longer exceeding the predefined threshold.

10. The circuit of claim 8 or 9, wherein the adaptive current controller is further configured to:

setting a magnitude of the offset applied to the current control signal based on a magnitude of the load at the output of the circuit; or

Setting an amplitude or rate of increase of the predefined ramp signal compared to the current-based indication of the voltage based on the amplitude of the load at the output of the circuit.

11. The circuit of claim 7, 8 or 9, wherein:

the circuit is configured as a multi-phase power conditioning circuit;

the first switching device, the inductor, the second switching device, and a current comparator are configured as a first phase of the multi-phase power conditioning circuit;

the multi-phase power conditioning circuit includes at least a second phase having another inductor; and

preventing the clock-influencing current of the circuit from being applied to the inductor of at least the first phase and the other inductor of at least the second phase of the multi-phase power conditioning circuit during the adaptive current control mode of operation.

12. A method implemented by a switching power regulator to increase output current in response to a transient load on the switching power regulator, the method comprising:

detecting the transient load at an output of the switching power regulator;

in response to detecting the transient load, masking a clock signal of the switching power regulator to prevent the clock signal from interrupting current application to an inductor of the switching power regulator;

activating a first switching device of the switching power regulator to initiate application of the current to the inductor of the switching power regulator;

sensing, at a first node operatively coupled to the first switching device, an amount of the current flowing into the inductor to provide a first indication of current flow in the inductor;

deactivating the first switching device in response to the first indication of current flow meeting a predefined threshold for maximum inductor current;

in response to deactivating the first switching device, activating a second switching device of the switching power regulator to enable the current to continue to flow through the inductor;

sensing, at a second node operatively coupled to the second switching device, an amount of current flowing into the inductor to provide a second indication of current flow in the inductor;

comparing the second indication of current flow to a control signal based on an output voltage of the switching power regulator when the second switching device is activated;

deactivating the second switching device in response to the second indication of current flow satisfying the control signal based on the output voltage of the switching power regulator; and

activating the first switching device to restart application of the current to the inductor of the switching power regulator effective to increase an amount of the current flowing into the inductor and to the output of the switching power regulator.

13. The method of claim 12, further comprising:

applying an offset to the control signal effective to increase an average amount of the current flowing into the inductor for at least a portion of the time during which the clock signal is masked; or

Configuring the offset applied to the control signal based on a magnitude of the transient load at the output of the switching power regulator such that the magnitude of the offset corresponds to the magnitude of the transient load at the output of the switching power regulator.

14. The method of claim 13, further comprising:

generating the offset in response to detecting the transient load at the output of the switching power regulator;

comparing a current corresponding to the control signal based on the output voltage to a predefined threshold for unmasking the clock signal or stopping generation of the offset; and

in response to the current no longer exceeding the predefined threshold, unmasking the clock signal; or

Ceasing generation of the offset in response to the current no longer exceeding the predefined threshold.

15. The method of claim 14, wherein the predefined threshold is a ramp signal that increases over time, and the method further comprises:

generating the ramp signal based on a predefined setting of a rate at which the ramp signal increases or an amplitude of the ramp signal; and

configuring the predefined setting of the rate or the amplitude of the ramp signal based on an amplitude of the transient load at the output of the switching power regulator.

Background

Switching power supplies are commonly used to power various components in computing and electrical equipment. Typically, a switching power supply regulates power received at one voltage to another voltage at which the power is provided to components of the device. In some cases, the current consumption of the device components may increase significantly during operation, which may be referred to as transient load or load step. If this increased current consumption cannot be met, the output voltage of the switching power supply will drop or fall until the switching power supply recovers. However, before this occurs, when the components are turned off or cannot operate at low voltages, the low or reduced voltage at the switching power supply output may render the device inoperable. Some device manufacturers have attempted to address the supply voltage droop problem by increasing the capacitance at the output of the switching regulator. However, increasing the number or size of the output capacitors increases circuit complexity, consumes valuable layout area, and increases overall device cost.

Disclosure of Invention

This disclosure describes apparatus and techniques for adaptive current control for fast transient response. In various aspects, a load increase at an output of a switching power regulator (switching regulator) is detected. In response to detecting the increase in the load, a clock of the switching regulator is prevented from affecting the application of current to an inductor of the switching regulator. A first switching device of the switching regulator applies current to the inductor until the inductor current reaches a maximum or peak current level. Then, a second switching device of the switching regulator enables current to flow through the inductor until the inductor current reaches the current control signal. A current control signal is provided based on an output voltage of the switching power regulator. In addition, an offset may be applied to the current control signal to further increase the average inductor current (e.g., more quickly reactivate the first switching device). These operations may be repeated without interrupting the clock to rapidly increase the inductor current and thereby increase the current provided to the output of the switching regulator in response to an increase in the load at the output. Thus, during load transients, the adaptive current control mode helps relieve stress to increase the control loop bandwidth, which in turn may increase the noise immunity of the regulator.

In some aspects, a method implemented by a switching power regulator to increase an output current in response to an increase in a load on the switching power regulator. The method detects an increase in load at an output of the switching power regulator. In response to an increase in load, the method initiates an adaptive current control mode of the switching power regulator in which a clock of the switching power regulator is prevented from affecting the application of current to an inductor of the switching power regulator. The method comprises implementing a first phase of the adaptive current control mode in which the current is applied from an input of the switching power regulator to an inductor of the switching power regulator via a first switching device until the inductor current reaches a predefined level of maximum current.

The method also includes implementing a second phase of the adaptive current control mode in which the current is enabled to flow through the inductor via a second switching device from a potential lower than the input of the switching power regulator until the inductor current reaches a current control signal based on the output voltage of the switching power regulator. The method detects a reduction in load at the output when the switching power regulator is operating in an adaptive current control mode. In response to a decrease in the load at the output, the method includes switching the switching power regulator to operate in a steady-state mode, wherein a clock of the switching power regulator affects the application of the current to an inductor of the switching power regulator.

In other aspects, a circuit for regulating power includes a first switching device coupled to an input of the circuit, an inductor having a first end coupled to the first switching device and a second end coupled to an output of the circuit, and a second switch coupled between the first end of the inductor and a potential lower than the output of the circuit, the second switch being generally grounded. The circuit also includes first and second sensing electronic circuits configured to provide first and second indications of current flowing through the first and second switching devices, respectively. The clock of the circuit is operatively coupled to the drive electronics of the first switching device and the second switching device. The circuit also includes a current comparator having an output operably coupled to the drive electronics and a first input operably coupled to the second sense electronics, and an error amplifier having an input operably coupled to the output of the circuit and an output coupled to a second input of the current comparator.

An adaptive current controller associated with a circuit is configured to detect an increase in a load at an output of the circuit and to cause the circuit to operate in an adaptive current control mode in response to the increase in the load, wherein a clock-affecting current of the circuit is prevented from being applied to an inductor of the circuit. A controller implements a first phase of the adaptive current control mode in which the current is applied to the inductor via the first switching device until a first indication of current flowing through the inductor reaches a predefined level of maximum inductor current. The controller then implements a second phase of the adaptive current control mode in which the current is enabled to flow through the inductor via the second switching device until the current comparator determines that a second indication of the current flowing through the inductor reaches a current control signal provided via an output of the error amplifier. The controller is further configured to detect a decrease in a load at the output when the circuit is operating in the adaptive current control mode. In response to a decrease in the load at the output, the controller causes the circuit to operate in a steady-state mode in which a clock of the circuit affects the current applied to an inductor of the circuit.

In other aspects, a method implemented by a switching power regulator to increase output current in response to a transient load on the switching power regulator. The method includes detecting a transient load at an output of a switching power regulator and masking a clock signal of the switching power regulator in response to detecting the transient load to prevent the clock signal from interrupting current application to an inductor of the switching power regulator. The method includes activating a first switching device of the switching power regulator to initiate application of the current to an inductor of the switching power regulator, and sensing an amount of current flowing into the inductor at a first node operatively coupled to the first switching device to provide a first indication of a current flow of the inductor. Deactivating the first switching device in response to the current flow satisfying a first indication of a predefined threshold for maximum inductor current.

The method then activates a second switching device of the switching power regulator to continue the current flow through the inductor in response to deactivating the first switching device and senses an amount of current flowing into the inductor at a second node operatively coupled to the second switching device to provide a second indication of current flow in the inductor. Comparing a second indication of current flow to a control signal based on an output voltage of the switching power regulator when the second switching device is activated. In response to the current flow satisfying a second indication of the control signal based on the output voltage of the switching power regulator, deactivating the second switching device and activating the first switching device to restart application of the current to the inductor of the switching power regulator effective to increase the amount of current flowing into the inductor and the output of the switching power regulator.

The details of one or more implementations of adaptive current control in a switching power regulator for fast transient response are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. This summary is provided to introduce a selection of subject matter that is further described in the detailed description and the accompanying drawings. Accordingly, this summary should not be considered to describe essential features nor should it be considered to limit the scope of the subject matter of the appended claims.

Drawings

The present disclosure describes apparatus and techniques for adaptive current control for fast transient response with reference to the following figures. The use of the same or similar reference numbers throughout the description and the figures may indicate similar features or components:

fig. 1 illustrates an example operating environment including a user device that includes a switching power regulator and is capable of implementing various aspects of adaptive current control for fast transient response.

FIG. 2 illustrates an example of a power system including the adaptive current controller and adaptive current control electronics shown in FIG. 1.

Fig. 3 illustrates an example configuration of a single phase switching power regulator including adaptive current control electronics.

Fig. 4 illustrates an example configuration of a multiphase switching power regulator including adaptive current control electronics.

Fig. 5 illustrates an example method for implementing an adaptive current control mode for a switching power regulator.

Fig. 6A and 6B illustrate an example method of masking a clock signal and activating a switching device of a switching power regulator to increase an inductor current to an output of the switching power regulator.

FIG. 7 illustrates an example graph of inductor current regulated according to one or more aspects of adaptive current control.

Fig. 8 illustrates an example graph of output voltage and inductor current of a switching power regulator implementing aspects of adaptive current control.

FIG. 9 illustrates an example method for implementing aspects of adaptive current control in a multi-phase power switching regulator.

Fig. 10 illustrates additional exemplary graphs of respective inductor phase currents and output voltages of a multi-phase switching power regulator implementing aspects of adaptive current control.

Fig. 11 illustrates an example graph of output voltages and corresponding inductor phase currents of a multiphase switching power regulator implementing aspects of adaptive current control.

Fig. 12 illustrates an example system-on-chip (SoC) environment in which techniques for adaptive current control for fast transient response may be implemented.

Detailed Description

Conventional techniques for regulating power typically implement Pulse Width Modulation (PWM) to control the current applied to an energy storage element (e.g., an inductor) of a power circuit. Typically, the switches are used to modulate the current applied to the inductor based on the duty cycle of a PWM waveform or pulse train generated by the logic of the power supply circuit. In some cases, PWM control is implemented at a fixed frequency, where the period of the PWM scheme is governed by a clock signal that controls the application of current during or at the end of a given modulation period. One example of a power conditioner implementing fixed frequency switching is a leading edge modulation current mode (e.g., valley mode) conditioner, which is used to power a mobile device processor core rail (e.g., for central and graphics processing units (CPUs) and GPUs)). Leading edge current mode modulation may include low side current sensing, which alleviates duty cycle and/or switching frequency limitations associated with high side sensing, cycle-by-cycle inductor current regulation, which makes implementation of multi-phase current sharing easier and fixes switching frequency, which enables multi-phase operation without the need for phase synchronization using complex Phase Locked Loops (PLLs). Accordingly, Power Management Integrated Circuits (PMICs) implementing leading edge current mode control or valley mode control are typically used to power CPU, GPU and/or memory power rails in battery powered devices.

However, the fixed frequency characteristics of the leading edge current mode PMIC may impair PMIC performance in terms of transient loads or high current steps, such as increasing the current slew rate of the CPU and GPU typically associated with mobile devices. Conventional solutions to address poor transient load performance include adding or increasing the size of the output capacitor on the power supply at additional cost and increasing the design volume, or limiting the CPU speed, which directly compromises the user experience. Leading edge current mode PMIC may also perform poorly when power is regulated at the lower voltages associated with the CPU and GPU. Generally, leading edge current mode modulation, also referred to as valley current control mode, can be viewed as the inverse logic of the various ways in which the peak current control mode is implemented. Thus, the small signal model of the peak current control mode can be applied to the valley current control mode, where the high side current sensing of the peak current control mode is replaced with the low side current sensing. While low-side current sensing reduces the complexity of low output voltage regulation (e.g., high input/output duty cycle), the performance of valley mode current comparators may be degraded by low output voltages due to noise issues. Various slope compensation schemes can alleviate the noise problem, but for the same low duty cycle case, the resulting loop gain and bandwidth of the leading edge design will be more limiting than the trailing edge (or peak current) control. For these reasons, more expensive and more complex Constant On Time (COT) controlled PMICs are typically used for low voltage applications, rather than leading edge current mode control or valley current controlled PMICs.

In contrast to conventional leading edge current mode or valley current control schemes, the present disclosure describes aspects of adaptive current control for fast transient response. Generally, the described aspects provide for an improvement in response to transient loads (e.g., load step or high current slew rates) by increasing inductor current, and thus increasing output current, and then enabling the switching regulator to transition (e.g., after a transient load in response to a current increase) to fixed frequency operation (e.g., at a minimum or nominal current load) to a valley current control mode for steady state operation.

In some aspects, an adaptive current control enabled switching regulator includes a high-side switch through which current is applied to an inductor of the switching regulator and thus to an output of the switching regulator. Typically, an effective way to deliver current to the inductor is to open the high-side switch until a maximum or peak current limit of the switching regulator (e.g., inductor or high-side switch current limit) is reached. Unlike the conventional valley current control mode, the adaptive current control mode may mask or disable the clock signal of the switching regulator that normally turns off the high-side switch. By disabling the clock signal, the switching regulator may manage the current flowing into the inductor based on the peak current limit and a valley current comparator configured for adaptive current control. Thus, a valley current comparator may be used to control the valley current level of the inductor current based on the offset output of the error amplifier (e.g., VC) in combination with the peak current limit. In some aspects, a current sense offset may be introduced to the output of the error amplifier to increase the level of valley current, thereby increasing the average inductor current by increasing the threshold of minimum current flowing through the inductor. In doing so, the adaptive current control mode may be responsive to transient loads having increased peak and/or average current levels to substantially reduce or reduce the voltage drop at the switching regulator output. This increased current can reduce the voltage drop for the same amount of output capacitance, or allow the designer to use less output capacitance for a given amount of voltage drop, thereby reducing the cost and design volume allocated to the output capacitance.

For example, when a load step is applied to the output of a switching regulator that implements adaptive current control, the control loop of the switching regulator may be based on an error amplifier (e.g., V |)_C) Is responsive to the output of (a). As a worst case scenario, consider when the switching regulator wakes up from a light load Pulse Frequency Modulation (PFM) mode to a load step requirement with an output of high slew rate, such as tens of a/μ Sec for a current intensive processor. In various aspects, in response to a transition from PFM mode to PWM mode, an adaptive current controller may generate a pulse signal to mask or disable operation of a clock of a switching regulator and apply an offset to an output of an error amplifier. As the transient load subsides and steady state operation approaches, generation of the pulse signal ceases and the clock signal and/or slope compensation signal resumes for steady state operation. In some cases, such an adaptive current control mode or control loop is more tolerant of variations in operating conditions (e.g., various load demand levels) and circuit component values (e.g., output capacitor number or size).

Generally, the pulse signal is generated at an appropriate timing and length to effectively increase the current for fast transient response and to seamlessly transition or return to the clock-based steady-state operation of the switching regulator. As described herein, there are various embodiments by which an adaptive current control pulse signal is generated or derived, such as based on output voltage dip detection, error voltage rising edge, error current of an operational transconductance amplifier, or similar combinations. By implementing this and other aspects of adaptive current control, the output current of the switching regulator may be increased or maximized based on load demand (or load request), and overshoot of smaller load steps may be reduced. Alternatively or additionally, adaptive current control may be applied to single phase switching regulators or multi-phase switching regulators as described throughout this disclosure.

In various aspects, a user device includes a switching power regulator and an adaptive current controller (current controller) implemented according to one or more aspects of adaptive current control. The current controller detects an increase in a load (e.g., a transient load) at an output of a switching power regulator (switching regulator). In response to detecting the increase in the load, the current controller prevents a clock of the switching regulator from affecting the application of current to an inductor of the switching regulator. The current controller activates a first switching device of the switching regulator to apply current to the inductor until the inductor current reaches a maximum current level. The current controller then activates a second switching device of the switching regulator to enable current to flow through the inductor when the first switching device is inactive until the inductor current reaches a current control signal or threshold. The current control signal is provided based on an output voltage of the switching regulator. Further, in response to activation of the first and second switching devices, an offset may be applied to the current control signal to further increase the average inductor current. These operations may be repeated without interrupting the clock to rapidly increase the inductor current to increase the current provided to the switching regulator output in response to an increase in the load at the output. By doing so, the switching regulator can respond to a transient load by rapidly increasing the current through the inductor and reduce or mitigate the voltage drop at the output of the switching regulator.

The following discussion describes an operating environment, techniques that may be employed in the operating environment, and various devices or systems in which components of the operating environment may be embodied. In the context of the present disclosure, reference is made to an operating environment by way of example only.

Example Environment

Fig. 1 illustrates an example environment 100 including a user device 102 in which aspects of adaptive current control for fast transient response may be implemented. User device 102 may be implemented as any suitable device, some of which are shown as a smartphone 104, a tablet 106, a laptop 108, a wearable computing device 110 (e.g., a smart watch), a broadband router 112 (e.g., a mobile hotspot), and an automotive computing system 114 (e.g., a navigation and entertainment system). Although not shown, the user device 102 may also be implemented as a mobile station (e.g., a fixed or mobile STA), a mobile communication device, a client device, a user device, a mobile phone, an entertainment device, a gaming device, a mobile gaming machine, a personal media device, a media player device, a health monitoring device, a drone, a camera, a wearable smart device, an internet appliance capable of wireless networking and browsing, an internet of things device, and/or other types of user devices. User device 102 may provide other functionality or include components or interfaces that are omitted from fig. 1 for clarity or visual brevity.

User device 102 includes one or more processors 116 and computer-readable media 118, which may include memory media or storage media. The processor 116 may be implemented as a general purpose processor (e.g., of a multi-core Central Processing Unit (CPU) or Application Processor (AP)), an Application Specific Integrated Circuit (ASIC), a Graphics Processing Unit (GPU), or a system on a chip (SoC) having other components of the user device 102 integrated therein. The computer-readable medium 118 may include any suitable type of memory medium or storage medium, such as Read Only Memory (ROM), Programmable ROM (PROM), Random Access Memory (RAM), Dynamic RAM (DRAM), Static RAM (SRAM), or flash memory. In the context of this discussion, the computer-readable medium 118 of the user device 102 is implemented as at least one hardware-based or physical storage device that does not include a transient signal or carrier wave. Applications, firmware, and/or an operating system (not shown) of user device 102 may be embodied as processor-executable instructions on computer-readable media 118, which may be executed by processor 116 to provide the various functions described herein. The computer-readable media 118 may also store device data 120, such as user data or user media accessible through an application, firmware, or operating system of the user device 102.

In this example, the computer readable medium 118 also includes an adaptive current controller 122 (current controller 122) described throughout this disclosure. In general, the current controller 122 may implement one or more aspects of adaptive current control to increase the amount of current provided to the inductor of the switching regulator, such as in response to an increase in the load on the switching regulator. In some cases, the current controller 122 masks the clock signal, masks the slope compensation signal, applies an offset to the output of the error amplifier, and so forth. Alternatively or additionally, the current controller 122 may implement an adaptive current control mode in which a clock signal is prevented from affecting or interrupting the application of current to the inductor of the switching regulator. According to an adaptive current control mode, the current controller 122 may implement a control loop in which the inductor current is controlled based on a maximum current level of the inductor and based on a low side sense of an offset output of the error amplifier. By doing so, the current controller 122 may increase the amount of current provided to the output of the switching regulator, such as in response to a load step or transient load. How the current controller 122 is implemented and used is different and is described throughout this disclosure.

User device 102 may also include a display 124, a transceiver 126, an I/O port 128, and/or a sensor 130. The display 124 may be operatively coupled with one of the processors 116 (e.g., a Graphics Processing Unit (GPU)) and configured to graphically present an operating system or application of the user device 102. The transceiver 126 may be configured to enable wired or wireless communication of data (e.g., the device data 120) over a wired or wireless network according to any suitable communication protocol. The I/O ports 128 of the user device 102 may include USB ports, coaxial cable ports, and other serial or parallel connectors (including internal connectors) for coupling the user device to various components, peripherals, or accessories, such as a keyboard, a microphone, or a camera.

User device 102 also includes sensors 130 that enable user device 102 to sense various attributes, changes, stimuli, or characteristics of the environment in which user device 102 operates. For example, the sensors 130 may include various motion sensors, ambient light sensors, acoustic sensors, capacitive sensors, infrared sensors, temperature sensors, radar sensors, or magnetic sensors. Alternatively or additionally, the sensor 130 may enable interaction with a user of the user device 102 or receive input from a user of the user device 102, such as through touch sensing or proximity sensing. In some aspects of adaptive current control, the current controller 122 may monitor the sensors 130, such as receiving temperature data or feedback via one of the sensors 130. Based on the temperature data, the current controller 122 can vary the amplitude or duration of the offset or pulse signal in implementing adaptive current control.

The power system 132 provides regulated power to components of the user device 102, such as the processor 116, CRM 118, display 124, transceiver 126, I/O port 128, or sensors 130. In this example, the power system 132 includes one or more switching power regulators 134 (switching regulators 134) and adaptive current control electronics 136(ACC electronics 136). The switching regulator 134 may be configured to provide power to the various components of the user device 102 at different respective voltage levels. For example, one of the switching regulators 134 may include a multi-phase switching regulator configured to step down battery power (e.g., 3.7 to 4.2V) or external power (e.g., 5.0V) to a voltage (e.g., 0.750V) at which the processor 116 consumes power to operate.

The ACC electronic circuit 136 may implement one or more aspects of adaptive current control, such as generating a pulse signal to mask the clock of the switching regulator 134 or provide an offset to the output of the error amplifier or other current control threshold. The current controller 122 may interact with the ACC electronic circuit 136 to implement various aspects described herein, such as by configuring a predefined current threshold, a predefined ramp signal, or a predefined offset that may be used to increase the current provided to the output of the switching regulator. How the ACC electronic circuit 136 is implemented and used is different and is described throughout this disclosure.

Fig. 2 illustrates at 200 an example of a power system including the adaptive current controller 122 and the ACC electronic circuit 136 shown in fig. 1. In this example, the power system 132 is operably coupled to a load 202 of the user device 102 that includes the processor 116, CRM 118, display 124, and transceiver 126 of the user device 102. The power system 132 may receive input power from an external power source 204 (e.g., an external AC/DC adapter) or one or more battery cells 206 electrically coupled to a battery or battery pack of the user device 102. Switching electronics 208, which may include charging or other power management circuitry, electrically couple the external power source 204 or the battery cell 206 to the switching regulator 134.

Generally, the switching regulator 134 regulates power provided by the external power source 204 or the battery cell 206 to provide power to components (e.g., the load 202) of the user device 102 at a voltage at which the components operate. For example, each of the switching regulators 134 may be configured as a single-phase or multi-phase switching regulator to provide power at a different respective voltage, such as 3.3 volts (e.g., for the display 124), 1.8 volts (e.g., for the CRM 118), 1.0 volt, 0.9 volt, 0.7 volt (e.g., for the processor 116), and so forth. Voltage regulation and other functions of the switching regulator 134 may be controlled by a power management integrated circuit 210(PMIC 210), which power management integrated circuit 210 may include registers and logic for implementing one or more power regulation schemes, such as PFM, PWM, valley current mode, adaptive current control mode, and so forth.

In various configurations, the user device 102 and components of the user device 102, such as the processor 116 and transceiver 126, may have multiple operational or power states, such as fully on, idle, standby, sleep, deep sleep, and off. Alternatively or additionally, some components (e.g., CPUs or GPUs) may also be configured for different performance states, such as maximum performance, nominal performance, power savings, and so on. Thus, the operating power and current consumed by the user device 102 and components of the user device (e.g., the load 202) may vary depending on the operating state, operating state transitions, or use of the user device 102 (or individual components). In some cases, a change in the operating state or processing requirements of the user device 102 generates a corresponding increase in the current requirements of the switching regulator. For example, when waking from a low power state to a fully active state, the processor 116 (e.g., CPU and GPU) may create a load step of transient load or current demand (e.g., tens of a/μ Sec) on one of the switching regulators 134 configured to provide power to the processor power rails.

The switching regulator 134 also includes or is associated with an ACC electronic circuit 136, and the ACC electronic circuit 136 may interact with the current controller 122 to implement various aspects of adaptive current control. In some cases, the ACC electronic circuit 136 or current controller 122 interacts with the PMIC 210 to affect or control the operation of the switching regulator 134. For example, the ACC electronic circuit 136 may generate a pulse via an addition block or comparator to mask the clock signal of the PMIC 210 or switching regulator 134, or offset the output of an error amplifier that provides a current control signal based on the output of the switching regulator 134. In some aspects, the current controller 122 interacts with the PMIC 210 to detect or receive an indication of a switching regulator mode (e.g., PFM or PWM), or an indication of a transition between switching regulator modes (e.g., PFM to PWM). Alternatively or additionally, an instance of the current controller 122 may be embodied on the PMIC 210, a microcontroller, or other logic configured to manage the operation of the switching regulator 134.

Fig. 3 illustrates an example configuration of a single-phase switching regulator including an ACC electronic circuit at 300. In this example, the instance of the adaptive current control circuit 136 and the current controller 122 are operably coupled with a switching regulator 134 configured as a single-phase regulator. The components and architecture shown in fig. 3 are presented as a non-limiting example of the manner in which adaptive current control may be implemented. Accordingly, the aspects described herein may be applied to or extended to any suitable switching power circuit to implement the various features of adaptive current control. Further, any coupling or connection between the various components may be direct or indirect, such as through one or more intervening components. Some irrelevant or redundant components (e.g., sense resistors or operational amplifiers) or electronic circuitry may also be omitted from this or other circuit diagrams for visual brevity and/or clarity. Such omissions are not to be construed as limitations, but rather as an example of the various ways in which aspects may be used or applied to a circuit to implement adaptive current control. In other words, the aspects (e.g., electronic circuits) described herein may also be implemented with any suitable number or combination of logic, registers, sensing electronics, amplifiers, current mirrors, comparators, and so forth.

As shown in fig. 3, the switching regulator 134 (regulator 134) includes a first switching device 302 and a second switching device 304 coupled between an input power source 306 and a lower potential (shown as ground 308). An inductor 310 of the regulator 134 is coupled between a switching node disposed between the first and second switching devices 302 and 304 and an output 312 of the regulator 134. In general, the first and second switching devices 302 and 304 regulate application and current flow from the input power source 306 through the inductor 310 to the output 312 of the regulator 134 based on the drive signal provided by the PMIC 210. A load 314 (e.g., load 202) is coupled to output 312, which may be modeled as a resistance or variable load on regulator 134. Regulator 134 also includes an output capacitance, illustrated as output capacitor 316, which may represent any suitable number, type, or size of output capacitors coupled to output 312.

Regulator 134 is capable of operating in a variety of control modes, such as a valley current control mode and an adaptive current control mode (e.g., a hybrid stitch mode). In this example, the control electronics and signals of regulator 134 include error amplifier 318, slope compensated ramp signal 320, low side sensing electronics 322, current comparator 324, and clock 326. Alternatively or additionally, the control electronics of the regulator 134 may also include high-side sensing electronics 328 to sense the current (e.g., peak current) flowing through the first switching device 302 into the inductor 310. In various aspects, the error amplifier 318 receives a voltage indication and a reference voltage 330 at the regulator output 312 to provide a control signal 332 (V) to the current comparator 324_C332) Error voltage or current control signal. In some embodiments, error amplifier 318 may include a feed-forward resistor-capacitor network 334 (RC)_FF334) To introduce a phase boost to compensate for the poles of the transfer function of regulator 134. In general, errorAmplifier 318 will generate an output or control signal 332 that attempts to force the voltage at output 312 of regulator 134 to match reference voltage 330. Thus, the error amplifier output or control signal 332 may indicate the degree, threshold, or level from which the output current of the regulator 134 should be increased (e.g., dropped from the voltage) to return to or meet the target voltage (e.g., 0.750V) for power regulation.

The current comparator 324 may add a slope compensation ramp signal 320 to the control voltage 332 to provide a slope compensation signal for controlling the current modulation of the regulator 134, such as during valley current control. The current comparator 324 may provide an indication (I) of the current 336 provided by the low side sensing electronic circuit of the current flowing through the second switching device 304_{S2_Sensed}336) Compared to the slope compensation signal to provide an output signal to set the reset-set flip-flop 338(RS flip-flop 338). The RS flip-flop 338 is operably coupled to the PMIC 210 and may selectively control or activate the drive electronics for the first switching device 302 or the second switching device 304. In some cases, the RS flip-flop 338 is set when the current comparator detects or determines that the indication 336 of the current (e.g., valley current) falls to or satisfies the compensation signal, at which time the first switch 302 is activated and the second switch 304 is deactivated.

Based on the output of the RS flip-flop 338, the first switching device 302 may apply current from the input power 306 to the inductor 310 to increase the current flow in the inductor. In valley current control, the first switching device 302 remains active and applies current to the inductor until the clock 326 resets the RS flip-flop 338, such as through an OR gate 340. Thus, in steady state operation or valley current control mode, the current of inductor 310 may be modulated based on the slope compensation signal and an indication of the low side switch current in one phase of operation and clock 326 in a second phase of operation. The OR gate 340 may also receive a current 342 (I) provided by a high side sensing electronic circuit of the current flowing through the first switching device 302_{S1_Sensed}342) To enable the adaptive current control mode.

In aspects of adaptive current control, the ACC electronic circuit 136 and/or the current controller 122 may manage or affect operation of components of the regulator 134 to increase the current provided at the output 312, such as in response to a transient load or load step. The current controller 122 or the ACC electronic circuit 136 may implement an adaptive current control mode in which the operation of the regulator (e.g., inductor current flow) is managed during a first phase based on a maximum current limit of the inductor 310 and during a second phase based on an offset current control signal, such as an offset output of the error amplifier 318. For example, the adaptive current controller 122 or the electronic circuit 136 may mask the signal of the clock 326, apply an offset to the control voltage 332 (e.g., a current control signal), or mask the slope compensation signal 320 from the current comparator 324. As shown in fig. 3, ACC electronic circuit 136 is coupled to the output of error amplifier 318, a clock 326 (e.g., a clock circuit enable line), and a current comparator 324 of regulator 134. In this example, ACC electronic circuit 136 includes a transient comparator 344, an RS flip-flop 346, AND (AND) gates 348 AND 350, with AND gates 348 AND 350 coupled to the output of RS flip-flop 346. In general, the ACC electronic circuit 136 may generate one or more signals (such as pulsed or masked signals) with appropriate timing and length to effectively cause the regulator 134 to provide an increased amount of current to quickly respond to a transient load or load step. The ACC electronic circuit 136 may then seamlessly transition or return the regulator 134 to clock-based steady-state operation with minimal overshoot.

The current controller 122 may initiate the adaptive current control or adaptive current control mode in response to any suitable indication of a transient load or a transient step on the output 312 of the regulator 134. In this example, a set input of the RS flip-flop 346 is coupled to an output of the PMIC 210 (not shown), logic, or another entity (e.g., the current controller 122) to receive an indication 352 of when the regulator 134 is to transition the Pulse Frequency Modulation (PFM) mode (e.g., light current load) to the Pulse Width Modulation (PWM) mode (e.g., increased/heavy current load). Alternatively or additionally, current controller 122 may initiate adaptive current control in response to detecting a dip in the output voltage at output 312 or detecting a rising edge in the output voltage provided by error amplifier 318.

Returning to FIG. 3, in response to the PFM/PWM transition 352, the output of the RS flip-flop 346 transitions to generate a mask signal 354 to clock and an offset 356 to current comparator. In some cases, the mask signal 354 and/or the offset 356 are or correspond to the start or initiation of an adaptive pulse during which the regulator 134 operates in an adaptive current control mode (e.g., initiates adaptive current control). The mask AND offset signals 354, 356 may be provided separately (e.g., without others) or in combination, or buffered via AND gates 348 AND 350. The shield signal 354 may shield the clock signal of the clock 326, disable the clock circuit, or otherwise prevent the clock 326 from interrupting or changing the current applied to the inductor 310 by the first switching device 302. In some cases, an offset 356 is applied to a current control signal (such as control signal 332 provided by error amplifier 318) to change a current control threshold (e.g., a valley current threshold) and enable an increased amount of current to flow into inductor 310. Alternatively or additionally, the offset 356 or another signal generated by logic of the ACC electronic circuit 136 may mask or disable the slope compensation signal 320 when the regulator 134 is operating in the adaptive current control mode.

In some aspects, the transient comparator 344 generates a signal that is or corresponds to the end or termination of an adaptive pulse during which the regulator 134 operates in an adaptive current control mode (e.g., terminates adaptive current control). In this example, the output of the transient comparator 344 of the ACC electronic circuit 136 is coupled to a reset input of an RS flip-flop 346, the RS flip-flop 346 generating a mask signal 354 and an offset 356. As shown in fig. 3, a first input of the transient comparator 344 may be coupled to an output of the error amplifier 318 to receive an indication 358 of the voltage or current based output of the error amplifier 318. The other input of transient comparator 344 is coupled to the source of transient ramp signal 360, although any fixed or variable threshold may be used.

In general, transient comparator 344 may compare the output of error amplifier 318 to transient ramp 360 (or other signal) to detect a reduction in the load on output 312 of regulator 134. In some cases, the decrease in load is detected relative to an increased amount of current provided to output 312 by the adaptive current control mode and/or an amount of time that regulator 134 achieves adaptive current control. As such, the transient ramp signal 360 may be configured or predefined to reduce overshoot of small current steps, or when the regulator 134 is operating under adaptive current control for a longer duration (e.g., longer than 50 μ Sec).

In response to the error amplifier output meeting or falling below the indication 358 of the transient ramp 360, the output of the transient comparator 344 transitions positive to reset the RS flip-flop 346, which stops generating the mask signal 354 to the clock 326 and the offset 356 to the current comparator 324. Alternatively or additionally, the reset of the RS flip-flop 346 may also unmask or resume the application of the slope compensation signal 320 to the current comparator 324 at the end of the adaptive current control mode. In this way, the generation of the mask clock 326 or variable pulses corresponding to operation according to the adaptive current control mode may be initiated based on the PFM/PWM conversion 352 and terminated by the transient comparator 344. Transient comparator 344 may compare the output of error amplifier 318 with a transient ramp signal 360, or any suitable variable or fixed signal.

In some aspects, the error amplifier 318 is implemented as an Operational Transconductance Amplifier (OTA) that provides a current-based output signal or error current based on the output voltage of the regulator and the reference voltage 330. Since the current-based output signal or output current of the OTA amplifier is the current control signal V_c332 (derivative), so a zero is effectively introduced into the adaptive current control loop, which may increase the control bandwidth. In such embodiments, ACC electronic circuit 136 may also include a current-to-voltage (I/V) block or transimpedance amplifier (not shown) coupled between error amplifier 318 and current comparator 324 or between error amplifier 318 and transient comparator 344.

Thus, in some aspects of adaptive current control, the transient comparator 344 compares the error amplifier current to a predefined voltage (e.g., the transient ramp 360) to determine when to reset the flip-flop 346 or end the variable length pulse generated by the adaptive current control, which changes the operation of the regulator 134 to increase the inductor current. In some cases, ACC electronic circuit 136 includes a current mirror (not shown) coupled to the output of error amplifier 318 such that transient comparator 344 compares the mirror of the error amplifier current to a predefined voltage or transient ramp signal 360. Alternatively or additionally, any of the signals described with respect to error amplifier 318, current comparator 324, and/or transient comparator 344 may be implemented as voltage-based or current-based signals, with a corresponding I/V or V/I block optionally disposed between the source and target components.

As another example, consider fig. 4, which illustrates an example configuration of a multiphase switching regulator 400 (multiphase regulator 400) including an ACC electronic circuit. In general, aspects of adaptive current control may be applied to multiphase regulators configured with any suitable number of phases, such as two-phase, three-phase, four-phase, etc. In this example, the multiphase regulator 400 is configured as a two-phase regulator having a first phase 402 and a second phase 404, although the described aspects may be applied or extended to additional phases. As shown in fig. 4, a first inductor 406 of the first phase 402 and a second inductor 408 of the second phase 404 are coupled to an output 410 of the multiphase regulator 400. Other components or signals associated with the phase may be configured similar to or different from the corresponding elements described with respect to the single phase regulator of fig. 3 with respect to phase 402 and/or phase 404.

In this example, the ACC electronic circuit 136 is operably coupled to a clock 326 and a current comparator 324 for respective first 402 and second 404 phase of the multiphase regulator 400. In some aspects, the current controller 122 and/or the ACC electronic circuit 136 may initiate an adaptive current control or adaptive current control mode in response to any suitable indication of a transient load or a transient step on the output 410 of the multiphase regulator 400. For example, in response to the PFM/PWM conversion 352, the ACC electronic circuit 136 may generate and provide a mask signal 354 to the clock 326 of the multiphase regulator 400 and an offset signal 356 to the current comparator 324 of the multiphase regulator 400 to increase the current flowing through the inductors 406 and 408.

In at least some aspects, advantages of adaptive current control include the ease and ease of commanding all phases of multiphase regulator 400 to a maximum inductor current ramp rate. This is due to the fact that the masking signal 356 blocks or delays the normal clock signal and/or uses the same peak current, and the error amplifier voltage controls the respective inductor current for each phase simultaneously. Alternatively or additionally, as load step dependent derivation of variable length pulses (e.g., transient pulses of the ACC electronic circuit 136), the phase drop signal (not shown) may also be masked to ensure that each and all phases of the multiphase regulator operate (e.g., turn on) simultaneously. At the termination of the adaptive current control mode, this does not affect the phase drop (e.g., recovery of clock 326 and slope compensation signal) after the end of the transient pulse, so any impact on regulator efficiency is minimal.

The ACC electronic circuit 136 may also end or terminate the adaptive current control mode operation of the multi-phase regulator when the transient load subsides. For example, in response to the output of the error amplifier output meeting or falling below the transient ramp 360, the output of the transient comparator 344 transitions positive to reset the RS flip-flop 346, which stops generating the mask signal 354 for the clock 326 and the offset 356 for the current comparator 324. Alternatively or additionally, the reset of the RS flip-flop 346 may also unmask or resume the application of the slope compensation signal 320 to the current comparator 324 at the end of the adaptive current control mode. In this way, the generation of the mask clock 326 or variable length pulses corresponding to operation according to the adaptive current control mode may be initiated based on the PFM/PWM conversion 352 and terminated by the transient comparator 344 based on the output of the error amplifier 318 and the transient ramp signal 360 (or any suitable variable or fixed signal).

Example method

Example methods 500, 600, and 900 are described with reference to fig. 5, 6A, and 6B, and 9, respectively, in accordance with one or more aspects of adaptive current control for fast transient response. In general, the methods 500, 600, and 900 illustrate a collection of operations (or actions) that may be performed, but are not necessarily limited to, the order or combination of operations shown herein. Moreover, any of the one or more operations may be repeated, combined, re-organized, skipped, or linked to provide a wide variety of additional and/or alternative approaches. In portions of the following discussion, reference may be made to environment 100 of fig. 1, the electronic circuits or components of fig. 2-4, the system of fig. 12, and/or the entities detailed in fig. 1, by way of example only. The techniques and apparatus described in this disclosure are not limited to embodiments or capabilities of those described by an entity or entities running on a device or with reference to the figures.

Fig. 5 illustrates an example method 500 for implementing an adaptive current control mode (e.g., a hybrid stitch mode), including operations performed by the current controller 122 and/or the ACC electronic circuit 136. In some aspects, the operations of method 500 may be implemented by a power supply circuit of an electronic device for improving a response to a transient load on the power supply circuit to effectively reduce or avoid output voltage droop.

At 502, an increase in load is detected at the output of a switching power regulator (regulator). In some cases, the load is detected based on the voltage at the regulator output. For example, the load may be detected based on a switching regulator transition from PFM mode to PWM mode, output voltage dip detection, error voltage rising edge, error current of an operational transconductance amplifier, or similar combinations.

At 504, an adaptive current control mode of the regulator is initiated. The adaptive current control mode prevents the regulator's clock from affecting the current application to the regulator's inductor. In some cases, the adaptive current control mode includes generating a variable length pulse signal to mask a clock signal or an offset current control signal. In this case, the magnitude of the predefined offset applied to the current control signal may be configured based on the magnitude of the load (e.g., load-dependent offset) on the output of the switching regulator. This may be effective to increase the average amount of inductor current flowing through the inductor when operating in the adaptive current control mode.

At 506, a first phase of the adaptive current control mode is implemented. Typically, the first phase of the adaptive current control mode includes applying current to the inductor of the regulator until the inductor current reaches a maximum level. The first switching device or the high-side switching device of the switching regulator may be activated or fully opened to provide current to the inductor. The inductor current may be measured via sensing electronics operatively coupled to a terminal (e.g., source or drain) of the first switching device.

At 508, a second phase of the adaptive current control mode is implemented. The second phase of the adaptive current control mode includes flowing current through the inductor based on the output voltage of the regulator until the inductor current reaches a current control level. The second switching device or the low side switching device of the switching regulator may be activated or fully opened to continue current flow through the inductor. The current flowing into the inductor may be measured via sensing electronics operably coupled to a terminal (e.g., source or drain) of the second switching device.

At 510, it is determined whether the load at the output of the switching regulator has decreased. The voltage level at the circuit output may be compared to a reference voltage to determine whether the load has dropped. In some cases, the current-based derivative of the current control signal is compared to a predefined ramp signal to detect a reduction in the load. In this case, the amplitude or rate of increase of the predefined ramp signal may be set or configured based on the load amplitude (e.g., load-dependent ramp signal) at the circuit output. Alternatively or additionally, setting the amplitude or rate of increase of the predefined ramp signal may also effectively change the duration of time that the switching regulator operates in the adaptive current control mode.

From operation 510, the method 500 may return to operation 506 to implement another iteration of the first phase of the adaptive current control mode. For example, if the transient load or load step still exceeds the threshold amount of current provided at the output, the switching regulator may implement one or more additional iterations of the first and/or second stages of the adaptive current control mode to further increase the inductor current provided to the output. Alternatively, the method 500 may proceed to operation 512 to transition the switching regulator from the adaptive current control mode to the steady-state mode. For example, it may be determined that the load demand on the output of the switching regulator has decreased to a level at which steady state mode may be maintained.

At operation 512, the switching regulator transitions from the adaptive current control mode to the steady-state mode. In a steady-state mode, such as a valley current mode, the clock influence or control current of the switching regulator is applied to the inductor of the switching regulator. In some cases, the transition to steady state mode includes unmasking the clock signal, enabling the clock, recovering the slope compensation signal, removing the offset from the current control signal, and so forth. From operation 512 (e.g., after steady-state operation resumes), the method 500 may return to operation 502 to start another iteration of the method 500, such as in response to another load step or transient load on the output of the switching regulator.

Fig. 6A and 6B illustrate an example method 600 for masking a clock signal and activating a switching device of a switching regulator to increase an inductor current to an output of the switching regulator. In various embodiments, the current controller 122 and/or the ACC electronic circuit 136 may perform or cause the operations of the method 600.

At 602, a transient load is detected at an output of a switching regulator. The transient load may be detected in response to any suitable criteria, such as PMIC of a switching regulator initiating a transition from PFM mode to PWM mode, an output voltage dip at an output of the switching regulator, a rising edge of an output voltage provided by an error amplifier, or a current-based output provided by an error amplifier configured as a transconductance operational amplifier.

By way of example, consider fig. 7, which illustrates an example graph 700 of inductor current regulated according to one or more aspects of adaptive current control. As shown in graph 700, a transient load 702 is applied to the output of a switching regulator configured to implement adaptive current control. Here, it is assumed that signals are described with reference to the single-phase switching regulator of fig. 3 and the PMIC of the switching regulator is switched from the PFM mode to the PWM mode in response to detecting a dip in the output voltage.

At 604, the clock signal of the switching regulator is masked to prevent the clock signal from interrupting the application of current to the inductor of the switching regulator. In some embodiments, the clock circuit may be disabled or deactivated to cause the clock circuit to stop the generation of the clock signal. Optionally, at 606, an offset is applied to the current control signal. The offset may be predefined or configurable based on the load applied to the output of the switching regulator. In general, applying an offset to the current control signal is effective to increase the average amount of current flowing in the inductor for at least the portion of the time that the clock signal is masked. In the context of this example, the clock signal is masked at time 704 and the transient current offset is applied to the error amplifier output at 706.

Optionally, at 608, the slope compensation signal is masked. Slope compensation may be masked or prevented from being applied to the current control signal, e.g., in addition to an offset applied to the current control signal. In some cases, the slope compensation signal is masked or disabled in response to a pulse signal generated when the switching regulator operates in the adaptive current control mode. Shielding or blocking the slope compensation signal may effectively prevent the slope compensation signal from affecting the current applied to the inductor of the switching regulator. Referring to fig. 7, the compensation signal is masked from the error amplifier output at time 708, such as when the adaptive current control mode is enabled.

At 610, a first switching device of a switching regulator is activated to initiate application of current to an inductor. The first switching device or the high-side switching device may be fully opened to apply current to the inductor from the input of the switching regulator to ramp up the inductor current. In some cases, the amount of current flowing into or through the inductor is monitored via sensing electronics operatively coupled to the terminals of the first switching device. In the context of this example, the gate (gate) of the top or high-side switching device is activated at 710 to ramp up the current in the inductor of the switching regulator.

At 612, a first switching device of the switching regulator is deactivated in response to an amount of current flowing into the inductor satisfying a predefined threshold for a maximum current. For example, the amount of current flowing into the inductor may be compared to a predefined threshold for maximum current to reset the drive logic associated with the first switching device. In some aspects, operations 610 and 612 are implemented as part of a first phase of an adaptive current control mode in which application of current to an inductor current is adjusted based on a threshold value of a maximum inductor current. Continuing the ongoing example, the gate of the top or high-side switching device is deactivated at 712 to stop applying current to the inductor of the switching regulator.

At 614, a second switching device of the switching regulator is activated to enable current to continue to flow through an inductor of the switching regulator. The second switch or low side switching device may be fully opened to allow current to flow through the inductor from a lower potential. As current flows through the regulator, the amount of inductor current may decrease or decay over time. In some cases, the amount of current flowing through the inductor is monitored via sensing electronics operatively coupled to the terminals of the second switching device. In the context of this example, the gate of the bottom or low-side transistor is activated at 714 to enable current to flow through the inductor. Starting at operation 614 shown in fig. 6A, the method 600 proceeds to operation 618 as shown at 616 in fig. 6B.

At 618, the amount of current flowing into the inductor is compared to the current control signal. The current control signal or threshold may be a voltage signal or a current signal provided based on a difference between an output voltage of the switching regulator and a reference voltage. The current control signal may also include an offset that is applied to increase the average amount of inductor current. At 620, the second switching device is deactivated in response to the amount of current flowing into the inductor satisfying the current control signal. In some aspects, operations 614, 618, and 620 are implemented as part of the second stage of the adaptive current control mode, where the inductor current is adjusted (e.g., a droop or decay current) based on the offset current control signal. Continuing with the present example, when the inductor current satisfies the transient current offset signal (e.g., error amplifier output plus offset) at 716, the gate of the bottom or low-side transistor is deactivated.

Optionally, at 622, a first switching device of the regulator is activated to restart applying current to the inductor. This may be effective to increase the amount of current flowing into the inductor and to the regulator output. In some cases, operation 622 is performed to provide an increased amount of current in response to determining that the transient load or load step still meets a predefined threshold (e.g., an output voltage dip or voltage drop) for operating the switching regulator in the adaptive current control mode. The gate of the top transistor is again activated to ramp up the current in the inductor, as shown at 718, until the peak current limit is again reached at 720.

Optionally, at 624, a decrease in the transient load is detected on the output of the switching regulator. In some cases, the current or current mirror of the control signal provided by the error amplifier is compared to a predefined threshold for detecting a load reduction or transitioning the switching regulator to steady state operation. Alternatively or additionally, the predefined threshold may include a ramp signal having an initial amplitude and/or an increased rate configured based on the amplitude of the ramp signal (e.g., a load-dependent ramp signal). Configuring the amplitude or rate of increase of the predefined ramp signal may effectively change the duration of time that the switching regulator operates in the adaptive current control mode.

Optionally, at 626, the clock signal of the switching regulator is unshielded. This may enable the clock to interrupt or control the application of current to the inductor of the switching regulator. In other words, in response to a decrease in load at the switching regulator output, the switching regulator may transition from an adaptive current control mode to a steady-state PWM operation, where a clocked current is applied to the inductor. In some cases, the switching regulator enters a valley current control mode at operation 626.

Optionally, at 628, if applied, the offset is removed from the current control signal, such as restoring the current control signal for steady state operation. Optionally, at 630, the slope compensation signal may also be unmasked to restore the application of the signal to the current control signal. To summarize the present example, when the error amplifier output falls at 722, the clock signal recovers at 724 and the slope compensation signal recovers at 726, and the switching regulator transitions to fixed frequency operation at 728.

By implementing adaptive current control, the voltage drop at the output of the switching regulator can be reduced for various levels of load steps. As another example, consider fig. 8, which illustrates at 800 an example graph 802 of an output voltage and an example graph 804 of an inductor current for a switching regulator implementing adaptive current control. In response to a load step 806 of approximately 3.8 amps, the inductor current ramps up at 808 based on a peak or maximum current limit on the inductor of the switching regulator and the offset current control signal. By doing so, the voltage drop 810 at the output of the switching regulator can be reduced by approximately 50% from the nominal voltage, as compared to the performance of conventional fixed frequency switching. For example, under adaptive current control, the voltage may drop from 750mV to 680mV (-10%), while a fixed frequency switch may typically drop to 590mV (-21%), at which time the CPU or GPU component may not be operational.

Fig. 9 illustrates an example method 900 for implementing adaptive current control in a multi-phase power switching regulator, including operations performed by the current controller 122 and/or the ACC electronic circuit 136. In some aspects, the operations of method 900 may be implemented by a multi-phase power supply circuit of an electronic device to improve response to a transient load and reduce an amount of voltage droop associated with the transient load.

At 902, a transient load is detected at an output of a multi-phase switching regulator. Transient responses may be detected based on one or more criteria, such as a transition from PFM mode to PWM mode, an output voltage dip at the output of a switching regulator, a rising edge of an output voltage provided by an error amplifier, or an increase in a current-based output provided by an error amplifier configured as a transconductance operational amplifier.

At 904, clock circuits of respective drive electronics operably coupled to the multiple phases of the multiphase switching regulator are disabled. In some cases, clock signals of multiple phases of the multiphase switching regulator are masked. The offset may also be applied to a current control signal based on the output voltage of the switching regulator. Alternatively or additionally, the application of the slope compensation signal to the current control signal may be stopped when the clock circuit is disabled.

At 906, the respective high-side switches of the multiple phases are activated to initiate current flow in the respective inductors of the multiple phases. The high-side switch may ramp up a respective current in the inductor of each of the multiple phases while being turned on. At 908, the respective high-side switches of the multiple phases are deactivated in response to an amount of current flowing in the respective inductors reaching a maximum current threshold. For each phase, the amount of current flowing in the inductor may be compared to a threshold value independent of the maximum inductor current for the other phases. In other words, each inductor of the multi-phase switching regulator may ramp up to a maximum current before being deactivated.

By way of example, consider fig. 10, which illustrates at 1000 an example inductor current graph 1002 and an example output voltage graph 1004 of a multi-phase switching regulator implementing aspects of adaptive current control. In the context of a three-phase switching regulator, in response to detecting a load step, the high-side switches of all three phases are activated at 1006 to ramp up the respective inductor currents until the currents reach a peak current limit. In other words, since the normal clock signal is delayed and all inductor currents are controlled simultaneously using the same peak current and error amplifier voltage (with offset), all phases of the switching regulator can be commanded to the maximum inductor current ramp rate to increase the current at the regulator output in response to the transient load. As shown in fig. 10, with the derived load step related transient pulses (e.g., clock mask and offset signals), the phase cut signals may also be masked to ensure that all phases operate simultaneously. In this way, adaptive current control may not affect phase cut after transient load subsides, thereby minimizing the impact on the overall efficiency of the switching regulator.

At 910, the respective low-side switches of the multiple phases are activated to enable current to continue to flow through the respective inductors. The low-side switch of each of the multiple phases may be activated independently of the other low-side switch, such as when a maximum current threshold is reached for the corresponding inductor. At 912, the respective low side switches of the multiple phases are deactivated based on a comparison of an amount of current flowing into the respective inductors to a current control signal provided by the error amplifier. In some cases, the current control signal is offset or increased to cause a higher amount of mean current to flow through the respective inductor.

Optionally, at 914, the respective high-side switches of the multiple phases are activated to restart the current flow in the respective inductors. This may be effective to increase the amount of current flowing to the regulator output. In some cases, operation 914 is performed in response to determining that the transient load or load step still satisfies a predefined threshold (e.g., an output voltage dip or voltage drop) for operating the multi-phase switching regulator in the adaptive current control mode. In the context of fig. 10, the current controller reactivates the three-phase high-side switches to restart current flow and again ramps up the current in the respective inductors until a peak current limit is reached to increase the current flow to the output of the multiphase switching regulator.

Optionally, at 916, a clock circuit is enabled to resume clock-based operation of the multiphase regulator. In some cases, the clock circuit is enabled in response to determining that a transient load or transient step on the output of the multi-phase switching regulator has decreased or subsided. Enabling the clock circuit may include unmasking a clock signal of the switching regulator to enable clock-based or fixed frequency control of the switching regulator. Alternatively or additionally, the application of the offset to the current control signal may be stopped and/or the application of the slope compensation signal to the current control signal may be resumed.

To summarize the present example, the three-phase switching regulator returns to steady-state operation at 1008 after recovering from a drop in output voltage 1010. Here, note that by implementing adaptive current control, the multi-phase switching regulator can achieve similar voltage droop performance (-10% nominal voltage) by one-third of the output capacitance typically used by fixed frequency switching regulators. As such, in some embodiments, aspects of adaptive current control may reduce the cost, manufacturing complexity, and design space associated with switching regulator output capacitance by approximately 66%. This in turn can increase the price, battery life, and competitiveness of devices having switching regulators implementing adaptive current control.

As another example, consider fig. 11, which illustrates at 1100 an example output voltage plot 1102 and an example inductor current plot 1104 for a multiphase switching regulator implementing adaptive current control. In this example, a load step 1106 of 6 amps and a load step 1108 of 12 amps with a slew rate of 120A/μ Sec are applied to the output of the multiphase switching regulator. As shown, the implementation of adaptive current control greatly improves the transient response to these large load steps. By ramping up the inductor current in the three inductors of the multiphase switching regulator, the voltage drops at 1110 and 1112 are reduced to prevent interruption of components (e.g., CPU and GPU) coupled to the output of the multiphase switching regulator. By doing so, this may eliminate the need to limit current-intensive CPU/GPU components, thereby improving or preserving device performance and improving user experience.

Example System

Fig. 12 illustrates an example system on a chip (SoC) that may implement aspects of adaptive current control for transient load responses. The SoC 1200 may be embodied as or in any type of user equipment 102, user equipment, apparatus, other device or system, as described with reference to fig. 1-11. Although described with reference to chip-based packaging, the components shown in fig. 12 may also be embodied as other systems or component configurations, such as, but not limited to, Power Management Integrated Circuits (PMICs), power conditioning circuits, Switch Mode Power Supplies (SMPS), Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), Digital Signal Processors (DSPs), Complex Programmable Logic Devices (CPLDs), System In Package (SiP), package on package (PoP), processing and communication chipsets, communication coprocessors, sensor coprocessors, and so forth.

In this example, SoC 1200 includes a communication transceiver 1202 and a wireless modem 1204 that enable wired or wireless communication of data 1206 (e.g., received data, data being received, data scheduled for broadcast, packetized data, etc.). In some aspects, the wireless modem 1204 is implemented as a multi-mode multi-band modem or baseband processor that can be configured to communicate in accordance with various communication protocols and/or in different frequency bands. The wireless modem 1204 may include a transceiver interface (not shown) for communicating coded or modulated signals with transceiver electronics and/or controlling a Radio Frequency (RF) front end.

The data 1206 or other system content can include configuration settings of the system or various components (e.g., various current thresholds as described herein), media content stored by the system, and/or information associated with a user of the system. The media content stored on the system-on-chip 1200 may include any type of audio, video, and/or image data. The system-on-chip 1200 also includes one or more data inputs 1208 via which any type of data, media content, and/or inputs can be received, such as user input, user-selectable input (explicit or implicit), or any other type of audio, video, and/or image data received from a content and/or data source. Alternatively or additionally, data input 1208 may include various data interfaces, which may be implemented as any one or more of a serial and/or parallel interface, a wireless interface, a network interface, and as any other type of communication interface that enables communication with other devices or systems.

The system-on-chip 1200 includes one or more processor cores 1210 that process various computer-executable instructions to control the operation of the system-on-chip 1200 and to enable adaptive current control techniques for fast transient response. Alternatively or in addition, the system-on-chip 1200 may be implemented with any one or combination of hardware, firmware, or fixed logic electronic circuitry that is implemented in connection with processing and control circuits, which are generally shown at 1212. Although not shown, the system-on-chip 1200 may also include a bus, interconnect, crossbar, or fabric that couples the various components within the system.

System 1200 also includes a memory 1214 (e.g., a computer-readable medium), such as one or more memory circuits, that enables persistent and/or non-transitory data storage and, thus, does not include a transitory signal or carrier wave. Examples of memory 1214 include ROM, RAM, DRAM, SRAM, or flash memory. Memory 1214 provides data storage for system data 1206, as well as firmware 1216, applications 1218, and any other types of information and/or data related to operational aspects of system-on-chip 1200. For example, firmware 1216 may be maintained as processor-executable instructions of an operating system (e.g., a real-time OS) within memory 1214 and executed on one or more processor cores 1210.

Applications 1218 may include a system manager, such as any form of a control application, software application, signal processing and control module, system-specific native code, abstraction module, or gesture module, among others. The memory 1214 may also store system components or utilities to implement various aspects of adaptive current control for fast transient response, such as the adaptive current controller 122 (current controller 122) and configurable current threshold and offset registers (not shown). The current controller 122 and the registers may be embodied as combined or separate components, examples of which are described with reference to the corresponding entities or functions shown in fig. 1-11.

In some aspects, system-on-chip 1200 also includes additional processors or co-processors to enable other functions, such as graphics processor 1220, audio processor 1222, and image sensor processor 1224. Graphics processor 1220 may render graphical content associated with a user interface, an operating system, or an application of system-on-chip 1200. In some cases, the audio processor 1222 encodes or decodes audio data and signals, such as audio signals and information associated with a voice call or encoded audio data for playback. Image sensor processor 1224 may be coupled to an image sensor and provide image data processing, video capture, and other visual media conditioning and processing functions.

The processor and co-processor of the system-on-chip 1200 may be operably coupled with an instance of the switching regulator 134 implemented in or with the system-on-chip 1200. The switching regulator 134 may comprise a single-phase or multi-phase switching regulator, as described with reference to fig. 1-11. The system-on-chip 1200 is also implemented with an ACC electronic circuit 136, the ACC electronic circuit 136 being operatively coupled to the switching regulator 134 and the current controller 122. In some aspects, the current controller 122 and the adaptive current control electronics 136 may interact with the switching regulator 134 to implement adaptive current control in the system-on-chip 1200 for fast transient response as described herein.

The system-on-chip 1200 may also include a security processor 1226 to support various security, encryption, and cryptographic operations, such as providing secure communication protocols and encrypted data storage. Although not shown, the security processor 1226 may include one or more cryptographic engines, cryptographic libraries, hash modules, or random number generators to support encryption and cryptographic processing of information or communications for the system-on-chip 1200. Alternatively or additionally, the system-on-chip 1200 may include a positioning and location engine 1228 and a sensor interface 1230. In general, the position and location engine 1228 may provide position or location data (e.g., dead reckoning navigation) by processing signals of Global Navigation Satellite Systems (GNSS) and/or other motion or inertial sensor data. The sensor interface 1230 enables the system-on-chip 1200 to receive data from various sensors, such as capacitive and motion sensors.

Variants

Although the above-described apparatus and methods are described in the context of adaptive current control for switching power regulators for consumer devices, power circuits, and electronic systems, the described apparatus, systems, and methods are non-limiting and may be applied to other contexts, consumer device configurations, or power conversion environments.

In general, the components, modules, methods, and operations described herein may be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Some operations of example methods may be described in the general context of executable instructions stored on a computer-readable storage memory local and/or remote to a computer processing system, and embodiments may include software applications, programs, functions, and so on. Alternatively or additionally, any of the functions described herein may be performed, at least in part, by one or more hardware logic components, such as, but not limited to, a PMIC, an FPGA, an ASIC, an ASSP, a SoC, a CPLD, a coprocessor, a context hub, a motion coprocessor, a sensor coprocessor, and the like.

In a first method implemented by a switching power regulator to increase an output current in response to an increase in a load on the switching power regulator, including detecting an increase in the load at an output of the switching power regulator, initiating an adaptive current control mode of the switching power regulator in response to the increase in the load, in which adaptive current control mode a clock effect of the switching power regulator is prevented from applying a current to an inductor of the switching power regulator, implementing a first phase of the adaptive current control mode in which the current is applied from an input of the switching power regulator to the inductor of the switching power regulator via a first switching device until the inductor current reaches a predetermined level of maximum current, implementing a second phase of the adaptive current control mode, in the second phase of the adaptive current control mode, enabling the current to flow through the inductor via a second switching device from a potential lower than an input of the switching power regulator until the inductor current reaches a current control signal based on an output voltage of the switching power regulator, detecting a decrease in a load at the output when the switching power regulator operates in the adaptive current control mode, and in response to the decrease in the load at the output, switching the switching power regulator to operate in a steady state mode in which a clock of the switching power regulator affects application of the current to an inductor of the switching power regulator.

In addition to the first method described above, an apparatus for regulating power includes, a first switching device coupled to an input of a circuit, an inductor having a first end coupled to the first switching device and a second end coupled to an output of the circuit, a second switch coupled between the first end of the inductor and a potential below the input of the circuit, first and second sensing electronic circuits, configured to provide first and second indications of current flowing through the first and second switching devices, respectively, a clock operatively coupled to the drive electronics of the first switching device and the second switching device, a current comparator, having an output operatively coupled to the drive electronics and a first input operatively coupled to the second sense electronics, an error amplifier, having an input operatively coupled to the output of the circuit and an output coupled to the second input of the current comparator, and an adaptive current controller. An adaptive current controller is configured to detect an increase in a load at an output of the circuit, cause the circuit to operate in an adaptive current control mode in response to the increase in the load, prevent a clock-affected current of the circuit from being applied to an inductor of the circuit in the adaptive current control mode, implement a first phase of the adaptive current control mode in which the current is applied to the inductor via the first switching device until a first indication of the current flowing through the inductor reaches a predetermined level of a maximum inductor current, implement a second phase of the adaptive current control mode in which the current is enabled to flow through the inductor via the second switching device until the current comparator determines that a second indication of the current flowing through the inductor reaches via the error amplification The output of the current control signal provided by the output of the current control circuit; when the circuit is operating in the adaptive current control mode, a decrease in the load at the output is detected, and in response to the decrease in the load at the output, the circuit is transitioned from the adaptive current control mode to operating in a steady-state mode in which a clock of the circuit affects application of the current to an inductor of the circuit.

In addition to the above-described methods and apparatus, a second method implemented by a switching power regulator to increase an output current in response to a transient load on the switching power regulator includes detecting a transient load at an output of the switching power regulator, in response to detecting the transient load, masking a clock signal of the switching power regulator to prevent the clock signal from interrupting application of current to an inductor of the switching power regulator, activating a first switching device of the switching power regulator to initiate application of the current to the inductor of the switching power regulator, sensing an amount of current flowing into the inductor at a first node operatively coupled to the first switching device to provide a first indication of a current flow to the inductor, in response to the first indication of current flow satisfying a predefined threshold of maximum inductor current, deactivating a first switching device, activating a second switching device of the switching power regulator to continue the current flow through the inductor in response to deactivating the first switching device, sensing an amount of current flowing into the inductor at a second node operatively coupled to the second switching device to provide a second indication of current flow in the inductor, comparing the second indication of current flow to a control signal based on an output voltage of the switching power regulator when the second switching device is activated, deactivating the second switching device in response to the second indication of current flow satisfying the control signal based on the output voltage of the switching power regulator, and activating the first switching device to restart application of the current to the inductor of the switching power regulator, effectively increasing the amount of current flowing into the inductor and to the output of the switching power regulator.

In addition to any of the methods or apparatus described above, operating the switching power regulator in the adaptive current control mode further comprises applying a predefined offset to the current control signal effective to increase an average amount of inductor current flowing through the inductor.

In addition to any of the methods or apparatus described above, operating the switching power regulator in the adaptive current control mode further comprises comparing a current-based derivative of the current control signal to a predefined ramp signal to detect a reduction in load at the output.

In addition to any of the methods or apparatus described above, operating the switching power regulator in the adaptive current control mode further comprises masking a slope compensation signal applied to the current control signal during the steady state mode operation to prevent the slope compensation signal from affecting current application to the inductor.

In addition to any of the methods or apparatus described above, the predefined offset applied to the current control signal is configured based on an amplitude of the load at the output of the switching power regulator, or the amplitude or rate of increase of the predetermined ramp signal compared to the derivative of the current control signal is configured based on an amplitude of the load at the output of the switching power regulator.

In addition to any of the methods or apparatus described above, the first stage of implementing an adaptive current control mode includes, at a first node operatively coupled to the first switching device, sensing an amount of current applied to an inductor of the switching power regulator to provide a first indication of the inductor current, and deactivating the first switching device in response to the first indication of inductor current meeting a predefined threshold of the maximum current level; or a second stage of implementing an adaptive current control mode includes, at a second node operatively coupled to the second switching device, sensing an amount of current flowing through an inductor of the switching power regulator to provide a second indication of the inductor current, and when the second switching device is activated, comparing the second indication of the inductor current to a control signal based on an output voltage of the switching power regulator.

In addition to any of the methods or apparatus described above, detecting an increase in load at an output of the switching power regulator based on at least one of: the switching power regulator switches from a Pulse Frequency Modulation (PFM) mode to a Pulse Width Modulation (PWM) mode, an output voltage dip at an output of the switching power regulator, a rising edge of the output voltage provided by an error amplifier operatively coupled to an output of the switching power regulator providing the current control signal, or a current-based output provided by the error amplifier operatively coupled to the output of the switching power regulator.

In addition to any of the methods or apparatus described above, a circuit is configured to apply an offset to an output signal of the error amplifier to effectively increase an average amount of current flowing into the inductor for at least a portion of the time the circuit is operating in the adaptive current control mode.

In addition to any of the methods or apparatus described above, the circuit further includes at least one logic gate configured to generate the offset in response to detecting the transient load at an output of the circuit, and a comparator configured to: comparing a current-based voltage indication at an output of the circuit to a predefined ramp signal to transition the circuit to the steady-state mode or stop generating the offset, and transitioning the circuit to the steady-state mode in response to the current-based indication no longer exceeding the predefined ramp signal or stop generating the offset in response to the current-based indication no longer exceeding the predefined threshold.

In addition to any of the methods or apparatus described above, the adaptive current controller is further configured to set a magnitude of the offset applied to the current control signal based on a magnitude of a load at the output of the circuit, or to set a magnitude or rate of increase of a predefined ramp signal compared to the current-based voltage indication based on the magnitude of the load at the output of the circuit.

In addition to any of the methods or apparatus described above, the amplitude or rate of increase of the predetermined ramp signal is set based on the amplitude of the load at the output of the circuit to effectively change the duration of time that the circuit operates in the adaptive current control mode.

In addition to any of the methods or apparatus described above, the circuit is configured as a multi-phase power conditioning circuit, the first switching device, the inductor, the second switching device, and a current comparator configured as a first phase of the multi-phase power conditioning circuit, the multi-phase power conditioning circuit including at least a second phase having another inductor, the clock-affected current of the circuit being prevented from being applied to the inductor of at least the first phase and the another inductor of at least the second phase of the multi-phase power conditioning circuit during the adaptive current control mode of operation.

In addition to any of the methods or apparatus described above, the method further includes applying an offset to the control signal for at least a portion of the time during which the clock signal is masked effective to increase an average amount of current flowing in the inductor, and/or configuring the offset applied to the control signal based on a magnitude of the transient load at the output of the switching power regulator such that the magnitude of the offset corresponds to the magnitude of the transient load at the output of the switching power regulator.

In addition to any of the methods or apparatus described above, in response to detecting a transient load at an output of the switching power regulator, a current corresponding to the control signal based on the output voltage is compared to a predefined threshold for cancelling the masking clock signal or stopping generating the offset, and the masking clock signal is cancelled in response to the current no longer exceeding the predefined threshold, or the offset is stopped being generated in response to the current no longer exceeding the predefined threshold.

In addition to any of the methods or apparatus described above, the predefined threshold is a ramp signal that increases over time, and further comprising generating the ramp signal based on a predetermined setting of a rate at which the ramp signal increases or an amplitude of the ramp signal, and/or configuring the predetermined setting of the rate or the amplitude of the ramp signal based on an amplitude of a transient load at an output of the switching power regulator.

In addition to any of the methods or apparatus described above, the application of the slope compensation signal to the control signal based on the output voltage of the switching power regulator is stopped while the offset is applied to the control signal to effectively prevent the slope compensation signal from affecting the application of current to the inductor of the switching power regulator.

In addition to any of the methods or apparatus described above, detecting a decrease in transient load at an output of the switching power regulator and in response to detecting the decrease in transient load: the method further includes the steps of canceling the clock signal of the shielded switching power regulator to effect clock-based control of the switching power regulator based on at least the clock signal and the second indication of current flow in the inductor, stopping application of the offset to the control signal based on the switching power regulator output voltage, or resuming application of the slope compensation signal to the control signal based on the power output voltage.