阅读说明：本技术 一种短时掉电可恢复系统和短时掉电恢复方法 (Short-time power failure recoverable system and short-time power failure recovering method ) 是由 屈盼让 李军 呼明亮 蔡晓乐 肖鹏 于方春 于 2021-09-01 设计创作，主要内容包括：本发明公开一种短时掉电可恢复系统和短时掉电恢复方法,系统包括：电源模块、掉电恢复控制器、处理器和复位芯片；电源模块具有短时掉电保持能力,监控该电源模块的输入电压,并发出掉电指示信号；掉电恢复控制器根据掉电指示信号的变化,在开始掉电时刻产生并输出第一中断信号,以及根据掉电指示信号的变化,在电源模块的输入电压在掉电保持能力范围外恢复时产生并输出复位信号,复位信号传输至复位芯片的复位输入引脚,以通过复位芯片复位短时工作在电压不稳定状态的处理器和掉电恢复控制器。本发明的技术方案解决了现有机载设备在短时掉电情况下,因电源模块的电压不稳定而导致的掉电现场数据丢失以及机载设备的部分功能异常的问题。(The invention discloses a short-time power failure recoverable system and a short-time power failure recovering method, wherein the system comprises: the power supply module, the power failure recovery controller, the processor and the reset chip are arranged in the power supply module; the power supply module has short-time power-down holding capacity, monitors the input voltage of the power supply module and sends a power-down indicating signal; the power failure recovery controller generates and outputs a first interrupt signal at the time of starting power failure according to the change of the power failure indication signal, generates and outputs a reset signal when the input voltage of the power supply module recovers outside the range of power failure holding capacity according to the change of the power failure indication signal, and transmits the reset signal to a reset input pin of a reset chip so as to reset the processor and the power failure recovery controller which work in an unstable voltage state for a short time through the reset chip. The technical scheme of the invention solves the problems of power failure field data loss and partial function abnormity of the airborne equipment caused by unstable voltage of the power module under the condition of short-time power failure of the conventional airborne equipment.)

1. A short power down recovery system, comprising: the power supply module, the power failure recovery controller, the processor and the reset chip are arranged in the power supply module;

the power module is used for supplying power to each device in the short-time power-down recoverable system and has short-time power-down retention capacity;

the power supply module is also used for monitoring the input voltage of the power supply module and sending a power failure indication signal according to the input voltage, and the power failure indication signal is transmitted to the power failure recovery controller;

the power failure recovery controller is connected with the power module and used for generating and outputting a first interrupt signal at the time of starting power failure according to the change of the power failure indication signal, and the first interrupt signal is transmitted to an interrupt input pin of the processor so as to indicate the processor that the power module enters a short-time power failure state;

the power failure recovery controller is also used for generating and outputting a reset signal when the input voltage of the power module recovers outside the power failure holding capacity range according to the change of the power failure indication signal, the reset signal is transmitted to a reset input pin of the reset chip, and the reset output pin of the reset chip is respectively connected to the reset input pin of the processor and the reset input pin of the power failure recovery controller, so that the processor and the power failure recovery controller which work in a voltage unstable state for a short time are reset through the reset chip.

2. The short-time power-down recoverable system according to claim 1, wherein a hysteresis comparator is configured inside the power module, and the hysteresis comparator has a high threshold and a low threshold, the high threshold is a lowest voltage at which the short-time power-down recoverable system can normally operate, and the low threshold is a highest voltage at which the short-time power-down recoverable system cannot operate;

the power module is used for sending out power-down indication signals according to input voltage, and comprises:

when the input voltage is greater than the high threshold, outputting a high-level power-down indication signal;

when the input voltage is smaller than the low threshold, outputting a low-level power-down indication signal;

when the input voltage is between the high threshold and the low threshold, keeping the output level unchanged;

the power failure recovery controller is used for generating and outputting a first interrupt signal, and comprises:

the power failure recovery controller generates and outputs a first interrupt signal when the power failure indication signal changes from a high level to a low level.

3. The short-term power-down recoverable system according to claim 2, wherein the power-down recovery controller is implemented on programmable logic, and comprises: the power failure recovery system comprises a timer, a power failure recovery enabling register and an overtime indicating register, wherein the power failure recovery controller is connected with a processor through a parallel bus.

4. The short-term power-down recoverable system according to claim 3, wherein the power-down recovery controller has two operating conditions:

in case 1, when the value of the power failure recovery enable register is 0, the power failure recovery controller does not respond to the power failure indication signal;

and 2, when the value of the power failure recovery enabling register is 1, the power failure recovery controller generates a first interrupt signal and a reset signal according to the power failure indication signal and assigns a value to the overtime indication register.

5. The short power-down recoverable system according to claim 4,

the value of the power failure recovery enabling register is that the processor is configured through a parallel bus interface, and the initial value is 0 and indicates that the power failure recovery function is forbidden by default;

the timer duration is configured by the processor through a parallel bus interface, and is used for starting timing when the value of the power failure recovery enabling register is set to be 1 and the power failure indication signal is changed from high level to low level, and is also used for resetting the timer when the power failure indication signal is changed from low level to high level and the value of the overtime indication register is 0;

and the overtime indication register is used for being set to be 1 when the timer is overtime, the value of 0 represents that the timer is not overtime, and the value of the overtime indication register is read by the processor through the parallel bus interface period.

6. The short power-down recoverable system according to claim 5,

the power failure recovery controller is also used for generating and outputting a second interrupt signal at the overtime moment of the timer so as to indicate the processor that the power failure time of the power supply module exceeds the short-time power failure holding capacity of the power supply module and indicate the processor to record power failure field data.

7. A short-time power failure recovery method, which is implemented by using the short-time power failure recovery system as claimed in any one of claims 1 to 6, the method comprising:

step 1, a power supply module sends out a power failure indication signal according to the input voltage of the power supply module;

step 2, the power failure recovery controller generates and outputs a first interrupt signal at the time of starting power failure according to the change of the power failure indication signal so as to indicate the processor that the power supply module enters a short-time power failure state;

and 3, generating and outputting a reset signal by the power failure recovery controller when the input voltage of the power supply module recovers outside the power failure holding capacity range according to the change of the power failure indication signal so as to reset the processor and the power failure recovery controller which work in an unstable voltage state for a short time.

8. The short power loss recovery method according to claim 7,

in the step 2, the power failure recovery controller specifically generates and outputs a first interrupt signal when the power failure indication signal changes from a high level to a low level.

9. The short-term power loss recovery method according to claim 8, wherein the power loss recovery controller comprises a timer, a power loss recovery enable register and a timeout indication register; the timer is used for starting timing at the moment of sending the first interrupt signal; before step 3, the method further comprises:

step 2a, when the power failure indication signal is changed from low level to high level and the value of the overtime indication register is 0, the timer is cleared;

and 2b, generating and outputting a second interrupt signal at the overtime moment of the timer so as to indicate the processor that the power-down time of the power supply module exceeds the short-time power-down holding capacity of the power supply module and indicate the processor to record power-down field data.

10. The short power loss recovery method according to claim 3,

in the step 3, the power failure recovery controller specifically generates and outputs a reset signal when the value of the timeout indication register is 1 and the power failure indication signal changes from a low level to a high level.

Technical Field

The invention relates to the technical field of digital circuits, in particular to a short-time power failure recoverable system and a short-time power failure recoverable method.

Background

In the field of aviation airborne with high reliability requirements, a power module of airborne equipment often has short-term power-down retention capability to cope with complex airborne power supply environments.

However, under the condition of short-time power failure, the onboard equipment lacks power failure early warning capability and short-time power failure restorable capability, so that the conditions of power failure field data loss and part of functions of the onboard equipment, which are caused by unstable voltage of the power module, are easily caused.

Disclosure of Invention

The purpose of the invention is as follows: in order to solve the problems in the background art, embodiments of the present invention provide a short-time power failure recoverable system and a short-time power failure recovery method, so as to solve the problems of power failure field data loss and partial function abnormality of an onboard device caused by unstable voltage of a power module in a short-time power failure situation of an existing onboard device.

The technical scheme of the invention is as follows: the embodiment of the invention provides a short-time power failure recoverable system, which comprises: the power supply module, the power failure recovery controller, the processor and the reset chip are arranged in the power supply module;

the power module is used for supplying power to each device in the short-time power-down recoverable system and has short-time power-down retention capacity;

the power supply module is also used for monitoring the input voltage of the power supply module and sending a power failure indication signal according to the input voltage, and the power failure indication signal is transmitted to the power failure recovery controller;

the power failure recovery controller is connected with the power module and used for generating and outputting a first interrupt signal at the time of starting power failure according to the change of the power failure indication signal, and the first interrupt signal is transmitted to an interrupt input pin of the processor so as to indicate the processor that the power module enters a short-time power failure state;

the power failure recovery controller is also used for generating and outputting a reset signal when the input voltage of the power module recovers outside the power failure holding capacity range according to the change of the power failure indication signal, the reset signal is transmitted to a reset input pin of the reset chip, and the reset output pin of the reset chip is respectively connected to the reset input pin of the processor and the reset input pin of the power failure recovery controller, so that the processor and the power failure recovery controller which work in a voltage unstable state for a short time are reset through the reset chip.

Optionally, in the short-time power-down recoverable system, a hysteresis comparator is configured inside the power module, and the hysteresis comparator has a high threshold and a low threshold, where the high threshold is a lowest voltage at which the short-time power-down recoverable system normally operates, and the low threshold is a highest voltage at which the short-time power-down recoverable system cannot operate;

the power module is used for sending out power-down indication signals according to input voltage, and comprises:

when the input voltage is greater than the high threshold, outputting a high-level power-down indication signal;

when the input voltage is smaller than the low threshold, outputting a low-level power-down indication signal;

when the input voltage is between the high threshold and the low threshold, keeping the output level unchanged;

the power failure recovery controller is used for generating and outputting a first interrupt signal, and comprises:

the power failure recovery controller generates and outputs a first interrupt signal when the power failure indication signal changes from a high level to a low level.

Optionally, in the system that can recover from a power failure in a short time as described above, the power failure recovery controller is built on a programmable logic device, and includes: the power failure recovery system comprises a timer, a power failure recovery enabling register and an overtime indicating register, wherein the power failure recovery controller is connected with a processor through a parallel bus.

Optionally, in the short-time power-down recoverable system as described above, the power-down recovery controller has two working conditions:

in case 1, when the value of the power failure recovery enable register is 0, the power failure recovery controller does not respond to the power failure indication signal;

and 2, when the value of the power failure recovery enabling register is 1, the power failure recovery controller generates a first interrupt signal and a reset signal according to the power failure indication signal and assigns a value to the overtime indication register.

Alternatively, a brief power down as described above may restore the system,

the value of the power failure recovery enabling register is that the processor is configured through a parallel bus interface, and the initial value is 0 and indicates that the power failure recovery function is forbidden by default;

the timer duration is configured by the processor through a parallel bus interface, and is used for starting timing when the value of the power failure recovery enabling register is set to be 1 and the power failure indication signal is changed from high level to low level, and is also used for resetting the timer when the power failure indication signal is changed from low level to high level and the value of the overtime indication register is 0;

and the overtime indication register is used for being set to be 1 when the timer is overtime, the value of 0 represents that the timer is not overtime, and the value of the overtime indication register is read by the processor through the parallel bus interface period.

Alternatively, a brief power down as described above may restore the system,

the power failure recovery controller is also used for generating and outputting a second interrupt signal at the overtime moment of the timer so as to indicate the processor that the power failure time of the power supply module exceeds the short-time power failure holding capacity of the power supply module and indicate the processor to record power failure field data.

The embodiment of the invention also provides a short-time power failure recovery method, which is implemented by adopting the short-time power failure recovery system, and comprises the following steps:

step 1, a power supply module sends out a power failure indication signal according to the input voltage of the power supply module;

step 2, the power failure recovery controller generates and outputs a first interrupt signal at the time of starting power failure according to the change of the power failure indication signal so as to indicate the processor that the power supply module enters a short-time power failure state;

and 3, generating and outputting a reset signal by the power failure recovery controller when the input voltage of the power supply module recovers outside the power failure holding capacity range according to the change of the power failure indication signal so as to reset the processor and the power failure recovery controller which work in an unstable voltage state for a short time.

Alternatively, in the short power loss recovery method as described above,

in the step 2, the power failure recovery controller specifically generates and outputs a first interrupt signal when the power failure indication signal changes from a high level to a low level.

Optionally, in the short-time power failure recovery method, the power failure recovery controller includes a timer, a power failure recovery enable register, and an overtime indication register; the timer is used for starting timing at the moment of sending the first interrupt signal; before step 3, the method further comprises:

step 2a, when the power failure indication signal is changed from low level to high level and the value of the overtime indication register is 0, the timer is cleared;

and 2b, generating and outputting a second interrupt signal at the overtime moment of the timer so as to indicate the processor that the power-down time of the power supply module exceeds the short-time power-down holding capacity of the power supply module and indicate the processor to record power-down field data.

Alternatively, in the short power loss recovery method as described above,

in the step 3, the power failure recovery controller specifically generates and outputs a reset signal when the value of the timeout indication register is 1 and the power failure indication signal changes from a low level to a high level.

The invention has the beneficial effects that: the embodiment of the invention provides a short-time power-down recoverable system and a short-time power-down recovering method, in the short-time power-down recoverable system, a power-down recovery controller constructed on a programmable logic device is used for monitoring a power-down indicating signal output by a power module, a first interrupt signal and a reset signal are generated by logically judging the change of the power-down indicating signal and are respectively input to an interrupt pin of a processor and a manual reset pin of a reset chip, so that the short-time power-down recovering function of the system is realized, the anti-interference capability of system power supply is obviously enhanced, for example, for the short-time power-down condition, the processor is not instructed to record power-down field data after the first interrupt signal is sent, timing is started when the first interrupt signal is sent, and under the condition that a timer is not overtime and the power module is recovered (namely, the power-down time of the power module exceeds the short-time power-down maintaining capability), at the moment, the power failure does not affect the system, and the timer is stopped and reset; in addition, after the timer is overtime, a second interrupt signal is sent, which indicates that the power-down time of the power supply module exceeds the short-time power-down holding capacity of the power supply module, so as to instruct the processor to record power-down field data; the working mode of the short-time power-down recoverable system improves the robustness of the system. The short-time power failure recoverable system provided by the embodiment of the invention is particularly suitable for the field of airborne computers which work in strong electromagnetic radiation environments and have higher safety requirements.

Drawings

Fig. 1 is a schematic structural diagram of a short-time power-down recoverable system according to an embodiment of the present invention;

fig. 2 is a flowchart of a short-time power failure recovery method according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an operating principle of the short-time power failure recovery method according to the embodiment shown in fig. 2.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

In the field of aerospace, a power module of an airborne device generally has a short-term power-down retention capability to cope with a complex power supply environment. However, under the condition of short-time power failure, due to the fact that the onboard equipment lacks power failure early warning capability and short-time power failure restorable capability, power failure field data loss and partial function abnormity of the onboard equipment caused by unstable input voltage are easily caused.

Aiming at the problems of short-time power failure of airborne equipment, on one hand, the embodiment of the invention provides a short-time power failure recoverable system. In a high-reliability application scene, a power supply module sends a power failure indication signal by monitoring the input voltage of the power supply module, when the power failure indication signal is changed from a low level to a high level, the FPGA is indicated to generate an early warning signal, an indication processor records power failure field data, when the input voltage of the power supply module is recovered within a power failure holding capacity range (time threshold), the FPGA generates a reset signal so as to reset a processor and a power failure recovery controller which work in a voltage unstable state for a short time, and the system is recovered to a normal working mode, so that the system has important application value. On the other hand, aiming at the system with the power supply short-time power failure protection capability, the embodiment of the invention also provides a short-time power failure recovery method, which is used for monitoring the input voltage of the system, identifying the power supply power failure behavior and providing necessary power failure early warning and recovery indication for system decision and has important significance.

The following specific embodiments of the present invention may be combined, and the same or similar concepts or processes may not be described in detail in some embodiments.

Fig. 1 is a schematic structural diagram of a system that can recover from a short-time power failure according to an embodiment of the present invention. The short-time power failure recoverable system provided by the embodiment of the invention comprises: the power failure recovery device comprises a power module, a power failure recovery controller, a processor and a reset chip.

In the structure of the short-time power-down recoverable system shown in fig. 1, the power module can not only supply power to each device in the short-time power-down recoverable system, but also has short-time power-down retention capability. In addition, the power supply module can also monitor the input voltage of the power supply module, send out a power failure indication signal according to the input voltage and transmit the power failure indication signal to the power failure recovery controller.

In the embodiment of the invention, the power supply module monitors the input voltage and generates a power failure indication signal POW _ VUV, and the POW _ VUV output by the power supply module is transmitted to a user IO of the power failure recovery controller.

The functions of the power failure recovery controller connected with the power module include: on one hand, according to the change of the power-down indication signal, a first interrupt signal is generated and output at the time of starting power-down, and the first interrupt signal is transmitted to an interrupt input pin of the processor so as to indicate the processor that the power supply module enters a short-time power-down state. In practical application, the power failure recovery controller generates a first interrupt signal CPU _ INT when the POW _ VUV changes from a low level to a high level, and outputs the first interrupt signal CPU _ INT to an interrupt input pin of the processor from the user IO.

On the other hand, the power failure recovery controller can also generate and output a reset signal when the input voltage of the power module recovers outside the power failure holding capacity range according to the change of the power failure indication signal, the reset signal is transmitted to a reset input pin of the reset chip, and the reset output pin of the reset chip is respectively connected to the reset input pin of the processor and the reset input pin of the power failure recovery controller, so that the processor and the power failure recovery controller which work in a voltage unstable state for a short time are reset through the reset chip. In practical application, the power failure recovery controller generates a reset signal RST _ OUT when POW _ VUV is deactivated, and outputs the reset signal RST _ OUT to a manual reset pin of a reset chip from a user IO of the power failure recovery controller.

In an implementation manner of the embodiment of the present invention, a hysteresis comparator is configured inside the power module, and the hysteresis comparator has a high threshold and a low threshold, where the high threshold is a lowest voltage at which the short-time power-down recoverable system can normally operate, and the low threshold is a highest voltage at which the short-time power-down recoverable system cannot operate. In this implementation, the power supply module specifically generates the power down indication signal POW _ VUV through the hysteresis comparator.

In the specific implementation of this implementation, the power module sends out the specific implementation of the power down indication signal according to the input voltage, that is, the working principle of the hysteresis comparator is as follows:

when the input voltage is greater than the high threshold, outputting a high-level power-down indication signal;

when the input voltage is smaller than the low threshold, outputting a low-level power-down indication signal;

the output level is maintained constant when the input voltage is between the high threshold and the low threshold.

Based on the above implementation manner of outputting the power-down indication signal by the power module, the power-down indication signal output by the power module may have a change condition, and accordingly, in the embodiment of the present invention, the specific implementation manner of generating and outputting the first interrupt signal by the power-down recovery controller may include:

the power failure recovery controller generates and outputs a first interrupt signal when the power failure indication signal is changed from a high level to a low level, wherein the first interrupt signal is an early warning when the power supply module is in power failure.

The power failure recovery controller in the embodiment of the invention is constructed on a programmable logic device, namely the power failure recovery controller is realized based on the programmable logic device, and the power failure recovery controller can comprise: the POWER failure recovery system comprises a timer, a POWER failure recovery enabling register and an overtime indication register, wherein the POWER failure recovery controller is connected with a processor through a parallel bus, the input of the POWER failure recovery controller comprises a POWER failure indication signal POWER _ FLAG, and the output of the POWER failure recovery controller comprises a first interrupt signal CPU _ INT and a reset signal RST _ OUT.

It should be noted that, the value of the power down recovery enable register in the power down recovery controller may be configured by the processor through the parallel bus interface, and the initial value is 0, which indicates that the power down recovery function is prohibited by default.

Based on the above description of the internal structure and functions of each device of the power failure recovery controller, the power failure recovery controller has the following two working conditions:

in case 1, when the value of the power failure recovery enabling register is 0, namely the power failure recovery state is prohibited, the power failure recovery controller does not respond to the power failure indication signal;

and 2, when the value of the power failure recovery enabling register is 1, namely the power failure recovery enabling register is in a power failure recovery enabling state, the power failure recovery controller generates a first interrupt signal and a reset signal according to the power failure indication signal, and assigns a value to the overtime indication register.

In a specific implementation of the embodiment of the present invention, the duration of the timer is configured by the processor through the parallel bus interface, and is used to start timing when the value of the power failure recovery enable register is set to 1 and the power failure indication signal changes from a high level to a low level, that is, to start timing when the first interrupt signal is sent out. The timer is also configured to clear the timer when the power down instruction signal changes from low level to high level and the value of the timeout instruction register is 0.

In a specific implementation of the embodiment of the present invention, a TimeOut indication register TimeOut in the power failure recovery controller is configured to be set to 1 when the timer is overtime, a value of the TimeOut indication register TimeOut is 0, which indicates that the timer is not overtime, and a value of the TimeOut indication register TimeOut is periodically read by the processor through the parallel bus interface.

Further, the power failure recovery controller in the embodiment of the present invention is further configured to generate and output a second interrupt signal at a time when the timer is overtime, so as to indicate to the processor that the power failure time of the power supply module exceeds the short-time power failure retention capability thereof, and indicate to the processor to record power failure field data.

The short-time power failure restorable system provided by the embodiment of the invention realizes the short-time power failure restorable function of the system by monitoring the power failure indication signal output by the power module through the power failure restorable controller constructed on the programmable logic device, generating a first interrupt signal and a reset signal through logically judging the change of the power failure indication signal, and respectively inputting the first interrupt signal and the reset signal into the interrupt pin of the processor and the manual reset pin of the reset chip, thereby obviously enhancing the anti-jamming capability of the system for supplying power, for example, for the short-time power failure condition, the processor is not instructed to record power failure field data after the first interrupt signal is sent, timing is started when the first interrupt signal is sent, so that the system is not influenced by power failure under the condition that the timer is not overtime and the power module is restored (namely, the power failure time of the power module exceeds the short-time power failure maintaining capability of the power module), the timer should be stopped and reset; in addition, after the timer is overtime, a second interrupt signal is sent, which indicates that the power-down time of the power supply module exceeds the short-time power-down holding capacity of the power supply module, so as to instruct the processor to record power-down field data; the working mode of the short-time power-down recoverable system improves the robustness of the system. The short-time power failure recoverable system provided by the embodiment of the invention is particularly suitable for the field of airborne computers which work in strong electromagnetic radiation environments and have higher safety requirements.

Based on the short-term power failure recoverable system provided by the above embodiment of the present invention, an embodiment of the present invention further provides a short-term power failure recovery method, which is executed by the short-term power failure recoverable system provided by any of the above embodiments of the present invention, fig. 2 is a flowchart of a short-term power failure recovery method provided by an embodiment of the present invention, and fig. 3 is a schematic diagram of a working principle of the short-term power failure recovery method provided by the embodiment shown in fig. 2, and the short-term power failure recovery method may include the following steps:

step 1, a power supply module sends out a power failure indication signal according to the input voltage of the power supply module;

step 2, the power failure recovery controller generates and outputs a first interrupt signal at the time of starting power failure according to the change of the power failure indication signal so as to indicate the processor that the power supply module enters a short-time power failure state;

and 3, generating and outputting a reset signal by the power failure recovery controller when the input voltage of the power supply module recovers outside the power failure holding capacity range according to the change of the power failure indication signal so as to reset the processor and the power failure recovery controller which work in an unstable voltage state for a short time.

In practical application, in step 2, the power failure recovery controller specifically generates and outputs a first interrupt signal when the power failure indication signal changes from a high level to a low level. As shown in fig. 3, the time point of sending the first interrupt signal is (i) early warning when power is down, that is, the first interrupt signal is used for early warning when power is down.

In an implementation manner of the embodiment of the present invention, the power failure recovery controller may include a timer, a power failure recovery enable register, and an overtime indication register; the timer is used for starting timing at the moment of sending the first interrupt signal, namely after 'early warning during power failure' in figure 2, the timer starts timing; correspondingly, before step 3, the method provided in the embodiment of the present invention may further include:

and 2a, when the power failure indication signal is changed from low level to high level and the value of the overtime indication register is 0, clearing the timer.

The time described in step 2a corresponds to "recovery before timeout" in fig. 2, in which case, the processor is not required to record the power failure field data, and the timer is cleared.

And 2b, generating and outputting a second interrupt signal at the overtime moment of the timer so as to indicate the processor that the power-down time of the power supply module exceeds the short-time power-down holding capacity of the power supply module and indicate the processor to record power-down field data.

The time described in step 2b corresponds to "time out of timer" in fig. 2, and the time sends out a second interrupt signal for indicating that the power-down time of the power supply module exceeds the short-time power-down retention capability, and at this time, the processor is required to record the power-down field data.

In the specific implementation of the embodiment of the present invention, in step 3, the power failure recovery controller specifically generates and outputs the reset signal when the value of the timeout indication register is 1 and the power failure indication signal changes from a low level to a high level.

The time described in step 3 corresponds to "resume after timeout" in fig. 2, in this case, since the value of the timeout indication register is already set to 1 when the timer is overtime, it indicates that the timer is overtime, and the processor records the power failure field data according to the second interrupt signal at the time when the timer is overtime, and then the initial states of the power failure recovery controller and the reset chip can be recovered through the reset signal.

The short-time power failure recovery method provided by the embodiment of the invention has the advantages that the power failure recovery controller is constructed on the basis of the programmable logic device, the power failure behavior is identified by monitoring the power failure indication signal and setting the timer, the power failure early warning and reset indication (recovery after timeout) is provided for system decision, the power failure recovery method has the capability of recovering before timeout and indicating the timeout of the timer, the power interference resistance of the system in a complex power supply environment is obviously improved, and the system robustness is enhanced.

The following describes a specific implementation of the short-time power failure recoverable system and the short-time power failure recovery method according to the embodiments of the present invention with a specific implementation example.

The specific embodiment first provides a system capable of recovering from a short-time power failure, and as shown in fig. 1, the system mainly includes: the power failure recovery device comprises a power module, a power failure recovery controller (constructed on a programmable logic device), a processor and a reset chip.

The power supply module has a short-time power failure maintaining function, monitors input voltage of each device in the system while supplying power to the devices in the system, generates a power failure indication signal POW _ VUV, connects the POW _ VUV to user IO of the programmable logic device, indicates that the input voltage of the power supply is lower than a power failure threshold when the POW _ VUV is changed from low level to high level, and cancels the POW _ VUV to indicate that the input voltage of the power supply is recovered.

The programmable logic device monitors a power failure indication signal POW _ VUV in real time, generates a first interrupt signal CPU _ INT when the POW _ VUV is changed from a low level to a high level, and outputs the first interrupt signal CPU _ INT to an interrupt pin of the processor from a user IO; the reset signal RST _ OUT is generated at POW _ VUV deactivation and is output from its user IO to the manual reset pin of the reset chip.

When the first interrupt signal CPU _ INT is effective, the processor executes an interrupt reset program, enters a power-down mode, and stores important data.

And the reset output of the reset chip is simultaneously connected to the reset pins of the processor and the programmable logic device, and when RST _ OUT is received, the reset chip simultaneously resets the processor and the programmable logic device.

The short-time power-down recoverable system provided by the specific embodiment mainly comprises a power module, a power-down recovery controller, a processor and a reset chip. The specific embodiment aims at the high-safety design requirement of the airborne computer, on the premise that a system power module has short-time power-down retention capacity, the power-down recovery controller is applied to monitor a power-down indicating signal output by the power module, and the interrupt and reset signals are generated through logic judgment and are respectively input to an interrupt pin of a processor and a manual reset pin of a reset chip, so that the short-time power-down recovery function of the system is realized, the power-interference resistance capacity is obviously enhanced, and the system robustness is improved.

In the short-time POWER-down recoverable system provided by this embodiment, an input of the POWER-down recovery controller includes a POWER-down indication signal POWER _ FLAG, and an output thereof includes a first interrupt signal CPU _ INT and a reset signal RST _ OUT. When the system input voltage is higher than the voltage high threshold POWER _ HTHR, the POWER _ FLAG is set to 1, which indicates that the system is normally powered; and when the input voltage of the system is lower than the voltage low threshold POWER _ LTHR, setting the POWER _ FLAG to 0 to indicate that the system starts to POWER down. The first interrupt signal CPU _ INT is output by a user IO of the programmable logic device onto an interrupt pin of the processor. The reset signal RST _ OUT is output to a receiving reset pin of the reset chip by a user IO of the programmable logic device.

In the specific embodiment, the power failure recovery controller is realized based on a programmable logic device, the power failure recovery controller internally comprises a timer, a power failure recovery enabling register and an overtime indication register TimeOut, and the power failure recovery controller interacts with the processor through a parallel bus interface. The timing duration of the timer is equal to the power-down holding time of the power module, and the timer can be configured by the processor through the parallel bus; the default initial value of the power failure recovery enabling register is 0, which indicates that the power failure recovery function is forbidden, and the power failure recovery enabling register can also be configured by the processor through the parallel bus; the TimeOut indication register, TimeOut, may be read by the processor through a parallel bus cycle, with a value of 1 indicating a timer TimeOut.

After the short-time power failure recovery system is powered on, the processor configures a power failure recovery enabling register to be 1 through a parallel bus, so that the power failure recovery function is enabled. When the POWER _ FLAG is changed from high to low due to the reduction of the input voltage of the system, indicating that POWER failure starts, enabling a CPU _ INT by a POWER failure recovery controller at the moment, generating POWER failure early warning to a processor, and starting a timer; when the timer does not arrive and the POWER _ FLAG is changed from low to high, the input voltage is indicated to be recovered within the POWER-down holding capacity range of the POWER module, the POWER-down does not influence the system at this time, and the timer is stopped and reset; when the timer just arrives and the POWER _ FLAG is still low, the POWER-down time of the input voltage is indicated to reach the maximum POWER-down holding time of the POWER module, at the moment, the TimeOut is set to be 1, and a second interrupt signal CPU _ INT2 is sent out to prompt the processor to enter a POWER-down mode; when the timer is overtime and the POWER _ FLAG is changed from low to high, the system input voltage is indicated to be recovered after complete POWER failure, and the POWER failure controller outputs a reset signal RST _ OUT at the moment to enable the system to recover a normal working mode.

Based on the above description of the operating principle of the POWER down recovery controller, with reference to fig. 2, the POWER down recovery controller specifically includes the following four conditions in response to POWER _ FLAG:

early warning in power failure: enabling the CPU _ INT1 at the falling edge moment of the POWER _ FLAG, and starting a timer; sending a first interrupt signal to inform a processor of early warning;

recovery before timeout: judging TimeOut at the rising edge moment of POWER _ FLAG, if the TimeOut is 0, stopping the timing of the timer, and clearing the count value of the timer; the power module is recovered, the controller resets the internal timer of the power module, and the TimeOut is set to be 0;

time-out of the timer: enabling the CPU _ INT2 at the time when the timer reaches, and setting the TimeOut to be 1; the timer starts timing after sending out the first interrupt signal, and sends out the second interrupt signal after overtime so as to indicate the power-down time of the power supply module to exceed the short-time power-down retention capacity of the power supply module to the processor;

fourthly, recovering after overtime: at the rising edge time of POWER _ FLAG, TimeOut is determined, and RST _ OUT is enabled if TimeOut is 1.

The power failure recovery controller in this embodiment is implemented based on a programmable logic device, interacts with the processor through a parallel bus interface, and has an input that further includes a power failure indication signal and an output that further includes an interrupt output and a reset output. In the specific embodiment, the timer is arranged in the power failure recovery controller, the power failure behavior is identified by monitoring the power failure indication signal, the interrupt output and the reset output are generated, the power failure early warning and the reset indication are provided for system decision, the power interference resistance of the system in the complex power supply environment is obviously improved, and the robustness of the system is enhanced.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.