阅读说明：本技术 显示面板的驱动方法、显示装置及存储介质 (Display panel driving method, display device and storage medium ) 是由 上官修宁 王铁钢 姜海斌 郑峰 于 2021-08-06 设计创作，主要内容包括：本申请实施例提供了显示面板的驱动方法、显示装置及存储介质,显示面板包括在列方向上依次排列的多个扫描分区,每个扫描分区包括至少一行像素单元,获取扫描分区在第一刷新率下的第一扫描时长以及扫描分区在第二刷新率下的第二扫描时长；调整扫描分区在第一刷新率下的第一扫描时长,使得调整后的第一扫描时长与第二扫描时长相等；获取在调整第一扫描时长后的第一刷新率对应的目标数据电压值；在第一刷新率时,根据目标数据电压值控制每个扫描分区的像素单元发光。本申请实施例能够保证不同行的扫描分区的数据电压信号的漏电量相同,进而保证不同行的扫描分区的像素单元的发光亮度一致,提升显示面板的显示效果。(The embodiment of the application provides a driving method of a display panel, a display device and a storage medium, wherein the display panel comprises a plurality of scanning subareas which are sequentially arranged in a column direction, each scanning subarea comprises at least one row of pixel units, and a first scanning duration of the scanning subarea at a first refresh rate and a second scanning duration of the scanning subarea at a second refresh rate are obtained; adjusting the first scanning duration of the scanning subarea at the first refresh rate to ensure that the adjusted first scanning duration is equal to the second scanning duration; acquiring a target data voltage value corresponding to a first refresh rate after the first scanning duration is adjusted; and controlling the pixel unit of each scanning subarea to emit light according to the target data voltage value at the first refresh rate. The embodiment of the application can ensure that the leakage quantities of the data voltage signals of the scanning subareas of different rows are the same, further ensure that the luminous brightness of the pixel units of the scanning subareas of different rows is consistent, and improve the display effect of the display panel.)

1. A method for driving a display panel, wherein the display panel is capable of displaying at a first refresh rate and displaying at a second refresh rate, and the second refresh rate is greater than the first refresh rate, the display panel includes a plurality of scanning sub-areas sequentially arranged in a column direction, each of the scanning sub-areas includes at least one row of pixel units, and the method includes:

acquiring a first scanning duration of the scanning subarea at the first refresh rate and a second scanning duration of the scanning subarea at the second refresh rate;

adjusting a first scanning duration of the scanning partition at the first refresh rate to enable the adjusted first scanning duration to be equal to the second scanning duration;

acquiring a target data voltage value corresponding to the first refresh rate after the first scanning duration is adjusted;

and controlling the pixel unit of each scanning subarea to emit light according to the target data voltage value at the first refresh rate.

2. The method according to claim 1, wherein the adjusting the first scan duration of the scan partition at the first refresh rate such that the adjusted first scan duration is equal to the second scan duration comprises:

acquiring a third scanning duration of the plurality of scanning partitions at the first refresh rate;

determining a target scanning line number according to the third scanning duration and a second scanning duration of the scanning partition at the second refresh rate;

and adjusting the scanning line number of the first refresh rate to the target scanning line number.

3. The method of claim 1, wherein the pixel unit comprises a plurality of color sub-pixels;

acquiring a target data voltage value corresponding to the first refresh rate after the first scanning duration is adjusted, specifically including:

after the first scanning duration is adjusted, performing gamma debugging on the display panel at the first refresh rate to obtain sub-data voltage values corresponding to sub-pixels of each color under each gray scale.

4. The method according to claim 3, wherein said controlling the pixel cells of each of the scan partitions to emit light according to the target data voltage value at the first refresh rate specifically comprises:

and driving each color sub-pixel to emit light according to the sub-data voltage value corresponding to each color sub-pixel under the current gray scale at the first refresh rate.

5. The method of claim 1, wherein each of the pixel cells comprises a pixel drive circuit comprising:

a storage module for storing a data voltage signal;

the control end of the switch module is electrically connected with a target scanning signal line, and the first end of the switch module is electrically connected with the storage module;

the method further comprises the following steps:

and controlling the voltage value of the cut-off level output by the target scanning signal line to be adjusted from a first voltage value to a second voltage value, wherein the second voltage value is greater than the first voltage value.

6. The method of claim 5, wherein the switch module comprises:

a threshold compensation module, a control end of which is electrically connected to a first scanning signal line, a first end of which is electrically connected to a control end of a driving module in the pixel driving circuit, and a second end of which is electrically connected to the first end of the driving module, and is configured to be turned on in response to a turn-on level of the first scanning signal line in a threshold compensation stage, so that the data voltage signal performs threshold compensation on the control end of the driving module;

the target scanning signal line includes the first scanning signal line.

7. The method of claim 5 or 6, wherein the switch module comprises:

a first reset module, a control end of which is electrically connected to a second scanning signal line, a first end of which is electrically connected to a first end of the memory module, and a second end of which is electrically connected to a reference voltage signal line, and is configured to be turned on in response to a turn-on level of the second scanning signal line in an initialization stage, so as to initialize the first end of the memory module;

the target scanning signal line includes the second scanning signal line.

8. The method of claim 7, further comprising:

and controlling the voltage value of the reference voltage signal output by the reference voltage signal end to be adjusted from a third voltage value to a fourth voltage value, wherein the fourth voltage value is greater than the third voltage value.

9. A display device, characterized in that the display device comprises: processor, memory and computer program stored on the memory and executable on the processor, which computer program, when executed by the processor, carries out the steps of the method of driving a display panel according to any one of claims 1 to 8.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, realizes the steps of the driving method of the display panel according to any one of claims 1 to 8.

Technical Field

The present application relates to the field of display technologies, and in particular, to a driving method of a display panel, a display device, and a storage medium.

Background

The refresh rate may be understood as the frequency with which the electron beam repeatedly scans the image on the display screen. Generally, the higher the refresh rate, the better the displayed image (picture) stability. In order to meet the requirements of different display screens, display panels (such as Cathode Ray Tube (CRT) display panels, Liquid Crystal Display (LCD) panels, Light Emitting Diode (LED) display panels, and Organic Light Emitting Diode (OLED) display panels) usually have various refresh rates. For example, it is common to display at a refresh rate of 60Hz at the time of normal display, and display at a refresh rate of 90Hz or higher, for example, at the time of game screen display.

The inventor of the present application finds that when the refresh rate of the display panel is switched, for example, the refresh rate is switched from a low refresh rate to a high refresh rate or from the high refresh rate to the low refresh rate, a significant brightness difference occurs between different display areas of the display panel, and the display effect is poor.

Disclosure of Invention

The embodiment of the application provides a driving method of a display panel, a display device and a storage medium, which can weaken or even eliminate the brightness difference of different display areas of the display panel when the refresh rate is switched, and improve the display effect.

In a first aspect, an embodiment of the present application provides a method for driving a display panel, where the display panel is capable of displaying according to a first refresh rate and displaying according to a second refresh rate, and the second refresh rate is greater than the first refresh rate, the display panel includes a plurality of scanning partitions sequentially arranged in a column direction, each scanning partition includes at least one row of pixel units, and the method includes:

acquiring a first scanning duration of a scanning partition at a first refresh rate and a second scanning duration of the scanning partition at a second refresh rate;

adjusting the first scanning duration of the scanning subarea at the first refresh rate to ensure that the adjusted first scanning duration is equal to the second scanning duration;

acquiring a target data voltage value corresponding to a first refresh rate after the first scanning duration is adjusted;

and controlling the pixel unit of each scanning subarea to emit light according to the target data voltage value at the first refresh rate.

In a second aspect, an embodiment of the present application provides a display device, including: a processor, a memory and a computer program stored on the memory and executable on the processor, the computer program, when executed by the processor, implementing the steps of the driving method of the display panel as provided by the first aspect.

In a third aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the driving method for a display panel provided in the first aspect.

The display panel comprises a plurality of scanning subareas which are sequentially arranged in a column direction, each scanning subarea comprises at least one row of pixel units, and a first scanning duration of the scanning subarea at a first refresh rate and a second scanning duration of the scanning subarea at a second refresh rate are obtained; adjusting the first scanning duration of the scanning subarea at the first refresh rate to ensure that the adjusted first scanning duration is equal to the second scanning duration; acquiring a target data voltage value corresponding to a first refresh rate after the first scanning duration is adjusted; and controlling the pixel unit of each scanning subarea to emit light according to the target data voltage value at the first refresh rate. By adjusting the scanning duration of each scanning subarea at the first refresh rate to be the same as the scanning duration at the second refresh rate, the leakage time of the transistors of the scanning subareas of different rows can be ensured to be the same even under the condition of switching the refresh rates, so that the loss amount (leakage amount) of the data voltage signals of the scanning subareas of different rows is ensured to be the same, the consistency of the light-emitting brightness of the pixel units of the scanning subareas of different rows is ensured, and the display effect of the display panel is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram illustrating the effect of switching the refresh rate of the display panel from 90Hz to 60 Hz;

FIG. 2 is a schematic diagram of data voltage signal writing when the display panel is switched from a 60Hz refresh rate to a 90Hz refresh rate;

FIG. 3 is a schematic diagram of leakage of a pixel unit;

fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 5 is a schematic flowchart of another driving method for a display panel according to an embodiment of the present disclosure;

fig. 6 is a schematic flowchart illustrating a driving method of a display panel according to another embodiment of the present disclosure;

FIG. 7 is a schematic diagram illustrating data voltage signal writing when the display panel is switched from the first refresh rate to the second refresh rate;

fig. 8 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present disclosure;

FIG. 10 is a detailed circuit diagram of the pixel driving circuit shown in FIG. 9;

fig. 11 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present disclosure;

FIG. 12 is a detailed circuit diagram of the pixel driving circuit shown in FIG. 11;

fig. 13 is a flowchart illustrating a driving method of a display panel according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the prior art:

as mentioned above, when the display panel switches the refresh rate, for example, from a low refresh rate to a high refresh rate or from a high refresh rate to a low refresh rate, a significant brightness difference occurs between different display areas of the display panel, and the display effect is poor.

As shown in fig. 1, when the display panel is switched from the 90Hz refresh rate to the 60Hz refresh rate, the display panel may have a problem that the upper display area is darker and the lower display area is brighter in the first frame of the 60Hz refresh rate, i.e. the upper and lower display areas are not uniform in brightness.

In order to solve the above technical problems, the inventors of the present application have studied the causes of the above technical problems. The results of the research conducted by the inventors of the present application (i.e., the causes of the above-described technical problems) will be described below with reference to fig. 2 and 3.

As shown in fig. 2, when the display panel is switched from the 60Hz refresh rate to the 90Hz refresh rate, the time required for the row 1 pixel units of the display panel to write the data voltage signal from the i-th frame to the i + 1-th frame needs one frame time corresponding to a complete 60Hz refresh rate (n-1) × Δ t1), the time required for the row 2 pixel units to write the data voltage signal from the i-th frame to the i + 1-th frame needs (n-2) × Δ t1+ Δ t2, the time required for the row 3 pixel units to write the data voltage signal from the i-th frame to the i + 1-th frame needs (n-3) × Δ t1+2 × Δ t2, … …, and the time required for the row n (last row) pixel units to write the data voltage signal from the i-th frame to the i + 1-th frame needs one frame time corresponding to a complete 90Hz refresh rate (n-1) × t 2). Since the scanning duration Δ t1 of each row of pixel units corresponding to the 60Hz refresh rate is greater than the scanning duration Δ t2 of each row of pixel units corresponding to the 90Hz refresh rate, when the display panel is switched from the 60Hz refresh rate to the 90Hz refresh rate, the time required by the 1 st row of pixel units to write the data voltage signal from the i-th frame to the i + 1-th frame is the longest, the time required by the last row of pixel units to write the data voltage signal from the i-th frame to the i + 1-th frame is the shortest, and the time required by the 1 st row of pixel units to the last row of pixel units is gradually reduced. In contrast, when the display panel is switched from a 90Hz refresh rate to a 60Hz refresh rate, the time required from the 1 st row of pixel cells to the last row of pixel cells gradually increases.

As shown in fig. 3, for each row of pixel cells, the data voltage signal written in the i-th frame is stored in the memory module 11 during the period from the writing of the data voltage signal in the i-th frame to the writing of the data voltage signal in the i + 1-th frame (referred to as a data holding time). However, the transistor T1' connected to the memory module cannot be completely turned off (leakage current) due to the influence of the characteristics of the transistor itself, so that when the data retention time of the pixel units in different rows is different, the leakage time of the transistor in the pixel unit in different rows is also different, and the loss amount (leakage amount) of the data voltage signal of the pixel unit in different rows is different. Since the magnitude of the voltage value of the data voltage signal affects the light-emitting luminance of the pixel unit, when there is a difference in the amount of loss of the data voltage signal of the pixel units in different rows, there is also a difference in the light-emitting luminance of the pixel units in different rows. Among them, the difference in light-emitting luminance between the pixel units in the 1 st row and the pixel units in the last row is most obvious. Therefore, when the display panel switches the refresh rate, a significant brightness difference occurs between different display areas of the display panel.

In view of the above research by the inventors, the embodiments of the present application provide a driving method of a display panel, a display device, and a storage medium, which can solve the technical problems that when the refresh rate of the display panel is switched, the display effect is poor due to the obvious brightness difference between different display areas.

The following describes a driving method of a display panel provided in an embodiment of the present application.

As shown in fig. 4, in the embodiment of the present application, the display panel 10 includes a plurality of scanning sub-regions s '(grouping) arranged in sequence in the column direction, each scanning sub-region s' includes at least one row of pixel units 100, a row of pixel units 100 may include a plurality of pixel units 100, and each pixel unit 100 may further include a plurality of color sub-pixels, for example, each pixel unit 100 may include a red color sub-pixel (R sub-pixel), a green color sub-pixel (G sub-pixel), and a blue color sub-pixel (B sub-pixel). In other examples, the pixel unit 100 may include other color sub-pixels, such as a white color sub-pixel (W sub-pixel), in addition to the R sub-pixel, the G sub-pixel, and the B sub-pixel, which is not limited in this embodiment.

With continued reference to fig. 4, the display panel 10 may include n rows of pixel cells arranged in sequence in the column direction, which may be sequentially divided into M scan partitions, such that each scan partition s' may include one or more rows of pixel cells 100. Wherein M is less than or equal to n, and M and n are positive integers.

Fig. 5 is a flowchart illustrating a driving method of a display panel according to an embodiment of the present disclosure. As shown in fig. 5, the method may include the following steps S101, S102, S103, and S104.

S101, acquiring a first scanning duration of the scanning partition at a first refresh rate and a second scanning duration of the scanning partition at a second refresh rate.

In the embodiment of the present application, the second refresh rate is greater than the first refresh rate, and the first refresh rate and the second refresh rate may be any refresh rate, such as 60Hz, 90Hz, 120Hz, or 144Hz, as long as the second refresh rate is greater than the first refresh rate, such as 90Hz and 60 Hz.

Taking the first refresh rate as 60Hz and the second refresh rate as 90Hz as an example, in S101, the first scan duration of each scanning partition at the refresh rate of 60Hz is obtained as 1.8ms, and the second scan duration of each scanning partition at the refresh rate of 90Hz is obtained as 1.2ms, for example. It should be noted that 1.8ms and 1.2ms are only exemplary, and the first scanning duration and the second scanning duration may be other values, and the embodiment of the present application is not limited thereto.

S102, adjusting the first scanning duration of the scanning subarea at the first refresh rate, so that the adjusted first scanning duration is equal to the second scanning duration.

Illustratively, the first scanning duration of each scanning partition at the 60Hz refresh rate is adjusted from 1.8ms to 1.2ms, i.e. such that the adjusted first scanning duration is equal to the second scanning duration, for example.

In some embodiments, as shown in fig. 6, S102 may specifically include the following steps S1021, S1022, and S1023.

And S1021, acquiring a third scanning duration of the plurality of scanning partitions at the first refresh rate. The third scanning duration may be understood as a total duration of scanning all the scanning partitions at the first refresh rate, that is, a frame time corresponding to the first refresh rate. For example, the display panel includes 10 scanning zones, a first refresh rate (e.g., 60Hz refresh rate) corresponds to a frame time of, for example, 18ms, a first scanning duration of each scanning zone at the first refresh rate is, for example, 1.8ms, and a third scanning duration of the plurality of scanning zones at the first refresh rate is 18 ms.

And S1022, determining the target scanning line number according to the third scanning time length and the second scanning time length of the scanning partition at the second refresh rate.

Specifically, a quotient of the third scanning duration and the second scanning duration is calculated to obtain a target scanning line number. For example, the second scan duration of each scan partition at the second refresh rate (e.g., 90Hz refresh rate) is, for example, 1.2ms, the third scan duration is 18ms, 18 ÷ 1.2 ═ 15, and then the target number of scan lines is 15. It was mentioned above that the display panel for example comprises 10 scanning sections, which 10 scanning sections may be referred to as real scanning sections, which 10 scanning sections are, as the name implies, actually present. And of the 15 calculated scan partitions, there are 5 virtual scan partitions (scan partitions that do not exist in reality) in addition to 10 real scan partitions. After scanning 10 real scanning partitions, wait for the scanning duration of 5 virtual scanning partitions to enter the next frame. Therefore, although the scanning duration of each scanning partition at the first refresh rate is changed, the frame time corresponding to the first refresh rate is still unchanged (for example, 18 ms).

S1023, adjusting the scanning line number of the first refresh rate to the target scanning line number.

After the target scan line count is calculated, in S1023, the scan line count of the first refresh rate is adjusted to the target scan line count.

S103, acquiring a target data voltage value corresponding to the first refresh rate after the first scanning duration is adjusted.

After the first scanning duration at the first refresh rate is adjusted, in order to ensure the display effect, the target data voltage value corresponding to the first refresh rate after the first scanning duration is adjusted generally needs to be determined again. It should be noted that the target data voltage value may include a plurality of sub data voltage values, where each sub data voltage value may correspond to a sub pixel of one of the colors in one gray scale. For example, when the display panel includes 0 to 255 grayscales and the pixel includes a red color sub-pixel, a green color sub-pixel, and a blue color sub-pixel, the target data voltage value may include 256 × 3 to 768 sub-data voltage values.

In some embodiments, the target data voltage value may be obtained by gamma correction/gamma debugging. Specifically, N gray levels can be selected from 0 to 255 gray levels as debugging binding points, sub-data voltage values corresponding to a red color sub-pixel, a green color sub-pixel and a blue color sub-pixel of each debugging binding point are obtained through gamma correction, and N is an integer larger than 0 and smaller than 255. For the gray scales of 0-255 except for N debugging binding points, the sub-data voltage values corresponding to the red color sub-pixel, the green color sub-pixel and the blue color sub-pixel under each gray scale can be calculated through linear interpolation.

Table 1 schematically shows sub-data voltage values corresponding to each of the red, green, and blue color sub-pixels of each debug bind for the first and second refresh rates when N is 14.

TABLE 1

As shown in table 1, for example, at the 1 gray level at the first refresh rate, the sub data voltage value corresponding to the red color R sub-pixel is 6.4022V (volt), the sub data voltage value corresponding to the green color G sub-pixel is 6.38989V, and the sub data voltage value corresponding to the blue color B sub-pixel is 6.33247V. At the 255 gray scale of the first refresh rate, the sub-data voltage value corresponding to the red color R sub-pixel is 3.71567V, the sub-data voltage value corresponding to the green color G sub-pixel is 3.75771V, and the sub-data voltage value corresponding to the blue color B sub-pixel is 3.36807V.

And S104, controlling the pixel unit of each scanning subarea to emit light according to the target data voltage value at the first refresh rate.

After adjusting the first scanning duration of each scanning partition at the first refresh rate, when the display panel displays according to the first refresh rate, the pixel unit of each scanning partition can be controlled to emit light according to the target data voltage value.

Specifically, in S104, at the first refresh rate, the pixel unit of each scanning partition is controlled to emit light according to the sub-data voltage values corresponding to the red, green, and blue sub-pixels at the current gray level. For example, when the current gray scale is 23 gray scales, the red sub-pixels in each scanning sub-area are controlled to emit light according to the sub-data voltage value (e.g., 5.6998V) corresponding to the red sub-pixels at 23 gray scales, the green sub-pixels in each scanning sub-area are controlled to emit light according to the sub-data voltage value (e.g., 5.80645V) corresponding to the green sub-pixels at 23 gray scales, and the blue sub-pixels in each scanning sub-area are controlled to emit light according to the sub-data voltage value (e.g., 5.5501V) corresponding to the blue sub-pixels at 23 gray scales.

As shown in fig. 7, by adjusting the first scan duration of each scan partition at the first refresh rate from Δ T1 to Δ T2, the time (data retention time) from the i-th frame writing data voltage signal to the i + 1-th frame writing data voltage signal of the scan partitions of different rows can be made equal, for example, all (n-1) × Δ T2+ T, T being, for example, the total scan duration of the virtual scan partition. Because the data retention time of the scanning subareas of different rows is the same, namely the leakage time of the transistors of the pixel units of different rows is the same, the loss (leakage) of the data voltage signals of the pixel units of different rows is the same, the consistency of the light-emitting brightness of the pixel units of the scanning subareas of different rows is further ensured, and the display effect of the display panel is improved.

As mentioned above, the main reasons for the differences in the light-emitting luminance of the pixel units in different rows are: the transistors connected to the memory module have leakage currents, and the leakage currents affect the leakage time to cause different loss amounts (leakage amounts) of the data voltage signals of the pixel units in different rows. In some embodiments, the gate voltage of the transistor may be increased to avoid the leakage current of the transistor, so that the data voltage signals of the pixel units in different rows have the same loss amount (e.g., are all 0). Therefore, the consistency of the brightness of the pixel units of the scanning subareas of different rows can be further ensured, and the display effect of the display panel is improved.

As shown in fig. 8, in some embodiments, each pixel cell 100 includes a pixel driving circuit, which may include:

the storage module 11, the storage module 11 is used for storing the data voltage signal;

and a control end of the switch module 12 is electrically connected with the target scanning signal line Sn, and a first end of the switch module 12 is electrically connected with the storage module 11.

The driving method of the display panel provided by the embodiment of the application can further include:

the voltage value of the cut-off level output by the control target scanning signal line Sn is adjusted from the first voltage value to a second voltage value, and the second voltage value is larger than the first voltage value.

The voltage of the control terminal of the switch module 12 is increased to avoid the leakage current of the switch module 12, so that the loss amounts of the data voltage signals of the pixel units in different rows are the same (for example, all are 0). Therefore, the consistency of the brightness of the pixel units of the scanning subareas of different rows can be further ensured, and the display effect of the display panel is improved.

As shown in fig. 9, in some embodiments, the switch module 12 may include:

the threshold compensation module 121, a control terminal of the threshold compensation module 121 is electrically connected to the first scan signal line S1, a first terminal of the threshold compensation module 121 is electrically connected to a control terminal of the driving module 13 in the pixel driving circuit, and a second terminal of the threshold compensation module 121 is electrically connected to the first terminal of the driving module 13 and the first terminal of the memory module 11, and is configured to be turned on in response to a turn-on level of the first scan signal line S1 during a threshold compensation phase, so that the data voltage signal performs threshold compensation on the control terminal of the driving module 13.

The target scan signal line Sn may include a first scan signal line S1. That is, the voltage value of the cut-off level output by the first scanning signal line S1 can be controlled to be adjusted from the first voltage value to the second voltage value, so as to avoid leakage current of the threshold compensation module 121, further ensure that the luminance of the pixel units in the scanning partitions of different rows is consistent, and improve the display effect of the display panel.

Specifically, as shown in fig. 10, the driving module 13 may include a first transistor T1 for driving the light emitting element to emit light; the memory module 11 may include a first capacitor C1 for storing the data voltage signal; the threshold compensation module 121 may include a second transistor T2, a control electrode of the second transistor T2 being electrically connected to the first scan signal line S1, a first electrode of the second transistor T2 being electrically connected to the control electrode of the first transistor T1, and a second electrode of the second transistor T2 being electrically connected to the first electrode of the first transistor T1, for being turned on in response to a turn-on level of the first scan signal line S1 during a threshold compensation phase, so that the data voltage signal threshold-compensates the control electrode of the first transistor T1.

It should be noted that, in order to improve the voltage endurance of the transistor and keep the circuit stable, the threshold compensation module 121 may adopt a double-gate transistor, that is, the threshold compensation module 121 may include at least two second transistors T2, and at least two second transistors T2 are arranged in series, so as to improve the voltage endurance of the transistor and keep the circuit stable.

Note that the transistors in the embodiments of the present application are described using P-type transistors as examples, but the transistors are not limited to P-type transistors, and may be replaced with N-type transistors. For a P-type transistor, the on level is low and the off level is high. That is, when the control terminal of the P-type transistor is at a low level, the first pole and the second pole of the P-type transistor are turned on, and when the control terminal of the P-type transistor is at a high level, the first pole and the second pole of the P-type transistor are turned off. In a specific implementation, the gate of each transistor is used as its control electrode, and according to the signal of the gate of each transistor and its type, the first electrode of each transistor can be used as its source, the second electrode as its drain, or the first electrode of each transistor can be used as its drain, and the second electrode as its source, which are not distinguished herein.

In the embodiments of the present application, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected to each other via one or more other components.

As shown in fig. 11, in some embodiments, the switch module 12 may include:

the first reset module 122, a control terminal of the first reset module 122 is electrically connected to the second scan signal line S2, a first terminal of the first reset module 122 is electrically connected to the first terminal of the memory module 11, and a second terminal of the first reset module 122 is electrically connected to the reference voltage signal terminal Vref, and is configured to be turned on in response to a turn-on level of the second scan signal line S2 in an initialization phase, so as to initialize the first terminal of the memory module 11 (i.e., the control terminal of the driving module 13).

The target scan signal line Sn may include a second scan signal line S2. That is, the voltage value of the cut-off level output by the second scan signal line S2 can be controlled to be adjusted from the first voltage value to the second voltage value, so as to avoid leakage current of the first reset module 122, further ensure that the luminance of the pixel units of the scan partitions in different rows is consistent, and improve the display effect of the display panel.

Specifically, as shown in fig. 12, the first reset module 122 may include a third transistor T3, a control electrode of the third transistor T3 being electrically connected to the second scan signal line S2, a first electrode of the third transistor T3 being electrically connected to the first capacitor C1, and a second electrode of the third transistor T3 being electrically connected to the reference voltage signal terminal Vref, and configured to be turned on in response to a turn-on level of the second scan signal line S2 in an initialization stage to initialize the control electrode of the first transistor T1.

In order to further avoid the leakage current of the first reset module 122, in some embodiments, the driving method of the display panel provided by the embodiment of the present application may further include: and controlling the voltage value of the reference voltage signal output by the reference voltage signal end to be adjusted to a fourth voltage value from the third voltage value, wherein the fourth voltage value is greater than the third voltage value. By improving the voltage value of the reference voltage signal output by the reference voltage signal end, the voltage difference between the potential of the second end of the first reset module and the potential of the first end of the first reset module can be reduced, and further the leakage current of the storage module to the reference voltage signal end through the first reset module is reduced or even eliminated. Further, the reference voltage signal output by the reference voltage signal terminal can be adjusted from a negative voltage to a positive voltage, so that the potential of the second terminal of the first reset module is the same as or close to the potential of the first terminal of the first reset module, and the leakage current of the first reset module is reduced or even eliminated to a greater extent.

In order to improve the voltage endurance of the transistors and keep the circuit stable, the first reset module 122 may also adopt double-gate transistors, that is, the first reset module 122 may include at least two third transistors T3, and at least two third transistors T3 are arranged in series, so as to improve the voltage endurance of the transistors and keep the circuit stable.

In some embodiments, the data voltage values of the color sub-pixels of the scanning partitions in different rows may also be compensated, and then the corresponding color sub-pixels in each scanning partition are controlled to emit light according to the compensated data voltage values of the color sub-pixels in each scanning partition, so that the brightness of each scanning partition is further ensured to be consistent when the refresh rate of the display panel is switched, and the display effect of the display panel is further improved.

Specifically, as shown in fig. 13, the driving method of the display panel provided in the embodiment of the present application may further include steps S105, S106, and S107.

And S105, acquiring the position information of each scanning partition in the column direction under the condition that the display panel is detected to be switched from the third refresh rate to the fourth refresh rate.

It should be noted that, in the embodiment of the present application, the third refresh rate and the fourth refresh rate may be any refresh rate, such as 60Hz, 90Hz, 120Hz, or 144Hz, as long as the third refresh rate and the fourth refresh rate are ensured to be different. The "third" of the third refresh rate and the "fourth" of the fourth refresh rate are only for convenience of distinguishing from the first refresh rate and the second refresh rate described above, and actually, the third refresh rate may be the first refresh rate or the second refresh rate. Correspondingly, the fourth refresh rate may be the second refresh rate or the first refresh rate.

In this embodiment of the application, the position information of each scanning partition in the column direction may be preset, for example, a partition number of each scanning partition may be preset, and the position information of each scanning partition in the column direction is represented by using the partition number of each scanning partition. The partition number of each scan partition may be understood as an arrangement number of each scan partition in the column direction. For example, the display panel includes 100 scanning sections, and then the section numbers of the 100 scanning sections may be 1, 2, 3, 4, 5, … …, 98, 99, and 100, respectively. Of course, other information may be utilized to characterize the position information of each scanning partition in the column direction, and the application is not limited thereto. After setting the position information of each scan division in the column direction, the set position information of each scan division in the column direction may be stored in a storage medium. In the case where it is detected that the display panel is switched from the third refresh rate to the fourth refresh rate, the positional information of each scanning section in the column direction may be retrieved from the storage medium.

And S106, determining a data voltage value corresponding to each color sub-pixel in each scanning partition according to the position information of each scanning partition, the predetermined compensation coefficient of each color sub-pixel and the predetermined reference data voltage value of each color sub-pixel.

In an example of the embodiment of the present application, the compensation coefficients of the sub-pixels with different colors may be different, for example, the compensation coefficient of the R sub-pixel may be k1, the compensation coefficient of the G sub-pixel may be k2, and the compensation coefficient of the B sub-pixel may be k3, and k1 ≠ k2 ≠ k 3. In another example, the compensation coefficients of the sub-pixels with different colors may also be the same, that is, k1 ═ k2 ═ k3, which may be flexibly adjusted according to the actual situation, and this is not limited in this embodiment of the application. Similarly, the reference data voltage values of the sub-pixels with different colors may be different or the same, which is not limited in this embodiment of the application.

In the embodiment of the present application, the compensation coefficient of each color sub-pixel may be predetermined. In some embodiments, for any one color sub-pixel (i-th color sub-pixel), the compensation coefficient of the i-th color sub-pixel may be a compensation coefficient between data voltage values of the i-th color sub-pixel when the first scan partition and the last scan partition reach the same luminance value in the column direction. For example, the luminance value of the last scan division is 550nit, the luminance value of the first scan division before compensation is 500nit, the data voltage value of the corresponding ith color sub-pixel is Vdata1, and the data voltage value of the corresponding ith color sub-pixel when the first scan division reaches 550nit is Vdata 2. Then, the compensation factor may be the ratio of Vdata2 to Vdata1, i.e., Vdata2/Vdata 1.

It is mentioned above that when the display panel is switched from the 60Hz refresh rate to the 90Hz refresh rate, the pixel cells in row 1 need a complete frame time corresponding to the 60Hz refresh rate from the i-th frame writing data voltage signal to the i + 1-th frame writing data voltage signal, and the pixel cells in row n (last row) need a complete frame time corresponding to the 90Hz refresh rate from the i-th frame writing data voltage signal to the i + 1-th frame writing data voltage signal. It can be understood that when the display panel is switched from a 60Hz refresh rate to a 90Hz refresh rate, the 1 st row of pixel cells are normally illuminated at the 60Hz refresh rate, and the last row of pixel cells are normally illuminated at the 90Hz refresh rate. That is, the light-emitting luminance of the line 1 pixel cell is equivalent to the light-emitting luminance of the display panel at the refresh rate of 60Hz, and the light-emitting luminance of the last line pixel cell is equivalent to the light-emitting luminance of the display panel at the refresh rate of 90 Hz. Similarly, the light-emitting luminance of the first scanning sub-area can be regarded as the light-emitting luminance of the display panel at the third refresh rate, and the light-emitting luminance of the last scanning sub-area can be regarded as the light-emitting luminance of the display panel at the fourth refresh rate.

Therefore, the light-emitting brightness of the first scanning subarea and the light-emitting brightness of the last scanning subarea can be determined according to the light-emitting brightness of the display panel at the third refresh rate and the light-emitting brightness of the display panel at the fourth refresh rate. Then, in order to eliminate the brightness difference between the first scanning sub-area and the last scanning sub-area, for any color sub-pixel (i-th color sub-pixel), a compensation coefficient between the data voltage values of the i-th color sub-pixel when the first scanning sub-area and the last scanning sub-area reach the same brightness value can be determined according to the first data voltage value of the i-th color sub-pixel when the test display panel reaches the first brightness value at the first test refresh rate and the second data voltage value of the i-th color sub-pixel when the test display panel reaches the second brightness value at the first test refresh rate.

The second brightness value is the brightness value of the test display panel under the second test refresh rate; one of the first test refresh rate and the second test refresh rate is a third refresh rate and the other is a fourth refresh rate. That is, the compensation coefficient of each color sub-pixel may be determined by adjusting the data voltage value of each color sub-pixel at the fourth refresh rate based on the luminance of the test display panel at the third refresh rate (keeping the luminance of the test display panel at the third refresh rate unchanged) so that the luminance of the test display panel at the fourth refresh rate is consistent with the luminance at the third refresh rate. Of course, the compensation coefficient of each color sub-pixel may also be determined by adjusting the data voltage value of each color sub-pixel at the third refresh rate based on the brightness of the test display panel at the fourth refresh rate (keeping the brightness of the test display panel at the fourth refresh rate unchanged), so that the brightness of the test display panel at the third refresh rate is consistent with the brightness of the test display panel at the fourth refresh rate.

In some embodiments, in order to better eliminate the brightness difference between different display areas of the display panel 10, the test display panel may be the display panel 10, or may also be another display panel of the same type as the display panel 10 or even of the same production batch, so as to ensure that there is no difference or a small difference between the test display panel and the display panel 10, thereby ensuring that the compensation coefficient of each color sub-pixel determined according to the test display panel is also suitable for the display panel 10, and further ensuring that the finally adjusted display panel 10 has a better display effect.

In some specific examples, in determining the compensation coefficient of the ith color sub-pixel, a second data voltage value of the ith color sub-pixel when the test display panel reaches the second brightness value at the third refresh rate may be calculated with a brightness value of the test display panel at the fourth refresh rate as a second brightness value (reference). Taking the third refresh rate as 60Hz and the fourth refresh rate as 90Hz as an example, the brightness value of the test display panel at 60Hz is 500nit, and the brightness value of the test display panel at 90Hz is 550 nit. In practical applications, the luminance value of the test display panel at 90Hz may be used as the reference luminance value (the luminance of the test display panel at 90Hz is kept unchanged), and then the data voltage value (i.e. the second data voltage value) of the ith color sub-pixel when the test display panel reaches the reference luminance value 550nit at 60Hz is calculated. Then, the ratio of the second data voltage value to the first data voltage value (for example, the data voltage value of the ith color sub-pixel when the luminance value of the test display panel is 500nit at 60 Hz) is calculated, so as to obtain the compensation coefficient of the ith color sub-pixel. A

For example, the data voltage value (first data voltage value) of the ith color sub-pixel when the luminance value of the test display panel is 500nit at 60Hz is Vdata1 ', the data voltage value (second data voltage value) of the ith color sub-pixel when the test display panel reaches the reference luminance value 550nit at 60Hz is Vdata 2', and the compensation coefficient of the ith color sub-pixel is Vdata2 '/Vdata 1'.

In other specific examples, when determining the compensation coefficient of the ith color sub-pixel, the second data voltage value of the ith color sub-pixel when the test display panel reaches the second brightness value at the fourth refresh rate may be calculated with the brightness value of the test display panel at the third refresh rate as the second brightness value (reference). Taking the third refresh rate as 60Hz and the fourth refresh rate as 90Hz as an example, the brightness value of the test display panel at 60Hz is 500nit, and the brightness value of the test display panel at 90Hz is 550 nit. In practical applications, the luminance value of the test display panel at 60Hz may be used as a reference luminance value (the luminance of the test display panel at 60Hz is kept unchanged), and then the data voltage value (i.e. the second data voltage value) of the ith color sub-pixel when the test display panel reaches the reference luminance value of 500nit at 90Hz is calculated. Then, the ratio of the second data voltage value to the first data voltage value (for example, the data voltage value of the ith color sub-pixel when the luminance value of the test display panel is 550nit at 90 Hz) is calculated, so as to obtain the compensation coefficient of the ith color sub-pixel. .

For example, the data voltage value (first data voltage value) of the ith color sub-pixel when the luminance value of the test display panel is 550nit at 90Hz is Vdata1 ', the data voltage value (second data voltage value) of the ith color sub-pixel when the test display panel reaches the reference luminance value of 500nit at 90Hz is Vdata 2', and the compensation coefficient of the ith color sub-pixel is Vdata2 '/Vdata 1'.

In S106, a data voltage value corresponding to each color sub-pixel in each scanning partition may be determined according to the position information of each scanning partition, a predetermined compensation coefficient of each color sub-pixel, and a predetermined reference data voltage value of each color sub-pixel.

As described previously, the position information of each scanning section in the column direction may include the section number, e.g., 1, 2, 3, 4, … …, n, of each scanning section.

As an example, S106 may specifically include:

and determining the data voltage value corresponding to each color sub-pixel in each scanning partition according to the partition serial number of each scanning partition, the partition number of the plurality of scanning partitions, the compensation coefficient of each color sub-pixel and the reference data voltage value of each color sub-pixel.

The number of the partitions of the plurality of scanning partitions may be understood as the number of scanning partitions in the display panel, for example, if the display panel includes M scanning partitions, the number of the partitions of the plurality of scanning partitions is M, and M is a positive integer.

Specifically, for the ith color sub-pixel, the first ratio, the product of the compensation coefficient of the ith color sub-pixel and the reference data voltage value of the ith color sub-pixel may be calculated to obtain the corresponding data voltage value of the ith color sub-pixel in each scanning partition. The first ratio may include a ratio of a partition number of each scanning partition to the number of partitions of the plurality of scanning partitions.

The expression for determining the data voltage value corresponding to the ith color sub-pixel in each scanning partition is as follows:

Vdata(x)＝x/M*k*Vdata0 (1)

where x denotes a partition number of each scanning partition, Vdata (x) denotes a data voltage value corresponding to the ith color sub-pixel in each scanning partition, k denotes a compensation coefficient of the ith color sub-pixel, and Vdata0 denotes a reference data voltage value of the ith color sub-pixel, that is, the first data voltage value described above.

Illustratively, when the display panel is switched from a higher refresh rate to a lower refresh rate, i.e. the third refresh rate is greater than the fourth refresh rate, e.g. the 90Hz refresh rate is switched to a 60Hz refresh rate, the data voltage value corresponding to the ith color sub-pixel in each scanning partition may be determined by the above expression (1). It is easily understood that when the display panel includes R sub-pixels, G sub-pixels, and B sub-pixels, the data voltage value corresponding to the R sub-pixels in each scanning partition, the data voltage value corresponding to the G sub-pixels in each scanning partition, and the data voltage value corresponding to the B sub-pixels in each scanning partition can be determined through the above steps and expression (1).

As another example, S106 may specifically include:

and determining the data voltage value corresponding to each color sub-pixel in each scanning partition according to the reciprocal of the partition serial number of each scanning partition, the compensation coefficient of each color sub-pixel and the reference data voltage value of each color sub-pixel.

The expression for determining the data voltage value for each color sub-pixel in each scan partition is as follows:

Vdata(x)＝1/x*k*Vdata0 (2)

where x denotes a partition number of each scanning partition, Vdata (x) denotes a data voltage value corresponding to the ith color sub-pixel in each scanning partition, k denotes a compensation coefficient of the ith color sub-pixel, and Vdata0 denotes a reference data voltage value of the ith color sub-pixel, that is, the first data voltage value described above.

Illustratively, when the display panel is switched from a lower refresh rate to a higher refresh rate, i.e. the third refresh rate is smaller than the fourth refresh rate, e.g. the 60Hz refresh rate is switched to a 90Hz refresh rate, the data voltage value corresponding to each color sub-pixel in each scanning partition may be determined by expression (2) above. It is easily understood that when the display panel includes R sub-pixels, G sub-pixels, and B sub-pixels, the data voltage value corresponding to the R sub-pixels in each scanning section, the data voltage value corresponding to the G sub-pixels in each scanning section, and the data voltage value corresponding to the B sub-pixels in each scanning section can be determined through the above steps and expression (2).

And S107, controlling the sub-pixels with the corresponding colors in each scanning partition to emit light according to the data voltage values corresponding to the sub-pixels with the colors in each scanning partition.

Specifically, for example, a driving integrated circuit (abbreviated as a driving IC) may transmit a data voltage value corresponding to each color sub-pixel in each scanning partition to a corresponding color sub-pixel in each scanning partition through a data signal line corresponding to each color sub-pixel in each scanning partition, for example, when a display panel includes R sub-pixels, G sub-pixels, and B sub-pixels, a data voltage value corresponding to R sub-pixels in each scanning partition may be transmitted to R sub-pixels in each scanning partition, a data voltage value corresponding to G sub-pixels in each scanning partition may be transmitted to G sub-pixels in each scanning partition, and a data voltage value corresponding to B sub-pixels in each scanning partition may be transmitted to B sub-pixels in each scanning partition. Therefore, the brightness of different scanning subareas is consistent, and the display effect of the display panel is improved.

The driving method of the display panel according to the embodiment of the present application, according to a first data voltage value of each color sub-pixel when the test display panel reaches a first brightness value at a first test refresh rate and a second data voltage value of each color sub-pixel when the test display panel reaches a second brightness value at the first test refresh rate, where the second brightness value is a brightness value of the test display panel at a second test refresh rate, obtains a compensation coefficient between data voltage values of each color sub-pixel when a first scanning sub-region and a last scanning sub-region in a column direction reach a same brightness value, then determines a data voltage value corresponding to each color sub-pixel in each scanning sub-region according to position information of different scanning sub-regions in the column direction, the compensation coefficient of each color sub-pixel, and a reference data voltage value of each color sub-pixel, and then determines a data voltage value corresponding to each color sub-pixel in each scanning sub-region according to the data voltage value corresponding to each color sub-pixel in each scanning sub-region, and the corresponding color sub-pixels in each scanning subarea are controlled to emit light, so that the brightness of each scanning subarea is consistent when the display panel switches the refresh rate, and the display effect of the display panel is improved.

Based on the driving method of the display panel provided by the above embodiment, correspondingly, the application further provides a specific implementation manner of the display device. Please see the examples below.

Fig. 14 shows a hardware structure diagram of a display device provided in an embodiment of the present application.

The electronic device may include a processor 1401 and a memory 1402 storing computer program instructions.

Specifically, the processor 1401 may include a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits configured to implement the embodiments of the present Application.

Memory 1402 may include mass storage for data or instructions. By way of example, and not limitation, memory 1402 may include a Hard Disk Drive (HDD), a floppy Disk Drive, flash memory, an optical Disk, a magneto-optical Disk, tape, or a Universal Serial Bus (USB) Drive or a combination of two or more of these. In one example, memory 1402 may include removable or non-removable (or fixed) media, or memory 1402 may be non-volatile solid-state memory. The memory 1402 may be internal or external to the integrated gateway disaster recovery device.

In one example, the Memory 1402 may be a Read Only Memory (ROM). In one example, the ROM may be mask programmed ROM, programmable ROM (prom), erasable prom (eprom), electrically erasable prom (eeprom), electrically rewritable ROM (earom), or flash memory, or a combination of two or more of these.

Memory 1402 may include Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software comprising computer-executable instructions and when the software is executed (e.g., by one or more processors), it is operable to perform operations described with reference to the methods according to an aspect of the application.

The processor 1401 reads and executes the computer program instructions stored in the memory 1402 to implement the method/steps in the above embodiments, and achieves the corresponding technical effect achieved by executing the method/steps in any of the examples shown in the above embodiments, and therefore, for brevity, no further description is provided here.

In one example, the electronic device can also include a communication interface 1403 and a bus 1410. As shown in fig. 14, the processor 1401, the memory 1402, and the communication interface 1403 are connected via a bus 1410 to communicate with each other.

The communication interface 1403 is mainly used for implementing communication between modules, apparatuses, units and/or devices in this embodiment of the present application.

The bus 1410 includes hardware, software, or both to couple the components of the electronic device to one another. By way of example, and not limitation, a Bus may include an Accelerated Graphics Port (AGP) or other Graphics Bus, an Enhanced Industry Standard Architecture (EISA) Bus, a Front-Side Bus (Front Side Bus, FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) Bus, an infiniband interconnect, a Low Pin Count (LPC) Bus, a memory Bus, a Micro Channel Architecture (MCA) Bus, a Peripheral Component Interconnect (PCI) Bus, a PCI-Express (PCI-X) Bus, a Serial Advanced Technology Attachment (SATA) Bus, a video electronics standards association local (VLB) Bus, or other suitable Bus or a combination of two or more of these. Bus 1410 may include one or more buses, where appropriate. Although specific buses are described and shown in the embodiments of the application, any suitable buses or interconnects are contemplated by the application.

In addition, in combination with the driving method of the display panel in the above embodiments, the embodiments of the present application may be implemented by providing a computer-readable storage medium. The computer readable storage medium having stored thereon computer program instructions; the computer program instructions, when executed by a processor, implement a method of driving a display panel as in any of the above embodiments. Examples of computer readable storage media include non-transitory computer readable storage media such as electronic circuits, semiconductor memory devices, ROMs, random access memories, flash memories, erasable ROMs (eroms), floppy disks, CD-ROMs, optical disks, and hard disks.

It is to be understood that the present application is not limited to the particular arrangements and instrumentality described above and shown in the attached drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions or change the order between the steps after comprehending the spirit of the present application.

The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic Circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.

It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.

Aspects of the present application are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware for performing the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.