阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 罗诺纬 吴华标 于 2020-06-05 设计创作，主要内容包括：本发明公开一种半导体装置及其制造方法,其中该半导体装置的制造方法包括：提供衬底,所述衬底包括第一区与第二区；在所述衬底的所述第一区与所述第二区的第一表面上形成材料层,并在所述衬底的所述第二区的所述第一表面上形成对准标记；自所述衬底的第二表面将杂原子引入所述第二区的所述衬底中；以及使所述杂原子与所述衬底反应,以在所述第二区的所述衬底中形成与所述对准标记重叠的介电层。通过本发明实施例的方法可以提升对准的精确度。(The invention discloses a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a substrate, wherein the substrate comprises a first area and a second area; forming a material layer on a first surface of the first and second regions of the substrate and forming an alignment mark on the first surface of the second region of the substrate; introducing heteroatoms into the substrate of the second region from a second surface of the substrate; and reacting the heteroatoms with the substrate to form a dielectric layer in the substrate of the second region overlapping the alignment mark. The method of the embodiment of the invention can improve the alignment accuracy.)

1. A method for manufacturing a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a first area and a second area;

forming an alignment mark in the substrate of the second region;

forming a material layer on a first surface of the first and second regions of the substrate;

introducing heteroatoms into the substrate of the second region from a second surface of the substrate; and

reacting the heteroatoms with the substrate to form a dielectric layer in the substrate of the second region overlapping the alignment mark.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the method for introducing a heteroatom into the substrate in the second region from the second surface of the substrate comprises:

forming a mask layer on the second surface of the substrate;

carrying out unfilled corner alignment on the substrate;

patterning the mask layer to form openings in the mask layer in the second region, the openings corresponding to the alignment marks;

carrying out an ion implantation process; and

the mask layer is removed.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising performing a thinning process on the substrate before the introduction of the hetero atoms into the substrate from the second surface of the substrate in the second region.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the heteroatom comprises oxygen, nitrogen, or a combination thereof.

5. The method for manufacturing a semiconductor device according to claim 1, wherein an n value of a refractive index of the dielectric layer is less than 1, 5.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the reacting the heteroatom with the substrate comprises performing a thermal process or an annealing process.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the dielectric layer is in contact with the alignment mark.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the dielectric layer and the alignment mark are separated by a part of the substrate.

9. A method for manufacturing a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a first area and a second area;

introducing heteroatoms into the substrate of the second region from a first surface of the substrate;

forming a material layer on the first surface of the substrate in the first and second regions and forming an alignment mark in the substrate in the second region; and

reacting the heteroatoms with the substrate to form a dielectric layer in the substrate of the second region overlapping the alignment mark.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the method for introducing a heteroatom into the substrate of the second region from the first surface of the substrate comprises:

forming a mask layer on the first surface of the substrate;

carrying out unfilled corner alignment on the substrate;

patterning the mask layer to form openings in the mask layer in the second region, the openings corresponding to the alignment marks;

carrying out an ion implantation process; and

the mask layer is removed.

11. The method of manufacturing a semiconductor device according to claim 9, wherein the heteroatom comprises oxygen, nitrogen, or a combination thereof.

12. The method of claim 9, wherein the reacting the heteroatom with the substrate comprises performing a thermal process or an annealing process.

13. The method for manufacturing a semiconductor device according to claim 9, wherein the dielectric layer is in contact with the alignment mark.

14. The method for manufacturing a semiconductor device according to claim 9, wherein the dielectric layer and the alignment mark are separated by a part of the substrate.

15. A semiconductor device, comprising:

a substrate including a first region and a second region;

an isolation structure in the substrate of the second region extending from a first surface of the substrate to a second surface of the substrate;

an alignment mark in the substrate of the second region, extending from the first surface of the substrate to the second surface of the substrate and at the same level as the isolation structure; and

a dielectric layer in the substrate of the second region and overlapping the alignment mark,

wherein a thickness of the substrate between the first surface to the second surface of the substrate in the second region is less than a thickness of the substrate between the first surface to the second surface of the substrate in the first region.

16. The semiconductor device of claim 15, wherein the first region and the second region are both in a chip region.

17. The semiconductor device according to claim 15, wherein an n value of a refractive index of the dielectric layer is less than 1, 5.

18. The semiconductor device of claim 15, wherein the dielectric layer comprises silicon oxide, silicon oxynitride, or a combination thereof.

19. The semiconductor device of claim 15, wherein the dielectric layer is in contact with the alignment mark or is separated by the substrate.

20. The semiconductor device of claim 15, wherein an area of the dielectric layer is larger than an area of the alignment mark.

Technical Field

The present invention relates to integrated circuits and methods of fabricating the same, and more particularly, to semiconductor devices and methods of fabricating the same.

Background

The accuracy of alignment becomes increasingly important in semiconductor processing, particularly after continued device miniaturization. When fabricating components on the back side, Through Silicon Alignment (TSA) capability is required to align the photomask with the Alignment mark. However, if a thicker thinned substrate is desired, the transparency of the thicker silicon substrate is too low to be aligned, and thus cannot have sufficient through-silicon alignment capability.

Disclosure of Invention

The present invention is directed to a semiconductor device and a method for manufacturing the same, which can improve the alignment capability of the back side of the wafer.

According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, including: providing a substrate, wherein the substrate comprises a first area and a second area; forming a material layer on a first surface of the first and second regions of the substrate and forming an alignment mark on the first surface of the second region of the substrate; introducing heteroatoms into the substrate of the second region from a second surface of the substrate; and reacting the heteroatoms with the substrate to form a dielectric layer in the substrate of the second region overlapping the alignment mark.

According to an embodiment of the present invention, the method for manufacturing a semiconductor device further includes performing a thinning process on the substrate before the introduction of the hetero atoms into the substrate from the second surface of the substrate in the second region.

According to an embodiment of the present invention, the heteroatom comprises oxygen, nitrogen or a combination thereof.

According to the embodiment of the invention, the n value of the refractive index of the dielectric layer is less than 1.5.

According to an embodiment of the present invention, the method of reacting the heteroatom with the substrate includes performing a thermal process or an annealing process.

According to the embodiment of the invention, the dielectric layer is in contact with the alignment mark.

According to the embodiment of the invention, the dielectric layer and the alignment mark are separated by part of the substrate.

An embodiment of the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein the substrate comprises a first area and a second area; introducing heteroatoms into the substrate of the second region from a first surface of the substrate; forming a material layer on the first surface of the substrate in the first and second regions and forming an alignment mark in the substrate in the second region; and reacting the heteroatoms with the substrate to form a dielectric layer in the substrate of the second region overlapping the alignment mark.

According to an embodiment of the present invention, the method of introducing heteroatoms into the substrate of the second region from the first surface of the substrate comprises: forming a mask layer on the first surface of the substrate; carrying out unfilled corner alignment on the substrate; patterning the mask layer to form openings in the mask layer in the second region, the openings corresponding to the alignment marks; carrying out an ion implantation process; and removing the mask layer.

According to an embodiment of the present invention, the heteroatom comprises oxygen, nitrogen or a combination thereof.

According to an embodiment of the present invention, the method of reacting the heteroatom with the substrate includes performing a thermal process or an annealing process.

According to the embodiment of the invention, the dielectric layer is in contact with the alignment mark.

According to the embodiment of the invention, the dielectric layer and the alignment mark are separated by part of the substrate.

An embodiment of the present invention provides a semiconductor device, including: a substrate including a first region and a second region; an isolation structure in the substrate of the second region extending from a first surface of the substrate to a second surface of the substrate; an alignment mark in the substrate of the second region, extending from the first surface of the substrate to the second surface of the substrate and at the same level as the isolation structure; and a dielectric layer in the substrate of the second region and overlapping the alignment mark, wherein a thickness of the substrate between the first surface to the second surface of the substrate of the second region is less than a thickness of the substrate between the first surface to the second surface of the substrate of the first region.

According to an embodiment of the present invention, the first region and the second region are both in a chip region.

According to the embodiment of the invention, the n value of the refractive index of the dielectric layer is less than 1.5.

According to an embodiment of the present invention, the dielectric layer includes silicon oxide, silicon oxynitride, or a combination thereof.

According to the embodiment of the invention, the dielectric layer is in contact with the alignment mark or is separated by the substrate.

According to the embodiment of the invention, the area of the dielectric layer is larger than that of the alignment mark, and the dielectric layer and the alignment mark are separated by the substrate.

Based on the above, the semiconductor device and the manufacturing method thereof of the present invention can maintain a sufficient thickness of the substrate and improve the accuracy of the back alignment.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

Fig. 1A to fig. 1H are schematic cross-sectional flow diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a top view of the second region of FIG. 1E;

FIGS. 3A to 3D are schematic cross-sectional flow diagrams illustrating a method of fabricating a semiconductor device according to a second embodiment of the present invention;

fig. 4A to 4H are schematic cross-sectional flow diagrams illustrating a method for fabricating a semiconductor device according to a third embodiment of the present invention;

fig. 5A to 5B are schematic cross-sectional flow charts illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention;

FIG. 6 is a flow chart of a method of manufacturing a semiconductor device;

fig. 7 is a flowchart of another method of manufacturing a semiconductor device.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1A to fig. 1H are schematic cross-sectional flow diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Fig. 6 is a flow chart illustrating a method of manufacturing a semiconductor device.

Referring to fig. 1A, a substrate 10 is provided. The substrate 10 includes a first region R1 and a second region R2. In some embodiments, first regions R1 are chip regions; the second region R2 is a cut lane. In another embodiment, first region R1 and second region R2 are both adjacent two regions of a chip region. The substrate 10 may be a doped silicon substrate, an undoped silicon substrate, a silicon-on-insulator (SOI) substrate, or an epitaxial substrate. The dopant of the doped silicon may be a P-type dopant, an N-type dopant, or a combination thereof.

Referring to fig. 1A and operation S10 of fig. 6, an isolation structure 12 is formed in the substrate 10 in the first region R1 to define an active region in the substrate 10 and an alignment mark 14 is formed in the substrate 10 in the second region R2. The isolation structures 12 and the alignment marks 14 may be made of the same material or different materials. The isolation structures 12 and the alignment marks 14 comprise an insulating material, such as silicon oxide, silicon nitride, or a combination thereof. The isolation structures 12 and the alignment marks 14 may be formed by a shallow trench isolation method. In some embodiments, the isolation structures 12 and the alignment marks 14 extend from the surface 10-1 of the substrate 10 to the surface 10-2' of the substrate 10, at the same level and with the same depth, but not limited thereto. Surface 10-1 of substrate 10 may also be referred to as a front surface and surface 10-2' may also be referred to as a back surface.

Referring to fig. 1A and 2, the alignment mark 14 of the second region R2 may have various shapes. For example, the alignment mark 14 may include a plurality of sets of structures, each set of structures includes a plurality of spaced-apart and parallel bars, and the bars and the substrate 10 are alternately disposed, but not limited thereto.

Next, referring to fig. 1A and action S12 of fig. 6, a material layer 16 is formed on the surface 10-1 of the substrate 10. Surface 10-1 may also be referred to as first surface 10-1. The material layer 16 may include a device layer and a metal interconnect structure. The device layer is, for example, an active device or a passive device. The active devices are, for example, transistors, diodes, or combinations thereof. Passive devices are for example resistors, capacitors, inductors or combinations thereof. Metal interconnect structures are used to connect devices in the device layer. The metal interconnect structure may include a plurality of dielectric layers and a plurality of conductive features. The conductive features may connect two or more devices in the device layer. The conductive features include contact holes, vias, and conductive lines. The plurality of conductive lines extend in a plane parallel to the surface 10-1 of the substrate 10, and the plurality of vias extend in a direction perpendicular to the surface 10-1 of the substrate 10 to connect two conductive lines adjacent in the longitudinal direction.

In some embodiments, various steps may be included before forming the isolation structures 12 and the alignment marks 14, or after forming the isolation structures 12 and the alignment marks 14 and before forming the material layer 16. For example, various P-type or N-type conductivity well regions, deep well regions, doped regions, etc. may be formed in the substrate 10.

Referring to fig. 1B and act S14 of fig. 6, a handling wafer 20 is placed on the material layer 16 of the substrate 10. The handle wafer 20 may be adhered to the material layer 16 by an adhesive layer (not shown). The adhesive layer may be an organic material or a polymeric material.

Referring to fig. 1C and 1D and actions S16 and S18 of fig. 6, the substrate 10 is turned over so that the surface 10-2' of the substrate 10a faces upward. Next, the substrate 10a is subjected to a thinning process from the surface 10-2' of the substrate 10 to form a substrate 10a thinned in thickness. Surface 10-2 of substrate 10a may also be referred to as a second surface or back surface. The distance d1 between the surface 10-2 of the substrate 10a and the surface of the isolation structure 12 or the distance d1 between the surface 10-2 of the substrate 10a and the surface of the alignment mark 14 is greater than 4 μm, for example, between 4 μm and 20 μm, or more.

Referring to fig. 1E, 2 and action S20 of fig. 6, a patterned mask layer 22 having an opening 23 is formed on the surface 10-2 of the substrate 10 a. The opening 23 exposes the surface 10-2 of the substrate 10a of the second region R2. The position of the opening 23 overlaps the position of the alignment mark 14, and the area of the opening 23 is larger than the area of the alignment mark 14, so as to cover the alignment mark 14 therein, as shown in fig. 2. The method of forming the patterned mask layer 22 can be performed, for example, by the following steps.

Please refer to fig. 1E and fig. 6 action S20₁To S20₃. A mask layer (e.g., a photoresist layer) is applied to the surface 10-2 of the substrate 10a and then baked. Thereafter, through the substrate 10a notch itself (notch) to perform the notch alignment process. Since the required accuracy of the opening 23 to be formed is low as long as it can cover the alignment mark 14 in the second region R2, the required accuracy can be achieved by the notch alignment process. Thereafter, a patterning process is performed through an exposure and development process to form an opening 23 in the mask layer 22 (e.g., a photoresist layer).

Next, referring to fig. 1E and fig. 6 operation S22, an ion implantation process 24 is performed using the mask layer 22 as a mask to introduce hetero atoms from the surface 10-2 of the substrate 10a into the substrate 10a in the second region R2 to form a doped region 26 with hetero atoms. The heteroatoms in doped region 26 are distributed between surface 10-2 of substrate 10a and alignment marks 14. The heteroatom is, for example, oxygen, nitrogen, or a combination thereof. The dosage of hetero atoms is, for example, 10¹³To 10²⁰/cm²。

Please refer to actions S24 and S28 of fig. 1F and fig. 6. The patterned mask layer 22 is removed. Thereafter, an annealing process 28 is performed to react the heteroatoms in the doped region 26 with the silicon in the substrate 10a to form a dielectric layer 26a in the substrate 10a of the second region R2. The annealing process 28 may be performed in a nitrogen environment (N)₂ambient) for 30 to 120 minutes. In some embodiments, the temperature of the annealing process 28 is, for example, between 450 degrees celsius and 1400 degrees celsius. In other embodiments, the temperature of the annealing process 28 is, for example, between 450 degrees celsius and 900 degrees celsius. In still other embodiments, the temperature of the annealing process 28 is, for example, between 450 degrees celsius and 750 degrees celsius. The dielectric layer 26a overlaps the alignment mark 14 in the longitudinal direction, and has an area larger than that of the alignment mark 14. The material of the dielectric layer 26a is, for example, silicon oxide, silicon oxynitride, or a combination thereof. The refractive index of the dielectric layer 26a is lower than that of silicon. Under visible light, the refractive index of the dielectric layer 26a has an n value between 0 and 2. In some embodiments, the refractive index of the dielectric layer 26a has an n value of less than 1.5 under visible light. In other embodiments, the refractive index of the dielectric layer 26a has an n-value of less than 1.46, or less, in visible light. For example, the dielectric layer 26a formed by annealing at 450 degrees celsius has a refractive index (n value) of about 1.41 in visible light. Dielectric formed by annealing at 600 degrees CelsiusThe refractive index (n value) of layer 26a in visible light is about 1.43. The dielectric layer 26a formed by annealing at 750 degrees celsius has a refractive index (n value) of about 1.46 in visible light. The depth of the dielectric layer 26a ranges from 4 μm to 20 μm, for example. In the present embodiment, the top surface of the dielectric layer 26a is coplanar with the surface 10-2 of the substrate 10a, but not limited thereto. The bottom surface of dielectric layer 26a may be in contact with alignment mark 14 or may be separated by a non-zero distance d 1'. The distance d 1' ranges less than 4 μm.

Referring to fig. 1G and act S30 of fig. 6, another patterned mask layer 30 is formed on the surface 10-2 of the substrate 10 a. Patterned masking layer 30 has a plurality of openings 32. The patterned mask layer 30 is formed as follows. Please refer to fig. 1G and act S30 of fig. 6₁To S30₃. Another mask layer (not shown) is formed on the surface 10-2 of the substrate 10 a. The mask layer may include a pad oxide layer, a silicon nitride layer and a photoresist layer in sequence from bottom to top. In the present invention, since the substrate 10a above the alignment mark 14 has been replaced with the dielectric layer 26a, the thickness of the substrate 10a between the surface 10-1 and the surface 10-2 of the substrate 10a of the second region R2 is smaller than the thickness of the substrate 10a between the surface 10-1 and the surface 10-2 of the substrate 10a of the first region R1. Since the refractive index (n value) of the dielectric layer 26a can be greatly reduced to below 1.5, the dielectric layer 26a is transparent under the irradiation of light, and thus the alignment process can be performed through the alignment mark 14 of the second region R2. Then, a patterning process of the photoresist layer is performed through an exposure and development process, and then, an etching process is performed on the silicon nitride layer and the pad oxide layer to form the opening 32.

In the embodiment where the bottom surface of the dielectric layer 26a contacts the surface of the alignment mark 14, since there is only the transparent dielectric layer 26a above the alignment mark 14, a through silicon-free alignment process can be performed when forming the patterned mask layer 30, and light only needs to pass through the dielectric (through silicon) without passing through silicon (through silicon), thereby having a relatively high alignment accuracy. In embodiments having a distance d1 'between the bottom surface of dielectric layer 26a and the surface of alignment mark 14, alignment may still be achieved by a through-silicon process since the range of distance d 1' is less than 4 μm. Therefore, the formed opening 32 can be accurately formed at a desired position. For example, the position of the opening 32 corresponds to the isolation structure 12.

Thereafter, please refer to actions S32 and S34 of fig. 1H and fig. 6. A deep trench (not shown) is formed in the substrate 10a using the patterned mask layer 30 as a mask, and then an insulating material is backfilled in the deep trench to form an isolation structure 34. The method of backfilling an insulating material in the deep trench is, for example, forming an insulating material, such as silicon oxide, silicon nitride, or a combination thereof, on the surface 10-2 of the substrate 10 and in the deep trench. Thereafter, a planarization process is performed to remove excess insulating material. The planarization process is, for example, a chemical mechanical polishing process. Thereafter, the patterned mask layer 30 is removed. Isolation structures 34 may correspond to, or even be aligned with, isolation structures 12. Isolation structures 34 may be aligned with a portion of isolation structures 12 in isolation structures 12. Isolation structure 34 may be in contact with isolation structure 12 or may be spaced a non-zero distance. The depth of the isolation structures 34 ranges, for example, from 4 μm to 20 μm. Since the depth of the isolation structures 34 is quite deep, they may also be referred to as deep trench isolation structures.

Thereafter, the subsequent process may be performed again. For example, a Photodiode (PD) region or the like may be formed in the substrate 10a between two adjacent isolation structures 34. In the present embodiment, since the distance d1 between the surface 10-2 of the substrate 10 and the isolation structures 12 is relatively large and the isolation structures 34 have a relatively large depth, the photodiode region formed in the substrate 10a between the isolation structures 34 may have a relatively large area. Thereafter, separation of the handle wafer 20 from the substrate 10a and other processes may also be included.

Fig. 3A to fig. 3D are schematic cross-sectional flow diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the invention.

Please refer to actions S20 and S22 of fig. 3A and fig. 6. After the steps corresponding to actions S10 to S18 of fig. 1A to 1D and fig. 6 are performed in accordance with the method of the first embodiment described above, a patterned mask layer 22 having openings 23 is formed on the surface 10-2 of the thinned substrate 10 a. Thereafter, an ion implantation process 24 'is performed to introduce heteroatoms from the surface 10-2 of the substrate 10a into the substrate 10a of the second region R2 to form a doped region 26' with heteroatoms. Doped region 26 'is located slightly different from doped region 26, and the top surface of doped region 26' is spaced apart from surface 10-2 of substrate 10a by a non-zero distance d 2. The species of the heteroatom in the doped region 26' may be the same as the species of the heteroatom in the doped region 26. The dose of the heteroatoms in the doped region 26' may be the same as the dose of the heteroatoms in the doped region 26. However, in the present embodiment, the ion implantation process 24 'is performed at a different energy than the ion implantation process 24, such that the top surface of the doped region 26' is spaced a non-zero distance from the surface 10-2 of the substrate 10 a.

Referring to actions S24 and S28 of FIG. 3B and FIG. 6, the mask layer 22 is removed according to the method of the first embodiment. Thereafter, an annealing process 28 is performed to react the heteroatoms in the doped region 26 'with the silicon in the substrate 10a to form a dielectric layer 26 a' in the substrate 10a of the second region R2. The temperature of the annealing process 28 is, for example, 450 degrees celsius to 1400 degrees celsius. The dielectric layer 26a 'is of a material and has an area similar to that of the dielectric layer 26a, but the top surface of the dielectric layer 26 a' is lower than the surface 10-2 of the substrate 10 a. In other words, the top surface of the dielectric layer 26 a' is still covered by the substrate 10 a. The distance d2 between the top surface of the dielectric layer 26 a' and the surface 10-2 of the substrate 10a ranges, for example, from greater than 0 to less than 4 μm. The bottom surface of dielectric layer 26a may be in contact with alignment mark 14 or may be separated by a non-zero distance d 2'. The sum of the distances d2 and d 2' ranges less than 4 μm. However, if the distance d2 or the sum of the distances d2 and d 2' exceeds 4 μm, it means that the thickness of the substrate 10a on the alignment mark 14 is too thick to be transparent under the irradiation of light, which may result in the failure of accurately performing through-silicon alignment in the subsequent alignment process.

Referring to fig. 3C and act S30 of fig. 6, another patterned mask layer 30 is formed on the surface 10-2 of the substrate 10 a. Patterned masking layer 30 has a plurality of openings 32. The position of the opening 32 corresponds to the isolation structure 12, for example. The method of forming the patterned mask layer 30 may be in accordance with the method of the first embodiment. Although the substrate 10a still remains above the dielectric layer 26a ', since the thickness of the substrate 10a (i.e., the distance d2) is quite thin and the dielectric layer 26 a' is transparent, the alignment can be achieved by only a through silicon (through silicon) alignment process. Similarly, if the substrate 10a is still left between the dielectric layer 26a ' and the alignment mark 14, the alignment can still be achieved by the through-silicon process since the sum of the thickness of the substrate 10a (i.e., the distance d2 ') and the thickness of the substrate 10a above the dielectric layer 26a ' (i.e., the distance d2) is less than 4 μm.

Referring to actions S32 and S34 of fig. 3D and fig. 6, the isolation structure 34 is formed in the substrate 10a according to the method of the first embodiment. Thereafter, the patterned mask layer 30 is removed, and the subsequent processes are performed.

According to the above embodiments, the dielectric layer corresponding to the alignment mark in the substrate is formed after the substrate is thinned, however, the invention is not limited thereto. The dielectric layer overlapping the alignment marks may also be formed prior to thinning of the substrate, as will be described by way of example below.

Fig. 4A to 4H are schematic cross-sectional flow diagrams illustrating a method for manufacturing a semiconductor device according to a third embodiment of the invention. FIG. 7 is a flow chart illustrating another method of fabricating a semiconductor device.

Please refer to fig. 4A and S102 and S104 of fig. 7. A patterned masking layer 22 is formed on surface 10-1 of substrate 10. The patterned mask layer 22 has an opening 23 exposing the surface 10-2 of the substrate 10a of the second region R2. The patterned mask layer 22 may be formed using the method of the first embodiment described above. Next, an ion implantation process 24 'is performed to introduce heteroatoms from the surface 10-1 of the substrate 10a into the substrate 10a of the second region R2 to form a doped region 26' with heteroatoms. The ion implantation process 24 ' may be performed using the ion implantation process 24 ' described above in the second embodiment such that the top surface of the doped region 26 ' is a non-zero distance d3 from the surface 10-2 of the substrate 10 a. The distance d3 is at least equal to or greater than the depth of the alignment mark 14 to be formed subsequently.

Referring to fig. 4B and operations S106 and S108 of fig. 7, the patterned mask layer 22 is removed. Thereafter, an annealing process 28 may be selectively performed to react the heteroatoms in the doped region 26 'with the silicon in the substrate 10a to form a dielectric layer 26 a' in the substrate 10a of the second region R2. The annealing process 28 may be performed using the method of the first embodiment described above. However, the embodiments of the present invention are not limited thereto. In some embodiments, the annealing process 28 may be omitted, and the annealing process 28 may be replaced by a thermal process followed by another process. For example, the annealing process 28 may be replaced by a subsequent dopant activation process for forming doped regions of the isolation structure 12 and the material layer 16, or a dielectric layer deposition process for metal interconnect structures.

Please refer to fig. 4C and operations S110 and S112 of fig. 7. Isolation structures 12 and alignment marks 14 are formed in substrate 10. The isolation structure 12 is located in the first region R1; the alignment mark 14 is located in the second region R2, and overlaps the dielectric layer 26a in the longitudinal direction. Thereafter, a material layer 16 is formed on the isolation structures 12 and the alignment marks 14. The isolation structures 12, the alignment marks 14 and the material layer 16 may be formed according to the method described in the first embodiment above. Alignment mark 14 may be in contact with the surface of dielectric layer 26a 'or may be separated by a non-zero distance d 3'. The distance d 3' ranges, for example, from greater than 0 to less than 4 μm.

In some alternative embodiments, the ion implantation process 24 'for forming the doped region 26' may also be performed after forming the isolation structure 12 and the alignment mark 14 and before forming the material layer 16. Similarly, in some other embodiments, various steps may be included before forming the doped region 26', or before forming the isolation structure 12 and the alignment mark 14, or after forming the isolation structure 12 and the alignment mark 14 and before forming the material layer 16. For example, various P-type or N-type conductivity well regions, deep well regions, doped regions, etc. may be formed in the substrate 10.

Please refer to fig. 4D to fig. 4F and operations S114, S116 and S118 of fig. 7. The handle wafer 20 is placed on the material layer 16 of the substrate 10 and then flipped over so that the substrate 10a is positioned on the handle wafer 10. Thereafter, a thinning process of the substrate 10 is performed to form a substrate 10a thinned in thickness. The distance d4 between the surface 10-2 of the substrate 10a and the surface of the isolation structure 12 is greater than 4 μm, for example between 4 μm and 20 μm, or greater. In some embodiments, during the thinning process of the substrate 10, portions of the dielectric layer 26 a' are also thinned. In other embodiments, dielectric layer 26 a' is not thinned during the thinning process of substrate 10. After the thinning process of the substrate 10 is performed, the dielectric layer 26 a' is exposed. The top surface of the dielectric layer 26 a' is coplanar with the surface 10-2 of the substrate 10 a. The bottom surface of dielectric layer 26a 'is in contact with the surface of alignment mark 14 or is separated by a non-zero distance d 3'. The distance d 3' ranges less than 4 μm.

Referring to fig. 4G and act S120 of fig. 7, a patterned mask layer 30 having an opening 32 is formed on the surface 10-2 of the substrate 10a according to the method of the first embodiment. Similarly, the bottom surface of the dielectric layer 26a 'is in contact with the surface of the alignment mark 14 or the bottom surface of the dielectric layer 26 a' is spaced apart from the surface of the alignment mark 14 by a distance d3 ', and a through-silicon-free alignment process or a through-silicon alignment process may be performed during the formation of the patterned mask layer 30, so that light may directly pass through the transparent dielectric layer 26 a' or through the thin silicon to the alignment mark 14 for alignment purposes by the alignment mark 14.

Please refer to fig. 4H and operations S122 and S124 of fig. 7. In accordance with the method of the first embodiment described above, an isolation structure 34 is formed in the substrate 10 a. Thereafter, the patterned mask layer 30 is removed, and the subsequent processes are performed.

Fig. 5A to 5B are schematic cross-sectional flow diagrams illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the invention.

Referring to fig. 5A and operation S118 of fig. 7, after the steps corresponding to fig. 4A to 4D and operations S102 to S116 of fig. 7 are performed according to the method of the first embodiment, a thinning process is performed on the substrate 10 from the surface 10-2' of the inverted substrate 10 to form the substrate 10 b. The distance d5 between the surface 10-2 of the substrate 10b and the surface of the isolation structure 12 is, for example, 4 μm to 20 μm. In the present embodiment, the substrate 10 does not expose the top surface of the dielectric layer 26a during the thinning process, so the surface 10-2 of the substrate 10b is higher than the top surface of the dielectric layer 26a ', and the top surface of the dielectric layer 26 a' is covered by the substrate 10 b. In other words, the distance d6 between the top surface of the dielectric layer 26 a' and the surface 10-2 of the substrate 10b is, for example, greater than 0 and less than 4 μm. However, if the distance d6 exceeds 4 μm, it means that the thickness of the substrate 10a on the dielectric layer 26 a' is too thick to be transparent under the irradiation of light, which results in the failure to accurately perform through-silicon alignment.

Likewise, the bottom surface of dielectric layer 26a 'may be in contact with alignment mark 14 or may be separated by a non-zero distance d 6'. The sum of the distances d6 and d 6' ranges less than 4 μm.

Referring to fig. 5B and actions S120 to S124 of fig. 7, the isolation structure 34 is formed in the substrate 10B according to the steps of the third embodiment corresponding to fig. 4G and 4H. And then carrying out subsequent processes. Similarly, since the distance d6 itself or the sum of the distances d6 and d 6' is less than 4 μm, the alignment can be achieved by a through-the-thin silicon alignment process during the formation of the isolation structures 34.

In summary, in the embodiments of the present invention described above, the thickness of the substrate above the alignment mark can be reduced by forming a dielectric layer in the substrate overlapping the alignment mark. Since the thickness of the substrate above the alignment marks is rather thin, the photolithography process can be performed by a through-thin silicon alignment process or a through-silicon-free alignment process when fabricating the components on or from the back side of the wafer. Therefore, the method of the embodiment of the invention can ensure that the substrate has enough thickness and can improve the accuracy of the wafer back alignment.