阅读说明：本技术 控制pwm信号死区时间的方法、控制器及相关的电子设备 (Method for controlling dead time of PWM signal, controller and related electronic equipment ) 是由 肖良 欧曦 李萌 白俊华 董俊丽 于 2021-09-28 设计创作，主要内容包括：本发明公开了一种控制PWM信号死区时间的方法、控制器及相关的电子设备。该方法包括以下步骤：S1,启动第一PWM波形发生器,以使第一PWM波形发生器输出第一信号；第一PWM波形发生器为负极性；S2,等待预定时间；S3,启动第二PWM波形发生器,以使第二PWM波形发生器输出第二信号；第二PWM波形发生器为正极性。本发明在第一个PWM信号发生器输出的第一个信号出现下降沿后,通过等待死区时间再让第二个PWM信号发生器输出第二个信号的高电平,再通过对两个PWM信号发生器输出信号的占空比的控制保证第二个信号的下降沿后至少经过死区时间,第一个信号才出现高电平,通过两个死区时间保证两个PWM信号发生器输出的信号不会出现同时为高电平。(The invention discloses a method for controlling dead time of a PWM signal, a controller and related electronic equipment. The method comprises the following steps: s1, starting the first PWM waveform generator to make the first PWM waveform generator output the first signal; the first PWM waveform generator is negative; s2, waiting for a preset time; s3, starting the second PWM waveform generator to enable the second PWM waveform generator to output a second signal; the second PWM waveform generator is positive in polarity. After the first signal output by the first PWM signal generator has a falling edge, the second PWM signal generator outputs the high level of the second signal by waiting for dead time, and the control of the duty ratio of the output signals of the two PWM signal generators ensures that the first signal has the high level after the falling edge of the second signal at least passes through the dead time, and ensures that the signals output by the two PWM signal generators are not simultaneously at the high level by the two dead time.)

1. A method of controlling a dead time of a PWM signal, comprising the steps of:

step S1, starting a first PWM waveform generator to enable the first PWM waveform generator to output a first signal; the first PWM waveform generator is negative in polarity;

step S2, waiting for a predetermined time;

step S3, starting a second PWM waveform generator to enable the second PWM waveform generator to output a second signal; the second PWM waveform generator is positive;

wherein the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time for executing the step S3; the dead time, the duty ratio of the first signal and the duty ratio of the second signal meet the following conditions: d1+ D2+ (2 XT 1)/T2 is less than or equal to 1; where D1 is the duty ratio of the first signal, D2 is the duty ratio of the second signal, T1 is the dead time, and T2 is the period of the first signal.

2. The method of claim 1, wherein said step S2 further comprises:

with the loop statement, a predetermined time is waited.

3. The method of claim 1, wherein said step S3 further comprises:

the second PWM waveform generator is enabled.

4. The method of claim 1, wherein the step S1 is preceded by the steps of:

initializing a second PWM waveform generator;

configuring a frequency and duty cycle of the second PWM waveform generator.

5. The method of claim 4, wherein the step S1 is preceded by the steps of:

reading a first control value of a control register of the second PWM waveform generator into a cache;

rewriting the first control value in the cache to a second control value;

said enabling said second PWM waveform generator comprises the steps of:

writing the second control value into a control register of the second PWM waveform generator;

wherein, the state of the first control value for enabling the control bit of the PWM waveform generator is not enabled, and the state of the second control value for enabling the control bit of the PWM waveform generator is enabled.

6. A controller for controlling a dead time of a PWM signal, comprising:

the first starting module is used for starting the first PWM waveform generator so that the first PWM waveform generator outputs a first signal; the first PWM waveform generator is negative in polarity;

a waiting module for waiting for a predetermined time;

the second starting module is used for starting the second PWM waveform generator so that the second PWM waveform generator outputs a second signal; the second PWM waveform generator is positive;

wherein the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time for executing the step S3; the dead time, the duty ratio of the first signal and the duty ratio of the second signal meet the following conditions: d1+ D2+ (2 XT 1)/T2 is less than or equal to 1; where D1 is the duty ratio of the first signal, D2 is the duty ratio of the second signal, T1 is the dead time, and T2 is the period of the first signal.

7. The controller of claim 6, wherein said second enabling module further comprises:

an enable sub-module to enable the second PWM waveform generator.

8. The controller of claim 6, further comprising:

an initialization module for initializing the second PWM waveform generator;

a configuration module to configure a frequency and duty cycle of the second PWM waveform generator.

9. The controller of claim 8, further comprising:

the reading module is used for reading a first control value of a control register of the second PWM waveform generator into a cache;

the rewriting module is used for rewriting the first control value in the cache into a second control value;

the enabling sub-module includes:

a write-in submodule for writing the second control value into a control register of the second PWM waveform generator;

wherein, the state of the first control value for enabling the control bit of the PWM waveform generator is not enabled, and the state of the second control value for enabling the control bit of the PWM waveform generator is enabled.

10. An electronic device characterized by comprising the controller according to any one of claims 6 to 9.

Technical Field

The invention relates to a method for controlling the dead time of a PWM (pulse-width modulation) signal, a controller for controlling the dead time of the PWM signal and related electronic equipment, and belongs to the technical field of electric pulses.

Background

Pwm (pulse Width modulation) is an abbreviation for pulse Width modulation. It is to modulate the width of a series of pulses to obtain the required waveform (including shape and amplitude), and digitally encode the level of analog signals, that is, to adjust the change of signal, energy, etc. by adjusting the change of duty ratio.

In recent years, the smart home industry has become a new tuyere. In the field of smart homes, PWM is increasingly used very widely, for example, in smart lighting fixtures. The requirement of intelligence house to PWM signal also becomes higher and higher, two power device's the condition around the intelligence house electrical apparatus often uses, power device generally all can produce the delay effect when opening/closing because of junction capacitance, this kind of delay effect probably leads to the front and back power device to open simultaneously, and then causes the condition of heavy current damage equipment, for accurate control dead time, power device around the intelligence house electrical apparatus often adopts PWM signal control, dead time is the guard time who avoids the front and back power device to open simultaneously and design. If the dead time is too small, the risk of large current caused by the difference between the sheets still exists; if the dead time is too large, the efficiency of the power device may be reduced.

In chinese patent No. CN110557013B, a PWM dead time control system is disclosed. The system comprises a controllable charging and discharging current generation module, a dead time generation module and a logic circuit module, and the generation and the controllability of the PWM dead time are realized by mainly utilizing an analog circuit. However, this system uses a large number of PMOS transistors, NMOS transistors, and logic gate circuits, which makes the circuit complicated. How to control the dead time of two-way PWM signal generators with fewer devices is still one of the problems to be solved in the art.

Disclosure of Invention

The invention aims to provide a method for controlling the dead time of a PWM signal.

Another technical problem to be solved by the present invention is to provide a controller for controlling a dead time of a PWM signal.

Another object of the present invention is to provide an electronic device for controlling a dead time of a PWM signal.

According to a first aspect of the embodiments of the present invention, there is provided a method for controlling a dead time of a PWM signal, including the steps of:

step S1, starting the first PWM waveform generator to make the first PWM waveform generator output the first signal; the first PWM waveform generator is negative;

step S2, waiting for a predetermined time;

step S3, starting the second PWM waveform generator to make the second PWM waveform generator output the second signal; the second PWM waveform generator is positive;

wherein the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time for executing the step S3; the dead time, the duty ratio of the first signal and the duty ratio of the second signal meet the following conditions: d1+ D2+ (2 XT 1)/T2 is less than or equal to 1; where D1 is the duty ratio of the first signal, D2 is the duty ratio of the second signal, T1 is the dead time, and T2 is the period of the first signal.

Preferably, step S2 includes the following steps:

waiting for a predetermined time using a loop statement;

preferably, step S3 includes the following steps:

enabling the second PWM waveform generator;

preferably, before step S1, the method further includes the following steps:

initializing a second PWM waveform generator;

the frequency and duty cycle of the second PWM waveform generator are configured.

Preferably, before step S1, the method further includes the following steps:

reading a first control value of a control register of a second PWM waveform generator into a cache;

rewriting the first control value in the cache to a second control value;

enabling the second PWM waveform generator, comprising the steps of:

writing the second control value into a control register of a second PWM waveform generator;

wherein, the state of the control bit for enabling the PWM waveform generator in the first control value is not enabled, and the state of the control bit for enabling the PWM waveform generator in the second control value is enabled.

According to a second aspect of the embodiments of the present invention, there is provided a controller for controlling a dead time of a PWM signal, including:

the first starting module is used for starting the first PWM waveform generator so that the first PWM waveform generator outputs a first signal; the first PWM waveform generator is negative;

a waiting module for waiting for a predetermined time;

the second starting module is used for starting the second PWM waveform generator so that the second PWM waveform generator outputs a second signal; the second PWM waveform generator is positive;

wherein the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time for executing the step S3; the dead time, the duty ratio of the first signal and the duty ratio of the second signal meet the following conditions: d1+ D2+ (2 XT 1)/T2 is less than or equal to 1; where D1 is the duty ratio of the first signal, D2 is the duty ratio of the second signal, T1 is the dead time, and T2 is the period of the first signal.

Preferably, the waiting module includes:

a waiting submodule for waiting for a predetermined time using the loop statement;

preferably, the second starting module comprises:

an enable sub-module for enabling the second PWM waveform generator;

preferably, the controller further comprises:

the initialization module is used for initializing the second PWM waveform generator;

and the configuration module is used for configuring the frequency and the duty ratio of the second PWM waveform generator.

Preferably, the controller further comprises:

the reading module is used for reading a first control value of a control register of the second PWM waveform generator into a cache;

the rewriting module is used for rewriting the first control value in the cache into a second control value;

an enable sub-module comprising:

the writing submodule is used for writing the second control value into a control register of the second PWM waveform generator;

wherein, the state of the control bit for enabling the PWM waveform generator in the first control value is not enabled, and the state of the control bit for enabling the PWM waveform generator in the second control value is enabled.

According to a third aspect of embodiments of the present invention, there is provided an electronic apparatus including the controller of any one of the above.

Compared with the prior art, the invention ensures that the first signal appears high level only after the falling edge of the second signal by controlling the duty ratio of the output signals of the two PWM signal generators and the signals output by the two PWM signal generators do not appear high level at the same time by waiting for dead time after the falling edge of the first signal output by the first PWM signal generator appears and then enabling the second PWM signal generator to output high level of the second signal.

Drawings

FIG. 1 is a flow chart of a method for controlling the dead time of a PWM signal according to the present invention;

FIG. 2 is a schematic diagram of two dead time schedules in an embodiment of the present invention;

FIG. 3 is a diagram illustrating the elapsed time of step S3 according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of the prior art, which continuously starts two PWM signal generators to output waveform time differences;

FIG. 5 is a schematic diagram of a controller for controlling the dead time of the PWM signal according to the present invention;

fig. 6 is a flowchart of a method for controlling the dead time of the PWM signal in the intelligent lamp.

Detailed Description

The technical contents of the invention are described in detail below with reference to the accompanying drawings and specific embodiments.

Fig. 1 is a flowchart of a method for controlling a dead time of a PWM signal according to a first embodiment of the present invention. The method at least comprises the following steps:

step S1, starting the first PWM waveform generator to make the first PWM waveform generator output the first signal; the first PWM waveform generator is negative;

step S2, waiting for a predetermined time;

step S3, starting the second PWM waveform generator to make the second PWM waveform generator output the second signal; the second PWM waveform generator is positive;

wherein the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time for executing the step S3; the dead time, the duty ratio of the first signal and the duty ratio of the second signal meet the following conditions: d1+ D2+ (2 XT 1)/T2 is less than or equal to 1; where D1 is the duty ratio of the first signal, D2 is the duty ratio of the second signal, T1 is the dead time, and T2 is the period of the first signal.

The main execution body of the invention is a controller (Central Processing Unit), and the controller controls the start of the PWM waveform generator through instructions. The two PWM waveform generators of the present invention operate at the same frequency.

The PWM waveform generator is divided into a negative polarity PWM waveform generator and a positive polarity PWM waveform generator, wherein the negative polarity PWM waveform generator firstly outputs a low level signal (generates a falling edge which is changed from high to low) after starting, and the positive polarity PWM waveform generator firstly outputs a high level signal (generates a rising edge which is changed from low to high) after starting. In addition, the frequencies of the signals output by the two PWM waveform generators are the same, so as long as the first signal and the second signal of one period meet the requirement of establishing the dead time, the first signal and the second signal in all the following periods meet the requirement of establishing the dead time.

Under a specific application scene, the devices controlled by two paths of PWM signals cannot work simultaneously. For example, due to the limitation of power supply, two LED bulbs in the lamp, which are respectively controlled by two PWM signal generators, cannot operate simultaneously, and if both bulbs cannot operate in a full power state during simultaneous operation (dead zone), the brightness of the two bulbs is too dark or other faults occur. At this time, two PWM signal generators are required to be matched with each other, when one PWM signal generator outputs high level to control a relay to be conducted to start one lamp bulb, the other PWM signal generator must output low level to close the other lamp bulb.

The situation that the logic controller controls the signals output by the two PWM waveform generators must avoid the situation (the control logics of the two PWM waveform generators are not high at the same time), but the situation that the signal output by a certain PWM signal generator is in an indefinite state in a certain period of time can be objectively caused due to hardware limitation. For example, the controller controls the first signal to have a falling edge, and the signal on the hardware cannot be immediately changed from a high level to a low level, but there is a switching process during which the output signal is in an indeterminate state. If the other PWM signal generator outputs a high signal during this time, it may happen that both PWM signal generators output a high signal at the same time. Therefore, it is generally necessary to wait for a signal in an indefinite state to stabilize at a low level and then change another signal to a high level. This time of waiting is referred to as dead time. In short, the dead time is the waiting time for one PWM signal generator to wait for the signal output from another PWM signal generator to become low from high level and then output high level signal.

In practical applications, the dead time may be longer than the time for a signal to stabilize from high to low and output low. Because the purpose of establishing the dead time is to prevent the two PWM signal controlled power devices from operating simultaneously. The PWM signal is usually used to control the switching of the power device, even if the PWM signal is stable, the switching of the power device needs another time to reach the stability, and the dead time in the practical application is the sum of the two end times of the signal stability and the power device switching state stability. The dead time is determined by hardware performance, and some hardware has a high speed of switching high and low levels, so that the dead time is short, and conversely, the dead time is long.

Fig. 2 is a schematic diagram of two dead time positions according to the embodiment of the present invention, as shown in fig. 2, PWM1 is a first PWM signal, PWM2 is a second PWM signal, and a1-B1 are time differences of two PWM signals. In the figure, "1" is a region where the first dead time is scheduled, and "2" is a region where the second dead time is scheduled. The invention firstly starts the first PWM signal generator to output the first signal, after the first PWM signal generator is successfully started, the first signal has the first falling edge, the signal is changed from high level to low level, at the moment, the signal is unstable, the second PWM signal generator is started after waiting for the first dead time (1 in figure 2), and the second signal output by the second PWM signal generator is changed from low level to high level.

The level of the first signal output by the hardware of the first PWM waveform generator with negative polarity is unstable within a certain time after the falling edge is generated, so as to prevent the second signal output by the second PWM waveform generator with positive polarity and the first signal from being simultaneously in high level. The second PWM waveform generator of the present invention waits for the first signal to stabilize to a low level from the occurrence of a falling edge (i.e., a dead time) and then starts outputting a high level, and such waiting enables outputting a high level of the second signal while ensuring that the first signal stabilizes to a low level. This prevents the second signal from being high when the first signal may output high even if the state is uncertain.

The first dead time is formed by staggering the starting time of the two PWM signal generators, the first PWM signal generator with negative polarity is started first, the first signal is changed from high to low, and the second signal output by the second PWM signal generator after the dead time is passed is changed from low to high. The first dead time is composed of two parts, the first part is the predetermined time waiting for step S2, and the second part is the time required for step S3 to start the second PWM signal generator. The predetermined time is user settable as desired, whereas the prior art time to start the second PWM signal generator typically requires three steps to be performed:

1. initializing a second PWM signal generator;

2. configuring the frequency and duty cycle of a second PWM signal generator;

3. the second PWM signal generator is enabled.

In step 1, initializing the PWM waveform generator, where the initialization may specifically include turning on a clock gate of the PWM, and switching a mode of a TIMER to a PWM operating mode. And 2, configuring the duty ratio and the frequency of the PWM waveform generator, and writing into a register of the PWM waveform generator for storing the two information.

The time to start the second PWM signal generator is a random value. Fig. 4 shows the time difference of output waveforms of two PWM signal generators in a prior art, which are continuously activated. Here, the two PWM signal generators are both positive in polarity, PWM1 is the waveform of the output signal of the PWM waveform generator started earlier, PWM2 is the waveform of the output signal of the PWM waveform generator started later, and the time difference between the start of outputting the high level by PWM1 and the start of outputting the high level by PWM2 (a 1-a2 in the figure) is the time required to complete the above-mentioned 3 steps (excluding the predetermined time waiting in the step S2). The normal software flow PWM waveform period start position time difference is a random value because there is not one continuous operation between enable PWM1 and enable PWM2, but three steps, and the program is compiled and may insert other operations into the discontinuous operation for efficiency reasons.

Thus, a part of the dead time is controllable (preset time) and another part is not controllable (time to activate the second PWM signal generator). But the proportion of the uncontrollable part in the dead time can be reduced through optimization, and the precision of controlling the dead time is improved.

On the basis of the first embodiment described above, the second embodiment of the present invention further provides an improved method, namely:

step S2, further comprising the steps of:

waiting for a predetermined time using a loop statement;

step S3, further comprising the steps of:

enabling the second PWM waveform generator;

before step S1, the method further includes the following steps:

initializing a second PWM waveform generator;

the frequency and duty cycle of the second PWM waveform generator are configured.

In practical applications, the loop statement of the waiting time may be while (- -delay), or for (i ═ 0; i < delay; i + +). Wherein delay is a time difference parameter operable by a user for setting the predetermined time, and has a fixed corresponding relationship with the predetermined time. The control accuracy of the while (-delay) sentence is higher than that of for (i ═ 0; i < delay; i + +) for a predetermined time, and it is proposed to use the while (-delay) sentence.

If it is while (-delay), and delay is 1, the C language code of this while (-delay) may be compiled to generate the following assembly statement:

LOOP:

SUBS R0,#1

BNE LOOP

wherein, R0 is delay, R0 data-1 per LOOP, if R0>0, BNE statement jumps to LOOP, otherwise, LOOP ends. The execution time of the SUBS statement is 1 controller clock cycle, the execution time of the BNE statement is 3 controller clock cycles if the LOOP is skipped, and is 1 controller clock cycle if the LOOP is not skipped, namely, the execution time of each cycle where the statement is skipped is 4 controller clock cycles, the cycle is ended in the last cycle, and the execution time of the cycle which is not skipped is 2 controller clock cycles. The total execution time of while (-delay) is (delay x 4-2) controller clock cycles (i.e., is a predetermined time).

The second embodiment changes the sequence of the steps for starting the PWM signal generator, and moves the step 1 and the step 2 for starting the second PWM signal generator to the step S1, so that the time of the step S3 can be shortened, the proportion of the uncontrollable part to the dead time can be reduced, and the accuracy of controlling the dead time can be improved. FIG. 3 is a diagram illustrating the time consumption of the second embodiment step S3, and the execution time of the step S3 is theoretically 8 controller clock cycles before moving step S1 and step S2 to step S1.

In practical applications, the execution time of step S3 can be further shortened from the aspect of the execution efficiency of the C language code, so as to improve the control accuracy of the dead time.

On the basis of the second embodiment, the present invention further provides a method, before step S1, further comprising the following steps:

reading a first control value of a control register of a second PWM waveform generator into a cache;

rewriting the first control value in the cache to a second control value;

enabling the second PWM waveform generator, comprising the steps of:

writing the second control value into a control register of a second PWM waveform generator;

wherein, the state of the control bit for enabling the PWM waveform generator in the first control value is not enabled, and the state of the control bit for enabling the PWM waveform generator in the second control value is enabled.

In practical application, the language C statement enabling the second PWM waveform generator is:

PWM2->CR|＝1；

after compiling by a compiler, observing an assembly instruction angle, and unfolding the following three instructions:

1) reading the value of the PWM2 control register;

2) modifying the enable bit therein to be 1;

3) the new PWM2 value is written to the PWM2 control register.

According to the splitting, the C language code can be split into two sentences:

pwm2_val＝PWM2->CR|1；

PWM2->CR＝pwm2_val。

where pwm2_ val is an intermediate variable in the cache. The present embodiment carries out step 1) and step 2) before step S1 (theoretically 6 controller clock cycles), and then performs step 3 only in step S3), which can further compress the time of step S3 to 2 controller clock cycles (theoretical value).

Regardless of step S2, the C language code of steps S1 and S3 may be adjusted to:

pwm1_val＝PWM1->CR|1；

PWM2_ val ═ PWM2- > CR | 1; (before step S1)

Step S1: PWM1- > CR ═ PWM1_ val;

step S3: PWM2- > CR ═ PWM2_ val.

The loop statement of step S2 is placed between step S1 and step S3, and at the time of compiling, the compiler can be prevented from inserting other operations between step S1 and step S3, so that the time to activate the second PWM signal generator is no longer a random time but a fixed time. Thus, if a while (delay) statement is used in step S2, the relationship between the dead time and the parameter delay is (4 × delay-2+2) × controller clock period equal to 4 × delay × controller clock period, that is, the time difference between the start of the first PWM signal generator output signal and the start of the second PWM signal generator output signal. If the controller clock is 32MHz, the dead time is delay times 0.125 μ s.

The manner in which the first dead time is formed and improved is described above. A second dead time ("2" in fig. 2) is also included in the present invention. After the falling edge of the second signal, the first signal needs to output a high level at least after the dead time.

If the second dead time is to be formed, it is necessary to control the duty ratios of the two PWM signal generators. So that the position of "2" can insert a dead time. In the limit, two dead time periods and a high-level pulse time of the first signal and a high-level pulse time of the second signal are present in a period of the first signal (equal to a period of the second signal), that is, a first dead time period + a high-level pulse time of the second signal is equal to a time of one period of the first signal, and thus D1+ D2+ (2 × T1)/T2 is equal to 1; where D1 is the duty ratio of the first signal (since the first signal is negative, high level corresponds to null for the first signal), D2 is the duty ratio of the second signal, T1 is the dead time, and T2 is the period of the first signal. If D1+ D2+ (2 × T1)/T2<1, the second dead time passes in the "2" region, the first signal will become high after a period of time, and the high levels of the two PWM signals will not overlap. If D1+ D2+ (2 XT 1)/T2>1, the "2" region cannot meet the dead time requirement. Or the case where the high levels of the first signal and the second signal are "overlapped" in the "2" region.

Alternatively, the first PWM signal generator may be of positive polarity, followed by an inverter gate. At this time, D1+ D2+ (2 XT 1)/T2 ≦ 1, and D1 is the duty ratio of the first signal. Because the speed of the gate circuit of the inverter is very fast, the passing time delay of the signal is ns level, and the time difference of the two paths of PWM signals is mu s level, whether the dead time is met or not can be considered when calculating.

In the embodiment of the invention, the time difference between the output signal of the first PWM signal generator and the output signal of the second PWM signal generator can be accurately set, so that whether the two PWM signals meet the dead time condition can be judged according to the signal time difference, the duty ratio of the first PWM signal and the duty ratio of the second PWM signal. Namely, D1+ D2+ (2 XT 1)/T2 is less than or equal to 1.

After the first signal output by the first PWM signal generator has a falling edge, the second PWM signal generator outputs the high level of the second signal by waiting for dead time, and the control of the duty ratio of the output signals of the two PWM signal generators ensures that the first signal has the high level after the falling edge of the second signal at least passes through the dead time, and ensures that the signals output by the two PWM signal generators are not simultaneously at the high level by the two dead time.

Fig. 5 is a controller for controlling a dead time of a PWM signal according to a fourth embodiment of the present invention, which includes at least:

the first starting module is used for starting the first PWM waveform generator so that the first PWM waveform generator outputs a first signal; the first PWM waveform generator is negative;

a waiting module for waiting for a predetermined time;

the second starting module is used for starting the second PWM waveform generator so that the second PWM waveform generator outputs a second signal; the second PWM waveform generator is positive;

wherein the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time for executing the step S3; the dead time, the duty ratio of the first signal and the duty ratio of the second signal meet the following conditions: d1+ D2+ (2 XT 1)/T2 is less than or equal to 1; where D1 is the duty ratio of the first signal, D2 is the duty ratio of the second signal, T1 is the dead time, and T2 is the period of the first signal.

On the basis of the fourth embodiment, the present invention further provides a controller. In the controller, the waiting module specifically includes:

a waiting submodule for waiting for a predetermined time using the loop statement;

the second starting module specifically comprises:

an enable sub-module for enabling the second PWM waveform generator;

the controller further comprises:

the initialization module is used for initializing the second PWM waveform generator;

and the configuration module is used for configuring the frequency and the duty ratio of the second PWM waveform generator.

On the basis of the fourth embodiment, the present invention further provides a controller, further comprising:

the reading module is used for reading a first control value of a control register of the second PWM waveform generator into a cache;

the rewriting module is used for rewriting the first control value in the cache into a second control value;

an enable sub-module comprising:

the writing submodule is used for writing the second control value into a control register of the second PWM waveform generator;

wherein, the state of the control bit for enabling the PWM waveform generator in the first control value is not enabled, and the state of the control bit for enabling the PWM waveform generator in the second control value is enabled.

A fifth embodiment of the present invention provides an electronic apparatus including the controller of any one of the above.

The electronic equipment in the embodiment of the invention can be an intelligent lamp, and the intelligent lamp can be provided with wifi, Bluetooth or infrared and other remote communication modules. The communication module may communicate with a terminal. The terminal can be a computer, a mobile phone or a remote controller.

Next, taking the terminal as a remote controller, the two PWM signal generators controlling the on/off of the two bulbs, and setting the dead time as an example, a method flow for controlling the dead time of the PWM signal in the intelligent lamp is described with reference to fig. 6. The method specifically comprises the following steps:

step S1, setting PWM duty ratio of lamp 1, PWM duty ratio brightness of lamp 2 and time difference parameter by remote controller, sending to controller, and requesting controller to enable PWM signal generator of lamp 1 and lamp 2;

step S2, the controller determines whether the dead time condition is satisfied according to the parameters, if not, the controller sends a notice to the remote controller to request the user to change the data, and the step S1 is returned; if yes, go to step S4;

step S3, sending a notice to the remote controller to request the user to change the data, and turning to step S1;

step S4, the controller initializes the first PWM signal generator of lamp 1 and the second PWM signal generator of lamp 2, and sets duty ratios and frequencies of the first PWM signal generator and the second PWM signal generator;

step S5, the controller reads the data of the control register of the first PWM signal generator and the data of the control register of the second PWM signal generator into the cache, and modifies the state of the enable bit of the two cache data to "enable";

step S6, the controller writes the data enabling the first PWM signal generator into the control register of the first PWM signal generator from the buffer, and enables the first PWM signal generator;

step S7, the controller waits for a predetermined time;

in step S8, the controller writes data enabling the second PWM signal generator from the buffer into the control register of the second PWM signal generator, enabling the second PWM signal generator.

The method for controlling the dead time of the PWM signal, the controller and the related electronic device provided by the present invention are described in detail above. It will be apparent to those skilled in the art that any obvious modifications thereof can be made without departing from the spirit of the invention, which infringes the patent right of the invention and bears the corresponding legal responsibility.