阅读说明：本技术 一种计算机硬件故障报警系统及方法 (Computer hardware fault alarm system and method ) 是由 王善勤 吴昌雨 刘东旭 梁金荣 陈开兵 吴昊 于 2021-09-10 设计创作，主要内容包括：本发明涉及计算机硬件技术领域,具体是一种计算机硬件故障报警系统及方法,包括数据采集、报警控制器、局域网和维修终端,所述数据采集包括电脑主板侦测卡、储存模块和计算机硬件。本发明采用电脑主板侦测卡对计算机硬件进行检测,并将故障检测信息存入储存模块进行备份,同时电脑主板侦测卡将故障检测信息传输给报警控制器进行报警,而报警控制器通过GPRS和GSM将故障检测信息分别传输给显示终端、中心主机和移动终端,此时,中心主机可将计算机硬件故障信息和故障解决数据库调出并在显示终端展示,从而可以克服计算机硬件出现故障时,处理周期长,浪费时间,耽误工作和生活的问题。(The invention relates to the technical field of computer hardware, in particular to a computer hardware fault alarm system and a computer hardware fault alarm method. The computer hardware fault detection system adopts the computer mainboard detection card to detect the computer hardware, and stores the fault detection information into the storage module for backup, meanwhile, the computer mainboard detection card transmits the fault detection information to the alarm controller for alarming, and the alarm controller transmits the fault detection information to the display terminal, the central host and the mobile terminal respectively through GPRS and GSM.)

1. A computer hardware fault alarm system is characterized in that: including data acquisition, alarm controller, LAN and maintenance terminal, data acquisition includes that computer motherboard detects card, storage module and computer hardware, and storage module integration detects the card at computer motherboard on, computer motherboard detects the card and inserts behind PCI or the ISA slot, and the display screen of taking will demonstrate various codes according to the progress of starting on the card when starting the computer, the LAN includes GPRS and GSM, maintenance terminal includes display terminal, central host computer and mobile terminal.

2. The computer hardware fault alarm system of claim 1, wherein: the computer mainboard detection card detects a computer hardware circuit and stores fault information into the storage module.

3. The computer hardware fault alarm system of claim 1, wherein: the computer mainboard detection card transmits computer hardware fault information to the alarm controller through the electric signal, and the alarm controller receives the fault electric signal to alarm.

4. The computer hardware fault alarm system of claim 1, wherein: and the alarm controller transmits the computer hardware fault information to the display terminal, the central host and the mobile terminal through GPRS and GSM respectively.

5. The computer hardware fault alarm system of claim 1, wherein: the central host computer stores computer hardware fault information and a fault solution database, and can call the computer hardware fault information and the fault solution database out and display the information on the display terminal.

6. The computer hardware fault alarm system of claim 1, wherein: the computer hardware comprises a CPU, a memory, a mainboard, a hard disk drive, an optical disk drive, an expansion card, a connecting wire, a power supply, a display, a mouse and a keyboard.

7. A computer hardware fault alarm method is characterized in that: the detection of the computer mainboard detection card comprises the following steps:

s1, starting hardware fault detection, and judging whether a computer has the sound of a calling call;

s2, detecting whether the memory is normal or not when the computer has the sound of the calling call; the computer detects whether the power supply is plugged well or not when the calling sound does not exist;

s3, detecting whether the power supply is plugged well, wherein the problem still exists after the power supply is plugged well, and replacing the power supply, if not, please plug the power supply;

s4, the memory is normal, the computer is started, the hardware fault detection is finished, the computer is not started, and the keyboard, the mainboard, the memory and the power supply are checked;

s5, the memory is abnormal, whether the buzzer rings or not is observed, the buzzer does not ring, and a computer hardware engineer is consulted;

s6, sounding by a buzzer, wherein the sounding frequency is not less than 3, and please check the keyboard and the mainboard; ringing times are less than 3, and checking the memory bank;

and S7, judging whether the memory bank is loosened or not, inserting the memory bank again without loosening, and replacing the memory bank.

8. The computer hardware fault alarm method of claim 7, wherein: the S3 specifically includes:

s31, after the power supply is replaced, returning the sound of the calling call to the computer for re-detection;

s32, after the power supply is plugged, the sound of the calling call returned to the computer is detected again.

9. The computer hardware fault alarm method of claim 7, wherein: the S4 specifically includes:

s41, after the keyboard, the mainboard, the memory and the power supply are checked, the sound of the calling call is returned to the computer for re-detection.

10. The computer hardware fault alarm method of claim 7, wherein: the S5 specifically includes:

s51, after consulting a computer hardware engineer, returning the computer to detect the sound of the calling call again;

the S6 specifically includes:

s61, after the keyboard and the mainboard are checked, the sound of the calling call returned to the computer is detected again;

the S7 specifically includes:

s71, after the memory bank is replaced, returning the sound of the calling call of the computer to detect again;

and S72, after the memory bank is inserted again, the sound of the calling call returned to the computer is detected again.

Technical Field

The invention relates to the technical field of computer hardware, in particular to a computer hardware fault alarm system and a computer hardware fault alarm method.

Background

Computer hardware (Computerhardware) refers to the general name given to various physical devices in a computer system, consisting of electronic, mechanical, and opto-electronic components, etc. The physical devices form an organic whole according to the requirements of the system structure to provide a material basis for the operation of computer software. Briefly, the computer hardware functions to input and store programs and data, and to execute the programs to manipulate the data into a usable form. When the user needs the data, the data is output in a mode required by the user.

From the appearance, the microcomputer is composed of a main case and external equipment. The main case mainly comprises a CPU, an internal memory, a mainboard, a hard disk drive, an optical disk drive, various expansion cards, a connecting wire, a power supply and the like; the external devices include a mouse, a keyboard, and the like.

Through retrieval, chinese patent No. CN106802835A discloses a computer hardware troubleshooting analysis system, comprising: the hardware fault detection system is electrically connected with the fault analysis system, the fault analysis system comprises an information receiving module, an analysis comparison module and an information output module, the information receiving module, the analysis comparison module and the information output module are sequentially connected, the information output module is electrically connected with a display system, a scheme output module and a display module are arranged in the display system, and the scheme output module is electrically connected with the display module.

Chinese patent No. CN107544875A discloses a computer hardware fault diagnosis system based on FPGA, which includes a data processing circuit; the data processing circuit is connected with the data latch circuit; the data latch circuit is connected with the single chip microcomputer system; the single chip microcomputer system is connected with the liquid crystal display circuit; the data processing circuit is respectively connected with the data decoding circuit, the address decoding circuit, the clock circuit and the state machine control. According to the computer hardware fault diagnosis system based on the FPGA, a signal acquisition and processing circuit is programmed and built on the FPGA, and a hardware circuit is designed on the FPGA by adopting a VHDL (very high speed digital Living description language) hardware description language according to the self power-on self-inspection principle of a computer to realize a series of processing such as data storage, analysis, extraction and the like; the liquid crystal is controlled by the 51 single chip microcomputer to realize the Chinese characters of computer hardware faults.

However, with the continuous development of computer technology, computers have been more and more moved into the work and life of people, while the general consumers have relatively lacked knowledge about the fault diagnosis of various physical devices constituting a computer system and computer hardware providing material basis for the operation of computer software, and when the computer hardware fails, the processing period is long, time is wasted, and work and life are delayed, so that the development of a computer hardware fault alarm system and method is urgently needed.

Disclosure of Invention

The invention aims to provide a computer hardware fault alarm system and a computer hardware fault alarm method, which are used for solving the problems of long processing period, time waste and work and life delay when computer hardware is in fault in the background technology.

The technical scheme of the invention is as follows: the utility model provides a computer hardware fault alarm system, includes data acquisition, alarm controller, LAN and maintenance terminal, data acquisition includes that computer motherboard detects card, storage module and computer hardware, and storage module integration detects the card at computer motherboard, computer motherboard detects the card and inserts PCI or ISA slot back, will show various codes according to the progress of starting from the display screen of taking on the card when starting the computer, the LAN includes GPRS and GSM, maintenance terminal includes display terminal, central host computer and mobile terminal.

Furthermore, the computer mainboard detection card detects a computer hardware circuit and stores fault information into the storage module.

Furthermore, the computer mainboard detection card transmits computer hardware fault information to the alarm controller through the electric signal, and the alarm controller receives the fault electric signal to alarm.

Further, the alarm controller transmits the computer hardware fault information to the display terminal, the central host and the mobile terminal through GPRS and GSM respectively.

Furthermore, computer hardware fault information and a fault solution database are stored in the central host, and the central host can call out the computer hardware fault information and the fault solution database and display the information on the display terminal.

Further, the computer hardware comprises a CPU, a memory, a motherboard, a hard disk drive, an optical disk drive, an expansion card, a connection line, a power supply, a display, a mouse, and a keyboard.

A computer hardware fault alarm method, computer mainboard detection card detection includes the following steps:

s1, starting hardware fault detection, and judging whether a computer has the sound of a calling call;

s2, detecting whether the memory is normal or not when the computer has the sound of the calling call; the computer detects whether the power supply is plugged well or not when the calling sound does not exist;

s3, detecting whether the power supply is plugged well, wherein the problem still exists after the power supply is plugged well, and replacing the power supply, if not, please plug the power supply;

s4, the memory is normal, the computer is started, the hardware fault detection is finished, the computer is not started, and the keyboard, the mainboard, the memory and the power supply are checked;

s5, the memory is abnormal, whether the buzzer rings or not is observed, the buzzer does not ring, and a computer hardware engineer is consulted;

s6, sounding by a buzzer, wherein the sounding frequency is not less than 3, and please check the keyboard and the mainboard; ringing times are less than 3, and checking the memory bank;

and S7, judging whether the memory bank is loosened or not, inserting the memory bank again without loosening, and replacing the memory bank.

Further, the S3 specifically includes:

s31, after the power supply is replaced, returning the sound of the calling call to the computer for re-detection;

s32, after the power supply is plugged, the sound of the calling call returned to the computer is detected again.

Further, the S4 specifically includes:

s41, after the keyboard, the mainboard, the memory and the power supply are checked, the sound of the calling call is returned to the computer for re-detection.

Further, the S5 specifically includes:

s51, after consulting a computer hardware engineer, returning the computer to detect the sound of the calling call again;

the S6 specifically includes:

s61, after the keyboard and the mainboard are checked, the sound of the calling call returned to the computer is detected again;

the S7 specifically includes:

s71, after the memory bank is replaced, returning the sound of the calling call of the computer to detect again;

and S72, after the memory bank is inserted again, the sound of the calling call returned to the computer is detected again.

The invention provides a computer hardware fault alarm system and a method thereof through improvement, compared with the prior art, the invention has the following improvement and advantages:

(1) the computer hardware fault detection system adopts the computer mainboard detection card to detect the computer hardware, and stores the fault detection information into the storage module for backup, meanwhile, the computer mainboard detection card transmits the fault detection information to the alarm controller for alarming, and the alarm controller transmits the fault detection information to the display terminal, the central host and the mobile terminal respectively through GPRS and GSM.

Drawings

The invention is further explained below with reference to the figures and examples:

FIG. 1 is a block diagram of the alarm system of the present invention;

FIG. 2 is a diagram of the alarm processing architecture of the present invention;

FIG. 3 is a diagram of the hardware architecture of the computer of the present invention;

FIG. 4 is a flow chart of the computer hardware detection of the present invention.

Detailed Description

The present invention will be described in detail with reference to fig. 1 to 4, and the technical solutions in the embodiments of the present invention will be clearly and completely described, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention provides a computer hardware fault alarm system through improvement, as shown in fig. 1-4, comprising a data acquisition unit, an alarm controller, a local area network and a maintenance terminal, wherein the data acquisition unit comprises a computer mainboard detection card, a storage module and computer hardware, the storage module is integrated on the computer mainboard detection card, after the computer mainboard detection card is inserted into a PCI or ISA slot, a display screen carried by the card displays various codes according to the starting progress when a computer is started, the local area network comprises GPRS and GSM, and the maintenance terminal comprises a display terminal, a central host and a mobile terminal.

Furthermore, the computer mainboard detection card detects a computer hardware circuit and stores fault information into the storage module.

Further, the computer mainboard detection card transmits computer hardware fault information to an alarm controller through an electric signal, the alarm controller receives the fault electric signal to alarm, and the model of the alarm controller is QLT-68B.

Further, the alarm controller transmits the computer hardware fault information to the display terminal, the central host and the mobile terminal through GPRS and GSM respectively, and the alarm controller transmits the fault information to the mobile terminal through GSM short messages.

Furthermore, the central host stores computer hardware fault information and a fault solution database, and the central host can call the computer hardware fault information and the fault solution database out and display the information on the display terminal.

Further, the computer hardware includes a CPU, a memory, a motherboard, a hard disk drive, an optical disk drive, an expansion card, a connection line, a power supply, a display, a mouse, and a keyboard.

A computer hardware fault alarm method, computer mainboard detection card detection includes the following steps:

s1, starting hardware fault detection, and judging whether a computer has the sound of a calling call;

s2, detecting whether the memory is normal or not when the computer has the sound of the calling call; the computer detects whether the power supply is plugged well or not when the calling sound does not exist;

s3, detecting whether the power supply is plugged well, wherein the problem still exists after the power supply is plugged well, and replacing the power supply, if not, please plug the power supply;

s4, the memory is normal, the computer is started, the hardware fault detection is finished, the computer is not started, and the keyboard, the mainboard, the memory and the power supply are checked;

s5, the memory is abnormal, whether the buzzer rings or not is observed, the buzzer does not ring, and a computer hardware engineer is consulted;

s6, sounding by a buzzer, wherein the sounding frequency is not less than 3, and please check the keyboard and the mainboard; ringing times are less than 3, and checking the memory bank;

and S7, judging whether the memory bank is loosened or not, inserting the memory bank again without loosening, and replacing the memory bank.

Further, S3 specifically includes:

s31, after the power supply is replaced, returning the sound of the calling call to the computer for re-detection;

s32, after the power supply is plugged, the sound of the calling call returned to the computer is detected again.

Further, S4 specifically includes:

s41, after the keyboard, the mainboard, the memory and the power supply are checked, the sound of the calling call is returned to the computer for re-detection.

Further, S5 specifically includes:

s51, after consulting a computer hardware engineer, returning the computer to detect the sound of the calling call again;

s6 specifically includes:

s61, after the keyboard and the mainboard are checked, the sound of the calling call returned to the computer is detected again;

s7 specifically includes:

s71, after the memory bank is replaced, returning the sound of the calling call of the computer to detect again;

and S72, after the memory bank is inserted again, the sound of the calling call returned to the computer is detected again.

Example one

A computer hardware fault alarm method, a computer mainboard detecting card detecting fault code includes:

FF. 00, C0, D0, CF, F1, or nothing indicates that the CPU has failed

C1, C6, C3, D3, D4, D6, D8, B0, A7 and E1 represent the condition of no memory exception

24. 25, 26, 01, 0A, 0B, 2A, 2B, 31 represent no video card

Some integrated display card mainboards 23, 24 and 25 can be normally lighted, some VIA chipset displays 13 can be lighted, some mainboard displays 0B in brands can be normally lighted, some mainboard displays 4E can be normally lighted, and some INTEL chipset mainboard displays 26 or 16 can be normally lighted;

the combined cycle jump of C1, C6, C3, 01, 02 is mostly I/0 bad or flush BIOS

If display 05, ED, 41 then brush BIOS00 directly; configuration of the displayed system; that is, control INI19 is booted in;

1. processor test 1, processor state verification, if the test fails, the loop is infinite; the testing of processor registers is about to start and the non-maskable interrupt is about to be disabled; CPU register testing is ongoing or fails;

2. determining the type of diagnosis (normal or manufacturing); disable if the keyboard buffer contains data; disabling the non-maskable interrupt; by delaying the start; CMOS write/read is in progress or malfunctioning;

3. clearing 8042 the keyboard controller, issuing the TESTKBD command (AAH), and completing the power-on delay; ROMBIOS checks that a component is in progress or malfunctioning;

4. resetting the 8042 keyboard controller and verifying TESTKBRD; a keyboard controller soft reset/power-on test; the testing of the programmable interval timer is ongoing or malfunctioning;

5. if the manufacturing tests 1 to 5 are repeated continuously, the 8042 control state can be obtained; soft reset/power on has been determined; the ROM is to be started; DMA is initially ready to be in progress or malfunctioning;

6. making the die initially ready, disabling the video, parity, DMA die, and clearing the DMA die, all page registers, and CMOS stop bytes; the booted ROM calculates a ROMBIOS checksum and checks whether the keyboard buffer is cleared; DMA initial page register read/write tests are in progress or are malfunctioning;

7. processor test 2, verifying the operation of the CPU register; the ROMBIOS checks that the sum is normal, the keyboard buffer is cleared, and a BAT (basic assurance test) command is issued to the keyboard;

8. making CMOS timer as initial preparation, and updating timer normally; a BAT command has been issued to the keyboard, i.e. is to be written; RAM update checking is ongoing or malfunctioning;

9. EPROM checks the sum and must equal zero to pass; verifying a basic assurance test of the keyboard, and then verifying a keyboard command byte; the first 64KRAM test is in progress;

0A initially prepares the video interface; sending out keyboard command byte codes, namely writing command byte data; the first 64KRAM chip or data line fails, shifts;

0B test 8254 channel 0; writing into keyboard controller command bytes, namely, sending out blocking/unlocking commands of pins 23 and 24; the first 64KRAM odd/even logic failure;

0C test 8254 lane 1; keyboard controller pins 23, 24 are locked/unlocked; a NOP command has been issued; address line failure of the first 64 KRAN;

0D：

1) checking whether the CPU speed is matched with a system clock;

2) checking whether the programmed value of the control chip meets the initial setting;

3) testing a video channel, and if the video channel fails, ringing a horn; a processed NOP command; then testing the CMOS stop register; first parity failure of 64KRAM

0E test CMOS stop byte; CMOS stops the register read/write test; the CMOS checksum will be calculated; initializing an input/output port address;

0F test extended CMOS; the computed CMOS checksum is written into the diagnostic byte; the CMOS starts initial preparation;

10. testing DMA channel 0; the CMOS is initially prepared, and a CMOS state register is to initially prepare for date and time; the first 64KRAM bit 0 fault;

11. testing the DMA channel 1; the CMOS status register is initially prepared, i.e., the DMA and interrupt controllers are to be disabled; the first 64DKRAM bit 1 failure;

12. testing a DMA page register; disabling the DMA controller 1 and the interrupt controllers 1 and 2; i.e., the video display and initially prepare port B; the first 64DKRAM bit 2 failure;

13. testing 8741 the keyboard controller interface; the video display has been disabled and port B has been initially prepared; will begin die initialization/memory auto-detection; the first 64DKRAM bit 3 failure;

14. testing a memory update trigger circuit; the auto-detect at die initialization/memory ends; 8254 timer test is about to start; the first 64DKRAM bit 4 failure;

15. testing the system memory of the first 64K; channel 2 timer tested half; 8254 the 2 nd channel timer is about to complete; first 64DKRAM bit 5 failure;

16. establishing 8259 an interrupt vector table; the 2 nd channel timer test is finished; 8254 the 1 st channel timer is about to complete; the first 64DKRAM bit 6 failure;

17. adjusting video input/output work, and starting if a video BIOS is installed; the 1 st channel timer test is finished; 8254 the 0 th channel timer is about to complete the test; the first 64DKRAM bit 7 failure;

18. testing the video memory, and if the selected video BIOS is installed to pass through, the video memory can be bypassed; the 0 th channel timer test is finished; will begin updating the memory; the first 64DKRAM bit 8 failure;

19. testing an interrupt controller (8259) mask bit for lane 1; the updating of the memory has already started and will then be completed; the first 64DKRAM bit 9 failed;

1A testing the interrupt controller (8259) mask bit for lane 2; the memory refresh line is being triggered, i.e. 15 microsecond on/off time is to be checked; the first 64DKRAM bit 10 failure;

1B testing the level of the CMOS battery; completing the 30 microsecond test of the updating time of the memory; the basic 64K memory test is about to begin; the first 64DKRAM 11 th bit failed;

1C testing the CMOS inspection sum; the first 64DKRAM bit 12 failure;

1D setting the CMOS configuration; the first 64DKRAM bit 13 failure;

1E determining the size of the system memory and comparing it to the CMOS value; the first 64DKRAM 14 th bit failed;

1F testing 64K memory up to 640K; the first 64DKRAM bit 15 failure;

20. measuring a fixed 8259 discontinuity; starting a basic 64K memory test; testing an address line; slave DMA register tests are in progress or malfunctioning;

21. maintaining unmaskable interrupt (NMI) bits (parity or input/output channel checking); passing the address line test; will trigger parity; the main DMA register test is in progress or malfunctioning;

22. test 8259 interrupt function; end trigger parity; serial data read/write testing will begin; the master interrupt mask register tests are ongoing or malfunctioning;

23. testing the 8086 virtual mode and 8086 page mode of the protection mode; the basic 64K serial data read/write test is normal; any adjustments immediately prior to initiation of interrupt vector initialization; the slave interrupt mask latch test is in progress or malfunctioning;

24. measuring an extended memory of 1MB or more; any adjustments prior to vector initialization are complete, i.e., initial preparation of the interrupt vector is to begin; setting an ES segment address register registry to a high end of a memory;

25. testing all memories except the first 64K; completing initial preparation of an interrupt vector; the input/output port of 8042 will be read for the beginning of a rotary discontinuity; loading an interrupt vector is ongoing or malfunctioning;

26. testing exceptional conditions of the protection mode; readout 8042 input/output ports; the global data is initially prepared for the start of the rotary type interruption; turning on the A20 address line; making it participate in addressing;

27. determining a control or mask RAM for the cache memory; finishing initial preparation of all 1 data; any initial preparation after the interrupt vector will then be done; the keyboard controller tests are in progress or are out of order;

28. determining the control of the cache or the specific 8042 keyboard controller; initial preparation after completing the interrupt vector; setting a monochrome mode; CMOS power failure/checksum calculation is ongoing;

29. setting a monochrome mode, namely setting a color mode; a check of the validity of the CMOS configuration is ongoing;

2A making the keyboard controller to make initial preparation; the set color mode, namely the trigger parity before the ROM test is carried out; emptying a 64K basic memory;

2B making the disk drive and controller initially ready; triggering parity to end; i.e. any adjustments required before controlling the optional video ROM check; screen memory tests are ongoing or malfunctioning;

2C checking the serial port and making it initially ready; processing before completing video ROM control; the optional video ROM is to be viewed and controlled; screen initial preparation is in progress or malfunctioning;

2D detecting the parallel port and making the parallel port initially prepared; optional video ROM control has been completed, i.e., control of any other processing immediately after the video ROM return control is performed; screen kickback testing is ongoing or malfunctioning;

2E initially preparing the hard disk drive and controller; recovery from processing after video ROM control; if no EGA/VGA is found, a display memory read/write test is carried out; detecting that a video ROM is in progress;

2F detecting the math coprocessor and making it as initial preparation; no EGA/VGA was found; a display memory read/write test is about to start;

30. establishing a basic memory and an extended memory; passing a display memory read/write test; scanning inspection is to be carried out; the screen is considered to be operational;

31. detection was performed from C800: 0 to EFFF: 0, selecting ROM, and making it as initial preparation; if the read/write test or the scanning check of the display memory fails, another read/write test of the display memory is to be performed; a monochrome monitor is operable;

32. programming I/O chips such as COM/LTP/FDD/sound equipment on the mainboard to be suitable for a set value; passing another display memory read/write test; but will perform another display scan check; the color monitor (column 40) is operational;

33. the video display checks for completion; the off-type of the display will be checked by using the regulating switch and the actual card insertion; a color monitor (80 columns) is operable;

34. a verified display adapter; setting a display mode; timer tick interrupt testing is ongoing or malfunctioning;

35. completing setting the display mode; the data area of the BIOSROM is to be checked; shutdown tests are ongoing or malfunctioning;

36. checked bios rom data area; a cursor for setting the power-on information; a-20 failure in the gate circuit;

37. identifying that cursor setting of the power-on information is complete; the power-on information is to be displayed; an unexpected interruption in the protection mode;

38. completing displaying the power-on information; a new cursor position is to be read; RAM testing is ongoing or address failure > FFFFH;

39. the position of the cursor is read out and stored, and a quote information string is to be displayed;

the 3A reference information string display is finished; displaying ESC information; interval timer channel 2 tests or fails;

3B initially prepares the auxiliary cache memory with OPTI circuit slices (486 only); it has been shown that < ESC > information is found; virtual mode, memory test is about to start; calendar clock testing on a daily basis is ongoing or malfunctioning;

3C sets up a flag to allow access to the CMOS setting; serial port testing is ongoing or malfunctioning;

3D initializes keyboard/PS 2 mouse/PNP device and total memory node; parallel port testing is ongoing or malfunctioning; 3E attempts to open the L2 cache; math co-processor testing is ongoing or malfunctioning;

40. the test of preparing a virtual mode has already been started; to be checked from video memory; adjusting the speed of the CPU to be accurately matched with a peripheral clock;

41. the interrupt is open, the data will be initialized so that 0: 0 detects memory transitions (interrupt controller or bad memory) are recovered after the video memory is verified; preparing a descriptor table; system card selection fails;

42. displaying window entering SETUP; the descriptor table is ready; performing a memory test in a virtual mode; expanding CMOSRAM failures;

43. if the BIOS is plugged and used, initializing a serial port and a parallel port; entering a virtual mode; namely, realizing interruption for the diagnosis mode;

44. BIOS interrupts are initialized when an interrupt is implemented (e.g., diagnostic switch is turned on; data is to be initially prepared to check for memory wrap at 0: 0; BIOS interrupts are initialized);

45. initializing a math coprocessor; the data is initially prepared; i.e. checking the memory at 0: 0 wrap and find the size of the system memory;

46. the test memory has returned; after the size of the memory is calculated, the memory is written into a page to test the memory; checking the ROM version of the read only memory;

47. trying to write a page in the expanded memory; i.e., writing substantially 640K of memory to a page;

48. the base memory has been written to a page; a memory that is to be determined to be 1MB or more; video inspection, CMOS reconfiguration;

49. finding out the memory below 1BM and checking; a memory that is to be determined to be 1MB or more;

4A, finding out a memory with the volume of more than 1MB and checking; the BIOSROM data area is checked; initializing a video;

the 4BBIOSROM data area is checked to be less than ESC and the memory above 1MB is cleared for soft reset;

4C clear 1MB or more of memory (soft reset) i.e. 1MB or more of memory is to be cleared; a mask video BIOSROM;

4D has cleared more than 1MB of memory (soft reset); the size of the memory will be preserved;

4E, if an error is detected; displaying error information on the display, and waiting for the client to press the < F1 > key to continue; start the test of the memory: (no soft reset); a test that will show the first 64K memory; displaying copyright information;

4F, reading and writing soft and hard disk data, and performing DOS (disk operating system) guidance; starting to display the size of the memory, which is to be updated by the memory under test; serial and random memory tests are to be performed;

50. storing the CMOS value in the current BIOS monitoring time zone into the CMOS; completing the memory test below 1 MB; i.e. the size of the high speed memory for relocation and masking; sending the CPU type and speed to a screen;

51. testing 1MB or more of memory;

52. initializing all ISA read-only memories (ROMs), and finally allocating IRQ numbers to the PCIs and the like; memory testing above 1MB has been completed; preparing to return to the real address mode; entering keyboard detection;

53. if the BIOS is not plug-and-play BIOS, initializing a serial port, a parallel port and setting a time seed value; the sizes of a CPU register and a memory are saved, and a real address mode is entered;

54. successfully starting the real address mode; a register to be saved when recovery is to be prepared for shutdown; scanning the 'strike key';

55. the register is reset and the address line of gate A-20 will be disabled;

56. successfully disabling the address line of A-20; the BIOSROM data area is checked; the keyboard test is finished;

57. the BIOSROM data area is half checked; continuing the operation;

58. the checking of the data area of the BIOSROM is finished; clear found < ESC > message; an unset interrupt test;

59. cleared < ESC > message; the information is displayed; the test of the DMA and the interrupt controller is about to start;

the 5A display is set by pressing the "F2" key;

5B testing the basic memory address;

5C testing 640K basic memory;

60. setting a virus protection function of a boot sector of a hard disk; testing through a DMA page register; the video memory is to be inspected; testing the extended memory;

61. displaying a system configuration table; the video memory is checked to be finished; testing the DMA # 1 basic register;

62. start system boot with interrupt 19H; testing through DMA # 1 basic register; testing the DMA # 2 register; testing the extended memory address line;

63. testing through DMA # 2 basic register; the BIOSROM data area is checked;

64. half of the BIOSROM data area is checked and the process is continued;

65. the checking of the BIOSROM data area is finished; the DMA devices 1 and 2 will be programmed;

66. the DMA devices 1 and 2 end programming; the number 59 interrupt controller is used for initial preparation; optimally configuring a Cache registry;

67. 8259 the initial preparation has ended; starting a keyboard test;

68. enabling the external Cache and the internal Cache of the CPU to work;

6A, testing and displaying an external Cache value;

6C displaying the masked content;

6E displaying the auxiliary configuration information;

69. sending the detected error code to a screen for display;

70. detecting whether the configuration is wrong;

71. testing a real-time clock;

72. scanning for keyboard errors;

7A lock keyboard;

7C, setting a hardware interrupt vector;

7E testing whether a math processor is installed;

73. starting the keyboard test, clearing and checking whether the key is clamped or not, namely restoring the keyboard; turning off the programmable input/output device;

74. finding out the wrongly stuck key of the keyboard restoration; will send out the test command of the keyboard control port;

75. when the keyboard controller interface test is finished, command bytes are written and the circular buffer is initially prepared; detecting and installing a fixed RS232 interface (serial port);

76. the command byte is written, and the initial preparation of the global data is completed; that is, whether the key is locked or not is checked;

77. whether the key is locked or not is checked, namely whether the memory is mismatched with the CMOS is checked; detecting and installing a fixed parallel port;

78. the size of the checked memory; that is, a soft error and password or bypass arrangement is to be displayed;

79. the password has been checked; programming just prior to a bypass schedule; reopening the programmable I/O device and detecting whether the fixed I/O has conflict;

80. completing programming before arrangement; programming of the CMOS arrangement will be performed;

81. restoring a clean screen from the CMOS scheduler; the following programming is to be performed; initializing a BIOS data area;

82. completing the arranged programming; displaying power-on screen information;

8A displays the first screen information; initializing an extended BIOS data area;

8B shows the information: i.e. to mask the main and video BIOS;

8C successfully masks the main and video BIOS, programming of post CMOS scheduling options will begin; initializing a floppy drive controller;

8D options programming has been scheduled, followed by inspection for mice slippage and initial preparation;

8E detecting the mouse and completing the initial preparation; i.e. the hard and floppy disks will be reset;

the 8F diskette has been inspected, the diskette will be prepared initially, then the diskette is prepared;

83. finishing the configuration of the soft magnetic disc; will test for the presence of a hard disk; initializing a hard disk controller;

84. ending the hard disk existence test; then, configuring a hard disk; initializing a local bus hard disk controller;

85. completing the configuration of the hard disk; the data area of the BIOSROM is to be checked; jumping to a user path 2;

86. the data area of the BIOSROM is half checked; continuing the operation;

87. setting the size of the basic and extended memories after the data area of the BIOSROM is checked; turning off the A-20 address line;

88. the size of the memory is adjusted according to the support of mouse and hard disk 47; a soon to be verified display memory;

89. restoring after checking the display memory; to be performed with C800: initial preparation before 0 option ROM control; the "ES segment" registry is cleared;

90. c800: any initial preparation before option-ROM control 0 is finished, followed by check and control of option-ROM;

91. the control of the option ROM is completed; any processing required immediately after option ROM resume control; searching ROM selection;

92. any initial preparation required after the option ROM test is complete; a data area or a printer basic address where a timer is to be established;

93. return operation after setting timer and printer basic address; setting an RS-232 basic address; mask ROM selection;

94. return after RS-232 base address; initial preparation of coprocessor test is to be performed;

95. finishing initial preparation before testing the coprocessor; then making the coprocessor make initial preparation; establishing power supply energy-saving management;

96. the coprocessor makes initial preparation, namely any initial preparation after the coprocessor is tested;

97. initial preparation after completion of the coprocessor will check the extended keyboard, keyboard identifiers, and number locks; opening a hardware interrupt;

98. when the extended keyboard is checked, the identification mark is set, and the digital lock is switched on or off, a keyboard identification command is sent out;

a0 sends out keyboard identification command; the keyboard identification mark is to be restored; setting time and date;

a1 keyboard identification mark is recovered; then testing the cache memory;

the A2 cache test is finished; any soft errors will be displayed; checking the keyboard lock;

a3 soft error display is finished; setting the speed of keyboard striking;

a4, adjusting the striking rate of the keyboard, namely setting the waiting state of the memory; initializing a repeated input rate of the keyboard;

a5 finishing the preparation of the waiting state of the memory; then the screen is cleared;

the A6 screen has been cleared; will initiate parity and unmaskable interrupts;

a7 has enabled unmaskable interrupts and parity; the optional ROM to be controlled is set at E000: any initial preparation required for 0;

a8 controls ROM at E000: the initial preparation before 0 ends, and then the control E000: any initial preparation required after 0; clearing the "F2" key tip;

a9 is determined from control E000: 0ROM return, i.e., control E000: any initial preparation required after 0 option ROM;

AA in E000: initial preparation after 0 controls option ROM ends; i.e. the configuration of the display system; scanning the striking of the F2 key;

an AC entry setting;

AE clears the power-on self-inspection mark;

b0 checking for noncritical errors;

b2 power-on self-check is completed to prepare for entering the operating system to boot;

b4 buzzer sounds one sound;

b6 detecting password settings (optional);

b8 clearing all description tables;

BC clearing the check value;

the BE program default value enters a control chip and accords with a modulatable binary default value table; clear screen (optional);

BF testing CMOS establishment value; detecting virus and prompting to make data backup;

c0 initializes the cache; pilot with interrupt 19;

c1 memory self-checking; searching for a mark of '55' or 'AA' in the guide sector;

c3 first 256K memory test;

c5 copying BIOS from ROM to make quick self-check;

c6 cache self-check;

the CA checks the Micronies overspeed buffer memory (if present) and makes initial preparation;

the CC shuts down the non-maskable interrupt handler.

The working principle is as follows: computer mainboard detection card detects computer hardware to store the fault detection information in storage module and backup, computer mainboard detection card simultaneously gives the alarm controller with fault detection information transmission and reports to the police, and alarm controller passes through GPRS and GSM and gives the display terminal with fault detection information respectively, central host computer and mobile terminal, at this moment, central host computer can be transferred out computer hardware fault information and trouble solution database and show at display terminal, thereby can overcome when computer hardware breaks down, the processing cycle is long, waste time, hinder the problem of work and life.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.