阅读说明：本技术 显示装置 (Display device ) 是由 中川贵史 池田隆之 小林英智 宍户英明 胜井秀一 木村清贵 于 2020-04-28 设计创作，主要内容包括：提供一种被窄边框化了的显示装置。显示装置包括彼此重叠的第一层、第二层以及第三层,第一层包括栅极驱动电路及数据驱动电路,第二层包括解复用电路,第三层包括显示部,在显示部中像素排列为矩阵形状,解复用电路的输入端子与数据驱动电路电连接,解复用电路的输出端子与像素电连接,栅极驱动电路及数据驱动电路包括与像素重叠的区域,栅极驱动电路及数据驱动电路不明确地分开而具有彼此重叠的区域,并且栅极驱动电路及数据驱动电路的个数可以都为五个以上。(Provided is a display device having a narrowed frame. The display device includes a first layer, a second layer, and a third layer which overlap with each other, the first layer including a gate driver circuit and a data driver circuit, the second layer including a demultiplexer circuit, the third layer including a display portion in which pixels are arranged in a matrix shape, an input terminal of the demultiplexer circuit being electrically connected to the data driver circuit, an output terminal of the demultiplexer circuit being electrically connected to the pixels, the gate driver circuit and the data driver circuit including regions which overlap with the pixels, the gate driver circuit and the data driver circuit being not clearly separated and having regions which overlap with each other, and the number of the gate driver circuit and the data driver circuit may be five or more.)

1. A display device, comprising:

a first layer, a second layer and a third layer overlapping each other,

wherein the first layer comprises a gate driving circuit and a data driving circuit,

the second layer includes a de-multiplexing circuit,

the third layer includes a display portion and a display portion,

the pixels are arranged in a matrix shape in the display section,

the input terminal of the demultiplexing circuit is electrically connected to the data driving circuit,

the output terminals of the demultiplexing circuit are electrically connected to the pixels,

the gate driving circuit includes a region overlapping the pixel,

the data driving circuit includes a region overlapping the pixel,

and, the gate driving circuit includes a region overlapping with the data driving circuit.

2. The display device according to claim 1, wherein the first and second light sources are arranged in a matrix,

wherein the demultiplexing circuit includes a region overlapping the pixel.

3. The display device according to claim 1 or 2, further comprising a D/A conversion circuit,

wherein the D/A conversion circuit comprises a potential generation circuit and a pass transistor logic circuit,

the potential generating circuit is provided outside the data driving circuit,

the pass transistor logic circuit is disposed in the data driving circuit,

The number of the transfer transistor logic circuits provided in the D/a conversion circuit is smaller than the number of columns of the pixels provided in the display section,

the number of the potential generating circuits provided in the D/a conversion circuit is smaller than the number of the transfer transistor logic circuits,

the potential generating circuit generates a plurality of potentials at different levels,

and the transfer transistor logic circuit receives image data and outputs any one of the plurality of potentials generated by the potential generation circuit based on a digital value of the image data.

4. The display device according to claim 3, wherein the first and second light sources are arranged in a matrix,

the number of the transmission transistor logic circuits is less than one half of the column number of the pixels.

5. The display device according to any one of claims 1 to 4,

wherein the pixel includes a transistor containing a metal oxide in a channel formation region,

and the metal oxide contains In, an element M (M is Al, Ga, Y or Sn), and Zn.

6. A display device, comprising:

a first layer, a second layer and a third layer overlapping each other,

wherein the first layer comprises a gate driving circuit, a first data driving circuit, a second data driving circuit, a third data driving circuit, a fourth data driving circuit, and a fifth data driving circuit,

The second layer includes a first demultiplexing circuit, a second demultiplexing circuit, a third demultiplexing circuit, a fourth demultiplexing circuit, and a fifth demultiplexing circuit,

the third layer comprises a first display part, a second display part, a third display part, a fourth display part and a fifth display part,

the first pixels are arranged in a matrix shape in the first display section,

the second pixels are arranged in a matrix shape in the second display section,

third pixels are arranged in a matrix shape in the third display section,

fourth pixels are arranged in a matrix shape in the fourth display section,

fifth pixels are arranged in a matrix shape in the fifth display section,

an input terminal of the first demultiplexing circuit is electrically connected to the first data driving circuit,

an input terminal of the second demultiplexing circuit is electrically connected to the second data driving circuit,

an input terminal of the third demultiplexing circuit is electrically connected to the third data driving circuit,

an input terminal of the fourth demultiplexing circuit is electrically connected to the fourth data driving circuit,

an input terminal of the fifth demultiplexing circuit is electrically connected to the fifth data driving circuit,

an output terminal of the first demultiplexing circuit is electrically connected to the first pixel,

An output terminal of the second demultiplexing circuit is electrically connected to the second pixel,

an output terminal of the third demultiplexing circuit is electrically connected to the third pixel,

an output terminal of the fourth demultiplexing circuit is electrically connected to the fourth pixel,

an output terminal of the fifth demultiplexing circuit is electrically connected to the fifth pixel,

the gate driving circuit includes a region overlapping the first pixel,

the first data driving circuit includes a region overlapping the first pixel,

the second data driving circuit includes a region overlapping the second pixel,

the third data driving circuit includes a region overlapping with the third pixel,

the fourth data driving circuit includes a region overlapping with the fourth pixel,

the fifth data driving circuit includes a region overlapping with the fifth pixel,

and, the gate driving circuit includes a region overlapping with the first data driving circuit.

7. The display device according to claim 6, wherein the first and second light sources are arranged in a matrix,

wherein the first demultiplexing circuit includes a region overlapping the first pixel,

the second demultiplexing circuit includes a region overlapping the second pixel,

The third demultiplexing circuit includes a region overlapping the third pixel,

the fourth demultiplexing circuit includes a region overlapping the fourth pixel,

and the fifth demultiplexing circuit includes a region overlapping with the fifth pixel.

8. The display device according to claim 6 or 7, further comprising a D/A conversion circuit,

wherein the D/A conversion circuit includes a potential generation circuit, a first transfer transistor logic circuit, a second transfer transistor logic circuit, a third transfer transistor logic circuit, a fourth transfer transistor logic circuit, and a fifth transfer transistor logic circuit,

the potential generating circuit is provided outside the first to fifth data driving circuits,

the first pass transistor logic circuit is disposed in the first data driver circuit,

the second pass transistor logic circuit is disposed in the second data driver circuit,

the third pass transistor logic circuit is disposed in the third data driver circuit,

the fourth pass transistor logic circuit is disposed in the fourth data driver circuit,

the fifth pass transistor logic circuit is disposed in the fifth data driver circuit,

The number of the first transfer transistor logic circuits provided in the D/a conversion circuit is smaller than the number of columns of the first pixels provided in the first display section,

the number of the second transfer transistor logic circuits provided in the D/a conversion circuit is smaller than the number of columns of the second pixels provided in the second display section,

the number of the third transfer transistor logic circuits provided in the D/a conversion circuit is smaller than the number of columns of the third pixels provided in the third display section,

the number of the fourth transfer transistor logic circuits provided in the D/a conversion circuit is smaller than the number of columns of the fourth pixels provided in the fourth display section,

the number of the fifth transfer transistor logic circuits provided in the D/a conversion circuit is smaller than the number of columns of the fifth pixels provided in the fifth display section,

the number of the potential generating circuits provided in the D/a conversion circuit is smaller than the number of the first transfer transistor logic circuits,

the number of the potential generating circuits provided in the D/a conversion circuit is smaller than the number of the second transfer transistor logic circuits,

The number of the potential generating circuits provided in the D/a conversion circuit is smaller than the number of the third transfer transistor logic circuits,

the number of the potential generating circuits provided in the D/a conversion circuit is smaller than the number of the fourth transfer transistor logic circuits,

the number of the potential generating circuits provided in the D/a conversion circuit is smaller than the number of the fifth transfer transistor logic circuits,

the potential generating circuit generates a plurality of potentials at different levels,

and the first to fifth transfer transistor logic circuits receive image data and output any one of the plurality of potentials generated by the potential generation circuit based on a digital value of the image data.

9. The display device according to claim 8, wherein the first and second light sources are arranged in a matrix,

wherein the number of the first pass transistor logic circuits is less than one of two minutes of the number of columns of the first pixels,

the number of the second pass transistor logic circuits is less than one of two minutes of the number of columns of the second pixels,

the number of the third pass transistor logic circuits is less than one of two minutes of the number of columns of the third pixels,

the number of the fourth pass transistor logic circuits is less than one of two minutes of the number of columns of the fourth pixels,

And the number of the fifth transfer transistor logic circuits is less than one of two halves of the number of the columns of the fifth pixels.

10. The display device according to any one of claims 6 to 9,

wherein the first to fifth pixels include transistors containing a metal oxide in a channel formation region,

and the metal oxide contains In, an element M (M is Al, Ga, Y or Sn), and Zn.

Technical Field

One embodiment of the present invention relates to a display device.

Note that one embodiment of the present invention is not limited to the above-described technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, an illumination device, an input/output device, and a driving method or a manufacturing method of these devices. The semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics.

Background

As a semiconductor material which can be used for a transistor, an oxide semiconductor using a metal oxide has attracted attention. For example, patent document 1 discloses the following semiconductor device: a semiconductor device in which a plurality of oxide semiconductor layers are stacked, wherein an oxide semiconductor layer serving as a channel of the plurality of oxide semiconductor layers contains indium and gallium, and the content ratio of indium is higher than that of gallium, so that field-effect mobility (which may be simply referred to as mobility or [ mu ] FE) is improved.

Since the metal oxide which can be used for the semiconductor layer can be formed by a sputtering method or the like, it can be used for a semiconductor layer of a transistor which constitutes a large-sized display device. Further, since a part of the manufacturing equipment for transistors using polysilicon or amorphous silicon can be improved and utilized, equipment investment can be suppressed. Further, a transistor using a metal oxide has high field-effect mobility compared with a transistor using amorphous silicon, so that a high-function display device provided with a driver circuit can be realized.

In addition, wearable display devices and fixed display devices have become popular as display devices for Augmented Reality (AR) or Virtual Reality (VR). Examples of wearable Display devices include Head Mounted Displays (HMDs) and glasses type Display devices. Examples of the fixed Display device include a Head-Up Display (HUD).

Further, a digital camera or the like as an electronic apparatus having an image pickup device is provided with a viewfinder for confirming an image to be photographed before photographing, and the electronic viewfinder is used for the viewfinder. The electronic viewfinder is provided with a display portion on which an image captured by the imaging device can be displayed as an image. For example, patent document 2 discloses an electronic viewfinder capable of obtaining good visibility continuously from the center portion of an image to the edge portion of the image.

[ Prior Art document ]

[ patent document ]

[ patent document 1] Japanese patent application laid-open No. 2014-7399

[ patent document 2] Japanese patent application laid-open No. 2012-42569

Disclosure of Invention

Technical problem to be solved by the invention

A display device such as a Head Mounted Display (HMD) having a display surface close to a user has the following problems: the user is more likely to see the pixels and may feel a strong grainy feel, sometimes reducing the immersion or presence of the AR or VR. Further, the electronic viewfinder includes an eyepiece portion, as in the optical viewfinder, and the user's eyes approach the eyepiece portion to confirm an image displayed on the display portion of the electronic viewfinder. Therefore, the display portion of the electronic viewfinder is close to the user. Thus, a user can easily see the pixels provided in the display portion and can feel a strong graininess. Accordingly, a display device having fine pixels is required as an HMD and an electronic viewfinder. For example, the pixel density is preferably 1000ppi or more, more preferably 2000ppi or more, and further preferably 5000ppi or more. Further, the display device provided in the electronic viewfinder is preferably capable of displaying a clear image of 4K (the number of pixels is 3840 × 2160), 5K (the number of pixels is 5120 × 2880), or higher, for example.

On the other hand, in the case where the pixel density is high, it is necessary to integrally provide a transistor and the like in a driver circuit such as a data driver circuit and the like at high density. However, since high-density integration is limited, the occupied area of the data driving circuit with respect to the area of the display portion may increase. This results in an increase in the bezel which is an area without a display portion.

An object of one embodiment of the present invention is to provide a display device having a narrow frame. Another object of one embodiment of the present invention is to provide a small display device. Another object of one embodiment of the present invention is to provide a display device with a high degree of freedom in layout. Another object of one embodiment of the present invention is to provide a display device with high pixel density. Another object of one embodiment of the present invention is to provide a display device capable of displaying a high-definition image. Another object of one embodiment of the present invention is to provide a display device capable of displaying a high-quality image. Another object of one embodiment of the present invention is to provide a display device capable of displaying an image with a high realistic sensation. Another object of one embodiment of the present invention is to provide a display device capable of displaying a high-luminance image. Another object of one embodiment of the present invention is to provide a display device which operates at high speed. Another object of one embodiment of the present invention is to provide a display device with low power consumption. Another object of one embodiment of the present invention is to provide a display device which is inexpensive. Another object of one embodiment of the present invention is to provide a highly reliable display device. Another object of one embodiment of the present invention is to provide a novel display device. Another object of one embodiment of the present invention is to provide a method for operating the display device. It is another object of an embodiment of the present invention to provide an electronic device including the display device.

Note that the description of these objects does not hinder the existence of other objects. Note that one mode of the present invention is not required to achieve all the above-described objects. The other objects than the above can be derived from the description of the specification, the drawings, the claims, and the like.

Means for solving the problems

One embodiment of the present invention is a display device including a first layer, a second layer, and a third layer which overlap with each other, the first layer including a gate driver circuit and a data driver circuit, the second layer including a demultiplexer circuit, the third layer including a display portion in which pixels are arranged in a matrix shape, input terminals of the demultiplexer circuit being electrically connected to the data driver circuit, output terminals of the demultiplexer circuit being electrically connected to the pixels, the gate driver circuit including a region overlapping with the pixels, the data driver circuit including a region overlapping with the pixels, and the gate driver circuit including a region overlapping with the data driver circuit.

Further, in the above-described manner, the demultiplexing circuit may also include a region overlapping with the pixel.

Further, in the above-described mode, the display device may further include a D/a conversion circuit which may include a potential generation circuit and a transfer transistor logic circuit, the potential generation circuit may be provided outside the data driving circuit, the transfer transistor logic circuit may be provided in the data driving circuit, the number of the transfer transistor logic circuits provided in the D/a conversion circuit may be smaller than the number of columns of pixels provided in the display portion, the number of the potential generation circuits provided in the D/a conversion circuit may be smaller than the number of the transfer transistor logic circuits, the potential generation circuit may have a function of generating a plurality of potentials at different levels, and the transfer transistor logic circuit may have a function of receiving image data and outputting any one of a plurality of potentials generated by the potential generation circuit based on a digital value of the image data.

In the above aspect, the number of the transfer transistor logic circuits may be one-half or less of the number of the columns of the pixels.

In addition, In the above aspect, the pixel may include a transistor including a metal oxide In the channel formation region, and the metal oxide may include In, an element M (M is Al, Ga, Y, or Sn), and Zn.

In addition, one embodiment of the present invention is a display device including a first layer, a second layer, and a third layer which overlap with each other, the first layer including a gate driver circuit, a first data driver circuit, a second data driver circuit, a third data driver circuit, a fourth data driver circuit, and a fifth data driver circuit, the second layer including a first demultiplexer circuit, a second demultiplexer circuit, a third demultiplexer circuit, a fourth demultiplexer circuit, and a fifth demultiplexer circuit, the third layer including a first display portion in which first pixels are arranged in a matrix shape, a second display portion in which second pixels are arranged in a matrix shape, a third display portion in which third pixels are arranged in a matrix shape, and a fifth display portion in which fourth pixels are arranged in a matrix shape, in the fifth display section, the fifth pixels are arranged in a matrix shape, the input terminal of the first demultiplexing circuit is electrically connected to the first data driving circuit, the input terminal of the second demultiplexing circuit is electrically connected to the second data driving circuit, the input terminal of the third demultiplexing circuit is electrically connected to the third data driving circuit, the input terminal of the fourth demultiplexing circuit is electrically connected to the fourth data driving circuit, the input terminal of the fifth demultiplexing circuit is electrically connected to the fifth data driving circuit, the output terminal of the first demultiplexing circuit is electrically connected to the first pixel, the output terminal of the second demultiplexing circuit is electrically connected to the second pixel, the output terminal of the third demultiplexing circuit is electrically connected to the third pixel, the output terminal of the fourth demultiplexing circuit is electrically connected to the fourth pixel, the output terminal of the fifth demultiplexing circuit is electrically connected to the fifth pixel, the gate driving circuit includes a region overlapping with the first pixel, the first data driving circuit includes a region overlapping the first pixel, the second data driving circuit includes a region overlapping the second pixel, the third data driving circuit includes a region overlapping the third pixel, the fourth data driving circuit includes a region overlapping the fourth pixel, the fifth data driving circuit includes a region overlapping the fifth pixel, and the gate driving circuit includes a region overlapping the first data driving circuit.

Further, in the above manner, the first demultiplexing circuit may include a region overlapping the first pixel, the second demultiplexing circuit may include a region overlapping the second pixel, the third demultiplexing circuit may include a region overlapping the third pixel, the fourth demultiplexing circuit may include a region overlapping the fourth pixel, and the fifth demultiplexing circuit may include a region overlapping the fifth pixel.

Further, in the above-described manner, the display device may further include a D/a conversion circuit, the D/a conversion circuit may include a potential generation circuit, a first transfer transistor logic circuit, a second transfer transistor logic circuit, a third transfer transistor logic circuit, a fourth transfer transistor logic circuit, and a fifth transfer transistor logic circuit, the potential generation circuit may be provided outside the first to fifth data driving circuits, the first transfer transistor logic circuit may be provided in the first data driving circuit, the second transfer transistor logic circuit may be provided in the second data driving circuit, the third transfer transistor logic circuit may be provided in the third data driving circuit, the fourth transfer transistor logic circuit may be provided in the fourth data driving circuit, the fifth transfer transistor logic circuit may be provided in the fifth data driving circuit, the number of first transfer transistor logic circuits provided in the D/a conversion circuit may be smaller than the number of columns of the first pixels provided in the first display portion, the number of second transfer transistor logic circuits provided in the D/a conversion circuit may be smaller than the number of columns of the second pixels provided in the second display portion, the number of third transfer transistor logic circuits provided in the D/a conversion circuit may be smaller than the number of columns of the third pixels provided in the third display portion, the number of fourth transfer transistor logic circuits provided in the D/a conversion circuit may be smaller than the number of columns of the fourth pixels provided in the fourth display portion, the number of fifth transfer transistor logic circuits provided in the D/a conversion circuit may be smaller than the number of columns of the fifth pixels provided in the fifth display portion, and the number of potential generation circuits provided in the D/a conversion circuit may be smaller than the number of columns of the first transfer transistor logic circuits The number of potential generating circuits provided in the D/a conversion circuit may be smaller than the number of second transfer transistor logic circuits, the number of potential generating circuits provided in the D/a conversion circuit may be smaller than the number of third transfer transistor logic circuits, the number of potential generating circuits provided in the D/a conversion circuit may be smaller than the number of fourth transfer transistor logic circuits, the number of potential generating circuits provided in the D/a conversion circuit may be smaller than the number of fifth transfer transistor logic circuits, the potential generating circuits may have a function of generating a plurality of potentials at different levels, and the first to fifth transfer transistor logic circuits may have a function of receiving image data and outputting any one of a plurality of potentials generated by the potential generation circuit based on a digital value of the image data.

In addition, in the above aspect, the number of the first transfer transistor logic circuits may be one or less of two times the number of columns of the first pixels, the number of the second transfer transistor logic circuits may be one or less of two times the number of columns of the second pixels, the number of the third transfer transistor logic circuits may be one or less of two times the number of columns of the third pixels, the number of the fourth transfer transistor logic circuits may be one or less of two times the number of columns of the fourth pixels, and the number of the fifth transfer transistor logic circuits may be one or less of two times the number of columns of the fifth pixels.

In addition, In the above aspect, the first to fifth pixels may include a transistor including a metal oxide In a channel formation region, and the metal oxide may include In, an element M (M is Al, Ga, Y, or Sn), and Zn.

Effects of the invention

According to one embodiment of the present invention, a display device having a narrow bezel can be provided. Further, according to an embodiment of the present invention, a small display device can be provided. Further, according to one embodiment of the present invention, a display device with a high degree of freedom in layout can be provided. Further, according to one embodiment of the present invention, a display device with high pixel density can be provided. Further, according to an embodiment of the present invention, a display device capable of displaying a high-definition image can be provided. Further, according to one embodiment of the present invention, a display device capable of displaying a high-quality image can be provided. Further, according to an embodiment of the present invention, a display device capable of displaying an image with a high presence feeling can be provided. Further, according to an embodiment of the present invention, a display device capable of displaying a high-luminance image can be provided. Further, according to one embodiment of the present invention, a display device which operates at high speed can be provided. Further, according to one embodiment of the present invention, a display device with low power consumption can be provided. Further, according to one embodiment of the present invention, an inexpensive display device can be provided. Further, according to one embodiment of the present invention, a highly reliable display device can be provided. Further, according to one embodiment of the present invention, a novel display device can be provided. Further, according to an embodiment of the present invention, there is provided a method of operating the display device. Further, according to an embodiment of the present invention, there can be provided an electronic apparatus including the display device.

Note that the description of these effects does not hinder the existence of other effects. Note that one embodiment of the present invention does not necessarily have all the above-described effects. The effects other than the above can be derived from the descriptions of the specification, the drawings, the claims, and the like.

Brief description of the drawings

Fig. 1A is a block diagram showing a configuration example of a display device, and fig. 1B is a schematic diagram showing a configuration example of a display device.

Fig. 2 is a block diagram showing a configuration example of the display device.

Fig. 3 is a block diagram showing a configuration example of the display device.

Fig. 4A to 4C are circuit diagrams showing a structural example of a pixel.

Fig. 5 is a timing chart showing an example of an operation method of the display device.

Fig. 6 is a block diagram showing a configuration example of the display device.

Fig. 7 is a block diagram showing a configuration example of the display device.

Fig. 8 is a block diagram showing a configuration example of the display device.

Fig. 9 is a block diagram showing a configuration example of the display device.

Fig. 10 is a block diagram showing a configuration example of the display device.

Fig. 11 is a block diagram showing a configuration example of the display device.

Fig. 12 is a block diagram showing a configuration example of the display device.

Fig. 13 is a circuit diagram showing a configuration example of the D/a conversion circuit.

Fig. 14 is a block diagram showing a structural example of the gate driver circuit.

Fig. 15A is a block diagram showing a configuration example of the register circuit, and fig. 15B is a circuit diagram showing a configuration example of the register circuit.

Fig. 16 is a schematic diagram showing the configuration of the gate driver circuit and the data driver circuit.

Fig. 17 is a plan view showing a configuration example of the gate driver circuit and the data driver circuit.

Fig. 18 is a sectional view showing a structural example of the display device.

Fig. 19 is a sectional view showing a structural example of the display device.

Fig. 20 is a sectional view showing a structural example of the display device.

Fig. 21 is a sectional view showing a structural example of the display device.

Fig. 22 is a sectional view showing a structural example of the display device.

Fig. 23 is a sectional view showing a structural example of the display device.

Fig. 24A and 24B are plan views showing a structural example of a pixel.

Fig. 25 is a plan view showing a structural example of a pixel.

Fig. 26 is a sectional view showing a structural example of a pixel.

Fig. 27A to 27E are diagrams illustrating a structure example of a light emitting element.

Fig. 28A is a plan view showing a structural example of a transistor, and fig. 28B and 28C are sectional views showing a structural example of a transistor.

Fig. 29A is a plan view showing a structural example of a transistor, and fig. 29B and 29C are sectional views showing a structural example of a transistor.

Fig. 30A is a plan view showing a structural example of a transistor, and fig. 30B and 30C are sectional views showing a structural example of a transistor.

Fig. 31A is a diagram illustrating a classification of a crystal structure of IGZO, fig. 31B is a diagram illustrating an XRD spectrum of the CAAC-IGZO film, and fig. 31C is a diagram illustrating a nanobeam electron diffraction pattern of the CAAC-IGZO film.

Fig. 32A to 32E are perspective views showing an example of an electronic apparatus.

Fig. 33A to 33G are perspective views showing an example of an electronic apparatus.

Modes for carrying out the invention

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments may be embodied in many different forms, and those skilled in the art will readily appreciate that the aspects and details thereof may be modified in various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

Note that in the drawings described in this specification, the size, layer thickness, and region of each component may be exaggerated for easier understanding.

The terms "first", "second", "third", and the like used in the present specification are attached to avoid confusion of the constituent elements, and are not limited in number.

In the present specification, for convenience, positional relationships of constituent elements will be described using terms such as "upper" and "lower" to indicate arrangement, with reference to the drawings. Further, the positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words are not limited to the words described in the specification, and the words may be appropriately changed depending on the case.

In this specification and the like, when the polarity of a transistor, the direction of current flow during circuit operation, and the like change, the functions of a source and a drain included in the transistor may be interchanged with each other. Thus, the words "source" and "drain" may be interchanged.

In the present specification and the like, the terms "electrode", "wiring", "terminal" and the like do not functionally limit the constituent elements. For example, an "electrode" is sometimes used as part of a "wiring", and vice versa. The term "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wirings" are integrally formed. Further, for example, a "terminal" is sometimes used as a part of a "wiring" or an "electrode", and vice versa. The term "terminal" includes a case where a plurality of "electrodes", "wirings", "terminals", and the like are integrally formed. Thus, for example, an "electrode" may be part of a "wiring" or a "terminal", for example, a "terminal" may be part of a "wiring" or an "electrode". The terms "electrode", "wiring", "terminal" and the like may be replaced with the terms "region" and the like.

In this specification and the like, the resistance value of the "resistor" may depend on the length of the wiring. The resistance value may be determined by connecting to a conductor having a resistivity different from that of the conductor used for the wiring. The resistance value is sometimes determined by doping the semiconductor with impurities.

In this specification and the like, "electrically connected" includes a direct connection and a connection via "an element having some electrical function". Here, the "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connection targets. Therefore, even if the description is "electrically connected," there may be a case where a wiring is merely extended without a physically connected portion in an actual circuit. Even if the description is "direct connection", different conductors may be connected to each other through a contact body. In addition, different conductors may contain one or more of the same element or different elements as a wiring.

In this specification and the like, the expressions "film" and "layer" may be interchanged with each other. For example, the terms "conductive layer", "insulating layer", and the like may be replaced with "conductive film" and "insulating film".

In this specification and the like, unless otherwise specified, an off-state current refers to a drain current when a transistor is in an off state (also referred to as a non-conductive state or an interruption state). In the n-channel transistor, the off state refers to a voltage V between the gate and the source, unless otherwise specified_gsBelow threshold voltage V_th(in p-channel type transistors V_gsHigher than V_th) The state of (1).

In the drawings, the size, thickness of layers, or regions may be exaggerated for clarity. Therefore, the present invention is not necessarily limited to the above dimensions. In addition, in the drawings, ideal examples are schematically shown, and therefore the present invention is not limited to the shapes, numerical values, and the like shown in the drawings. For example, in an actual manufacturing process, a layer, a resist mask, or the like may be unintentionally thinned by a process such as etching, but illustration thereof may be omitted for convenience of understanding. In the drawings, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, materials, and the like, and a repetitive description thereof will be omitted. Note that the same hatching is sometimes used when portions having the same function, material, and the like are shown, and no reference numeral is particularly attached.

In this specification and the like, the metal oxide refers to an oxide of a metal in a broad sense. The metal oxide is classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, the OS transistor can be referred to as a transistor including an oxide or an oxide semiconductor.

(embodiment mode 1)

In this embodiment, a display device according to an embodiment of the present invention will be described.

One embodiment of the present invention relates to a display device in which a first layer, a second layer, and a third layer are stacked. The first layer includes a gate driving circuit and a data driving circuit, the second layer includes a demultiplexing circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix shape. The gate driving circuit and the data driving circuit have a region overlapping the display portion. This makes it possible to reduce the size and the bezel of the display device according to one embodiment of the present invention.

In addition, the gate driver circuit and the data driver circuit are not clearly separated and have regions overlapping each other. This makes it possible to further reduce the size of the frame of the display device, as compared with the case where this region is not provided.

Here, in the case where the gate driver circuit and the data driver circuit do not overlap the display portion, the gate driver circuit and the data driver circuit are provided in a peripheral portion of the display portion, for example. In this case, it is difficult to provide more than two rows and two columns of display portions from the viewpoint of the installation position of the data driving circuit and the like. On the other hand, in the display device according to one embodiment of the present invention, the gate driver circuit and the data driver circuit are provided in a layer different from the layer in which the display portion is provided, so that they can have a region overlapping with the display portion, whereby more than two rows and two columns of display portions can be provided. That is, five or more gate driver circuits and five or more data driver circuits may be provided in the display device according to one embodiment of the present invention.

As described above, the gate driver circuit and the data driver circuit having the region overlapping the display portion can operate at higher speed than a display device in which the gate driver circuit and the data driver circuit do not overlap the display portion. Accordingly, the pixel density of the display device according to one embodiment of the present invention can be further increased as compared with a display device in which the gate driver circuit and the data driver circuit do not overlap the display portion. For example, the pixel density of the display device according to one embodiment of the present invention may be set to 1000ppi or more, 2000ppi or more, or 5000ppi or more. Therefore, the display device according to one embodiment of the present invention can display a high-definition image.

Here, in the case where the pixel density of the display device according to one embodiment of the present invention is high, it is necessary to integrate transistors and the like in a driver circuit such as a data driver circuit with high density. However, since high-density integration is limited, the occupied area of the data driving circuit with respect to the area of the display portion may increase. This results in an increase in the area of a portion of the data driving circuit that does not overlap with the display portion and an increase in the bezel, which is a region where there is no display portion.

On the other hand, as described above, the display device according to one embodiment of the present invention includes a demultiplexing circuit in the second layer. The input terminals of the demultiplexing circuit are electrically connected to the data driving circuit, and the output terminals of the demultiplexing circuit are electrically connected to the pixels. Specifically, when the demultiplexer circuit has a first output terminal and a second output terminal serving as output terminals, the first output terminal and the second output terminal are electrically connected to pixels in different columns, respectively. Thus, the demultiplexing circuit can have a function of switching the supply target of the image data generated by the data driving circuit. This can simplify the structure of the data driving circuit. Specifically, the number of elements such as transistors included in the data driving circuit can be reduced. This reduces the area occupied by the data driving circuit. Therefore, the area of the portion of the data driving circuit that does not overlap the display portion can be reduced. This makes it possible to reduce the frame size of the display device according to one embodiment of the present invention.

As described above, the demultiplexing circuit is provided neither in the layer in which the data driving circuit is provided nor in the layer in which the display portion is provided. Thus, a demultiplexer circuit having an area overlapping with the display portion can be provided while enhancing the degree of freedom of layout. Therefore, the display device according to one embodiment of the present invention can be further reduced in size and frame size as compared with a case where the demultiplexer circuit is provided in the same layer as the data driver circuit, for example.

< structural example 1 of display device 10 >

Fig. 1A is a block diagram showing a configuration example of a display device 10 which is a display device according to an embodiment of the present invention. The display device 10 includes a gate driving circuit 21, a data driving circuit 22, and a circuit 40. The display device 10 includes a display unit 33 in which pixels 34 are arranged in a matrix shape of m rows and n columns (m and n are integers of 1 or more). In addition, the display device 10 further includes a demultiplexing circuit 81.

In this specification and the like, when a plurality of elements are denoted by the same symbol, particularly when it is necessary to distinguish between them, symbols for identification such as "_ 1", "_ 2", "[ n ]", "[ m, n ]" may be added to the symbol. For example, pixel 34 of the first row and column is represented by pixel 34[1,1], and pixel 34 of the mth row and column is represented by pixel 34[ m, n ].

The data driving circuit 22 is electrically connected to an input terminal of the demultiplexing circuit 81 through a wiring 82. Further, the selection control signal input terminal of the demultiplexing circuit 81 is electrically connected to the wiring 83. Further, the demultiplexing circuit 81 includes a plurality of output terminals electrically connected to the pixels 34 through wirings 32 different from each other.

In this specification and the like, "an output terminal of a demultiplexer circuit" may mean any one of a plurality of output terminals included in the demultiplexer circuit. For example, the phrase "the wiring is electrically connected to the output terminal of the demultiplexer circuit" may mean that the wiring is electrically connected to any of the plurality of output terminals.

The gate driver circuit 21 is electrically connected to the pixels 34 through the wiring 31. The circuit 40 is electrically connected to the data driving circuit 22. The circuit 40 may be electrically connected to other circuits.

Fig. 1A shows a structure in which the pixels 34 in the same column are electrically connected to the same wiring 32 and the pixels 34 in the same row are electrically connected to the same wiring 31. In this specification and the like, for example, a wiring 32 electrically connected to a pixel 34 in a first column is denoted by a wiring 32[1], and a wiring 32 electrically connected to a pixel 34 in an nth column is denoted by a wiring 32[ n ]. Further, for example, a wiring 31 electrically connected to the pixel 34 in the first row is denoted by a wiring 31[1], and a wiring 31 electrically connected to the pixel 34 in the m-th row is denoted by a wiring 31[ m ].

The data driving circuit 22 has a function of generating image data. The image data is supplied to the demultiplexing circuit 81 through the wiring 82.

The demultiplexer circuit 81 has a function of outputting image data input to the input terminal from any one of a plurality of output terminals in accordance with a signal input to the selection control signal input terminal, that is, the potential of the wiring 83. For example, in the case where the demultiplexer 81 has a first output terminal and a second output terminal and the selection control signal is a 1-bit digital signal, when the selection control signal is at a high potential, the image data input to the demultiplexer 81 can be output from the first output terminal. On the other hand, when the selection control signal is low potential, the image data input to the demultiplexing circuit 81 may be output from the second output terminal. Further, the image data input to the demultiplexing circuit 81 may be output from the first output terminal when the selection control signal is at the low potential and output from the second output terminal when the selection control signal is at the high potential.

As described above, the image data input to the demultiplexing circuit 81 is output to the wiring 32 to be supplied to the pixels 34. Thus, the wiring 32 can function as a data line.

As described above, the demultiplexing circuit 81 has a plurality of output terminals, and one output terminal can be electrically connected to one wiring 32. Thus, the number of demultiplexing circuits 81 included in the display device 10 can be smaller than the number n of columns of pixels 34. For example, in the case where the demultiplexer circuit 81 has a first output terminal and a second output terminal as output terminals, the display device 10 may have n/2 demultiplexer circuits 81. In addition, in the case where the demultiplexer circuit 81 has a first output terminal, a second output terminal, and a third output terminal as output terminals, the display device 10 may have n/3 demultiplexer circuits 81. Further, in the case where the demultiplexing circuit 81 has first to k-th (k is an integer of 2 or more and n or less) output terminals as the output terminals, the display device 10 may have n/k demultiplexing circuits 81.

The number of bits of the selection control signal may be a number of bits corresponding to the number of output terminals included in the demultiplexer circuit 81. For example, in the case where the demultiplexing circuit 81 has first to fourth output terminals, the selection control signal may be a 2-bit digital signal. For example, in the case where the demultiplexing circuit 81 has first to k-th output terminals, the selection control signal may be log ₂(k) A digital signal of bits.

Fig. 1A shows a case where the demultiplexing circuit 81 has a first output terminal and a second output terminal as output terminals. In this case, as described above, the display apparatus 10 may have n/2 demultiplexing circuits 81.

In this specification and the like, the plurality of demultiplexing circuits 81 are referred to as a demultiplexing circuit 81[1], a demultiplexing circuit 81[2], and the like, respectively. For example, n/2 demultiplexer circuits 81 are referred to as a demultiplexer circuit 81[1] to a demultiplexer circuit 81[ n/2], respectively. Further, a wiring 82 electrically connected to an input terminal of the demultiplexer circuit 81[1] is referred to as a wiring 82[1], and a wiring 83 electrically connected to a selection control signal input terminal of the demultiplexer circuit 81[1] is referred to as a wiring 83[1 ]. Further, a wiring 82 electrically connected to an input terminal of the demultiplexer circuit 81[ n/2] is referred to as a wiring 82[ n/2], and a wiring 83 electrically connected to a selection control signal input terminal of the demultiplexer circuit 81[ n/2] is referred to as a wiring 83[ n/2 ].

The gate drive circuit 21 has a function of selecting the pixel 34 to which a potential corresponding to the image data generated by the data drive circuit 22 is written. For example, the gate drive circuit 21 may generate a selection signal to supply the selection signal to the pixels 34 of a specific row. The pixel 34 to which the selection signal is supplied can be written with a potential corresponding to image data.

Here, the gate drive circuit 21 selects, for example, the pixels 34 in the second row after selecting the pixels 34 in the first row, sequentially selects the pixels 34 in the m-th row, and then selects the pixels 34 in the first row again. That is, the gate drive circuit 21 has a function of scanning the pixels 34. Further, a selection signal can be supplied from the gate driver circuit 21 to the pixel 34 through the wiring 31. Thus, the wiring 31 functions as a scan line. In the case of performing interlace driving, for example, the pixels 34 in the third row or the subsequent rows are selected without selecting the pixels 34 in the second row after selecting the pixels 34 in the first row. For example, in the case where m is an even number, the pixels 34 of the even-numbered line may be sequentially selected after the pixels 34 of the odd-numbered line are sequentially selected.

The circuit 40 has, for example, a function of receiving image data as a basis of the image data generated by the data driving circuit 22 and supplying the received data to the data driving circuit 22. The circuit 40 also functions as a control circuit for generating a start pulse signal, a clock signal, and the like. In addition, the circuit 40 may have a function different from that of the gate driving circuit 21 and the data driving circuit 22.

The display section 33 has a function of displaying an image corresponding to the image data supplied to the pixels 34. Specifically, an image is displayed on the display section 33 by emitting light having luminance corresponding to the above-described image data from the pixels 34.

Further, the color of light emitted from the pixel 34 may be, for example, red, green, blue, or the like. For example, by providing the red light-emitting pixel 34, the green light-emitting pixel 34, and the blue light-emitting pixel 34 in the display unit 33, the display device 10 can display full color. In this case, the pixel 34 may be a sub-pixel.

Fig. 1B is a schematic diagram showing a structural example of the display device 10. As shown in fig. 1B, the display device 10 may have a stacked structure of a layer 20, a layer 80, and a layer 30. Fig. 1B shows a structure in which layer 80 is provided on layer 20 and layer 30 is provided on layer 80. An interlayer insulating layer may be provided between the layers 20 and 80 and between the layers 80 and 30. Further, the lamination order of the layer 20, the layer 80, and the layer 30 is not limited to the order shown in fig. 1B. For example, layer 80 may be disposed on layer 30 and layer 20 may be disposed on layer 80.

In the layer 20, for example, a gate driver circuit 21, a data driver circuit 22, and a circuit 40 can be provided. In the layer 80, for example, a demultiplexing circuit 81 may be provided. In the layer 30, for example, a display portion 33 may be provided. Here, the gate driver circuit 21, the data driver circuit 22, the circuit 40, and the like provided in the layer 20 are circuits necessary for driving the display device 10. Accordingly, these circuits may be referred to as driving circuits. Further, the demultiplexing circuit 81 may also be referred to as a drive circuit.

Fig. 2 is a diagram showing a structure example of the layer 20, the layer 80, and the layer 30 shown in fig. 1B. In fig. 2, the positional relationship of the layers 20 and 30 is shown by a dashed dotted line and a white circle, and the white circle of the layer 20 and the white circle of the layer 30 connected by the dashed dotted line overlap each other. The same applies to other drawings.

The display device 10 includes a region where the gate driver circuit 21 and the data driver circuit 22 provided in the layer 20 overlap with the display portion 33. For example, the gate driver circuit 21 and the data driver circuit 22 have regions overlapping the pixels 34. By stacking the gate driver circuit 21, the data driver circuit 22, and the display portion 33 so as to have a region overlapping each other, the area of the frame which is a region where the display portion 33 is not present can be reduced. This makes it possible to reduce the frame size of the display device 10. Further, the narrowing of the frame of the display device 10 can realize the miniaturization of the display device 10.

The gate driver circuit 21 and the data driver circuit 22 are not clearly separated and have regions overlapping each other. This region is region 23. By having the region 23, the total of the occupied areas of the gate driver circuit 21 and the data driver circuit 22 can be reduced. Thus, even if the area of the display portion 33 is small, the gate driver circuit 21 and the data driver circuit 22 can be provided so as not to exceed the area of the display portion 33. In addition, the area of the gate driver circuit 21 and the data driver circuit 22 that does not overlap the display portion 33 may be reduced. As described above, the frame of the display device 10 can be further narrowed and the display device can be further miniaturized as compared with the case where the region 23 is not provided.

Here, the display device 10 includes the demultiplexing circuit 81, whereby the data driving circuit 22 does not need to simultaneously generate all the image data supplied to the pixels 34 of the first to nth columns. For example, consider the following: the demultiplexer circuit 81 has a first output terminal and a second output terminal as output terminals, the first output terminal being electrically connected to the wiring 32 in the odd-numbered column, and the second output terminal being electrically connected to the wiring 32 in the even-numbered column. In this case, the data driving circuit 22 may generate the image data supplied to the pixels 34 of the even-numbered columns after generating the image data supplied to the pixels 34 of the odd-numbered columns. This can reduce the amount of data generated by the data driving circuit 22 at a time, and can simplify the structure of the data driving circuit 22. Specifically, for example, the number of elements such as transistors included in the data driving circuit can be reduced. This can reduce the occupied area of the data driving circuit 22. Therefore, even if the area of the display portion 33 is small, the data driving circuit 22 can be provided so as not to exceed the range of the display portion 33. Further, the area of the data driving circuit 22 not overlapping the display portion 33 may be reduced. As described above, the display device 10 can be reduced in size and frame size.

Further, the demultiplexing circuit 81 is provided neither in the layer in which the data driving circuit 22 is provided nor in the layer in which the display section 33 is provided. This makes it possible to provide the demultiplexer circuit 81 having an area overlapping the display unit 33 while increasing the degree of freedom of layout. For example, the demultiplexing circuit 81 is provided in such a manner as to have an area overlapping with the pixel 34. Therefore, the frame of the display device 10 can be further narrowed and downsized compared to a case where the demultiplexer circuit 81 is provided in the same layer 20 as the data driver circuit 22, for example. In addition, the length of the wiring 82 and the length of the wiring 32 are preferably as short as possible in order to suppress signal delay and the like due to the resistance of the wiring 82 and the resistance of the wiring 32. Therefore, it is preferable to provide the demultiplexing circuit 81 so as to have an area overlapping with the data driving circuit 22.

The circuit 40 may not overlap with the display portion 33. The circuit 40 may have a region overlapping with the display portion 33.

In addition, the gate driver circuit 21 and/or the circuit 40 may be provided in the layer 80. When the gate driver circuit 21 is provided in the layer 80, the gate driver circuit 21 and the demultiplexer circuit 81 may not be clearly separated and may have regions overlapping each other.

< example of the structure of the circuit 40 and the data driving circuit 22 >

Fig. 3 is a block diagram showing a configuration example of the circuit 40 and the data driving circuit 22. Further, fig. 3 shows a case where the demultiplexing circuit 81 shown in fig. 1A and 2 has two output terminals and the display device 10 includes n/2 demultiplexing circuits 81.

The circuit 40 includes a receiving circuit 41, a serial-parallel conversion circuit 42, and a potential generation circuit 46 a. The circuit 40 may include various circuits in addition to the above-described circuits. For example, the circuit 40 may include a control circuit having a function of generating a start pulse signal, a clock signal, and the like.

The data driving circuit 22 includes a buffer circuit 43, a shift register circuit 44, a latch circuit 45, a transfer transistor logic circuit 46b, and an amplifier circuit 47. Here, the number of the latch circuits 45, the pass transistor logic circuits 46b, and the amplifier circuits 47 may be the same as that of the demultiplexer circuits 81. Fig. 3 shows a case where the data driving circuit 22 includes one shift register circuit 44 and includes n/2 latch circuits 45, n/2 pass transistor logic circuits 46b, and n/2 amplifier circuits 47. In this specification and the like, for example, the n/2 latch circuits 45, the n/2 transfer transistor logic circuits 46b, and the n/2 amplifier circuits 47 are referred to as latch circuits 45[1] to 45[ n/2], transfer transistor logic circuits 46b [1] to 46b [ n/2], and amplifier circuits 47[1] to 47[ n/2], respectively. Here, for example, in the case where the data drive circuit 22 has n/2 transfer transistor logic circuits 46b, the potential generation circuit 46a and the transfer transistor logic circuits 46b [1] to 46b [ n/2] constitute a D/a (digital-analog) conversion circuit 46.

The receiving circuit 41 has a function of receiving data as a basis of the image signal generated by the data driving circuit 22. The data may be single-ended digital data. When data is received using a signal for data transmission such as a Low Voltage Differential Signaling (LVDS), the receiving circuit 41 may have a function of converting the signal into a signal specification capable of being internally processed.

The serial-parallel conversion circuit 42 has a function of converting single-ended data output from the reception circuit 41 in parallel. By providing the serial-parallel conversion circuit 42 in the circuit 40, data and the like can be transferred from the circuit 40 to the data drive circuit 22 and the like even if a load for transferring data and the like from the circuit 40 to the data drive circuit 22 and the like is large.

The buffer circuit 43 may be, for example, a unity gain buffer. The buffer circuit 43 has a function of outputting the same data as the data output from the serial-parallel conversion circuit 42. By providing the buffer circuit 43 in the data drive circuit 22, even if the potential corresponding to the data output from the serial-parallel conversion circuit 42 drops due to wiring resistance or the like when the data is transferred from the circuit 40 to the data drive circuit 22, the drop can be compensated for. Thus, even if a load is large when data or the like is transferred from the circuit 40 to the data driving circuit 22 or the like, a decrease in the driving capability of the data driving circuit 22 or the like can be suppressed.

The shift register circuit 44 has a function of generating a signal for controlling the operation of the latch circuit 45. The latch circuit 45 has a function of storing or outputting data output from the buffer circuit 43. In the latch circuit 45, any operation of storing or outputting data is selected in accordance with a signal supplied from the shift register circuit 44.

The D/a conversion circuit 46 has a function of converting the digital data output from the latch circuit 45 into analog image data. The potential generation circuit 46a has a function of generating a potential corresponding to the kind of the number of bits of data that can be D/a converted and supplying the potential to the transfer transistor logic circuit 46 b. For example, in the case where the D/a conversion circuit 46 has a function of converting digital data of 8 bits into analog image data, the potential generation circuit 46a can generate 256 kinds of potentials different from each other in level.

The transfer transistor logic circuit 46b has a function of receiving data from the latch circuit 45 and outputting any one of the potentials generated by the potential generation circuit 46a as an analog signal in accordance with a digital value of the data. For example, the greater the digital value of the data, the higher the potential output by the pass transistor logic circuit 46b can be.

As shown in fig. 3, in the display device 10, circuits constituting the D/a conversion circuit 46 may be provided in the data driving circuit 22 and the circuit 40, respectively. Specifically, a circuit such as the transfer transistor logic circuit 46b which is preferably provided in each data drive circuit may be provided in the data drive circuit 22, and a circuit such as the potential generation circuit 46a which is not necessarily provided in each data drive circuit may be provided in the circuit 40. Thus, for example, the number of potential generating circuits 46a included in the display device 10 can be smaller than that of the transfer transistor logic circuit 46 b. Therefore, the occupied area of the data driving circuit 22 can be reduced. Thus, even if the area of the display portion 33 is small, the data driving circuit 22 can be prevented from going out of the range of the display portion 33. Further, the area of the data driving circuit 22 which does not overlap the display portion 33 can be reduced. As described above, the frame of the display device 10 can be further narrowed and the display device can be further miniaturized. Here, the components of the circuits other than the D/a conversion circuit 46 may be provided in the data driving circuit 22 and the circuit 40, respectively.

The amplifier circuit 47 has a function of amplifying an analog signal output from the transfer transistor logic circuit 46b and outputting the analog signal to the wiring 82. By providing the amplifying circuit 47, image data displayed with an analog signal can be stably supplied to the demultiplexing circuit 81. As the amplifier circuit 47, a voltage follower circuit or the like having an operational amplifier or the like can be suitably used. In the case of using a circuit having a differential input circuit as an amplifier circuit, the offset voltage of the differential input circuit is preferably as close to 0V as possible.

In the case where the display device 10 does not have the demultiplexer circuit 81, the data driver circuit 22 needs to include, for example, n latch circuits 45, n transfer transistor logic circuits 46b, and n amplifier circuits 47. On the other hand, in the case where the display device 10 includes the demultiplexer circuit 81, as shown in fig. 3, the data driver circuit 22 may include n/2 latch circuits 45, n/2 pass transistor logic circuits 46b, and n/2 amplifier circuits 47. This can reduce the number of latch circuits 45, transfer transistor logic circuits 46b, and amplifier circuits 47 included in the data drive circuit 22. Specifically, the number of the latch circuits 45, the transfer transistor logic circuits 46b, and the amplifier circuits 47 included in the data driving circuit 22 may be smaller than the number n of columns of the pixels 34. This can reduce the number of elements such as transistors included in the data driving circuit 22, thereby reducing the area occupied by the data driving circuit 22. Therefore, even if the area of the display portion 33 is small, the data driving circuit 22 can be provided so as not to exceed the range of the display portion 33. Further, the area of the data driving circuit 22 not overlapping the display portion 33 may be reduced. As described above, the display device 10 can be reduced in size and frame size.

Here, fig. 3 shows a case where the demultiplexing circuit 81 has two output terminals. When the demultiplexer 81 has three or more output terminals, the number of latch circuits 45, pass transistor logic circuits 46b, and amplifier circuits 47 included in the data driver circuit 22 can be further reduced. This can further reduce the occupied area of the data driving circuit 22.

< example of Structure of Pixel 34 >

Fig. 4A and 4B are circuit diagrams showing a configuration example of the pixel 34. The pixel 34 shown in fig. 4A includes a liquid crystal element 570, a transistor 550, and a capacitor 560. In addition, in the pixel 34 shown in fig. 4A, if the capacitance of the liquid crystal element 570 or the like is sufficiently large, the capacitor 560 may not be provided.

One of a source and a drain of the transistor 550 is electrically connected to one electrode of the liquid crystal element 570. One electrode of the liquid crystal element 570 is electrically connected to one electrode of the capacitor 560. The other of the source and the drain of the transistor 550 is electrically connected to the wiring 32. A gate of the transistor 550 is electrically connected to the wiring 31. The other electrode of the capacitor 560 is electrically connected to the wiring 35. Note that a node at which one of the source and the drain of the transistor 550, one electrode of the liquid crystal element 570, and one electrode of the capacitor 560 are electrically connected is referred to as a node FD.

The potential of the other electrode in the liquid crystal element 570 is set as appropriate in accordance with the specification of the pixel 34. The alignment state of the liquid crystal element 570 is set based on the image data written to the pixel 34. Further, the common potential may be supplied to the other electrode in the liquid crystal element 570 included in each of the plurality of pixels 34. Further, a different potential may be supplied to the other electrode of the liquid crystal element 570 included in each of the pixels 34 in each row.

In addition, the pixel 34 illustrated in fig. 4B includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. Further, if the gate capacitance or the like of the transistor 554 is sufficiently large, the capacitor 562 may not be provided.

One of a source and a drain of the transistor 552 is electrically connected to a gate of the transistor 554. A gate of the transistor 554 is electrically connected to one electrode of the capacitor 562. One of a source and a drain of the transistor 554 is electrically connected to one electrode of the light-emitting element 572. The other of the source and the drain of the transistor 552 is electrically connected to the wiring 32. A gate of the transistor 552 is electrically connected to the wiring 31. The other of the source and the drain of the transistor 554 and the other electrode of the capacitor 562 are electrically connected to the wiring 35 a. The other electrode of the light-emitting element 572 is electrically connected to the wiring 35 b. Here, a node at which one of the source and the drain of the transistor 552, the gate of the transistor 554, and one electrode of the capacitor 562 are electrically connected is referred to as a node FD.

In the pixel 34 shown in fig. 4B, the wiring 35a can be supplied with a low potential, for example, and the wiring 35B can be supplied with a high potential, for example.

In the pixel 34 shown in fig. 4B, a current flowing through the light-emitting element 572 is controlled in accordance with the potential of the node FD, and thereby the light emission luminance from the light-emitting element 572 is controlled.

As the light-emitting element 572, an EL element using electroluminescence can be used. The EL element has a layer containing a light-emitting compound (hereinafter referred to as an EL layer) between a pair of electrodes. When a potential difference higher than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side, and electrons are injected into the EL layer from the cathode side. The injected electrons and holes are recombined in the EL layer, and thereby, a light-emitting substance included in the EL layer emits light.

The EL element is distinguished depending on whether the light emitting material is an organic compound or an inorganic compound, and generally the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by applying a voltage, electrons are injected from one electrode into an EL layer, and holes are injected from the other electrode into the EL layer. These carriers (electrons and holes) are recombined to form an excited state of the light-emitting organic compound, and light is emitted when the light-emitting organic compound returns from the excited state to a ground state. Due to such a mechanism, such a light-emitting element is called a current excitation type light-emitting element.

In this specification and the like, a voltage supplied to a display element such as a light-emitting element or a liquid crystal element refers to a difference between a potential applied to one electrode in the display element and a potential applied to the other electrode in the display element.

The EL layer may contain a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole-blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, a bipolar substance (a substance having a high electron-transporting property and a high hole-transporting property), or the like in addition to the light-emitting compound.

The EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink-jet method, or a coating method.

Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements according to their device structures. A dispersion-type inorganic EL element includes a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination-type light emission utilizing a donor level and an acceptor level. The thin film type inorganic EL element is a structure in which a light emitting layer is sandwiched between dielectric layers, and the dielectric layers sandwiching the light emitting layer are sandwiched between electrodes, and its light emission mechanism is localized type light emission utilizing inner shell electron transition of metal ions.

In order to extract light emission, at least one of the pair of electrodes of the light-emitting element may be transparent. A transistor and a light-emitting element are formed over a substrate, and the light-emitting element can employ a top emission structure in which light emission is extracted from a surface on the opposite side of the substrate, a bottom emission structure in which light emission is extracted from a surface on the substrate side, and a double-sided emission structure in which light emission is extracted from both surfaces.

Fig. 4C shows a modification example of the pixel 34 shown in fig. 4B. In the pixel 34 shown in fig. 4C, one of a source and a drain of the transistor 554 is electrically connected to one electrode of the light-emitting element 572 and the other electrode of the capacitor 562. On the other hand, the wiring 35a may not be electrically connected to the other electrode of the capacitor 562. In the pixel 34 shown in fig. 4C, the wiring 35a can be supplied with a high potential, for example, and the wiring 35b can be supplied with a low potential, for example.

< example of operation method of display device 10 >

Fig. 5 is a timing chart illustrating an example of an operation method of the display device 10 having the pixel 34 shown in fig. 4A to 4C. The timing chart shown in fig. 5 shows an example of an operation method of the display device 10 in the case where the demultiplexing circuit 81 has two output terminals and the display device 10 has n/2 demultiplexing circuits 81, for example. Fig. 5 shows an example of the operation method of the pixel 34[ i, j-1] and the pixel 34[ i, j ] (i is an integer of 1 to m inclusive, and j is an even number of 2 to n inclusive). Specifically, changes with time in the potential of the wiring 31[ i ], the potential of the wiring 83[ j/2], the potential of the wiring 82[ j/2], the potential of the wiring 32[ j-1], the potential of the wiring 32[ j ], the potential of the node FD [ j-1], and the potential of the node FD [ j ] are shown. Here, the node FD [ j-1] indicates the node FD that the pixel 34 in the j-1 th column has, and the node FD [ j ] indicates the node FD that the pixel 34 in the j-1 th column has.

The timing chart shown in fig. 5 shows operations performed to cause the data driving circuit 22 to generate image data and display an image corresponding to the image data on the display unit 33. Specifically, an operation of supplying an analog signal having a potential corresponding to the data D [ i, j-1] to the pixel 34[ i, j-1] and supplying an analog signal having a potential corresponding to the data D [ i, j ] to the pixel 34[ i, j ] is shown. Further, the selection control signal input from the wiring 83 to the demultiplexing circuit 81 is a 1-bit digital signal. When the potential of the wiring 83[ j/2] is high, the demultiplexer circuit 81 outputs the analog signal input from the input terminal to the wiring 32[ j-1 ]. On the other hand, when the potential of the wiring 83[ j/2] is low, the demultiplexer circuit 81[ j/2] outputs the analog signal input from the input terminal to the wiring 32[ j ].

In the timing chart shown in fig. 5, a high potential is denoted by "H" and a low potential is denoted by "L". For convenience of explanation, influences of various resistances such as wiring resistance, parasitic capacitance of a transistor, a wiring, and the like, threshold voltage of the transistor, and the like are not considered.

In the period T1, the potential of the wiring 83[ j/2] is set to a high potential, and the potential of the wiring 82[ j/2] is set to a potential corresponding to the data D [ i, j-1 ]. Thus, the potential of the wiring 32[ j-1] is a potential corresponding to the data D [ i, j-1 ]. Further, the potential of the wiring 31[ i ] is set to a high potential, so that the wiring 32[ j-1] is conductive to the node FD [ i, j-1 ]. Thus, the potential of the node FD [ j-1] becomes a potential corresponding to the data D [ i, j-1] to write the data D [ i, j-1] to the pixel 34[ i, j-1 ].

In the period T2, the potential of the wiring 83[ j/2] is set to a low potential, and the potential of the wiring 82[ j/2] is set to a potential corresponding to the data D [ i, j ]. Thus, the potential of the wiring 32[ j ] becomes a potential corresponding to the data D [ i, j ]. Further, the potential of the wiring 31[ i ] is set to a high potential, so that the wiring 32[ j ] is conductive to the node FD [ i, j ]. Thereby, the potential of the node FD [ j ] becomes a potential corresponding to the data D [ i, j ] to write the data D [ i, j ] to the pixel 34[ i, j ]. This is done, for example, for all pixels 34 included in the display device 10. Thereby, an image can be displayed on the display unit 33.

< structural example 2 of display device 10 >

Fig. 6 is a diagram showing a configuration example of the display device 10. The display device 10 shown in fig. 6 is different from the display device 10 shown in fig. 2 in that: the plurality of display portions 33 are provided in the layer 30, that is, the display portions provided in the layer 30 are divided. Fig. 6 shows a configuration example of the display device 10 in the case where three rows and three columns of the display sections 33 are provided in the layer 30. In the layer 30, the display portions 33 may be provided in two rows and two columns, or the display portions 33 may be provided in four rows and four columns or more. The number of rows and the number of columns of the display unit 33 provided in the layer 30 may be different from each other. In the display device 10 having the configuration shown in fig. 6, for example, one image is displayed using all the display portions 33.

In fig. 6, the wirings 31, 32, 82, and 83 are omitted for easy understanding, but in reality, the wirings 31, 32, 82, and 83 are provided in the display device 10 having the structure shown in fig. 6. In fig. 6, although the electrical connection relationship of the circuit 40 is omitted, the circuit 40 is actually electrically connected to the data driving circuit 22. As in fig. 6, other drawings may omit some of the components and the like.

For example, the same number of gate driver circuits 21 and data driver circuits 22 as the number of display portions 33 may be provided in the layer 20. In this case, the gate driver circuit 21 may be provided so as to overlap with the display portion 33 provided with the pixels 34 to which signals are supplied by the gate driver circuit 21. Further, the data driving circuit 22 may be provided in such a manner as to overlap with the display portion 33 provided with the pixels 34 supplied with image data by the data driving circuit 22.

By providing a plurality of display portions 33 and providing the gate driver circuit 21 and the data driver circuit 22 in accordance with the plurality of display portions 33, the number of pixels 34 provided in one display portion 33 can be reduced. Since the plurality of gate driver circuits 21 can be operated in parallel and the plurality of data driver circuits 22 can be operated in parallel, for example, the time required to write an image signal corresponding to one frame of image to the pixel 34 can be shortened. This can shorten one frame period and realize high-speed operation of the display device 10. Therefore, the number of pixels 34 included in the display device 10 can be increased to improve the resolution of the display device 10. In addition, the display device according to one embodiment of the present invention can further improve the resolution of an image that can be displayed by the display device, compared to a display device in which a gate driver circuit and a data driver circuit do not overlap with a display portion. Further, the clock frequency can be reduced, whereby the power consumption of the display device 10 can be reduced.

Here, in the case where the gate driver circuit and the data driver circuit do not overlap the display portion, the gate driver circuit and the data driver circuit are provided in a peripheral portion of the display portion, for example. In this case, it is difficult to provide more than two rows and two columns of display portions from the viewpoint of the installation position of the data driving circuit and the like. On the other hand, in the display device 10, the gate driver circuit and the data driver circuit are provided in a layer different from the layer in which the display portion is provided, so that they can have a region overlapping with the display portion, whereby more than two rows and two columns of display portions can be provided as shown in fig. 6. That is, five or more gate driving circuits and data driving circuits may be provided in the display device 10.

In short, the display device 10 can operate at a higher speed than a display device in which the gate driver circuit and the data driver circuit do not overlap with the display portion, for example. Accordingly, the pixel density of the display device 10 can be further increased compared to a display device in which the gate driver circuit and the data driver circuit do not overlap the display portion. For example, the pixel density of the display device 10 may be set to 1000ppi or more, 2000ppi or more, or 5000ppi or more. Therefore, the display device 10 can display a high-definition image. Thereby, a high-quality image without graininess can be displayed on the display device 10, and an image rich in reality can be displayed. Therefore, the display device 10 is particularly suitable for use in devices in which the display surface is close to the user, in particular, portable electronic devices, wearable electronic devices (wearable devices), electronic book reader terminals, and the like. Further, the present invention is suitably used for VR devices, AR devices, and the like. Further, the present invention is also suitable for a viewfinder such as an electronic viewfinder provided in a digital camera or the like as an electronic apparatus having an imaging device.

In addition, the resolution of an image that can be displayed by the display device 10 can be further improved as compared with a display device in which the gate driver circuit and the data driver circuit do not overlap with the display portion. For example, in the case where the display device 10 is applied to a viewfinder, the display device 10 can display an image of 4K, 5K, or higher resolution.

Here, in the case where the pixel density of the display device 10 is increased, it is necessary to integrally provide transistors and the like in a driving circuit such as the data driving circuit 22 and the like at high density. However, since high-density integration is limited, the occupied area of the data driving circuit 22 relative to the area of the display unit 33 may increase. This may cause the data driving circuit 22 to be out of range of the display section 33 or the area of a portion of the data driving circuit 22 not overlapping the display section 33 to be increased. Therefore, the bezel may be enlarged.

On the other hand, by providing the demultiplexer circuit 81 in the display device 10, the number of elements such as transistors included in the data driver circuit 22 can be reduced as described above, and thus the occupied area of the data driver circuit 22 can be reduced. Therefore, even when the pixel density of the display device 10 is high, the data driving circuit 22 can be suppressed from going out of the range of the display portion 33. In addition, the area of the region of the data driving circuit 22 that does not overlap the display portion 33 may be reduced. As described above, the display device 10 can be reduced in size and frame size.

In the case where a plurality of data driver circuits 22 and the like are provided in the layer 20 and a plurality of display portions 33 are provided in the layer 30, one circuit 40 may be provided in the display device 10 as in the case shown in fig. 2. Therefore, as shown in fig. 6, the circuit 40 may not overlap with all the display sections 33. The circuit 40 may have a region overlapping with any one of the display units 33.

Although fig. 6 shows a configuration example in which the same number of gate driver circuits 21 as the number of display portions 33 are provided, one embodiment of the present invention is not limited thereto. Fig. 7 is a modified example of the structure shown in fig. 6, and shows a structural example of the display device 10 provided with the same number of gate driver circuits 21 as the number of columns of the display section 33. Since the display device 10 having the configuration shown in fig. 7 includes three columns of the display portions 33, three gate driver circuits 21 are provided. Further, three rows of display portions 33 are provided, and one gate driver circuit 21 is commonly used by the three rows and one column of display portions 33.

Fig. 8 is a modification of the structure shown in fig. 6, and shows an example of the structure of the display device 10 provided with a plurality of display portions 33 and one gate driver circuit 21. In the display device 10 having the configuration shown in fig. 8, one gate driver circuit 21 is commonly used for the display portions 33 of three rows and three columns. In the display device 10 having the configuration shown in fig. 8, the gate driver circuit 21 may not overlap the display portion 33.

Although not shown, the number of the data driving circuits 22 may not be the same as the number of the display portions 33. The number of the data driving circuits 22 included in the display device 10 may be larger than the number of the display portions 33 provided in the display device 10, or may be smaller than the number of the display portions 33 provided in the display device 10.

Although fig. 2 shows a configuration example in which the circuit 40 is provided in the layer 20, the circuit 40 may not be provided in the layer 20. Fig. 9 is a modified example of the structure shown in fig. 2, and shows a structural example of the display device 10 in which the circuit 40 is provided in the layer 30. Further, the circuit 40 may be provided in the layer 80. Further, the constituent elements of the circuit 40 may be provided in two or three of the layers 20, 80, and 30.

Although fig. 2 shows a configuration example in which one display portion 33 and one data driving circuit are provided, more data driving circuits 22 than the display portion 33 may be provided. Fig. 10 is a modified example of the configuration shown in fig. 2, and shows an example of the configuration of the display device 10 in which two data driving circuits (a data driving circuit 22a and a data driving circuit 22b) are provided for one display portion 33.

In the display device 10 having the configuration shown in fig. 10, input terminals of odd-numbered demultiplexer circuits 81 (demultiplexer circuits 81[1], 81[3], and the like) are electrically connected to the data driving circuit 22a, and input terminals of even-numbered demultiplexer circuits 81 (demultiplexer circuits 81[2], 81[4], and the like) are electrically connected to the data driving circuit 22 b. In FIG. 10, n/2 is an even number.

The data driving circuit 22a has a function of generating image data representing an image displayed by the pixels 34 electrically connected to the output terminals of the odd-numbered demultiplexing circuits 81. The data driving circuit 22b has a function of generating image data representing an image displayed by the pixels 34 electrically connected to the output terminals of the even-numbered demultiplexing circuits 81. Further, one image may be displayed by the image data generated by the data driving circuit 22a and the image data generated by the data driving circuit 22 b.

Like the data driving circuit 22, the data driving circuit 22a and the data driving circuit 22b have regions overlapping with the display portion 33. For example, the data driving circuit 22a and the data driving circuit 22b have regions overlapping with the pixels 34, as in the data driving circuit 22. The data driving circuit 22a and the gate driving circuit 21 are not clearly separated and have a region 23a where they overlap each other. The data driving circuit 22b and the gate driving circuit 21 are not clearly separated and have a region 23b where they overlap each other.

As shown in fig. 10, by providing more data driver circuits than the display portion 33, the density of transistors and the like constituting the data driver circuits can be reduced. This can improve the degree of freedom in layout of the display device 10.

The structures of the data driving circuit 22a and the data driving circuit 22b may be the same as the structure of the data driving circuit 22 shown in fig. 3.

Although fig. 2 shows a configuration example in which one display portion 33 and one gate driver circuit are provided, more gate driver circuits than the display portion 33 may be provided. Fig. 11 is a modified example of the structure shown in fig. 2, and shows an example of the structure of a display device 10 in which two gate driver circuits (a gate driver circuit 21a and a gate driver circuit 21b) are provided for one display portion 33.

In the display device 10 of the structure shown in fig. 11, the pixels 34 of the odd-numbered row are electrically connected to the gate drive circuit 21a through the wiring 31a, and the pixels 34 of the even-numbered row are electrically connected to the gate drive circuit 21b through the wiring 31 b. The wirings 31a and 31b function as scanning lines, similarly to the wirings 31.

The gate driver circuit 21a has a function of generating a signal for controlling the operation of the pixels 34 in the odd-numbered rows and supplying the signal to the pixels 34 through the wiring 31 a. The gate driver circuit 21b has a function of generating a signal for controlling the operation of the pixel 34 in the even-numbered row and supplying the signal to the pixel 34 through the wiring 31 b.

Like the gate driver circuit 21, the gate driver circuit 21a and the gate driver circuit 21b have regions overlapping with the display portion 33. For example, the gate driver circuit 21a and the gate driver circuit 21b have regions overlapping with the pixels 34, as in the gate driver circuit 21. The gate driver circuit 21a and the data driver circuit 22 are not clearly separated and have a region 23c where they overlap each other. The gate driver circuit 21b and the data driver circuit 22 are not clearly separated and have a region 23d where they overlap each other.

As shown in fig. 11, by providing more gate driver circuits than the display portion 33, the density of transistors and the like constituting the gate driver circuits can be reduced. This can improve the degree of freedom in layout of the display device 10.

In the display device 10 having the structure shown in fig. 11, it is possible to write image data to all the pixels 34 in the even-numbered row by operating the gate drive circuit 21b after writing image data to all the pixels 34 in the odd-numbered row by operating the gate drive circuit 21 a. That is, the display device 10 having the structure shown in fig. 11 can operate in an interlaced scanning manner. By operating the display device 10 in the interlaced scanning mode, high-speed operation can be achieved and the frame rate can be increased. Further, the number of pixels 34 to which image data is written during one frame can be reduced to half as compared with the case where the display device 10 is caused to operate in the progressive scanning mode. Therefore, in the case where the display device 10 is operated in the interlace scanning manner, the clock frequency can be reduced as compared with the case where the display device 10 is operated in the progressive scanning manner, whereby the power consumption of the display device 10 can be reduced.

Although fig. 2 shows a configuration example in which only one end of the wiring 32 is connected to the output terminal of the demultiplexing circuit 81, a plurality of portions of the wiring 32 may be connected to the output terminal of the demultiplexing circuit 81. By connecting a plurality of portions of the wiring 32 to the data driving circuit 22, the wiring distance from the output terminal of the demultiplexing circuit 81 to the pixel 34 can be shortened. This can suppress signal delay and the like due to wiring resistance, parasitic capacitance, and the like, and can realize high-speed operation of the display device 10. Fig. 12 shows a configuration example of the display device 10 in the case where both ends of the wiring 32 are connected to the output terminals of the demultiplexing circuit.

In fig. 12, a demultiplexing circuit connected to one end of the wiring 32 is referred to as a demultiplexing circuit 81a, and a demultiplexing circuit connected to the other end of the wiring 32 is referred to as a demultiplexing circuit 81 b. Further, the input terminal of the demultiplexer 81a is electrically connected to the wiring 82a, and the input terminal of the demultiplexer 81b is electrically connected to the wiring 82 b. The selection control signal input terminal of the demultiplexer 81a is electrically connected to the wiring 83a, and the selection control signal input terminal of the demultiplexer 81b is electrically connected to the wiring 83 b.

Further, portions other than one end and the other end of the wiring 32 may be connected to the output terminals of the demultiplexer circuit. For example, the central portion of the wiring 32 may be connected to an output terminal of the demultiplexer circuit. By adding a connection portion of the wiring 32 and the output terminal of the demultiplexing circuit, signal delay and the like can be further suppressed, and high-speed operation of the display device 10 can be further realized. For example, one end of the wiring 32 and the central portion of the wiring 32 may be connected to the output terminal of the demultiplexer circuit, and the other end of the wiring 32 may not be connected to the output terminal of the demultiplexer circuit.

Further, a plurality of portions of the wiring 31 may be connected to one gate driver circuit 21. This can suppress signal delay and the like, and realize high-speed operation of the display device 10.

< example of the structure of the D/A conversion circuit 46 >

Fig. 13 is a circuit diagram showing a configuration example of the potential generation circuit 46a and the transfer transistor logic circuit 46b constituting the D/a conversion circuit 46. The D/a conversion circuit 46 having the structure shown in fig. 13 can convert the digital data DD of 8 bits into the analog image data IS. Further, as shown in fig. 3, the data driving circuit 22 may have a plurality of transfer transistor logic circuits 46b, but fig. 13 shows only one transfer transistor logic circuit 46b for convenience.

Here, for example, in the case where the digital data DD is 8-bit digital data, the digital data DD may be constituted by an eight-bit digital value DV. In this specification and the like, for example, a digital value DV of eight bits is represented in order from the lowest bit by a digital value DV <1> to a digital value DV <8 >. That is, for example, the digital values DV <1> to DV <8> each represent a 1-bit value (e.g., 0 or 1).

The potential generating circuit 46a of the structure shown in FIG. 13 includes resistors 48[1] to 48[256], and the resistors 48[1] to 48[256] are connected in series. That is, the D/a conversion circuit 46 may be a resistor string type D/a conversion circuit.

Resistor 48[1]]May be supplied with the potential VDD. Resistor 48[256] ]May be supplied with the potential VSS. Thus, the slave resistor 48[1 ]]To resistor 48[256]Each terminal of (2) outputs a potential V having a different level₁To V₂₅₆. Further, although fig. 13 shows the potential V₁The potential generating circuit 46a is exemplified as the potential VDD, but the potential V may be adopted₂₅₆The potential VSS is set as a structure. In addition, the resistor 48[256 ] may not be provided]While adopting the potential V₁Is at a potential VDD and a potential V₂₅₆The potential VSS is set as a structure.

In this specification and the like, for example, the potential VDD may be a high potential and the potential VSS may be a low potential.

The transfer transistor logic circuit 46b of the configuration shown in fig. 13 is constituted by an eight-stage transfer transistor 49. Specifically, the circuit of each stage branches into two paths, and the pass transistor logic circuit 46b has 256 paths in total. That is, the transfer transistor 49 is electrically connected in a phase-out manner. The analog image data IS may be output from one of the source and the drain of the eighth stage transfer transistor 49 as the last stage.

For example, the digital value DV may be<1>Supplied to the first stage transfer transistor 49 to convert the digital value DV<2>Supplied to the second stage transfer transistor 49, and the digital value DV<8>To the eighth stage pass transistor 49. With the above configuration, the potential of the image data IS can be the potential V according to the digital data DD ₁To V₂₅₆Any one of them. Accordingly, the digital image data can be converted into the analog image data IS.

The transfer transistor logic circuit 46b shown in fig. 13 includes both the n-channel transfer transistor 49 and the p-channel transfer transistor 49, but only the n-channel transfer transistor 49 may be provided. For example, in addition to the digital values DV <1> to DV <8>, complementary data thereof may be supplied to the gates of the transfer transistors 49 so that all the transfer transistors 49 provided in the transfer transistor logic circuit 46b are n-channel type transistors.

The configuration shown in fig. 13 can also be applied to a D/a conversion circuit 46 having a function of D/a converting digital data DD of a number of bits other than 8 bits. For example, by providing 1024 or 1023 resistors 48 in the potential generation circuit 46a and providing a 10-stage transfer transistor 49 in the transfer transistor logic circuit 46b, the D/a conversion circuit 46 can be made to have a function of D/a converting digital data DD of 10 bits.

< example of Structure of Gate drive Circuit 21 >

Fig. 14 is a block diagram showing a structural example of the gate drive circuit 21. The gate driver circuit 21a and the gate driver circuit 21b shown in fig. 11 may have the same configuration.

The gate drive circuit 21 includes a register circuit R composed of a plurality of set-reset flip-flops. The register circuit R is electrically connected to the wiring 31 serving as a scan line and has a function of outputting a signal to the wiring 31.

The signal RES is a reset signal, and for example, by setting the signal RES to a high potential, all outputs of the register circuit R can be set to a low potential. The signal SP is a start pulse signal, and when this signal is input to the gate driver circuit 21, the shift operation of the register circuit R can be started. The signal PWC is a pulse width control signal and has a function of controlling the pulse width of a signal output from the register circuit R to the wiring 31. The signals CLK [1], CLK [2], CLK [3] and CLK [4] are clock signals, and two of the signals CLK [1] to CLK [4] may be input to one register circuit R, for example.

Further, in the configuration shown in fig. 14, by using another wiring instead of the wiring 31 and the like electrically connected to the register circuit R, it is possible to apply to the shift register circuit 44 and the like included in the data drive circuit 22.

Fig. 15A is a diagram showing signals input to and output from the register circuit R. Here, fig. 15A shows a case where the signal CLK [1] and the signal CLK [3] are input as clock signals.

The signal FO is an output signal, for example, a signal output to the wiring 31. The signal SROUT is a shift signal and may be a signal LIN input to the register circuit R of the next stage. As described above, among the signals shown in fig. 15A, the signal RES, the signal PWC, the signal CLK [1], the signal CLK [3] and the signal LIN are signals input to the register circuit R, and the signal FO and the signal SROUT are signals output from the register circuit R.

Fig. 15B is a circuit diagram showing a configuration example of the register circuit R in which the input/output signals are the signals shown in fig. 15A. The register circuit R includes transistors 51 to 63, and capacitors 64 to 66.

One of a source and a drain of the transistor 51 is electrically connected to one of a source and a drain of the transistor 52, one of a source and a drain of the transistor 56, and one of a source and a drain of the transistor 59. A gate of the transistor 52 is electrically connected to one of a source and a drain of the transistor 53, one of a source and a drain of the transistor 54, and one of a source and a drain of the transistor 55, a gate of the transistor 58, a gate of the transistor 61, and one electrode of the capacitor 64. The other of the source and the drain of the transistor 56 is electrically connected to the gate of the transistor 57 and one electrode of the capacitor 65. The other of the source and the drain of the transistor 59 is electrically connected to the gate of the transistor 60 and one electrode of the capacitor 66. One of a source and a drain of the transistor 60 is electrically connected to one of a source and a drain of the transistor 61, a gate of the transistor 62, and the other electrode of the capacitor 66.

The signal LIN is input to the gate of the transistor 51 and the gate of the transistor 55. The gate of transistor 53 is input with signal CLK [3 ]. The gate of the transistor 54 is inputted with the signal RES. One of a source and a drain of the transistor 57 is inputted with a signal CLK [1 ]. The other of the source and the drain of the transistor 60 is input with a signal PWC.

One of the source and the drain of the transistor 62 and one of the source and the drain of the transistor 63 are electrically connected to one wiring 31, and as described above, the signal F0 is output from the wiring 31. The signal SROUT is output from the other of the source and the drain of the transistor 57, the one of the source and the drain of the transistor 58, and the other electrode of the capacitor 65.

The other of the source and the drain of the transistor 51, the other of the source and the drain of the transistor 53, the other of the source and the drain of the transistor 54, the gate of the transistor 56, the gate of the transistor 59, and the other of the source and the drain of the transistor 62 are supplied with the potential VDD. The other of the source and the drain of the transistor 52, the other of the source and the drain of the transistor 55, the other of the source and the drain of the transistor 58, the other of the source and the drain of the transistor 61, the other of the source and the drain of the transistor 63, and the other electrode of the capacitor 64 are supplied with the potential VSS.

The transistor 63 is a bias transistor and functions as a constant current source. The gate of the transistor 63 may be supplied with the potential Vbias as a bias potential.

The transistor 62 and the transistor 63 constitute a source follower circuit 67. The source follower circuit may be used as a buffer circuit. Therefore, by providing the source follower circuit 67 in the register circuit R, even if attenuation of a signal due to a wiring resistance, a parasitic capacitance, or the like occurs in the register circuit R, it is possible to suppress a potential drop of the signal FO due to the attenuation or the like. This can increase the speed of operation of the display device 10. Note that the source follower circuit 67 may be a circuit other than a source follower circuit as long as it functions as a buffer. For example, the source follower circuit 67 may be a source ground circuit.

< example of Structure of region 23 >

Fig. 16 is a diagram showing a configuration example of a region 23 which is a region where the gate driver circuit 21 and the data driver circuit 22 overlap. The regions 23a and 23b shown in fig. 10 and the regions 23c and 23d shown in fig. 11 may have the same configuration.

As shown in fig. 16, in the region 23, a region including an element constituting the gate driver circuit 21 and a region including an element constituting the data driver circuit 22 are regularly provided. In fig. 16, a transistor 71 is used as an element constituting the gate driver circuit 21, and a transistor 72 is used as an element constituting the data driver circuit 22.

Fig. 16 shows a case where regions including elements constituting the gate drive circuit 21 are provided in the first and third rows and regions including elements constituting the data drive circuit 22 are provided in the second and fourth rows. In the region 23, dummy elements are provided between regions including elements constituting the gate driver circuit 21. Further, dummy elements are provided between the regions including the elements constituting the data driving circuit 22. Fig. 16 shows a configuration example of the region 23 in the case where the four sides of the transistor 71 and the four sides of the transistor 72 are provided with the dummy transistor 73 as a dummy element.

By providing a dummy element such as the dummy transistor 73 in the region 23 and making the dummy element absorb impurities, diffusion of impurities into the transistor 71, the transistor 72, and the like can be suppressed. This can improve the reliability of the transistor 71, the transistor 72, and the like, and can improve the reliability of the display device 10. In fig. 16, the transistors 71, the transistors 72, and the dummy transistors 73 are arranged in a matrix shape, but may not be arranged in a matrix shape.

Fig. 17 is a plan view showing a structural example of a region 70 which is a part of the region 23. As shown in fig. 16 and 17, the region 70 includes one transistor 71, one transistor 72, and two dummy transistors 73. As shown in fig. 17, the transistor 71 includes a channel formation region 110, a source region 111, and a drain region 112. Further, a gate electrode 113 having a region overlapping with the channel formation region 110 is included.

In fig. 17, components such as a gate insulator are omitted. Fig. 17 does not clearly show the channel formation region, the source region, and the drain region, respectively.

An opening 114 is provided in source region 111, and source region 111 is electrically connected to wiring 115 through opening 114. An opening 116 is provided in drain region 112, and drain region 112 is electrically connected to wiring 117 through opening 116.

An opening 118 is provided in the gate electrode 113, and the gate electrode 113 is electrically connected to the wiring 121 through the opening 118. An opening 119 is provided in the wiring 115, and the wiring 115 is electrically connected to the wiring 122 through the opening 119. An opening 120 is provided in the wiring 117, and the wiring 117 is electrically connected to the wiring 123 through the opening 120. That is, the source region 111 is electrically connected to the wiring 122 through the wiring 115, and the drain region 112 is electrically connected to the wiring 123 through the wiring 117.

The transistor 72 includes a channel formation region 130, a source region 131, and a drain region 132. Further, a gate electrode 133 having a region overlapping with the channel formation region 130 is included.

An opening 134 is provided in the source region 131, and the source region 131 is electrically connected to the wiring 135 through the opening 134. An opening 136 is provided in the drain region 132, and the drain region 132 is electrically connected to the wiring 137 through the opening 136.

The gate electrode 133 is provided with an opening 138, and the gate electrode 133 is electrically connected to the wiring 141 through the opening 138. An opening 139 is provided in the wiring 135, and the wiring 135 is electrically connected to the wiring 142 through the opening 139. An opening 140 is provided in the wiring 137, and the wiring 137 is electrically connected to the wiring 143 through the opening 140. That is, the source region 131 is electrically connected to the wiring 142 through the wiring 135, and the drain region 132 is electrically connected to the wiring 143 through the wiring 137.

Further, the channel formation region 110 and the channel formation region 130 may be disposed in the same layer. The source and drain regions 111 and 112 and the source and drain regions 131 and 132 may be provided in the same layer. In addition, the gate electrode 113 and the gate electrode 133 may be provided in the same layer. Further, the wirings 115 and 117 may be provided in the same layer as the wirings 135 and 137. That is, the transistor 71 and the transistor 72 may be provided in the same layer. Accordingly, as compared with the case where the transistor 71 and the transistor 72 are provided in different layers, the manufacturing process of the display device 10 can be simplified, and the display device 10 can be provided at low cost.

Wirings 121 to 123 electrically connected to the transistors 71 constituting the gate driver circuit 21 are provided in the same layer. Further, wirings 141 to 143 electrically connected to the transistors 72 constituting the data driving circuit 22 are provided in the same layer. Further, the wirings 121 to 123 are provided in a layer different from the wirings 141 to 143. With the above configuration, an electrical short circuit between the transistor 71 as an element constituting the gate drive circuit 21 and the transistor 72 as an element constituting the data drive circuit 22 can be suppressed. Thus, even if the gate driver circuit 21 and the data driver circuit 22 are not clearly separated and have an overlapping region, it is possible to suppress the malfunction of the gate driver circuit 21 and the data driver circuit 22. This can improve the reliability of the display device 10.

In this specification and the like, "a layer identical to a" means, for example, a layer containing the same material formed in the same step as a.

Although the structure in which the wirings 141 to 143 are provided above the wirings 121 to 123 is shown in fig. 17, the wirings 141 to 143 may be provided below the wirings 121 to 123.

In addition, although a structure in which the wirings 121 to 123 extend in the horizontal direction and the wirings 141 to 143 extend in the vertical direction is shown in fig. 17, one embodiment of the present invention is not limited to this. For example, a structure in which the wirings 121 to 123 extend in the vertical direction and the wirings 141 to 143 extend in the horizontal direction may be employed. Alternatively, the wirings 121 to 123 and the wirings 141 to 143 may extend in the horizontal direction or the vertical direction.

The dummy transistor 73 includes a semiconductor 151 and a conductor 152. The conductive body 152 has a region overlapping with the semiconductor 151. The semiconductor 151 can be formed in the same layer as the channel formation regions of the transistor 71 and the transistor 72. In addition, the conductor 152 may be formed in the same layer as the gate electrodes of the transistors 71 and 72. The dummy transistor 73 may be provided without one of the semiconductor 151 and the conductor 152.

The semiconductor 151 and the conductor 152 may not be electrically connected to other wirings. Semiconductor 151 and/or electrical conductor 152 may be supplied with a constant potential. For example, the ground potential may be supplied.

< example of the sectional Structure of the display device 10 >

Fig. 18 is a sectional view showing a structural example of the display device 10. The display device 10 includes a substrate 701 and a substrate 705, and the substrate 701 and the substrate 705 are attached to each other with a sealant 712.

As the substrate 701, a single crystal semiconductor substrate such as a single crystal silicon substrate can be used. A semiconductor substrate other than a single crystal semiconductor substrate may be used as the substrate 701.

A transistor 441 and a transistor 601 are provided over a substrate 701. The transistor 441 may be a transistor provided in the circuit 40. The transistor 601 may be a transistor provided in the gate driving circuit 21 or a transistor provided in the data driving circuit 22. That is, the transistor 441 and the transistor 601 can be provided in the layer 20 shown in fig. 1B and the like.

The transistor 441 is formed of a conductor 443 serving as a gate electrode, an insulator 445 serving as a gate insulator, and a part of the substrate 701, and includes a semiconductor region 447 including a channel formation region, a low-resistance region 449a serving as one of a source region and a drain region, and a low-resistance region 449b serving as the other of the source region and the drain region. The transistor 441 may be of a p-channel type or an n-channel type.

The transistor 441 is electrically separated from other transistors by the element separation layer 403. Fig. 18 shows a case where the transistor 441 and the transistor 601 are electrically separated from each other with the element separation layer 403 interposed therebetween. The element separation layer 403 can be formed by a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

Here, in the transistor 441 shown in fig. 18, the semiconductor region 447 has a convex shape. The side surfaces and the top surface of semiconductor region 447 are covered with conductor 443 with insulator 445 interposed therebetween. Note that fig. 18 does not show a case where conductor 443 covers the side surfaces of semiconductor region 447. In addition, a material for adjusting work function can be used for the electric conductor 443.

Like the transistor 441, a transistor in which a semiconductor region has a convex shape can be referred to as a fin-type transistor because a convex portion of a semiconductor substrate is used. Further, an insulator used as a mask for forming the convex portion may be provided so as to be in contact with the top surface of the convex portion. Although fig. 18 illustrates a case where a convex portion is formed by processing a part of the substrate 701, a semiconductor having a convex portion may be formed by processing an SOI substrate.

The structure of the transistor 441 shown in fig. 18 is merely an example and is not limited to this structure, and an appropriate transistor can be used depending on a circuit structure, a circuit operation method, or the like. For example, the transistor 441 may be a planar transistor.

The transistor 601 can have the same structure as the transistor 441.

An insulator 405, an insulator 407, an insulator 409, and an insulator 411 are provided over the substrate 701 in addition to the element separation layer 403, the transistor 441, and the transistor 601. The insulator 405, the insulator 407, the insulator 409, and the insulator 411 have a conductor 451 embedded therein. Here, the height of the top surface of the conductor 451 may be substantially the same as the height of the top surface of the insulator 411.

The conductor 451 and the insulator 411 are provided with insulators 413 and 415. The insulator 413 and the insulator 415 have a conductive body 457 embedded therein. The conductive body 457 may be provided in the same layer as the wirings 121 to 123 shown in fig. 17, for example. Here, the height of the top surface of the conductive body 457 may be substantially the same as the height of the top surface of the insulator 415.

An insulator 417 and an insulator 419 are provided over the conductor 457 and the insulator 415. The insulator 417 and the insulator 419 have a conductor 459 embedded therein. The conductor 459 may be provided in the same layer as the wirings 141 to 143 shown in fig. 17, for example. Here, the height of the top surface of the conductor 459 may be substantially the same as the height of the top surface of the insulator 419.

Insulators 821 and 814 are provided on the conductors 459 and the insulators 419. The insulator 821 and the insulator 814 have a conductor 853 embedded therein. Here, the height of the top surface of the conductor 853 may be substantially the same as the height of the top surface of the insulator 814.

An insulator 816 is provided on the conductor 853 and the insulator 814. An electrical conductor 855 is embedded in the insulator 816. Here, the height of the top surface of the conductive body 855 may be made substantially the same as the height of the top surface of the insulator 816.

The conductor 855 and the insulator 816 are provided with an insulator 822, an insulator 824, an insulator 854, an insulator 844, an insulator 880, an insulator 874, and an insulator 881. The conductor 805 is embedded in the insulator 822, the insulator 824, the insulator 854, the insulator 844, the insulator 880, the insulator 874, and the insulator 881. Here, the height of the top surface of the conductor 805 may be substantially the same as the height of the top surface of the insulator 881.

The insulator 421 and the insulator 214 are provided on the conductor 817 and the insulator 881. The insulator 421 and the insulator 214 are embedded with the conductor 453. Here, the height of the top surface of the conductor 453 and the height of the top surface of the insulator 214 may be substantially the same.

The conductor 453 and the insulator 214 are provided with an insulator 216. An electrical conductor 455 is embedded in the insulator 216. Here, the height of the top surface of the conductive body 455 may be substantially the same as the height of the top surface of the insulator 216.

The conductor 455 and the insulator 216 are provided with an insulator 222, an insulator 224, an insulator 254, an insulator 244, an insulator 280, an insulator 274, and an insulator 281. The insulator 222, the insulator 224, the insulator 254, the insulator 244, the insulator 280, the insulator 274, and the insulator 281 have the conductor 305 embedded therein. Here, the height of the top surface of the conductor 305 may be substantially the same as the height of the top surface of the insulator 281.

The conductor 305 and the insulator 281 are provided with an insulator 361. The conductor 317 and the conductor 337 are embedded in the insulator 361. Here, the height of the top surface of the conductor 337 may be substantially the same as the height of the top surface of the insulator 361.

The conductor 337 and the insulator 361 are provided with insulators 363. Conductor 347, conductor 353, conductor 355, and conductor 357 are embedded in insulator 363. Here, the heights of the top surfaces of the conductor 353, the conductor 355, and the conductor 357 may be substantially the same as the height of the top surface of the insulator 363.

A connection electrode 760 is provided on the conductor 353, the conductor 355, the conductor 357, and the insulator 363. Further, an anisotropic conductor 780 is provided so as to be electrically connected to the connection electrode 760, and an FPC (flexible circuit board) 716 is provided so as to be electrically connected to the anisotropic conductor 780. By using the FPC716, various signals and the like can be supplied from the outside of the display device 10 to the display device 10.

As shown in fig. 18, a low-resistance region 449b functioning as the other of the source region and the drain region of the transistor 441 is electrically connected to an FPC716 through a conductor 451, a conductor 457, a conductor 459, a conductor 853, a conductor 855, a conductor 805, a conductor 817, a conductor 453, a conductor 455, a conductor 305, a conductor 317, a conductor 337, a conductor 347, a conductor 353, a conductor 355, a conductor 357, a connection electrode 760, and an anisotropic conductor 780. In fig. 18, three conductors of the conductor 353, the conductor 355, and the conductor 357 are illustrated as conductors having a function of electrically connecting the connection electrode 760 and the conductor 347, but one embodiment of the present invention is not limited to this. The number of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347 may be one, two, or four or more. By providing a plurality of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347, contact resistance can be reduced.

A transistor 800 is provided over the insulator 814. The transistor 800 may be a transistor provided in the demultiplexing circuit 81. That is, the transistor 800 may be a transistor provided in the layer 80 shown in fig. 1B or the like. The transistor 800 may be an OS transistor.

The conductor 801a and the conductor 801b are embedded in the insulator 854, the insulator 844, the insulator 880, the insulator 874, and the insulator 881. The conductor 801a is electrically connected to one of the source and the drain of the transistor 800, and the conductor 801b is electrically connected to the other of the source and the drain of the transistor 800. Here, the height of the top surfaces of the conductor 801a and the conductor 801b may be substantially the same as the height of the top surface of the insulator 881.

A transistor 550 is provided over the insulator 214. As described above, the transistor 550 may be a transistor provided in the pixel 34. That is, the transistor 550 may be provided in the layer 30 shown in fig. 1B or the like. As the transistor 550, an OS transistor can be used. The OS transistor has a feature of extremely low off-state current. Thus, the image data can be held for a long time, and the refresh frequency can be reduced. Thereby, power consumption of the display device 10 can be reduced.

The insulator 254, the insulator 244, the insulator 280, the insulator 274, and the insulator 281 have the conductor 301a and the conductor 301b embedded therein. The conductor 301a is electrically connected to one of the source and the drain of the transistor 550, and the conductor 301b is electrically connected to the other of the source and the drain of the transistor 550. Here, the heights of the top surfaces of the conductors 301a and 301b may be substantially the same as the height of the top surface of the insulator 281.

Further, an OS transistor or the like may be provided between a layer in which the transistor 441, the transistor 601, and the like are provided and a layer in which the transistor 800 and the like are provided. Further, an OS transistor or the like may be provided between a layer in which the transistor 800 or the like is provided and a layer in which the transistor 550 or the like is provided. Further, an OS transistor or the like may be provided over a layer over which the transistor 550 or the like is provided.

The insulator 361 has the conductor 311, the conductor 313, the conductor 331, the capacitor 560, the conductor 333, and the conductor 335 embedded therein. The conductor 311 and the conductor 313 are electrically connected to the transistor 550 and function as wirings. The conductor 333 and the conductor 335 are electrically connected to the capacitor 560. Here, the heights of the top surfaces of the conductors 331, 333, and 335 may be substantially the same as the height of the top surface of the insulator 361.

The conductor 341, the conductor 343, and the conductor 351 are embedded in the insulator 363. Here, the height of the top surface of the conductor 351 may be substantially the same as the height of the top surface of the insulator 363.

The insulator 405, the insulator 407, the insulator 409, the insulator 411, the insulator 413, the insulator 415, the insulator 417, the insulator 419, the insulator 821, the insulator 814, the insulator 880, the insulator 874, the insulator 881, the insulator 421, the insulator 214, the insulator 280, the insulator 274, the insulator 281, the insulator 361, and the insulator 363 may be used as an interlayer film or a planarizing film covering the respective underlying irregularities. For example, in order to improve the flatness of the top surface of the insulator 363, the top surface thereof may be planarized by a planarization process using a Chemical Mechanical Polishing (CMP) method or the like.

As shown in fig. 18, the capacitor 560 includes a lower electrode 321 and an upper electrode 325. An insulator 323 is provided between the lower electrode 321 and the upper electrode 325. That is, the capacitor 560 has a stacked structure in which the insulator 323 serving as a dielectric body is interposed between a pair of electrodes. Although fig. 18 shows an example in which the capacitor 560 is provided over the insulator 281, the capacitor 560 may be provided over an insulator different from the insulator 281.

Fig. 18 shows an example in which the conductor 801a, the conductor 801b, and the conductor 805 are formed in the same layer. Further, an example in which the conductor 811, the conductor 813, and the conductor 817 are formed in the same layer is shown. Note that an example in which the conductor 301a, the conductor 301b, and the conductor 305 are formed in the same layer is also shown. Note that an example in which the conductor 311, the conductor 313, the conductor 317, and the lower electrode 321 are formed in the same layer is also shown. Note that an example in which the conductor 331, the conductor 333, the conductor 335, and the conductor 337 are formed in the same layer is also shown. Note that an example in which the conductor 341, the conductor 343, and the conductor 347 are formed in the same layer is also shown. Note that an example in which the conductor 351, the conductor 353, the conductor 355, and the conductor 357 are formed in the same layer is also shown. By forming a plurality of conductors in the same layer in this manner, the manufacturing process of the display device 10 can be simplified, and thus the display device 10 can be provided at low cost. Further, they may be formed in different layers and contain different kinds of materials, respectively.

The display device 10 shown in fig. 18 includes a liquid crystal element 570. The liquid crystal element 570 includes an electric conductor 772, an electric conductor 774, and a liquid crystal layer 776 between the electric conductor 772 and the electric conductor 774. The conductive body 774 is provided on the substrate 705 side, and is used as a common electrode. The conductor 772 is electrically connected to the other of the source and the drain of the transistor 550 through the conductor 351, the conductor 341, the conductor 331, the conductor 313, and the conductor 301 b. The conductive body 772 is formed on the insulator 363 and is used as a pixel electrode.

The conductive body 772 may be made of a material having light transmittance for visible light or a material having reflectivity. As the light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like can be used. As the reflective material, for example, a material containing aluminum, silver, or the like can be used.

When a reflective material is used as the electric conductor 772, the display device 10 is a reflective liquid crystal display device. When a light-transmitting material is used for the conductor 772 and a light-transmitting material is used for the substrate 701 and the like, the display device 10 is a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. In the case of a transmissive liquid crystal display device, a pair of polarizing plates are provided so as to sandwich a liquid crystal element.

Although not shown in fig. 18, an alignment film provided in contact with the liquid crystal layer 776 may be used. Further, an optical member (optical substrate) such as a polarizing member, a phase difference member, and an antireflection member, and a light source such as a backlight and a side light can be appropriately provided.

Between the insulator 363 and the conductor 774, a structural body 778 is provided. The structure 778 is a columnar spacer and is provided to control a distance (cell gap) between the substrate 701 and the substrate 705. In addition, a spherical spacer may be used as the structure 778.

A light-shielding layer 738, a coloring layer 736, and an insulator 734 in contact with them are provided on the substrate 705 side. The light shielding layer 738 has a function of shielding light emitted from the adjoining area. Alternatively, the light-shielding layer 738 has a function of preventing external light from reaching the transistor 550 and the like. The colored layer 736 has a region overlapping with the liquid crystal element 570.

As the Liquid Crystal layer 776, a thermotropic Liquid Crystal, a low molecular Liquid Crystal, a Polymer Dispersed Liquid Crystal (PDLC), a Polymer Network Liquid Crystal (PNLC), a ferroelectric Liquid Crystal, an antiferroelectric Liquid Crystal, or the like can be used. In the case of the horizontal electric field method, a liquid crystal exhibiting a blue phase which does not require an alignment film may be used.

As modes of the liquid crystal element, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (axial Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an ECB (Electrically Controlled Birefringence) mode, a guest-host mode, and the like can be employed.

The liquid crystal layer 776 may be a dispersed liquid crystal using a polymer dispersed liquid crystal, a polymer network liquid crystal, or the like. In this case, a structure in which black and white display is performed without providing the colored layer 736 may be employed, or a structure in which color display is performed using the colored layer 736 may be employed.

As a method for driving the liquid crystal element, a time-division display method (also referred to as a field sequential driving method) in which color display is performed by a sequential color mixing method can be applied. In this case, a structure in which the coloring layer 736 is not provided may be employed. In the case of the time-division display method, for example, sub-pixels each representing R (red), G (green), and B (blue) are not required, and thus, there is an advantage that the aperture ratio and the definition of the pixel can be improved.

Although the display device 10 shown in fig. 18 uses a liquid crystal element as a display element, one embodiment of the present invention is not limited thereto. Fig. 19 is a modification of the display device 10 shown in fig. 18, and fig. 19 is different from the display device 10 shown in fig. 18 in that a light-emitting element is used as a display element.

The display device 10 shown in fig. 19 includes a light emitting element 572. The light-emitting element 572 includes a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 may have an organic compound as a light-emitting material. Further, an inorganic compound such as a quantum dot may be included. In addition, in fig. 19, a transistor 554 is shown instead of the transistor 550, and a capacitor 562 is shown instead of the capacitor 560. As shown in fig. 19, the transistor 554 has the same structure as the transistor 550, and the capacitor 562 has the same structure as the capacitor 560.

Examples of the material that can be used for the organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used for quantum dots include colloidal quantum dots, alloy-type quantum dots, Core Shell (Core Shell) type quantum dots, and Core-type quantum dots.

The display device 10 shown in fig. 19 is provided with an insulator 730 over an insulator 363. Here, the insulator 730 may cover a portion of the electrical conductor 772. Further, the light-emitting element 572 includes a translucent conductor 788 and is a top emission type light-emitting element. The light-emitting element 572 may have a bottom emission structure in which light is emitted to one side of the conductor 772 or a double-sided emission structure in which light is emitted to both sides of the conductor 772 and the conductor 788.

The light emitting element 572 may have a microcavity structure, which will be described in detail later. Thus, light of a predetermined color (for example, RGB) can be extracted without providing a colored layer, and the display device 10 can perform color display. By adopting a structure in which no coloring layer is provided, light absorption by the coloring layer can be suppressed. Thereby, the display device 10 can display a high-luminance image, and power consumption of the display device 10 can be reduced. Further, when the EL layer 786 is formed in an island shape in each pixel or the EL layer 786 is formed in a stripe shape in each pixel column, that is, when the EL layer 786 is formed by coating separately, a structure in which a colored layer is not provided may be employed.

Further, the light shielding layer 738 includes a region overlapping with the insulator 730. Further, the light shielding layer 738 is covered with the insulator 734. Further, the sealing layer 732 fills a space between the light emitting element 572 and the insulator 734.

Further, a structure 778 is provided between the insulator 730 and the EL layer 786. Further, a structural body 778 is provided between the insulator 730 and the insulator 734.

Fig. 20 is a modification of the display device 10 shown in fig. 19, and is different from the display device 10 shown in fig. 19 in that a colored layer 736 is provided. By providing the colored layer 736, the color purity of light extracted from the light-emitting element 572 can be improved. Therefore, the display device 10 can display a high-quality image. Further, since all the light-emitting elements 572 in the display device 10 can be light-emitting elements that emit white light, for example, it is not necessary to form the EL layer 786 by coating, and a high-definition display device 10 can be realized.

Although fig. 18 to 20 each illustrate a structure in which a transistor 441 and a transistor 601 each having a channel formation region formed in a substrate 701 are provided and an OS transistor is stacked over the transistor 441 and the transistor 601, one embodiment of the present invention is not limited to this. Fig. 21, 22, and 23 are modification examples of fig. 18 to 20, respectively, and are different from the display device 10 shown in fig. 18 to 20 in that a transistor 800, a transistor 550, or a transistor 554 is stacked over a transistor 602 and a transistor 603 which are OS transistors, instead of the transistor 441 and the transistor 601. That is, the display device 10 of the structure shown in fig. 21 to 23 is provided with a stack of three layers of OS transistors.

An insulator 613 and an insulator 614 are provided over a substrate 701, and a transistor 602 and a transistor 603 are provided over the insulator 614. Further, a transistor or the like may be provided between the substrate 701 and the insulator 613. For example, a transistor similar to the transistor 441 and the transistor 601 shown in fig. 18 to 20 may be provided between the substrate 701 and the insulator 613. Further, an OS transistor or the like may be provided between a layer in which the transistor 602, the transistor 603, and the like are provided and a layer in which the transistor 800 and the like are provided. Further, an OS transistor or the like may be provided between a layer in which the transistor 800 or the like is provided and a layer in which the transistor 550, the transistor 554, or the like is provided. Further, an OS transistor or the like may be provided over a layer in which the transistor 550, the transistor 554, or the like is provided.

The transistor 602 may be a transistor provided in the circuit 40. The transistor 603 may be a transistor provided in the gate driver circuit 21 or a transistor provided in the data driver circuit 22. That is, the transistor 602 and the transistor 603 can be provided in the layer 20 shown in fig. 1B and the like.

The transistor 602 and the transistor 603 can be transistors having the same structure as the transistor 550 or the like. The transistors 602 and 603 may be OS transistors having different structures from the transistors 550 and 554.

An insulator 616, an insulator 622, an insulator 624, an insulator 654, an insulator 644, an insulator 680, an insulator 674, and an insulator 681 are provided over the insulator 614 in addition to the transistor 602 and the transistor 603. The conductor 461 is embedded in the insulator 654, the insulator 644, the insulator 680, the insulator 674, and the insulator 681. Here, the height of the top surface of the conductor 461 may be substantially the same as the height of the top surface of the insulator 681.

The insulator 501 is provided on the conductor 461 and the insulator 681. The insulator 501 has a conductor 463 embedded therein. Here, the height of the top surface of the conductor 463 may be substantially the same as the height of the top surface of the insulator 501.

An insulator 503 is provided on the conductor 463 and the insulator 501. An electrical conductor 465 is embedded in the insulator 503. Here, the height of the top surface of the conductor 465 may be substantially the same as the height of the top surface of the insulator 503.

An insulator 505 is provided on the conductor 465 and the insulator 503. An electrical conductor 467 is embedded in the insulator 505. The conductor 467 may be provided in the same layer as the wirings 121 to 123 shown in fig. 19, for example. Here, the height of the top surface of the conductor 467 may be substantially the same as the height of the top surface of the insulator 505.

The insulator 507 is provided on the conductor 467 and the insulator 505. An electrical conductor 469 is embedded in the insulator 507. Here, the height of the top surface of the conductor 469 may be substantially the same as the height of the top surface of the insulator 507.

An insulator 509 is provided over the conductor 469 and the insulator 507. An electrical conductor 471 is embedded in the insulator 509. The conductor 471 can be provided in the same layer as the wirings 141 to 143 shown in fig. 19, for example. Here, the height of the top surface of the conductor 471 may be substantially the same as the height of the top surface of the insulator 509.

The conductor 471 and the insulator 509 are provided with an insulator 821 and an insulator 814. The insulator 821 and the insulator 814 have a conductor 853 embedded therein. Here, the height of the top surface of the conductor 853 may be substantially the same as the height of the top surface of the insulator 814.

As shown in fig. 21 to 23, one of a source and a drain of the transistor 602 is electrically connected to the FPC716 through a conductor 461, a conductor 463, a conductor 465, a conductor 467, a conductor 469, a conductor 471, a conductor 853, a conductor 855, a conductor 805, a conductor 817, a conductor 453, a conductor 455, a conductor 305, a conductor 317, a conductor 337, a conductor 347, a conductor 353, a conductor 355, a conductor 357, a connection electrode 760, and an anisotropic conductor 780.

The insulator 613, the insulator 614, the insulator 680, the insulator 674, the insulator 681, the insulator 501, the insulator 503, the insulator 505, the insulator 507, and the insulator 509 serve as interlayer films, and may also serve as planarization films covering the underlying uneven shapes.

By adopting the structure of the display device 10 shown in fig. 21 to 23, it is possible to use the OS transistors as all the transistors in the display device 10 while achieving the reduction in the frame size and the size of the display device 10. This eliminates the need to form different types of transistors, reduces the manufacturing cost of the display device 10, and provides the display device 10 at a low cost.

< example of Structure of sub-pixel >

Fig. 24A and 24B are plan views showing an example of the structure of a subpixel 901 which can be applied to a display device which is one embodiment of the present invention. The sub-pixel 901 may have a circuit configuration as shown in fig. 4C. That is, in the case where the pixel 34 includes the light emitting element 572, the pixel 34 may have the same structure as the sub-pixel 901 illustrated in fig. 24A and 24B. Here, the transistor 552 includes a back gate in addition to a gate, and the back gate is electrically connected to the wiring 31. In addition, the transistor 554 includes a back gate in addition to a gate, and the back gate is electrically connected to the other of the source and the drain of the transistor 554, the other electrode of the capacitor 562, and one electrode of the light-emitting element 572.

Fig. 24A shows conductors and semiconductors such as transistors, capacitors, and wirings included in the sub-pixel 901. Fig. 24B shows a conductive body 772 functioning as one electrode in the light emitting element 572 in addition to the structure shown in fig. 24A. In addition, in each of fig. 24A and 24B, a conductor or the like serving as another electrode in the light-emitting element 572 is omitted. Here, one electrode of the light emitting element 572 serves as a pixel electrode, and the other electrode of the light emitting element 572 serves as a common electrode.

As shown in fig. 24A and 24B, a subpixel 901 includes a conductor 911, a conductor 912, a semiconductor 913, a semiconductor 914, a conductor 915a, a conductor 915B, a conductor 916a, a conductor 916B, a conductor 917, a conductor 918, a conductor 919, a conductor 920, a conductor 921, a conductor 922, a conductor 923, a conductor 924, a conductor 925, a conductor 926, a conductor 927, a conductor 928, a conductor 929, a conductor 930, a conductor 931, and a conductor 772.

The conductor 911 and the conductor 912 are formed through the same process. The semiconductor 913 and the semiconductor 914 are formed in the same step, and are formed after the conductor 911 and the conductor 912 are formed. The conductors 915a and 915b and the conductors 916a and 916b are formed in the same step, and are formed after the conductors 911 and 912 are formed. The conductor 917 and the conductor 918 are formed in the same step, and are formed in subsequent steps including a semiconductor 913, a semiconductor 914, a conductor 915a, a conductor 915b, a conductor 916a, and a conductor 916 b.

The conductors 919 to 923 are formed by the same step, and are formed by a subsequent step through the conductor 917 and the conductor 918. The conductor 924 is formed through the conductors 919 to 923. The conductors 925 to 928 are formed through the same process, and are formed through a process subsequent to the process of the conductor 924. The conductors 929 to 931 are formed through the same process, and are formed through the processes after the conductors 925 to 928. The conductor 772 is formed through the processes after the conductors 929 to 931.

In this specification and the like, constituent elements formed through the same process are provided in the same layer. For example, since the conductor 911 and the conductor 912 can be formed through the same process, the conductor 911 and the conductor 912 can be provided in the same layer. The component formed through the post-process is provided in a layer above the component formed through the pre-process. For example, since the conductive bodies 929 to 931 can be formed through a process after the conductive bodies 925 to 928, the conductive bodies can be provided in a layer over the conductive bodies 925 to 928.

The conductor 911 serves as a back gate electrode of the transistor 552. The semiconductor 913 contains a channel formation region of the transistor 552. The conductor 915a functions as one of a source electrode and a drain electrode of the transistor 552. The conductor 915b functions as the other of the source electrode and the drain electrode of the transistor 552. Conductor 917 serves as the gate electrode of transistor 552.

Conductor 912 serves as the back gate electrode for transistor 554. Semiconductor 914 contains the channel forming region of transistor 554. Conductor 916a serves as one of the source and drain electrodes of transistor 554. Conductor 916b serves as the other of the source and drain electrodes of transistor 554. Conductive body 918 serves as a gate electrode for transistor 554.

Conductor 919 serves as one electrode in capacitor 562. Conductor 924 serves as the other electrode in capacitor 562. The conductive body 925 corresponds to the wiring 31 serving as a scan line. The conductor 929 corresponds to the wiring 32 serving as a data line. The conductor 930 corresponds to the wiring 35a serving as a power supply line. As described above, the electric conductor 772 functions as one electrode in the light emitting element 572.

Electrical conductor 911 is electrically connected to electrical conductor 920. The conductor 912 is electrically connected to the conductor 923. Conductor 915a is electrically connected to conductor 921. Conductor 915b is electrically connected to conductor 919. Conductor 916a is electrically connected to conductor 922.

Electrical conductor 916b is electrically connected to electrical conductor 923. That is, the conductor 912 serving as a back gate electrode of the transistor 554 and the conductor 916b serving as the other of the source electrode and the drain electrode of the transistor 554 are electrically connected through the conductor 923.

Conductor 917 is electrically connected to conductor 920. That is, a conductor 911 serving as a back gate electrode of the transistor 552 and a conductor 917 serving as a gate electrode of the transistor 552 are electrically connected through a conductor 920.

Electrical conductor 920 is electrically connected to electrical conductor 925. That is, a conductive body 917 functioning as a gate electrode of the transistor 552 and a conductive body 925 functioning as a scan line are electrically connected through the conductive body 920.

Conductor 918 is electrically connected to conductor 919. Conductor 921 is electrically connected to conductor 926. Conductor 922 is electrically connected to conductor 927. Electrical conductor 923 is electrically connected to electrical conductor 928. Electrical conductor 924 is electrically connected to electrical conductor 928.

Electrical conductor 926 is electrically connected to electrical conductor 929. That is, the conductor 915a serving as one of the source electrode and the drain electrode of the transistor 552 and the conductor 929 serving as the data line are electrically connected to each other through the conductor 921 and the conductor 926.

Electrical conductor 927 is electrically connected to electrical conductor 930. That is, the conductor 916a serving as one of the source electrode and the drain electrode of the transistor 554 and the conductor 930 serving as the power supply line are electrically connected to each other through the conductor 922 and the conductor 927.

Electrical conductor 928 is electrically connected to electrical conductor 931. Electrical conductor 931 is electrically connected to electrical conductor 772.

The semiconductor 913 and the semiconductor 914 may include a metal oxide, for example. Thus, the transistor 552 and the transistor 554 can be OS transistors.

Fig. 25 is a plan view showing a structural example of a pixel 902 constituted by sub-pixels 901 having the structure shown in fig. 24B. In fig. 25, a sub-pixel 901R shows a sub-pixel 901 having a function of emitting red light, a sub-pixel 901G shows a sub-pixel 901 having a function of emitting green light, and a sub-pixel 901B shows a sub-pixel 901 having a function of emitting blue light. As shown in fig. 25, the pixel 902 is composed of a sub-pixel 901R, a sub-pixel 901G, and a sub-pixel 901B. Specifically, one pixel 902 is composed of a subpixel 901R and a subpixel 901B provided in an upper stage and a subpixel 901G provided in a lower stage. One pixel 902 is constituted by a subpixel 901G provided in an upper stage, a subpixel 901R provided in a lower stage, and a subpixel 901B.

In fig. 25, each of the sub-pixels 901R, 901G, and 901B provided in the upper stage and the sub-pixels 901R, 901G, and 901B provided in the lower stage has a structure in which the sub-pixels are inverted right and left. With this configuration, the sub-pixels 901 of the same color are alternately arranged in the extending direction of the conductive body 925 serving as a scanning line. Thus, one data line may be electrically connected to the sub-pixels 901 having a function of emitting light of the same color. That is, two or more kinds of the subpixels 901 among the subpixels 901R, 901G, and 901B can be suppressed from being electrically connected to one data line.

Fig. 26 is a sectional view of the portion shown along the chain line a1-a2 in fig. 24B. A transistor 552 and a transistor 554 are provided over an insulator 1021. An insulator 1022 is provided over the transistor 552 and the transistor 554, and an insulator 1023 is provided over the insulator 1022. Further, the substrate is disposed in a layer below the insulator 1021. Further, the components of the layer 20 (the gate driver circuit 21, the data driver circuit 22, the circuit 40, and the like) and the components of the layer 80 (the demultiplexer circuit 81 and the like) shown in fig. 1B and the like may be provided between the substrate and the insulator 1021.

As shown in fig. 26, the conductors disposed in the different layers are electrically connected by a conductor 990 that functions as a plug. For example, conductor 915a and conductor 921 in a layer disposed over conductor 915a are electrically connected by conductor 990. Conductor 990 may have the same configurations as conductors 853, 805, 453, 305, 337, 353, 355, 357, 301a, 301b, 331, 351, 333, and 335 shown in fig. 18 and the like.

Insulators 1024 are provided on the conductors 919 to 923 and the insulator 1023. An electrical conductor 924 is disposed on the insulator 1024. Capacitor 562 is composed of conductor 919, insulator 1024, and conductor 924.

An insulator 1025 is provided over the conductor 924 and the insulator 1024. Insulator 1026 is provided over conductor 925 to conductor 928 and insulator 1025. Insulators 1027 are provided on the conductors 929 to 931 and the insulators 1026.

The insulator 1027 is provided with a conductor 772 and an insulator 730. Here, the insulator 730 may cover a portion of the electrical conductor 772. The light-emitting element 572 includes a conductor 772, an EL layer 786, and a conductor 788.

An adhesive layer 991 is provided on the conductor 788, and an insulator 992 is provided on the adhesive layer 991. The insulator 992 on the adhesive layer 991 can be formed through the following process. First, the insulator 992 is formed over a substrate different from the substrate over which the light-emitting element 572 and the like are formed. Next, the conductor 788 and the insulator 992 are bonded using the adhesive layer 991. Then, the substrate formed with the insulator 992 is peeled off. Through the above steps, the insulator 992 can be formed on the conductor 788.

A colored layer 993 is provided on the insulator 992. In fig. 26, a colored layer 993a and a colored layer 993b are shown as the colored layer 993. The substrate 995 is bonded to the colored layer 993 with an adhesive layer 994.

The colored layer 993b has a function of transmitting light of a color different from that of the colored layer 993 a. For example, the pixel 902 is configured by the sub-pixel 901R having a function of emitting red light, the sub-pixel 901G having a function of emitting green light, and the sub-pixel 901B having a function of emitting blue light, and when the colored layer 993a has a function of transmitting red light, the colored layer 993B has a function of transmitting green light or blue light.

By forming the colored layer 993 on the insulator 992, the colored layer 993 and the light-emitting element 572 can be easily aligned. This can improve the pixel density of the display device according to one embodiment of the present invention.

< example of Structure of light emitting element 572 >

Fig. 27A to 27E illustrate a structure example of the light emitting element 572. Fig. 27A shows a structure in which an EL layer 786 is sandwiched between an electric conductor 772 and an electric conductor 788 (a single-layer structure). As described above, the EL layer 786 contains a light-emitting material, for example, an organic compound as a light-emitting material.

Fig. 27B is a diagram showing a stacked-layer structure of the EL layer 786. Here, in the light-emitting element 572 having the structure shown in fig. 27B, the conductive body 772 serves as an anode, and the conductive body 788 serves as a cathode.

The EL layer 786 has a structure in which a hole injection layer 721, a hole transport layer 722, a light emitting layer 723, an electron transport layer 724, and an electron injection layer 725 are sequentially stacked over a conductor 772. Further, in the case where the electric conductor 772 serves as a cathode and the electric conductor 788 serves as an anode, the lamination order is reversed.

The light-emitting layer 723 has a structure in which a fluorescent light-emitting layer and a phosphorescent light-emitting layer which exhibit desired emission colors can be obtained by appropriately combining a light-emitting material and a plurality of materials. The light-emitting layer 723 may have a stacked structure of different emission colors. In this case, the light-emitting substance or the other substance used for each light-emitting layer of the stack may be different materials.

In the light-emitting element 572, for example, by using the optical microcavity resonator (microcavity) structure in which the conductor 772 is a reflective electrode and the conductor 788 is a semi-transmissive and semi-reflective electrode as shown in fig. 27B, light obtained from the light-emitting layer 723 in the EL layer 786 can be resonated between the electrodes, and light emitted through the conductor 788 can be enhanced.

When the conductor 772 of the light-emitting element 572 is a reflective electrode having a stacked-layer structure of a conductive material having reflectivity and a conductive material having translucency (transparent conductive film), optical adjustment can be performed by adjusting the thickness of the transparent conductive film. Specifically, the adjustment is preferably performed as follows: the distance between the conductors 772 and 788 is about m λ/2 (note that m is a natural number) with respect to the wavelength λ of light obtained from the light-emitting layer 723.

In order to amplify the desired light (wavelength: λ) obtained from the light-emitting layer 723, it is preferable to adjust as follows: the optical distance from the conductor 772 to the region (light-emitting region) where desired light of the light-emitting layer 723 can be obtained and the optical distance from the conductor 788 to the region (light-emitting region) where desired light of the light-emitting layer 723 can be obtained are both around (2m '+ 1) λ/4 (note that m' is a natural number). Note that the "light-emitting region" described herein refers to a recombination region of holes and electrons in the light-emitting layer 723.

By performing the optical adjustment, the spectrum of the specific monochromatic light that can be obtained from the light-emitting layer 723 can be narrowed, thereby obtaining light emission with good color purity.

Further, in the above case, strictly speaking, the optical distance between the electric conductor 772 and the electric conductor 788 can be said to be the total thickness from the reflection region in the electric conductor 772 to the reflection region in the electric conductor 788. However, since it is difficult to accurately determine the position of the reflective region in the conductor 772 or the conductor 788, the above-described effects can be sufficiently obtained by assuming that any position of the conductor 772 or the conductor 788 is a reflective region. Further, strictly speaking, the optical distance between the electric conductor 772 and the light emitting layer from which desired light can be obtained can be said to be the optical distance between the reflection region in the electric conductor 772 and the light emitting region in the light emitting layer from which desired light can be obtained. However, since it is difficult to accurately determine the reflection region in the conductive body 772 or the position of the light-emitting region in the light-emitting layer where desired light can be obtained, the above-described effects can be sufficiently obtained by assuming that an arbitrary position in the conductive body 772 is the reflection region and an arbitrary position in the light-emitting layer where desired light can be obtained is the light-emitting region.

The light emitting element 572 shown in fig. 27B has a microcavity structure, and therefore can extract light of different wavelengths (monochromatic light) even with the same EL layer. Thus, separate coating (e.g., R, G, B) is not required to obtain different emission colors. Thereby, high resolution is easily achieved. Further, it may be combined with a colored layer. Further, the emission intensity in the front direction having a specific wavelength can be enhanced, and low power consumption can be achieved.

The light-emitting element 572 shown in fig. 27B may not have a microcavity structure. In this case, by providing a colored layer by allowing the light-emitting layer 723 to emit white light, light of a predetermined color (such as RGB) can be extracted. In addition, when the EL layer 786 is formed, light of a predetermined color can be extracted without providing a colored layer by applying the layers so as to obtain different emission colors.

At least one of the conductor 772 and the conductor 788 is an electrode having light transmittance (a transparent electrode, a transflective electrode, or the like). When the electrode having light transmittance is a transparent electrode, the transmittance of visible light of the transparent electrode is 40% or more. In the case where the electrode is a transflective electrode, the reflectance of visible light of the transflective electrode is 20% or more and 80% or less, and preferably 40% or more and 70% or less. Further, the resistivity of these electrodes is preferably 1 × 10^-2Omega cm or less.

When the conductor 772 or the conductor 788 is a reflective electrode (reflective electrode), the reflectance of visible light of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. Further, the resistivity of the electrode is preferably 1 × 10 ^-2Omega cm or less.

The structure of the light-emitting element 572 may be the structure shown in fig. 27C. Fig. 27C shows a light-emitting element 572 having a stacked-layer structure (series structure) in which two EL layers (an EL layer 786a and an EL layer 786b) are provided between a conductor 772 and a conductor 788, and a charge generation layer 792 is provided between the EL layer 786a and the EL layer 786 b. By providing the light-emitting element 572 with a series structure, the current efficiency and the external quantum efficiency of the light-emitting element 572 can be improved. Thereby, a high-luminance image can be displayed on the display device 10. Further, power consumption of the display device 10 can be reduced. Here, the EL layers 786a and 786B may have the same structure as the EL layer 786 shown in fig. 27B.

The charge generation layer 792 has the following functions: when a voltage is supplied to the conductor 772 and the conductor 788, electrons are injected into one of the EL layers 786a and 786b, and holes are injected into the other. Therefore, when a voltage is supplied so that the potential of the conductive body 772 is higher than that of the conductive body 788, electrons are injected from the charge generation layer 792 to the EL layer 786a and holes are injected to the EL layer 786 b.

In addition, from the viewpoint of light extraction efficiency, the charge generation layer 792 preferably transmits visible light (specifically, the charge generation layer 792 has a visible light transmittance of 40% or more). In addition, charge-generating layer 792 may also have a lower electrical conductivity than electrical conductor 772 or electrical conductor 788.

The structure of the light-emitting element 572 may be the structure shown in fig. 27D. Fig. 27D shows a light-emitting element 572 having a series structure in which three EL layers (an EL layer 786a, an EL layer 786b, and an EL layer 786c) are provided between a conductor 772 and a conductor 788, and a charge generation layer 792 is provided between the EL layer 786a and the EL layer 786b and between the EL layer 786b and the EL layer 786 c. Here, the EL layers 786a, 786B, and 786c may have the same structure as the EL layer 786 shown in fig. 27B. By providing the light-emitting element 572 with the structure shown in fig. 27D, the current efficiency and the external quantum efficiency of the light-emitting element 572 can be further improved. Thereby, a higher luminance image can be displayed on the display device 10. In addition, the power consumption of the display device 10 can be further reduced.

The structure of the light-emitting element 572 may be the structure shown in fig. 27E. Fig. 27E shows a light-emitting element 572 having a series structure in which n EL layers (EL layers 786(1) to 786(n)) are provided between a conductive body 772 and a conductive body 788, and a charge generation layer 792 is provided between the EL layers 786. Here, the EL layers 786(1), (786) to 786(n) may have the same structure as the EL layer 786 shown in fig. 27B. Fig. 27E shows an EL layer 786(1) (EL layer 786 (m)), an EL layer 786(m +1), and an EL layer 786(n) in the EL layer 786. Here, m is an integer of 2 or more and less than n, and n is an integer greater than m. The larger the value of n is, the higher the current efficiency and the external quantum efficiency of the light-emitting element 572 can be. Thereby, a high-luminance image can be displayed on the display device 10. Further, power consumption of the display device 10 can be reduced.

< constituent Material of light-emitting element 572 >

Next, a constituent material that can be used for the light-emitting element 572 will be described.

< conductor 772 and conductor 788 >)

As the conductor 772 and the conductor 788, the following materials can be appropriately combined if the functions of the two electrodes can be satisfied. For example, metals, alloys, conductive compounds, mixtures thereof, and the like can be suitably used. Specific examples thereof include an In-Sn oxide (also referred to as ITO), an In-Si-Sn oxide (also referred to as ITSO), an In-Zn oxide, and an In-W-Zn oxide. In addition to the above, metals such as aluminum (Al), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), gallium (Ga), zinc (Zn), indium (In), tin (Sn), molybdenum (Mo), tantalum (Ta), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), silver (Ag), yttrium (Y), neodymium (Nd), and alloys appropriately combining these metals may be mentioned. In addition to the above, elements belonging to group 1 or group 2 of the periodic table (for example, rare earth metals such as lithium (Li), cesium (Cs), calcium (Ca), strontium (Sr), europium (Eu), and ytterbium (Yb)), alloys in which these are appropriately combined, graphene, and the like can be used.

< < hole injection layer 721 and hole transport layer 722 >)

The hole injection layer 721 is a layer for injecting holes from the conductor 772 or the charge generation layer 792 of the anode into the EL layer 786, and includes a material having a high hole injection property. Here, the EL layer 786 includes an EL layer 786a, an EL layer 786b, an EL layer 786c, and EL layers 786(1) to 786 (n).

Examples of the material having a high hole-injecting property include transition metal oxides such as molybdenum oxide, vanadium oxide, ruthenium oxide, tungsten oxide, and manganese oxide. In addition to the above, phthalocyanine-based compounds such as phthalocyanine (abbreviated as H) can be used₂Pc), copper phthalocyanine (abbreviation: CuPc), and the like; aromatic amine compounds such as 4,4' -bis [ N- (4-diphenylaminophenyl) -N-phenylamino]Biphenyl (DPAB), N' -bis {4- [ bis (3-methylphenyl) amino group]Phenyl } -N, N ' -diphenyl- (1,1' -biphenyl) -4,4' -diamine (abbreviated as DNTPD), etc.; or a polymer such as poly (3, 4-ethylenedioxythiophene)/poly (styrenesulfonic acid) (abbreviation:PEDOT/PSS), and the like.

As the material having a high hole-injecting property, a composite material including a hole-transporting material and an acceptor material (electron acceptor material) may be used. In this case, electrons are extracted from the hole-transporting material by the acceptor material to generate holes in the hole-injecting layer 721, and the holes are injected into the light-emitting layer 723 through the hole-transporting layer 722. The hole injection layer 721 may be a single layer made of a composite material including a hole-transporting material and an acceptor material (electron acceptor material), or may be a stack of layers formed using a hole-transporting material and an acceptor material (electron acceptor material).

The hole transporting layer 722 is a layer which transports holes injected from the conductive body 772 through the hole injecting layer 721 into the light emitting layer 723. Further, the hole-transporting layer 722 is a layer containing a hole-transporting material. As the hole-transporting material used for the hole-transporting layer 722, a material having the HOMO energy level which is the same as or close to that of the hole-injecting layer 721 is particularly preferably used.

As an acceptor material for the hole injection layer 721, an oxide of a metal belonging to groups 4 to 8 in the periodic table of elements can be used. Specifically, molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide can be given. Molybdenum oxide is particularly preferably used because it is also stable in the atmosphere, has low hygroscopicity, and is easy to handle. In addition to the above, examples include organic acceptors such as quinodimethane derivatives, tetrachlorobenzoquinone derivatives, and hexaazatriphenylene derivatives. Specifically, 7, 8, 8-tetracyano-2, 3, 5, 6-tetrafluoroquinodimethane (abbreviated as F) can be used₄TCNQ), chloranil, 2, 3, 6, 7, 10, 11-hexacyan-1, 4, 5, 8, 9, 12-hexaazatriphenylene (abbreviation: HAT-CN), and the like.

The hole-transporting material used for the hole-injecting layer 721 and the hole-transporting layer 722 preferably has a hole-transporting property of 10 ^{- 6}cm²A substance having a hole mobility of greater than/Vs. In addition, any substance other than the above may be used as long as it has a hole-transporting property higher than an electron-transporting property.

As the hole-transporting material, a pi-electron-rich heteroaromatic compound (for example, a carbazole derivative or an indole derivative) or an aromatic amine compound is preferably used, and specific examples are as follows: 4,4 '-bis [ N- (1-naphthyl) -N-phenylamino ] biphenyl (abbreviated to NPB or. alpha. -NPD), N' -bis (3-methylphenyl) -N, N '-diphenyl- [1, 1' -biphenyl ] -4, 4 '-diamine (abbreviated to TPD), 4' -bis [ N- (spiro-9, 9 '-bifluoren-2-yl) -N-phenylamino ] biphenyl (abbreviated to BSPB), 4-phenyl-4' - (9-phenylfluoren-9-yl) triphenylamine (abbreviated to BPAFLP), 4-phenyl-3 '- (9-phenylfluoren-9-yl) triphenylamine (abbreviated to mBPAFLP), 4-phenyl-4' - (9-phenyl-9H-carbazole-3- Base) triphenylamine (abbreviation: PCBA1BP), 3- [4- (9-phenanthryl) -phenyl ] -9-phenyl-9H-carbazole (abbreviation: PCPPn), N- (4-biphenyl) -N- (9, 9-dimethyl-9H-fluoren-2-yl) -9-phenyl-9H-carbazol-3-amine (abbreviation: pcsif), N- (1, 1' -biphenyl-4-yl) -N- [4- (9-phenyl-9H-carbazol-3-yl) phenyl ] -9, 9-dimethyl-9H-fluoren-2-amine (abbreviation: PCBBiF), 4' -diphenyl-4 "- (9-phenyl-9H-carbazol-3-yl) triphenylamine (abbreviation: PCBBi1BP), 4- (1-naphthyl) -4' - (9-phenyl-9H-carbazol-3-yl) triphenylamine (abbreviation: PCBANB), 4' -bis (1-naphthyl) -4 "- (9-phenyl-9H-carbazol-3-yl) triphenylamine (abbreviation: PCBNBB), 9-dimethyl-N-phenyl-N- [4- (9-phenyl-9H-carbazol-3-yl) phenyl ] fluoren-2-amine (abbreviation: PCBAF), N-phenyl-N- [4- (9-phenyl-9H-carbazol-3-yl) phenyl ] spiro-9, 9' -bifluorene-2-amine (abbreviation: PCBASF), 4',4 ″ -tris (carbazol-9-yl) triphenylamine (abbreviation: TCTA), 4',4 ″ -tris (N, N-diphenylamino) triphenylamine (abbreviation: TDATA), 4',4 ″ -tris [ N- (3-methylphenyl) -N-phenylamino ] triphenylamine (abbreviation: MTDATA), etc.; 1, 3-bis (N-carbazolyl) benzene (abbreviated as mCP), 4 '-bis (N-carbazolyl) biphenyl (abbreviated as CBP), 3, 6-bis (3, 5-diphenylphenyl) -9-phenylcarbazole (abbreviated as CzTP), 3' -bis (9-phenyl-9H-carbazole) (abbreviated as PCCP), 3- [ N- (9-phenylcarbazol-3-yl) -N-phenylamino ] -9-phenylcarbazole (abbreviated as PCzPCA1), 3, 6-bis [ N- (9-phenylcarbazol-3-yl) -N-phenylamino ] -9-phenylcarbazole (abbreviated as PCzPCA2), 3- [ N- (1-naphthyl) -N- (9-phenylcarbazol-3-yl) amino ] -9-phenylcarbazole Compounds having a carbazole skeleton such as carbazole (abbreviated as PCzPCN1), 1,3, 5-tris [4- (N-carbazolyl) phenyl ] benzene (abbreviated as TCPB), 9- [4- (10-phenyl-9-anthracenyl) phenyl ] -9H-carbazole (abbreviated as CzPA); compounds having a thiophene skeleton such as 4,4',4 "- (benzene-1, 3, 5-triyl) tris (dibenzothiophene) (abbreviated as DBT3P-II), 2, 8-diphenyl-4- [4- (9-phenyl-9H-fluoren-9-yl) phenyl ] dibenzothiophene (abbreviated as DBTFLP-III), 4- [4- (9-phenyl-9H-fluoren-9-yl) phenyl ] -6-phenyldibenzothiophene (abbreviated as DBTFLP-IV); and compounds having a furan skeleton such as 4,4' - (benzene-1, 3, 5-triyl) tris (dibenzofuran) (abbreviated as DBF3P-II) and 4- {3- [3- (9-phenyl-9H-fluoren-9-yl) phenyl ] phenyl } dibenzofuran (abbreviated as mmDBFFLBi-II).

Further, polymer compounds such as Poly (N-vinylcarbazole) (abbreviated as PVK), Poly (4-vinyltriphenylamine) (abbreviated as PVTPA), Poly [ N- (4- { N '- [4- (4-diphenylamino) phenyl ] phenyl-N' -phenylamino } phenyl) methacrylamide ] (abbreviated as PTPDMA), Poly [ N, N '-bis (4-butylphenyl) -N, N' -bis (phenyl) benzidine ] (abbreviated as Poly-TPD) and the like can be used.

Note that the hole-transporting material is not limited to the above-described materials, and one or more of various known materials may be used in combination for the hole injection layer 721 and the hole transport layer 722 as the hole-transporting material. The hole transport layer 722 may be formed of a plurality of layers. That is, for example, the first hole transport layer and the second hole transport layer may be stacked.

< light emitting layer 723 >)

The light-emitting layer 723 is a layer containing a light-emitting substance. As the light-emitting substance, a substance exhibiting a light-emitting color such as blue, violet, bluish-violet, green, yellowish green, yellow, orange, or red is suitably used. Here, as shown in fig. 27C to 27E, when the light-emitting element 572 includes a plurality of EL layers, by using different light-emitting substances in the light-emitting layer 723 provided in each of the EL layers, it is possible to obtain a structure in which different emission colors are exhibited (for example, white emission can be obtained by combining emission colors in a complementary color relationship). For example, in the case where the light-emitting element 572 has the structure shown in fig. 27C, by using different light-emitting substances between the light-emitting layer 723 provided in the EL layer 786a and the light-emitting layer 723 provided in the EL layer 786b, the emission color of the EL layer 786a can be made different from that of the EL layer 786 b. Further, a stacked structure in which one light-emitting layer has different light-emitting substances may be employed.

In addition, the light-emitting layer 723 may contain one or more organic compounds (host materials, auxiliary materials) in addition to a light-emitting substance (guest material). In addition, as the one or more organic compounds, one or both of a hole-transporting material and an electron-transporting material can be used.

The light-emitting substance which can be used for the light-emitting layer 723 is not particularly limited, and a light-emitting substance which converts singlet excitation energy into light in a visible light region or a light-emitting substance which converts triplet excitation energy into light in a visible light region can be used. Examples of the light-emitting substance include the following substances.

Examples of the light-emitting substance which converts singlet excitation energy into light emission include substances which emit fluorescence (fluorescent materials), and examples thereof include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives. In particular, the pyrene derivative is preferable because the luminescence quantum yield is high. Specific examples of the pyrene derivative include N, N ' -bis (3-methylphenyl) -N, N ' -bis [3- (9-phenyl-9H-fluoren-9-yl) phenyl ] pyrene-1, 6-diamine (abbreviated as 1,6mMemFLPAPRn), N ' -diphenyl-N, N ' -bis [4- (9-phenyl-9H-fluoren-9-yl) phenyl ] pyrene-1, 6-diamine (abbreviated as 1,6FLPAPRn), N ' -bis (dibenzofuran-2-yl) -N, N ' -diphenylpyrene-1, 6-diamine (abbreviated as 1,6FrAPrn), N ' -bis (dibenzothiophene-2-yl) -N, n '-Diphenylpyrene-1, 6-diamine (abbreviated as 1,6ThAPrn), N' - (pyrene-1, 6-diyl) bis [ (N-phenylbenzo [ b ] naphtho [1,2-d ] furan) -6-amine ] (abbreviated as 1,6BnfAPrn), N '- (pyrene-1, 6-diyl) bis [ (N-phenylbenzo [ b ] naphtho [1,2-d ] furan) -8-amine ] (abbreviated as 1,6BnfAPrn-02), N' - (pyrene-1, 6-diyl) bis [ (6, N-diphenylbenzo [ b ] naphtho [1,2-d ] furan) -8-amine ] (abbreviated as 1,6BnfAPrn-03), and the like. The pyrene derivative is a group of compounds effective for achieving a blue hue in one embodiment of the present invention.

In addition to the above, 5, 6-bis [4- (10-phenyl-9-anthracenyl) phenyl ] -2, 2 '-bipyridine (abbreviated as PAP2BPy), 5, 6-bis [4' - (10-phenyl-9-anthracenyl) biphenyl-4-yl ] -2, 2 '-bipyridine (abbreviated as PAPP2BPy), N' -bis [4- (9H-carbazol-9-yl) phenyl ] -N, N '-diphenylstilbene-4, 4' -diamine (abbreviated as YGA2S), 4- (9H-carbazol-9-yl) -4'- (10-phenyl-9-anthracenyl) triphenylamine (abbreviated as YGAPA), 4- (9H-carbazol-9-yl) -4' - (9, 10-diphenyl-2-anthryl) triphenylamine (abbreviation: 2YGAPPA), N, 9-diphenyl-N- [4- (10-phenyl-9-anthracenyl) phenyl ] -9H-carbazol-3-amine (abbreviation: PCAPA), 4- (10-phenyl-9-anthracenyl) -4' - (9-phenyl-9H-carbazol-3-yl) triphenylamine (abbreviation: PCBAPA), 4- [4- (10-phenyl-9-anthracenyl) phenyl ] -4' - (9-phenyl-9H-carbazol-3-yl) triphenylamine (abbreviation: pcbappaba), perylene, 2,5,8, 11-tetra (tert-butyl) perylene (abbreviation: TBP), N ″ - (2-tert-butylanthracene-9, 10-diylbis-4, 1-phenylene) bis [ N, N' -triphenyl-1, 4-phenylenediamine ] (abbreviation: DPABPA), N, 9-diphenyl-N- [4- (9, 10-diphenyl-2-anthracenyl) phenyl ] -9H-carbazol-3-amine (abbreviation: 2PCAPPA), N- [4- (9, 10-diphenyl-2-anthryl) phenyl ] -N, N' -triphenyl-1, 4-phenylenediamine (abbreviation: 2DPAPPA), and the like.

Examples of the light-emitting substance which converts triplet excitation energy into light emission include a substance which emits phosphorescence (phosphorescent material) and a Thermally Activated Delayed Fluorescence (TADF) material which exhibits Thermally Activated Delayed Fluorescence.

Examples of the phosphorescent material include an organometallic complex, a metal complex (platinum complex), a rare earth metal complex, and the like. Such a substance exhibits a different emission color (emission peak) for each substance, and is therefore appropriately selected and used as needed.

The following can be mentioned as examples of phosphorescent materials which exhibit blue or green color and have an emission spectrum with a peak wavelength of 450nm to 570 nm.

For example, tris {2- [5- (2-methylphenyl) -4- (2, 6-dimethylphenyl) -4H-1, 2, 4-triazol-3-yl-. kappa.N 2]Phenyl-kappa C iridium (III) (abbreviation: [ Ir (mpptz-dmp) ]₃]) Tris (5-methyl)-3, 4-diphenyl-4H-1, 2, 4-triazole (triazola)) iridium (III) (abbreviation: [ Ir (Mptz)₃]) Tris [4- (3-biphenyl) -5-isopropyl-3-phenyl-4H-1, 2, 4-triazole (triazolate)]Iridium (III) (abbreviation: [ Ir (iPrptz-3b)₃]) Tris [3- (5-biphenyl) -5-isopropyl-4-phenyl-4H-1, 2, 4-triazole (triazolate)]Iridium (III) (abbreviation: [ Ir (iPr5btz) ₃]) And organometallic complexes having a 4H-triazole skeleton; tris [ 3-methyl-1- (2-methylphenyl) -5-phenyl-1H-1, 2, 4-triazole (triazolate)]Iridium (III) (abbreviation: [ Ir (Mptz1-mp)₃]) Tris (1-methyl-5-phenyl-3-propyl-1H-1, 2, 4-triazole) iridium (III) (abbreviation: [ Ir (Prptz1-Me)₃]) And the like organometallic complexes having a 1H-triazole skeleton; fac-tris [1- (2, 6-diisopropylphenyl) -2-phenyl-1H-imidazole]Iridium (III) (abbreviation: [ Ir (iPrpmi)₃]) Tris [3- (2, 6-dimethylphenyl) -7-methylimidazo [1, 2-f ]]Phenanthridino (phenanthrinato)]Iridium (III) (abbreviation: [ Ir (dmpimpt-Me)₃]) And the like organic metal complexes having an imidazole skeleton; and bis [2- (4', 6' -difluorophenyl) pyridinato-N, C²']Iridium (III) tetrakis (1-pyrazolyl) borate (FIr 6 for short), bis [2- (4', 6' -difluorophenyl) pyridinato-N, C²']Iridium (III) picolinate (FIrpic), bis [2- (3, 5-bis-trifluoromethyl-phenyl) -pyridinato-N, C²']Iridium (III) picolinate (abbreviated as [ Ir (CF) ]₃ppy)₂(pic)]) Bis [2- (4', 6' -difluorophenyl) pyridinato-N, C²']Organometallic complexes in which an electron-withdrawing group-containing phenylpyridine derivative is a ligand, such as iridium (III) acetylacetonate (FIr (acac)).

The phosphorescent material exhibiting green or yellow color and having an emission spectrum with a peak wavelength of 495nm or more and 590nm or less includes the following materials.

For example, tris (4-methyl-6-phenylpyrimidine) iridium (III) (abbreviation: [ Ir (mppm))₃]) Tris (4-tert-butyl-6-phenylpyrimidine) iridium (III) (abbreviation: [ Ir (tBuppm)₃]) And (acetylacetonate) bis (6-methyl-4-phenylpyrimidine) iridium (III) (abbreviation: [ Ir (mppm)₂(acac)]) And (acetylacetonate) bis (6-tert-butyl-4-phenylpyrimidine) iridium (III) (abbreviation: [ Ir (tBuppm)₂(acac)])、(Acetylacetonate) bis [6- (2-norbornyl) -4-phenylpyrimidine]Iridium (III) (abbreviation: [ Ir (nbppm)₂(acac)]) (Acetylacetonate) bis [ 5-methyl-6- (2-methylphenyl) -4-phenylpyrimidine]Iridium (III) (abbreviation: [ Ir (mpmppm))₂(acac)]) (Acetylacetonate) bis {4, 6-dimethyl-2- [6- (2, 6-dimethylphenyl) -4-pyrimidinyl-. kappa.N 3]Phenyl-. kappa.C } Iridium (III) (abbreviation: [ Ir (dmppm-dmp) ]₂(acac)]) And (acetylacetonate) bis (4, 6-diphenylpyrimidine) iridium (III) (abbreviation: [ Ir (dppm)₂(acac)]) And the like, an organometallic iridium complex having a pyrimidine skeleton, bis (3, 5-dimethyl-2-phenylpyrazine) iridium (III) (abbreviation: [ Ir (mppr-Me)₂(acac)]) And (acetylacetonate) bis (5-isopropyl-3-methyl-2-phenylpyrazine) iridium (III) (abbreviation: [ Ir (mppr-iPr) ₂(acac)]) Etc. organometallic iridium complexes having pyrazine skeleton, tris (2-phenylpyridinium-N, C²') Iridium (III) (abbreviation: [ Ir (ppy)₃]) Bis (2-phenylpyridinato-N, C)²') Iridium (III) acetylacetone (abbreviation: [ Ir (ppy)₂(acac)]) Bis (benzo [ h ]]Quinoline) iridium (III) acetylacetone (abbreviation: [ Ir (bzq)₂(acac)]) Tris (benzo [ h ]) or a salt thereof]Quinoline) iridium (III) (abbreviation: [ Ir (bzq)₃]) Tris (2-phenylquinoline-N, C)^2＇) Iridium (III) (abbreviation: [ Ir (pq)₃]) Bis (2-phenylquinoline-N, C)²') Iridium (III) acetylacetone (abbreviation: [ Ir (pq)₂(acac)]) Etc. organometallic iridium complexes having a pyridine skeleton, bis (2, 4-diphenyl-1, 3-oxazole-N, C²') Iridium (III) acetylacetone (abbreviation: [ Ir (dpo)₂(acac)]) Bis {2- [4' - (perfluorophenyl) phenyl]pyridine-N, C²' } Iridium (III) acetylacetone (abbreviation: [ Ir (p-PF-ph)₂(acac)]) Bis (2-phenylbenzothiazole-N, C)²') Iridium (III) acetylacetone (abbreviation: [ Ir (bt)₂(acac)]) And organometallic complexes, tris (acetylacetonate) (monophenanthroline) terbium (III) (abbreviation: [ Tb (acac)₃(Phen)]) And the like.

Among the above compounds, organometallic iridium complexes having a pyridine skeleton (particularly, a phenylpyridine skeleton) or a pyrimidine skeleton are a group of compounds effective for achieving a green hue in one embodiment of the present invention.

The following can be mentioned as examples of phosphorescent materials which exhibit yellow or red color and have an emission spectrum with a peak wavelength of 570nm to 750 nm.

For example, (diisobutyrylmethaneato) bis [4, 6-bis (3-methylphenyl) pyrimidino]Iridium (III) (abbreviation: [ Ir (5mdppm)₂(dibm)]) Bis [4, 6-bis (3-methylphenyl) pyrimidino radical](Dipivaloylmethane) Iridium (III) (abbreviation: [ Ir (5 mddppm)₂(dpm)]) Bis [4, 6-di (naphthalen-1-yl) pyrimidinium radical](Dipivaloylmethane) Iridium (III) (abbreviation: [ Ir (d1npm)₂(dpm)]) And the like organic metal complexes having a pyrimidine skeleton; (acetylacetonato) bis (2, 3, 5-triphenylpyrazine) iridium (III) (abbreviation: [ Ir (tppr))₂(acac)]) Bis (2, 3, 5-triphenylpyrazine) (dipivaloylmethane) iridium (III) (abbreviation: [ Ir (tppr))₂(dpm)]) Bis {4, 6-dimethyl-2- [3- (3, 5-dimethylphenyl) -5-phenyl-2-pyrazinyl-. kappa.N]Phenyl-kappa C } (2, 6-dimethyl-3, 5-heptanedione-kappa)²O, O') iridium (III) (abbreviation: [ Ir (dmdppr-P)₂(dibm)]) Bis {4, 6-dimethyl-2- [5- (4-cyano-2, 6-dimethylphenyl) -3- (3, 5-dimethylphenyl) -2-pyrazinyl-. kappa.N]Phenyl- κ C } (2,2,6, 6-tetramethyl-3, 5-heptanedione- κ)²O, O') iridium (III) (abbreviation: [ Ir (dmdppr-dmCP)₂(dpm)]) (acetylacetone) bis [ 2-methyl-3-phenylquinoxalineato) ]-N，C^2’]Iridium (III) (abbreviation: [ Ir (mpq))₂(acac)]) (acetylacetone) bis (2, 3-diphenylquinoxalineato) -N, C^2’]Iridium (III) (abbreviation: [ Ir (dpq))₂(acac)]) (acetylacetonato) bis [2, 3-bis (4-fluorophenyl) quinoxalato)]Iridium (III) (abbreviation: [ Ir (Fdpq)₂(acac)]) And the like organic metal complexes having a pyrazine skeleton; tris (1-phenylisoquinoline-N, C)^2’) Iridium (III) (abbreviation: [ Ir (piq)₃]) Bis (1-phenylisoquinoline-N, C)²') Iridium (III) acetylacetone (abbreviation: [ Ir (piq)₂(acac)]) And the like organic metal complexes having a pyridine skeleton; 2, 3, 7, 8, 12, 13, 17, 18-octaethyl-21H, 23H-porphyrin platinum (II) (abbreviation [ PtOEP ]]) And platinum complexes; and tris (1, 3-diphenyl-1, 3-propanedione (propanoiono)) (monophenanthroline) europium (III) (abbreviation: [ Eu (DBM))₃(Phen)]) Tris [1- (2-thenoyl) -3, 3, 3-trifluoroacetone](Monophenanthroline) europium (III) (abbreviation: [ Eu (TTA))₃(Phen)]) And the like.

Among the above, organometallic iridium complexes having a pyrazine skeleton are a group of compounds effective for achieving a red hue in one embodiment of the present invention. In particular, organometallic iridium complexes having a cyano group such as [ Ir (dmdppr-dmCP)₂(dpm)]And the like, and is preferable because of its high stability.

As the blue light-emitting substance, a substance having a photoluminescence peak wavelength of 430nm to 470nm, preferably 430nm to 460nm, can be used. The green light-emitting substance may have a peak wavelength of photoluminescence of 500nm to 540nm, preferably 500nm to 530 nm. As the red light-emitting substance, a substance having a photoluminescence peak wavelength of 610nm or more and 680nm or less, preferably 620nm or more and 680nm or less can be used. In addition, solutions or films may be used for the measurement of photoluminescence.

By using the above compound together with the microcavity effect, the chromaticity can be more easily achieved. In this case, the thickness of the semi-transmissive and semi-reflective electrode (metal thin film portion) required to obtain the microcavity effect is preferably 20nm or more and 40nm or less, and more preferably more than 25nm and 40nm or less. When the thickness exceeds 40nm, the efficiency may be lowered.

As the organic compound (host material, auxiliary material) used for the light-emitting layer 723, one or more selected substances having an energy gap larger than that of a light-emitting substance (guest material) can be used. The hole-transporting material and the electron-transporting material described later can be used as a host material or an auxiliary material, respectively.

When the light-emitting substance is a fluorescent material, an organic compound having a large singlet excited state and a small triplet excited state is preferably used as a host material. For example, an anthracene derivative or a tetracene derivative is preferably used. Specifically, 9-phenyl-3- [4- (10-phenyl-9-anthryl) phenyl ] -9H-carbazole (abbreviated as PCzPA), 3- [4- (1-naphthyl) -phenyl ] -9-phenyl-9H-carbazole (abbreviated as PCPN), 9- [4- (10-phenyl-9-anthracene) phenyl ] -9H-carbazole (abbreviated as CzPA), 7- [4- (10-phenyl-9-anthryl) phenyl ] -7H-dibenzo [ c, g ] carbazole (abbreviated as cgDBCzPA), 6- [3- (9, 10-diphenyl-2-anthryl) phenyl ] -benzo [ b ] naphtho [1,2-d ] furan (abbreviated as 2mBnfPPA), 9-phenyl-10- {4- (9-phenyl-9H-fluoren-9-yl) biphenyl-4' -yl } anthracene (abbreviated as FLPPA), 5, 12-diphenyltetracene, 5, 12-bis (biphenyl-2-yl) tetracene, and the like.

When the light-emitting substance is a phosphorescent material, an organic compound having triplet excitation energy larger than triplet excitation energy (energy difference between a ground state and a triplet excited state) of the light-emitting substance may be selected as a host material. In this case, a heteroaromatic compound such as a zinc or aluminum-based metal complex, an oxadiazole derivative, a triazole derivative, a benzimidazole derivative, a quinoxaline derivative, a dibenzoquinoxaline derivative, a dibenzothiophene derivative, a dibenzofuran derivative, a pyrimidine derivative, a triazine derivative, a pyridine derivative, a bipyridine derivative, or a phenanthroline derivative, an aromatic amine, a carbazole derivative, or the like can be used.

Specifically, tris (8-quinolinolato) aluminum (III) (Alq) and tris (4-methyl-8-quinolinolato) aluminum (III) (Almq)₃) Bis (10-hydroxybenzo [ h ]]Quinoline) beryllium (II) (abbreviation: BeBq₂) Bis (2-methyl-8-quinolinol) (4-phenylphenol) aluminum (III) (abbreviation: BAlq), bis (8-hydroxyquinoline) zinc (II) (abbreviation: znq), bis [2- (2-benzoxazolyl) phenol]Zinc (II) (ZnPBO for short), bis [2- (2-benzothiazolyl) phenol]Metal complexes such as zinc (II) (ZnBTZ for short); 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1, 3, 4-oxadiazole (PBD), 1, 3-bis [5- (p-tert-butylphenyl) -1, 3, 4-oxadiazol-2-yl]Benzene (abbreviated as OXD-7), 3- (4-biphenyl) -4-phenyl-5- (4-tert-butylphenyl) -1, 2, 4-triazole (abbreviated as TAZ), 2' - (1, 3, 5-benzenetriyl) -tris (1-phenyl-1H-benzimidazole) (abbreviated as TPBI), bathophenanthroline (abbreviated as BPhen), bathocuproine (abbreviated as BCP), 2, 9-bis (naphthalen-2-yl) -4, 7-diphenyl-1, 10-phenanthroline (abbreviated as NBphen), 9- [4- (5-phenyl-1, 3, 4-oxadiazol-2-yl) phenyl]Heterocyclic compounds such as-9H-carbazole (abbreviated as CO11), and aromatic amination such as NPB, TPD and BSPBA compound (I) is provided.

Further, there may be mentioned anthracene derivatives, phenanthrene derivatives, pyrene derivatives, perylene derivatives, (chrysene) derivatives, dibenzo [ g, p ]]Condensed polycyclic aromatic compounds such as (chrysene) derivatives. Specific examples thereof include 9, 10-diphenylanthracene (DPAnth), N-diphenyl-9- [4- (10-phenyl-9-anthryl) phenyl]-9H-carbazole-3-amine (CzA 1-1 PA), 4- (10-phenyl-9-anthryl) triphenylamine (DPhPA), YGAPA, PCAPA, N, 9-diphenyl-N- {4- [4- (10-phenyl-9-anthryl) phenyl]Phenyl } -9H-carbazole-3-amine (PCAPBA), 9, 10-diphenyl-2- [ N-phenyl-N- (9-phenyl-9H-carbazole-3-yl) amino]Anthracene (2 PCAPA for short), 6, 12-dimethoxy-5, 11-diphenylN, N, N ', N ', N ", N", N ' "-octaphenyldibenzo [ g, p]-2, 7, 10, 15-tetramine (DBC 1 for short) and 9- [4- (10-phenyl-9-anthracene) phenyl]-9H-carbazole (CzPA), 3, 6-diphenyl-9- [4- (10-phenyl-9-anthryl) phenyl]-9H-carbazole (abbreviated as DPCzPA), 9, 10-bis (3, 5-diphenylphenyl) anthracene (abbreviated as DPPA), 9, 10-bis (2-naphthyl) anthracene (abbreviated as DNA), 2-tert-butyl-9, 10-bis (2-naphthyl) anthracene (abbreviated as t-BuDNA), 9' -bianthracene (abbreviated as BANT), 9' - (stilbene-3, 3' -diyl) phenanthrene (abbreviated as DPNS), 9' - (stilbene-4, 4' -diyl) phenanthrene (abbreviated as DPNS2), and 1,3, 5-tris (1-pyrenyl) benzene (abbreviated as TPB 3).

In addition, when a plurality of organic compounds are used for the light-emitting layer 723, a compound which forms an exciplex and a light-emitting substance are preferably used in combination. In this case, various organic compounds can be used in combination as appropriate, but in order to efficiently form an exciplex, it is particularly preferable to combine a compound which easily receives holes (a hole-transporting material) and a compound which easily receives electrons (an electron-transporting material). As specific examples of the hole-transporting material and the electron-transporting material, materials described in this embodiment can be used.

The TADF material is a material capable of converting (up-converting) a triplet excited state into a singlet excited state (reverse intersystem crossing) by a small amount of thermal energy and efficiently exhibiting luminescence (fluorescence) from the singlet excited state. The conditions under which the thermally activated delayed fluorescence can be obtained with high efficiency are as follows: the energy difference between the triplet excitation level and the singlet excitation level is 0eV or more and 0.2eV or less, and preferably 0eV or more and 0.1eV or less. The delayed fluorescence exhibited by the TADF material means luminescence having a spectrum similar to that of general fluorescence but having a very long lifetime. The life is 10^-6Second or more, preferably 10 ^-3For more than a second.

Examples of the TADF material include fullerene or a derivative thereof, an acridine derivative such as luteolin, and eosin. Further, metal-containing porphyrins containing magnesium (Mg), zinc (Zn), cadmium (Cd), tin (Sn), platinum (Pt), indium (In), palladium (Pd), or the like can be cited. Examples of the metal-containing porphyrin include protoporphyrin-tin fluoride complex (SnF)₂(Proto IX)), mesoporphyrin-tin fluoride complex (SnF)₂(Meso IX)), hematoporphyrin-tin fluoride complex (SnF)₂(Hemato IX)), coproporphyrin tetramethyl ester-tin fluoride complex (SnF)₂(Copro III-4Me)), octaethylporphyrin-tin fluoride complex (SnF)₂(OEP)), protoporphyrin-tin fluoride complex (SnF)₂(Etio I)) and octaethylporphyrin-platinum chloride complex (PtCl)₂OEP), and the like.

In addition to the above, 2- (biphenyl-4-yl) -4, 6-bis (12-phenylindolo [2, 3-a ] carbazol-11-yl) -1, 3, 5-triazine (PIC-TRZ), 2- {4- [3- (N-phenyl-9H-carbazol-3-yl) -9H-carbazol-9-yl ] phenyl } -4, 6-diphenyl-1, 3, 5-triazine (PCCzPTzn), 2- [4- (10H-phenoxazin-10-yl) phenyl ] -4, 6-diphenyl-1, 3, 5-triazine (PXZ-TRZ), 3- [4- (5-phenyl-5, heterocyclic compounds having a pi-electron-rich aromatic heterocycle and a pi-electron-deficient aromatic heterocycle, such as 10-dihydrophenazine-10-yl) phenyl ] -4, 5-diphenyl-1, 2, 4-triazole (PPZ-3TPT), 3- (9, 9-dimethyl-9H-acridin-10-yl) -9H-xanthen-9-one (ACRXTN), bis [4- (9, 9-dimethyl-9, 10-dihydroacridin) phenyl ] sulfone (DMAC-DPS), and 10-phenyl-10H, 10 ' H-spiro [ acridine-9, 9 ' -anthracene ] -10 ' -one (ACRSA). In addition, in the case where a pi electron-rich aromatic heterocycle and a pi electron-deficient aromatic heterocycle are directly bonded to each other, it is particularly preferable that both donor and acceptor of the pi electron-rich aromatic heterocycle and acceptor of the pi electron-deficient aromatic heterocycle are strong, and the energy difference between a singlet excited state and a triplet excited state is small.

In addition, in the case of using the TADF material, other organic compounds may be used in combination.

< < electron transport layer 724 >)

The electron transport layer 724 is a layer that transports electrons injected from the conductive body 788 through the electron injection layer 725 into the light emitting layer 723. Further, the electron transporting layer 724 is a layer containing an electron transporting material. The electron transporting material for the electron transporting layer 724 is preferably a material having a thickness of 1X 10^-6cm²A substance having an electron mobility of greater than/Vs. In addition, any substance other than the above may be used as long as it has a higher electron-transport property than a hole-transport property.

Examples of the material for electron transport include metal complexes having quinoline ligands, benzoquinoline ligands, oxazole ligands and thiazole ligands, oxadiazole derivatives, triazole derivatives, phenanthroline derivatives, pyridine derivatives and bipyridine derivatives. In addition to the above, a pi-electron deficient heteroaromatic compound such as a nitrogen-containing heteroaromatic compound may be used.

Specifically, Alq₃Tris (4-methyl-8-quinolinolato) aluminum (III) (Almq for short)₃) Bis (10-hydroxybenzo [ h ]]-quinoline) beryllium (abbreviation: BeBq₂)、BAlq、Zn(BOX)₂Bis [2- (2-hydroxyphenyl) -benzothiazoles]Zinc (abbreviation: Zn (BTZ)) ₂) (II), and 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1, 3, 4-oxadiazole (abbreviation: PBD), 1, 3-bis [5- (p-tert-butylphenyl) -1, 3, 4-oxadiazol-2-yl]Benzene (abbreviation: OXD-7), 3- (4' -biphenyl) -4-phenyl-5- (4) "-tert-butylphenyl) -1, 2, 4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenyl) -1, 2, 4-triazole (abbreviation: p-etaz), bathophenanthroline (abbreviation: bphen), bathocuproine (abbreviation: BCP), 4' -bis (5-methylbenzoxazol-2-yl) stilbene (abbreviation: BzOs), 2- [3- (dibenzothiophen-4-yl) phenyl]Dibenzo [ f, h ]]Quinoxaline (abbreviation: 2mDBTPDBq-II), 2- [ 3' - (dibenzothiophen-4-yl) biphenyl-3-yl]Dibenzo [ f, h ]]Quinoxaline (abbreviation: 2mDBTBPDBq-II), 2- [4- (3, 6-diphenyl-9H-carbazol-9-yl) phenyl]Dibenzo [ f, h ]]Quinoxaline (abbreviation: 2CzPDBq-III), 7- [3- (dibenzothiophene-4-yl) phenyl]Dibenzo [ f, h ]]Quinoxaline (abbreviation: 7mDBTPDBq-II) and 6- [3- (dibenzothiophen-4-yl) phenyl]Dibenzo [ f, h ]]Quinoxaline derivatives such as quinoxaline (abbreviated as 6mDBTPDBq-II) or dibenzoquinoxaline derivatives.

In addition, polymer compounds such as poly (2, 5-pyridyldiyl) (abbreviated as PPy), poly [ (9, 9-dihexylfluorene-2, 7-diyl) -co- (pyridine-3, 5-diyl) ] (abbreviated as PF-Py), poly [ (9, 9-dioctylfluorene-2, 7-diyl) -co- (2, 2 '-bipyridine-6, 6' -diyl) ] (abbreviated as PF-BPy) and the like can be used.

The electron-transporting layer 724 may be formed of a single layer or may be formed by stacking two or more layers made of the above-described substances.

< Electron injection layer 725 >)

The electron injection layer 725 is a layer containing a substance having a high electron injection property. As the electron injection layer 725, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF), or the like can be used₂) And lithium oxide (LiO)_x) And the like, alkali metals, alkaline earth metals, or compounds of these metals. In addition, erbium fluoride (ErF) may be used₃) And the like. In addition, an electron salt may also be used for the electron injection layer 725. Examples of the electron salt include a mixed oxide of calcium and aluminum to which electrons are added at a high concentration. Further, the electron-transporting layer 724 can be formed using the above-described materials.

In addition, a composite material in which an organic compound and an electron donor (donor) are mixed may be used for the electron injection layer 725. This composite material has excellent electron injection and electron transport properties because electrons are generated in an organic compound by an electron donor. In this case, the organic compound is preferably a material excellent in transporting generated electrons, and specifically, for example, an electron transporting material (a metal complex, a heteroaromatic compound, or the like) used for the electron transporting layer 724 as described above can be used. The electron donor may be any one that can donate electrons to an organic compound. Specifically, alkali metals, alkaline earth metals, and rare earth metals are preferably used, and examples thereof include lithium, cesium, magnesium, calcium, erbium, and ytterbium. In addition, alkali metal oxides or alkaline earth metal oxides are preferably used, and examples thereof include lithium oxide, calcium oxide, barium oxide, and the like. In addition, lewis bases such as magnesium oxide can also be used. Furthermore, organic compounds such as tetrathiafulvalene (TTF) may be used.

< < Charge generation layer 792 >)

The charge generation layer 792 has the following functions: when a voltage is applied to the electric conductor 772 and the electric conductor 788, electrons are injected into one EL layer 786 which is closer to the electric conductor 772 and holes are injected into one EL layer 786 which is closer to the electric conductor 788 of the two EL layers 786 which are in contact with the charge generation layer 792. For example, in the light-emitting element 572 having the structure shown in fig. 27C, the charge generation layer 792 has a function of injecting electrons into the EL layer 786a and injecting holes into the EL layer 786 b. The charge generation layer 792 may have a structure in which an electron acceptor (acceptor) is added to the hole-transporting material, or a structure in which an electron donor (donor) is added to the electron-transporting material. Alternatively, these two structures may be stacked. Further, by forming the charge generation layer 792 using the above materials, an increase in driving voltage of the display device 10 when EL layers are stacked can be suppressed.

When the charge generation layer 792 has a structure in which an electron acceptor is added to the hole-transporting material, the electron acceptor may be 7,7,8, 8-tetracyano-2, 3,5, 6-tetrafluoroquinodimethane (abbreviated as F)₄-TCNQ), chloranil, and the like. Further, there may be mentioned metals belonging to the elements of groups 4 to 8 of the periodic Table of the elements An oxide of (a). Specific examples thereof include vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, and rhenium oxide.

When the charge generation layer 792 has a structure in which an electron donor is added to the electron transporting material, an alkali metal, an alkaline earth metal, a rare earth metal, a metal belonging to group 2 or group 13 of the periodic table of the elements, and an oxide or a carbonate thereof can be used as the electron donor. Specifically, lithium (Li), cesium (Cs), magnesium (Mg), calcium (Ca), ytterbium (Yb), indium (In), lithium oxide, cesium carbonate, and the like are preferably used. Further, an organic compound such as tetrathianaphtalene (tetrathianaphtalene) may also be used as the electron donor.

In the case of manufacturing the light-emitting element 572, a vacuum process such as a vapor deposition method or a solution process such as a spin coating method or an ink jet method can be used. As the vapor deposition method, a physical vapor deposition method (PVD method) such as a sputtering method, an ion plating method, an ion beam vapor deposition method, a molecular beam vapor deposition method, or a vacuum vapor deposition method, a chemical vapor deposition method (CVD method), or the like can be used. In particular, the functional layer (the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer) and the charge generation layer included in the EL layer of the light emitting element can be formed by a method such as a vapor deposition method (vacuum vapor deposition method), a coating method (dip coating method, dye coating method, bar coating method, spin coating method, spray coating method), a printing method (an ink jet method, a screen printing (stencil printing) method, an offset printing (lithography printing) method, a flexographic printing (relief printing) method, a gravure printing method, or a micro contact printing method).

The materials of the functional layers (the hole injection layer, the hole transport layer, the light-emitting layer, the electron transport layer, and the electron injection layer) and the charge generation layer constituting the EL layer of the light-emitting element described in this embodiment mode are not limited to these, and any material may be used in combination as long as the function of each layer can be satisfied. As an example, a high molecular compound (oligomer, dendrimer, polymer, etc.), a medium molecular compound (compound between low and high molecules: molecular weight 400 to 4000), an inorganic compound (quantum dot material, etc.), or the like can be used. As the quantum dot material, a colloidal quantum dot material, an alloy type quantum dot material, a Core Shell (Core Shell) type quantum dot material, a Core type quantum dot material, or the like can be used.

At least a part of the configuration examples shown in this embodiment mode and the drawings corresponding to these examples can be implemented in appropriate combination with other configuration examples or drawings.

At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

(embodiment mode 2)

In this embodiment mode, a transistor which can be used for a display device which is one embodiment of the present invention will be described.

< structural example 1 of transistor >

Fig. 28A, 28B, and 28C are a top view and a cross-sectional view of a transistor 200A and the periphery of the transistor 200A, which can be used in a display device according to one embodiment of the present invention. The transistor 200A can be applied to a display device which is one embodiment of the present invention.

Fig. 28A is a top view of the transistor 200A. Fig. 28B and 28C are cross-sectional views of the transistor 200A. Here, fig. 28B is a sectional view along a chain line a1-a2 in fig. 28A, which corresponds to a sectional view in the channel length direction of the transistor 200A. Fig. 28C is a sectional view along a chain line A3-a4 in fig. 28A, which corresponds to a sectional view in the channel width direction of the transistor 200A. Note that, for ease of understanding, some of the constituent elements are omitted in the top view of fig. 28A.

As shown in fig. 28A to 28C, the transistor 200A includes: a metal oxide 230a disposed on a substrate (not shown); a metal oxide 230b disposed on the metal oxide 230 a; conductors 242a and 242b disposed on metal oxide 230b and separated from each other; an insulator 280 disposed on the conductors 242a and 242b and having an opening formed so as to overlap the conductors 242a and 242 b; a conductor 260 disposed in the opening; an insulator 250 disposed between the metal oxide 230b, the conductor 242a, the conductor 242b, and the insulator 280 and the conductor 260; and a metal oxide 230c disposed between the metal oxide 230b, the conductor 242a, the conductor 242b, and the insulator 280 and the insulator 250. Here, as shown in fig. 28B and 28C, the top surface of the conductive body 260 preferably substantially coincides with the top surfaces of the insulator 250, the insulator 254, the metal oxide 230C, and the insulator 280. Hereinafter, the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may be collectively referred to as an oxide 230. The conductors 242a and 242b may be collectively referred to as conductors 242.

In the transistor 200A shown in fig. 28B, the side surfaces of the conductors 242a and 242B on the conductor 260 side are substantially perpendicular to the bottom surface. Note that the transistor 200A shown in fig. 28A to 28C is not limited to this, and the angle formed by the side surface and the bottom surface of the conductor 242a and the conductor 242b may be 10 ° or more and 80 ° or less, and preferably 30 ° or more and 60 ° or less. The conductors 242a and 242b may have a structure in which the facing side surfaces thereof have a plurality of surfaces.

As shown in fig. 28A to 28C, an insulator 254 is preferably provided between the insulator 224, the metal oxide 230a, the metal oxide 230b, the conductor 242a, the conductor 242b, and the metal oxide 230C, and the insulator 280. Here, as shown in fig. 28B and 28C, the insulator 254 preferably contacts the side surface of the metal oxide 230C, the top surface and the side surface of the conductor 242a, the top surface and the side surface of the conductor 242B, the side surfaces of the metal oxide 230a and the metal oxide 230B, and the top surface of the insulator 224.

Note that in the transistor 200A, three layers of a metal oxide 230A, a metal oxide 230b, and a metal oxide 230c are stacked in a region where a channel is formed (hereinafter also referred to as a channel formation region) and in the vicinity thereof, but the present invention is not limited thereto. For example, the metal oxide 230b and the metal oxide 230c may have a two-layer structure or a stacked-layer structure of four or more layers. Further, in the transistor 200A, the conductive body 260 has a two-layer structure, but the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a stacked-layer structure of three or more layers. The metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may each have a stacked-layer structure of two or more layers.

For example, in the case where the metal oxide 230c has a stacked-layer structure composed of a first oxide and a second oxide over the first oxide, the first oxide may have the same composition as the metal oxide 230b, and the second oxide preferably has the same composition as the metal oxide 230 a.

Here, the conductor 260 functions as a gate electrode of the transistor, and the conductors 242a and 242b each function as a source electrode or a drain electrode. As described above, the conductor 260 is formed to be embedded in the opening of the insulator 280 and the region sandwiched between the conductors 242a and 242 b. Here, the conductors 260, 242a, and 242b are arranged so as to be self-aligned with the openings of the insulator 280. That is, in the transistor 200A, the gate electrode can be disposed between the source electrode and the drain electrode in self-alignment. Thus, the conductor 260 can be formed without providing a margin for alignment, and therefore, the area occupied by the transistor 200A can be reduced. This can realize an increase in pixel density of the display device. In addition, a display device with a narrow bezel can be realized.

As shown in fig. 28A to 28C, the conductor 260 preferably includes a conductor 260a disposed inside the insulator 250 and a conductor 260b disposed so as to be embedded inside the conductor 260 a.

The transistor 200A preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, and an insulator 224 disposed on the insulator 222. Preferably, a metal oxide 230a is disposed on the insulator 224.

In addition, an insulator 274 and an insulator 281 which are used as interlayer films are preferably provided over the transistor 200A. Here, the insulator 274 is preferably in contact with the top surfaces of the conductor 260, the insulator 250, the insulator 254, the metal oxide 230c, and the insulator 280.

The insulator 222, the insulator 254, and the insulator 274 preferably have a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like). For example, the insulators 222, 254, and 274 preferably have lower hydrogen permeability than the insulators 224, 250, and 280. The insulator 222 and the insulator 254 preferably have a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, or the like). For example, the insulators 222 and 254 preferably have lower oxygen permeability than the insulators 224, 250, and 280.

Here, insulator 224, oxide 230, and insulator 250 are separated from insulators 280 and 281 by insulator 254 and insulator 274. This can suppress impurities such as hydrogen and excessive oxygen contained in the insulators 280 and 281 from being mixed into the insulators 224, the metal oxides 230, and the insulators 250.

The semiconductor device preferably includes a conductor 240 (a conductor 240A and a conductor 240b) which is electrically connected to the transistor 200A and serves as a plug. Further, an insulator 241 (an insulator 241a and an insulator 241b) which is in contact with a side surface of the conductor 240 used as a plug is further included. That is, the insulator 241 is formed so as to be in contact with the inner walls of the openings of the insulator 254, the insulator 280, the insulator 274, and the insulator 281. Further, a first conductor of the conductors 240 may be provided in contact with a side surface of the insulator 241, and a second conductor may be provided inside the first conductor. Here, the height of the top surface of the conductor 240 and the height of the top surface of the insulator 281 may be substantially the same. In the transistor 200A, the first conductor of the conductors 240 and the second conductor of the conductors 240 are stacked, but the present invention is not limited to this. For example, the conductor 240 may have a single-layer structure or a stacked-layer structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by giving ordinal numbers in the order of formation.

In the transistor 200A, a metal oxide used as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the metal oxide 230A, the metal oxide 230b, and the metal oxide 230c) including the channel formation region. For example, as the metal oxide to be the channel formation region of the oxide 230, a metal oxide having a band gap of 2eV or more, preferably 2.5eV or more is preferably used.

The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, indium (In) or zinc (Zn) is preferably contained. In addition, it is preferable that the element M is contained. The element M may be one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), cobalt (Co), and the like. In particular, the element M is preferably aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn).

As shown in fig. 28B, the thickness of the region of the metal oxide 230B that does not overlap the conductor 242 may be thinner than the thickness of the region that overlaps the conductor 242. This is because a part of the top surface of the metal oxide 230b is removed when the conductive body 242a and the conductive body 242b are formed. When a conductive film serving as the conductor 242 is formed on the top surface of the metal oxide 230b, a low-resistance region may be formed in the vicinity of the interface with the conductive film. In this manner, by removing the low-resistance region between the conductive body 242a and the conductive body 242b on the top surface of the metal oxide 230b, the channel can be suppressed from being formed in this region.

According to one embodiment of the present invention, a display device which includes a transistor with a small size and has high pixel density can be provided. Further, a display device which includes a transistor with a large on-state current and has high luminance can be provided. Further, a display device which includes a transistor whose operation speed is high and whose operation speed is high can be provided. Further, a display device including a transistor with stable electric characteristics and having high reliability can be provided. Further, a display device which includes a transistor with a small off-state current and whose power consumption is low can be provided.

A detailed structure of the transistor 200A which can be used in a display device which is one embodiment of the present invention is described below.

The conductor 205 is disposed so as to include a region overlapping with the oxide 230 and the conductor 260. Further, the conductive body 205 is preferably provided in a manner of being embedded in the insulator 216. Here, the flatness of the top surface of the conductor 205 is preferably high. For example, the average surface roughness (Ra) of the top surface of the conductor 205 may be 1nm or less, preferably 0.5nm or less, and more preferably 0.3nm or less. This improves the flatness of the insulator 224 formed on the conductor 205, and improves the crystallinity of the metal oxide 230b and the metal oxide 230 c.

Here, the conductor 260 is sometimes used as a first gate (also referred to as a top gate) electrode. In addition, the conductive body 205 is sometimes used as a second gate (also referred to as a bottom gate) electrode. In this case, V of the transistor 200A can be controlled by independently changing the potential supplied to the conductor 205 without interlocking with the potential supplied to the conductor 260_th. In particular, V of the transistor 200A can be set by supplying a negative potential to the conductive body 205_thGreater than 0V and may reduce off-state current. Therefore, in the case where a negative potential is applied to the conductor 205, the drain current when the potential supplied to the conductor 260 is 0V can be reduced as compared with the case where a negative potential is not applied to the conductor 205.

Further, the conductive body 205 is preferably larger than the channel formation region in the metal oxide 230. In particular, as shown in fig. 28C, the conductive body 205 preferably extends to a region outside the end portion intersecting the metal oxide 230 in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap each other with an insulator interposed therebetween outside the side surface of the metal oxide 230 in the channel width direction.

That is, by having the above-described structure, the channel formation region of the metal oxide 230 can be electrically surrounded by the electric field of the conductive body 260 serving as the first gate electrode and the electric field of the conductive body 205 serving as the second gate electrode.

As shown in fig. 28C, the conductor 205 is extended to be used as a wiring. However, the present invention is not limited to this, and a conductor used as a wiring may be provided under the conductor 205.

As the conductor 205, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. In the drawings, the conductive body 205 is illustrated as a single layer, but the conductive body 205 may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above-described conductive material may be employed.

In addition, it is also possibleSo as to use a material having a function of suppressing hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N) under the conductive body 205₂O、NO、NO₂Etc.), copper atoms, etc., and functions as a diffusion of impurities (the impurities are not easily permeated). Further, it is preferable to use a conductor having a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, or the like) (not easily permeable to the oxygen). In the present specification, the "function of suppressing diffusion of an impurity or oxygen" refers to a function of suppressing diffusion of any or all of the impurity and the oxygen.

Further, when a conductor having a function of suppressing oxygen diffusion is used under the conductor 205, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 205. As the conductor having a function of suppressing oxygen diffusion, for example, tantalum nitride, ruthenium oxide, or the like is preferably used. Therefore, as the conductor 205, a single layer or a stacked layer of the above-described conductive material can be used.

The insulator 214 is preferably used as a barrier insulating film which suppresses entry of impurities such as water or hydrogen into the transistor 200A from the substrate side. Therefore, it is preferable to use a material having a function of suppressing hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N)₂O、NO、NO₂Etc.), copper atoms, etc., and functions to diffuse impurities such as copper atoms (the impurities are not easily permeated). Further, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, or the like) (the oxygen is not easily permeated).

For example, alumina, silicon nitride, or the like is preferably used as the insulator 214. This can prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200A side of the insulator 214. Further, oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side than the insulator 214.

The relative dielectric constant of the insulator 216, the insulator 280, and the insulator 281 used as the interlayer film is preferably lower than that of the insulator 214. By using a material having a low relative dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 216, the insulator 280, and the insulator 281, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having a void, or the like is suitably used.

Insulator 222 and insulator 224 are used as gate insulators.

Here, in the insulator 224 in contact with the metal oxide 230, oxygen is preferably desorbed by heating. In this specification and the like, oxygen desorbed by heating is sometimes referred to as excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be used as the insulator 224. By providing an insulator containing oxygen in contact with the metal oxide 230, oxygen defects in the metal oxide 230 can be reduced, and thus the reliability of the transistor 200A can be improved.

Specifically, as the insulator 224, an oxide material in which a part of oxygen is desorbed by heating is preferably used. The oxide in which oxygen is desorbed by heating means that the amount of oxygen desorbed as converted into oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0X 10¹⁸atoms/cm³Above, preferably 1.0X 10¹⁹atoms/cm³The above is more preferably 2.0 × 10¹⁹atoms/cm³Above, or 3.0 × 10²⁰atoms/cm³The above oxide film. The surface temperature of the membrane when TDS analysis is performed is preferably in the range of 100 ℃ to 700 ℃ or more, or 100 ℃ to 400 ℃ or less.

As shown in fig. 28C, the insulator 224 may have a thinner thickness in a region not overlapping with the insulator 254 and not overlapping with the metal oxide 230b than in other regions. In the insulator 224, a region not overlapping with the insulator 254 and not overlapping with the metal oxide 230b preferably has a thickness sufficient to diffuse the above-described oxygen.

The insulator 222 is preferably used as a barrier insulating film which suppresses impurities such as water and hydrogen from entering the transistor 200A from the substrate side, similarly to the insulator 214. For example, insulator 222 preferably has a lower hydrogen permeability than insulator 224. By surrounding the insulator 224, the metal oxide 230, the insulator 250, and the like with the insulator 222, the insulator 254, and the insulator 274, it is possible to suppress intrusion of impurities such as water and hydrogen from the outside into the transistor 200A.

Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, or the like) (the oxygen is not easily permeated). For example, insulator 222 preferably has a lower oxygen permeability than insulator 224. It is preferable that the insulator 222 has a function of suppressing diffusion of oxygen or impurities, because diffusion of oxygen contained in the metal oxide 230 to the substrate side can be reduced. Further, the reaction of the conductor 205 with oxygen contained in the insulator 224 and the metal oxide 230 can be suppressed.

As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used as an insulating material. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 222 is formed using such a material, the insulator 222 is used as a layer which suppresses release of oxygen from the metal oxide 230 or entry of impurities such as hydrogen into the metal oxide 230 from the peripheral portion of the transistor 200A.

Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Further, the insulator may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

Further, as the insulator 222, for example, a single layer or a stacked layer including aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate (SrTiO) may be used₃) Or (Ba, Sr) TiO₃(BST), and the like. When miniaturization and high integration of a transistor are performed, a problem of leakage current or the like may occur due to the thinning of a gate insulator. By using a high-k material as an insulator used as a gate insulator, the gate potential at the time of operation of the transistor can be reduced while maintaining the physical thickness.

The insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the laminated structure is not limited to the laminated structure made of the same material, and may be a laminated structure made of different materials. For example, an insulator similar to the insulator 224 may be provided under the insulator 222.

Metal oxide 230 includes metal oxide 230a, metal oxide 230b on metal oxide 230a, and metal oxide 230c on metal oxide 230 b. When the metal oxide 230a is provided under the metal oxide 230b, diffusion of impurities from a structure formed under the metal oxide 230a to the metal oxide 230b can be suppressed. When the metal oxide 230c is provided on the metal oxide 230b, diffusion of impurities from the structure formed above the metal oxide 230c to the metal oxide 230b can be suppressed.

The metal oxide 230 preferably has a stacked structure of oxides having different atomic number ratios of metal atoms. For example, In the case where the metal oxide 230 contains at least indium (In) and an element M, the atomic number ratio of the element M to other elements In the constituent elements of the metal oxide 230a is preferably larger than the atomic number ratio of the element M to other elements In the constituent elements of the metal oxide 230 b. The atomic number ratio of the element M to In the metal oxide 230a is preferably larger than the atomic number ratio of the element M to In the metal oxide 230 b. Here, as the metal oxide 230c, a metal oxide that can be used for the metal oxide 230a or the metal oxide 230b can be used.

Preferably, the energy of the conduction band bottom of metal oxide 230a and metal oxide 230c is higher than the energy of the conduction band bottom of metal oxide 230 b. In other words, the electron affinity of the metal oxide 230a and the metal oxide 230c is preferably smaller than that of the metal oxide 230 b. In this case, the metal oxide 230c preferably uses a metal oxide that can be used for the metal oxide 230 a. Specifically, the atomic number ratio of the element M to the other elements in the constituent elements of the metal oxide 230c is preferably larger than the atomic number ratio of the element M to the other elements in the constituent elements of the metal oxide 230 b. The atomic number ratio of the element M to In the metal oxide 230c is preferably larger than the atomic number ratio of the element M to In the metal oxide 230 b.

Here, the energy level of the conduction band bottom changes gently at the junction of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230 c. In other words, the above case can be expressed as the case where the energy levels of the conduction band bottoms of the junctions of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c are continuously changed or continuously joined. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface between the metal oxide 230a and the metal oxide 230b and the interface between the metal oxide 230b and the metal oxide 230 c.

Specifically, by including a common element (as a main component) in addition to oxygen in the metal oxide 230a and the metal oxide 230b and the metal oxide 230c, a mixed layer having a low defect state density can be formed. For example, when the metal oxide 230b is an In-Ga-Zn oxide, gallium oxide, or the like can be used as the metal oxide 230a and the metal oxide 230 c. In addition, the metal oxide 230c may have a stacked-layer structure. For example, a stacked-layer structure of an In-Ga-Zn oxide and a Ga-Zn oxide over the In-Ga-Zn oxide may be used, or a stacked-layer structure of an In-Ga-Zn oxide and a gallium oxide over the In-Ga-Zn oxide may be used. In other words, as the metal oxide 230c, a stacked-layer structure of an In — Ga — Zn oxide and an oxide containing no In may also be used.

Specifically, In: ga: 1, Zn: 3: 4[ atomic number ratio ] or 1: 1: 0.5[ atomic number ratio ] of metal oxide. In addition, as the metal oxide 230b, In: ga: zn is 4: 2: 3[ atomic number ratio ] or 3: 1: 2[ atomic number ratio ], or a mixture thereof. In addition, as the metal oxide 230c, In: ga: 1, Zn: 3: 4[ atomic number ratio ], In: ga: zn is 4: 2: 3[ atomic number ratio ], Ga: zn is 2: 1[ atomic number ratio ] or Ga: zn is 2: 5[ atomic number ratio ], or a mixture thereof. Specific examples of the case where the metal oxide 230c has a stacked-layer structure include In: ga: zn is 4: 2: 3[ atomic number ratio ] and Ga: zn is 2: 1[ atomic number ratio ], In: ga: zn is 4: 2: 3[ atomic number ratio ] and Ga: zn is 2: 5[ atomic number ratio ], In: ga: zn is 4: 2: 3[ atomic number ratio ] and a gallium oxide laminated structure.

At this time, the main path of the carriers is the metal oxide 230 b. By providing the metal oxide 230a and the metal oxide 230c with the above-described structures, the defect state density at the interface between the metal oxide 230a and the metal oxide 230b and the interface between the metal oxide 230b and the metal oxide 230c can be reduced. Therefore, the influence of the interface scattering on the carrier conduction is reduced, so that the transistor 200A can obtain a high-pass current and high-frequency characteristics. In addition, when the metal oxide 230c has a stacked structure, an effect of reducing the defect state density at the interface between the metal oxide 230b and the metal oxide 230c and an effect of suppressing diffusion of the constituent elements of the metal oxide 230c to the insulator 250 side are expected. More specifically, when the metal oxide 230c has a stacked-layer structure, since an oxide containing no In is located above the stacked-layer structure, In which can diffuse to the insulator 250 side can be suppressed. Since the insulator 250 is used as a gate insulator, the transistor characteristics are poor In the case where In is diffused therein. Thus, a highly reliable display device can be provided by providing the metal oxide 230c with a stacked structure.

Conductors 242 (conductors 242a and 242b) serving as source and drain electrodes are provided over the metal oxide 230 b. As the conductor 242, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element as a component, an alloy combining the above metal elements, or the like is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity, and thus are preferable.

When the conductor 242 is formed so as to be in contact with the metal oxide 230, the oxygen concentration in the metal oxide 230 in the vicinity of the conductor 242 may be reduced. In addition, a metal compound layer including the metal contained in the conductor 242 and the component of the metal oxide 230 may be formed in the vicinity of the conductor 242 in the metal oxide 230. In this case, the carrier density in the region of the metal oxide 230 near the conductive body 242 increases, and the resistance of the region decreases.

Here, the region between the conductor 242a and the conductor 242b is formed so as to overlap the opening of the insulator 280. Therefore, the conductor 260 can be disposed in self-alignment between the conductor 242a and the conductor 242 b.

Insulator 250 is used as a gate insulator. The insulator 250 is preferably disposed in contact with the top surface of the metal oxide 230 c. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability.

Similarly to the insulator 224, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 250. The thickness of the insulator 250 is preferably 1nm or more and 20nm or less.

Further, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably inhibits oxygen diffusion from the insulator 250 to the conductor 260. This can suppress oxidation of the conductor 260 due to oxygen in the insulator 250.

In addition, the metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, a metal oxide which is a high-k material having a high relative dielectric constant is preferably used as the metal oxide. By providing the gate insulator with a stacked structure of the insulator 250 and the metal oxide, a stacked structure having thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied at the time of the transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the Equivalent Oxide Thickness (EOT) of the insulator used as the gate insulator can be reduced.

Specifically, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like are preferably used as insulators containing an oxide of one or both of aluminum and hafnium.

Although the electric conductor 260 has a two-layer structure in fig. 28A to 28C, it may have a single-layer structure or a stacked-layer structure of three or more layers.

The conductor 260a preferably contains the above-mentioned hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, and nitrogen oxide molecule (N)₂O、NO、NO₂Etc.), copper atoms, etc. Further, a conductive material having a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, or the like) is preferably used.

Further, when the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b by oxygen contained in the insulator 250. As the conductive material having a function of suppressing oxygen diffusion, for example, tantalum nitride, ruthenium oxide, or the like is preferably used.

In addition, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used for the conductor 260 b. Further, since the conductor 260 is also used as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 260b may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above-described conductive material.

As shown in fig. 28A and 28C, in a region of the metal oxide 230b not overlapping with the conductor 242, that is, in a channel formation region of the metal oxide 230, a side surface of the metal oxide 230 is covered with the conductor 260. This makes it possible to easily influence the electric field of the conductor 260 used as the first gate electrode on the side surface of the metal oxide 230. This can improve the on-state current and frequency characteristics of the transistor 200A.

The insulator 254 is preferably used as a barrier insulating film for suppressing impurities such as water and hydrogen from entering the transistor 200A from the insulator 280 side, similarly to the insulator 214 and the like. For example, the insulator 254 preferably has a lower hydrogen permeability than the insulator 224. As shown in fig. 28B and 28C, the insulator 254 preferably contacts the side surfaces of the metal oxide 230C, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242B, the side surfaces of the metal oxide 230a and the metal oxide 230B, and the top surface of the insulator 224. With this structure, hydrogen contained in the insulator 280 can be prevented from entering the metal oxide 230 from the top surfaces or the side surfaces of the conductor 242a, the conductor 242b, the metal oxide 230a, the metal oxide 230b, and the insulator 224.

Further, the insulator 254 has a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, or the like) (the oxygen is not easily permeated). For example, insulator 254 preferably has a lower oxygen permeability than insulator 280 or insulator 224.

The insulator 254 is preferably formed by sputtering. By forming the insulator 254 by a sputtering method in an atmosphere containing oxygen, oxygen can be added to the vicinity of the region where the insulator 224 and the insulator 254 are in contact. Thereby, oxygen can be supplied from this region through the insulator 224 into the metal oxide 230. Here, by making the insulator 254 have a function of suppressing oxygen diffusion to the upper side, oxygen can be prevented from diffusing from the metal oxide 230 to the insulator 280. Further, by making the insulator 222 have a function of suppressing oxygen diffusion to the lower side, oxygen can be prevented from diffusing from the metal oxide 230 to the substrate side. In this manner, oxygen is supplied to the channel formation region in the metal oxide 230. Thereby, oxygen defects of the metal oxide 230 can be reduced and the transistor can be suppressed from normally-on.

As the insulator 254, for example, an insulator containing an oxide of one or more of aluminum and hafnium can be formed. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.

As described above, the insulator 254 is separated from the insulator 224, the metal oxide 230, and the insulator 250 by the insulator 254, and the insulator 224, the insulator 250, and the metal oxide 230 are covered with the insulator 254 having a barrier property against hydrogen. This can suppress the intrusion of impurities such as hydrogen from the outside of the transistor 200A, and can provide the transistor 200A with excellent electrical characteristics and reliability.

The insulator 280 is preferably provided on the insulator 224, the metal oxide 230, and the conductor 242 with the insulator 254 interposed therebetween. For example, the insulator 280 is preferably formed of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having a hole, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having a void is preferable because a region containing oxygen which is desorbed by heating is easily formed.

Further, the concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. In addition, the top surface of the insulator 280 may also be planarized.

The insulator 274 is preferably used as a barrier insulating film for suppressing impurities such as water and hydrogen from entering the insulator 280 from above, similarly to the insulator 214. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, or the like can be used.

Further, an insulator 281 used as an interlayer film is preferably provided over the insulator 274. As with the insulator 224 or the like, the concentration of impurities such as water or hydrogen in the insulator 281 is preferably reduced.

In addition, the conductors 240a and 240b are arranged in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductor 240a and the conductor 240b are provided with the conductor 260 interposed therebetween. The heights of the top surfaces of the conductors 240a and 240b and the top surface of the insulator 281 may be flush with each other.

Further, an insulator 241a is provided so as to be in contact with the insulator 281, the insulator 274, the insulator 280, and the inner wall of the opening of the insulator 254, and a first conductor of the conductor 240a is formed so as to be in contact with the side surface thereof. Conductor 242a is located at least partially at the bottom of the opening, and conductor 240a is in contact with conductor 242 a. Similarly, an insulator 241b is provided so as to contact the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of the conductor 240b is formed so as to contact the side surface thereof. Conductor 242b is located at least partially at the bottom of the opening, and conductor 240b is in contact with conductor 242 b.

The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a laminated structure.

When the conductor 240 has a stacked-layer structure, it is preferable to use the conductor having a function of suppressing diffusion of impurities such as water and hydrogen as described above as the conductor in contact with the metal oxide 230a, the metal oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, tantalum nitride, titanium nitride, ruthenium oxide, or the like is preferably used. A conductive material having a function of suppressing diffusion of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using such a conductive material, oxygen added to the insulator 280 can be prevented from being absorbed by the conductors 240a and 240 b. Further, impurities such as water and hydrogen can be prevented from entering the metal oxide 230 from the layer above the insulator 281 through the conductors 240a and 240 b.

As the insulators 241a and 241b, for example, insulators usable for the insulator 254 or the like may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 254, impurities such as water and hydrogen from the insulator 280 can be prevented from being mixed into the metal oxide 230 through the conductor 240a and the conductor 240 b. Further, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240 b.

Although not shown, a conductor used as a wiring may be disposed so as to be in contact with the top surface of the conductor 240a and the top surface of the conductor 240 b. As the conductor used for the wiring, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. The conductor may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above-described conductive material. The conductor may be formed to be embedded in the opening of the insulator.

< example of Structure of transistor 2>

Fig. 29A, 29B, and 29C are a top view and a cross-sectional view of a transistor 200B and the periphery of the transistor 200B, which can be used in a display device which is one embodiment of the present invention. The transistor 200B is a modification of the transistor 200A.

Fig. 29A is a top view of the transistor 200B. Fig. 29B and 29C are cross-sectional views of the transistor 200B. Here, fig. 29B is a sectional view along a chain line B1-B2 in fig. 29A, which corresponds to a sectional view in the channel length direction of the transistor 200B. Fig. 29C is a sectional view along a chain line B3-B4 in fig. 29A, which corresponds to a sectional view in the channel width direction of the transistor 200B. Note that, for easy understanding, some constituent elements are omitted in the top view of fig. 29A.

In the transistor 200B, the conductors 242a and 242B have regions overlapping with the metal oxide 230c, the insulator 250, and the conductor 260. Thus, the transistor 200B can be a transistor with high on-state current. Further, the transistor 200B may be a transistor which is easily controlled.

The conductor 260 serving as a gate electrode includes a conductor 260a and a conductor 260b over the conductor 260 a. The conductor 260a is preferably made of a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Further, a conductive material having a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, or the like) is preferably used.

By providing the conductor 260a with a function of suppressing oxygen diffusion, the material selectivity of the conductor 260b can be improved. That is, by including the conductor 260a, oxidation of the conductor 260b can be suppressed, and thus a decrease in conductivity can be suppressed.

The insulator 254 is preferably provided so as to cover the top and side surfaces of the conductor 260, the side surfaces of the insulator 250, and the side surfaces of the metal oxide 230 c. As the insulator 254, an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen is preferably used.

By providing the insulator 254, oxidation of the conductive body 260 can be suppressed. Further, by including the insulator 254, diffusion of impurities such as water and hydrogen contained in the insulator 280 into the transistor 200B can be suppressed.

< example of Structure of transistor 3>

Fig. 30A, 30B, and 30C are a top view and a cross-sectional view of a transistor 200C and the periphery of the transistor 200C, which can be used in a display device according to one embodiment of the present invention. The transistor 200C is a modification example of the transistor 200A.

Fig. 30A is a top view of the transistor 200C. Fig. 30B and 30C are cross-sectional views of the transistor 200C. Here, fig. 30B is a sectional view along a chain line C1-C2 in fig. 30A, which corresponds to a sectional view in the channel length direction of the transistor 200C. Fig. 30C is a sectional view along a chain line C3-C4 in fig. 30A, which corresponds to a sectional view in the channel width direction of the transistor 200C. Note that, for ease of understanding, some of the constituent elements are omitted in the top view of fig. 30A.

In transistor 200C, an insulator 250 is included on metal oxide 230C and a metal oxide 252 is included on insulator 250. Further, a conductive body 260 is included on the metal oxide 252, and an insulator 270 is included on the conductive body 260. Further, an insulator 271 is included on the insulator 270.

The metal oxide 252 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 252 for suppressing oxygen diffusion between the insulator 250 and the conductor 260, oxygen diffusion to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the metal oxide 230 can be suppressed. Further, oxidation of the conductive body 260 can be suppressed.

In addition, the metal oxide 252 may be used as a part of the gate electrode. For example, an oxide semiconductor which can be used as the metal oxide 230 can be used as the metal oxide 252. In this case, the conductive body 260 is formed by a sputtering method, whereby the resistance value of the metal oxide 252 can be reduced to be conductive. This may be referred to as an oc (oxide conductor) electrode.

In addition, metal oxide 252 is sometimes used as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, a metal oxide which is a high-k material having a high relative dielectric constant is preferably used as the metal oxide 252. By using this stacked structure, a stacked structure having thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor operates can be reduced while maintaining the physical thickness. Further, the Equivalent Oxide Thickness (EOT) of the insulating layer used as the gate insulator can be reduced.

Although the metal oxide 252 in the transistor 200C is illustrated as a single-layer structure, a stacked-layer structure of two or more layers may be employed. For example, a metal oxide used as part of the gate electrode may be stacked with a metal oxide used as part of the gate insulator.

When the transistor 200C has the metal oxide 252 and the metal oxide 252 is used as a gate electrode, the on-state current of the transistor 200C can be increased without reducing the influence of the electric field from the conductive body 260. Further, when the metal oxide 252 is used as a gate insulator, the distance between the conductive body 260 and the metal oxide 230 can be maintained by utilizing the physical thicknesses of the insulator 250 and the metal oxide 252. This can suppress a leakage current between the conductor 260 and the metal oxide 230. Thus, by providing the transistor 200C with the stacked-layer structure of the insulator 250 and the metal oxide 252, the physical distance between the conductor 260 and the metal oxide 230 and the electric field intensity applied from the conductor 260 to the metal oxide 230 can be easily adjusted.

Specifically, an oxide semiconductor which can be used for the metal oxide 230 can be used as the metal oxide 252 by reducing the resistance. Alternatively, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like are preferably used as the insulating layer containing an oxide of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than hafnium oxide. Therefore, crystallization is not easily caused in the heat treatment in the subsequent step, and therefore, this is preferable. Note that the metal oxide 252 is not an essential constituent element and can be designed appropriately according to desired transistor characteristics.

As the insulator 270, an insulating material having a function of suppressing permeation of impurities such as water and hydrogen and oxygen is preferably used. For example, aluminum oxide, hafnium oxide, or the like is preferably used. This prevents the conductor 260 from being oxidized by oxygen from above the insulator 270. Further, impurities such as water and hydrogen from above the insulator 270 can be prevented from entering the metal oxide 230 through the conductor 260 and the insulator 250.

Insulator 271 is used as a hard mask. By providing the insulator 271, the conductor 260 can be processed so that the side surface of the conductor 260 is substantially perpendicular to the substrate surface, and specifically, the angle formed by the side surface of the conductor 260 and the substrate surface can be 75 degrees or more and 100 degrees or less, preferably 80 degrees or more and 95 degrees or less.

Further, the insulator 271 may also serve as a barrier layer by using an insulating material having a function of suppressing permeation of impurities such as water and hydrogen and oxygen as the insulator 271. In this case, the insulator 270 may not be provided.

By selectively removing the insulator 270, the conductor 260, the metal oxide 252, the insulator 250, and the metal oxide 230c using the insulator 271 as a hard mask, the side surfaces thereof can be made substantially uniform, and a part of the surface of the metal oxide 230b can be exposed.

In addition, the transistor 200C includes a region 243a and a region 243b in a part of the surface of the exposed metal oxide 230 b. One of the regions 243a and 243b is used as a source region, and the other is used as a drain region.

For example, the regions 243a and 243b can be formed by introducing an impurity element such as phosphorus or boron into the surface of the exposed metal oxide 230b by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like. Note that in this embodiment and the like, the "impurity element" means an element other than the main component element.

Further, the region 243a and the region 243b may be formed by exposing a part of the surface of the metal oxide 230b, forming a metal film, and then performing heat treatment to diffuse elements contained in the metal film into the metal oxide 230 b.

The resistivity of a part of the region of the metal oxide 230b into which the impurity element is introduced is lowered. Thus, the region 243a and the region 243b may be referred to as an "impurity region" or a "low-resistance region".

By using the insulator 271 and/or the conductive body 260 as a mask, the region 243a and the region 243b can be formed in self-alignment. Therefore, the region 243a and/or the region 243b do not overlap with the conductive body 260, and parasitic capacitance can be reduced. In addition, the offset region is not formed between the channel formation region and the source-drain region (the region 243a or the region 243 b). By forming the regions 243a and 243b in a self-aligned manner, an increase in on-state current, a decrease in threshold voltage, an increase in operating frequency, and the like can be achieved.

Transistor 200C includes insulator 272 on the sides of insulator 271, insulator 270, conductor 260, metal oxide 252, insulator 250, and metal oxide 230C. The insulator 272 is preferably an insulator having a low relative permittivity. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, resin, or the like is preferably used. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having a hole is used for the insulator 272, an excess oxygen region can be easily formed in the insulator 272 in a later step, which is preferable. In addition, silicon oxide and silicon oxynitride are preferable because they have thermal stability. Further, the insulator 272 preferably has a function of diffusing oxygen.

In addition, in order to further reduce the off-state current, an offset region may be provided between the channel formation region and the source/drain region. The offset region is a region having a high resistivity and is a region in which the impurity element is not introduced. By introducing the impurity element after the insulator 272 is formed, an offset region can be formed. In this case, the insulator 272 is also used as a mask, like the insulator 271. Therefore, the region of the metal oxide 230b overlapping with the insulator 272 is not introduced with an impurity element, whereby the resistivity of the region can be kept high.

Further, the transistor 200C includes an insulator 254 over the insulator 272, the metal oxide 230. The insulator 254 is preferably formed by sputtering. By the sputtering method, an insulator with less impurities such as water and hydrogen can be formed.

The oxide film formed by sputtering may extract hydrogen from the formed structure. Accordingly, the insulator 254 absorbs hydrogen and water from the metal oxide 230 and the insulator 272. This can reduce the hydrogen concentration in the metal oxide 230 and the insulator 272.

< materials for Forming transistors >

Hereinafter, constituent materials that can be used for the transistor will be described.

< substrate >

As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., a yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or the like, a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like, and the like. Further, a semiconductor substrate having an Insulator region in the semiconductor substrate may be mentioned, and examples thereof include an SOI (Silicon On Insulator) substrate and the like. Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, a substrate including a metal nitride, a substrate including a metal oxide, or the like can be given. Further, an insulating substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, and the like can be given. Alternatively, a substrate provided with an element over such a substrate may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light-emitting element, a memory element, and the like.

< insulator >, a method for producing a semiconductor device, and a semiconductor device

Examples of the insulator include insulating oxides, nitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides.

For example, when miniaturization and high integration of a transistor are performed, a problem of leakage current or the like may occur due to the thinning of a gate insulator. By using a high-k material as an insulator used as a gate insulator, a low voltage can be achieved during operation of the transistor while maintaining a physical thickness. On the other hand, by using a material having a low relative permittivity for the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulator.

Examples of the insulator having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

Examples of the insulator having a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, resin, and the like.

Further, by surrounding a transistor using an oxide semiconductor with an insulator (the insulator 214, the insulator 222, the insulator 254, the insulator 274, and the like) having a function of suppressing transmission of impurities such as hydrogen and oxygen, electric characteristics of the transistor can be stabilized. As the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, aluminum titanium nitride, silicon oxynitride, or silicon nitride can be used.

Further, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen desorbed by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen which is released by heating is in contact with the metal oxide 230, oxygen defects contained in the metal oxide 230 can be filled.

< electric conductor >

As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or the like, an alloy containing the above metal element as a component, an alloy combining the above metal elements, or the like is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity, and thus are preferable. Further, a semiconductor having high conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide can be used.

Further, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked-layer structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined may also be employed. Further, a stacked-layer structure in which a material containing the above-described metal element and a conductive material containing nitrogen are combined may also be employed. Further, a stacked-layer structure in which a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may also be employed.

In addition, in the case where an oxide is used for a channel formation region of a transistor, a stacked-layer structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is preferably used as a conductive body used as a gate electrode. In this case, it is preferable that a conductive material containing oxygen be provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

In particular, as a conductor used as a gate electrode, a conductive material containing a metal element contained in a metal oxide forming a channel and oxygen is preferably used. In addition, a conductive material containing the metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon is added can be used. In addition, indium gallium zinc oxide containing nitrogen may also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel may be trapped. Alternatively, hydrogen entering from an insulator or the like on the outside may be trapped.

At least a part of the configuration examples shown in the embodiments and the drawings corresponding to these examples can be implemented in appropriate combination with other configuration examples or drawings.

At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

(embodiment mode 3)

In this embodiment mode, a metal oxide (hereinafter referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment modes will be described.

< Classification of Crystal Structure >

First, classification of crystal structures in an oxide semiconductor is described with reference to fig. 31A. Fig. 31A is a diagram illustrating classification of a crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn).

As shown in fig. 31A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". In addition, in "Amorphous" includes the complete Amorphous. The "crystal" includes CAAC (c-axis-aligned crystal), nc (nanocrystalline) and CAC (closed-aligned composite). In addition, the classification of "Crystalline" does not include single crystals, polycrystals and complex Amorphous. In addition, the category of "Crystal" includes single Crystal and multiple Crystal.

In addition, the structure in the portion of the outline shown in fig. 31A, which is thickened, is an intermediate state between "Amorphous" and "crystalline", and belongs to a novel boundary region (New crystalline phase). That is, the structure is completely different from "Amorphous" or "crystalline" which is energetically unstable.

In addition, the crystal structure of the film or the substrate can be evaluated using X-Ray Diffraction (XRD) spectroscopy. Here, fig. 31B shows an XRD spectrum obtained by GIXD (Grazing-inclusion XRD) measurement of the CAAC-IGZO film classified as "crystalloid". The GIXD method is also called a thin film method or Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in fig. 31B is simply referred to as XRD spectrum. Further, the composition of the CAAC-IGZO film shown In fig. 31B is In: ga: zn is 4: 2: 3[ atomic number ratio ]. Further, the CAAC-IGZO film shown in FIG. 31B had a thickness of 500 nm.

As shown in fig. 31B, a peak indicating clear crystallinity was detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation was detected in the vicinity of 31 ° 2 θ. As shown in fig. 31B, a peak near 31 ° 2 θ is asymmetric when the angle at which the peak intensity is detected is used as the axis.

In addition, the crystal structure of the film or the substrate can be evaluated using a Diffraction pattern (also referred to as a nanobeam Electron Diffraction) observed by a nanobeam Electron Diffraction method (NBED). FIG. 31C shows the diffraction pattern of the CAAC-IGZO film. Fig. 31C is a diffraction pattern observed from an NBED in which an electron beam is incident in a direction parallel to the substrate. Further, the composition of the CAAC-IGZO film shown In fig. 31C is In: ga: zn is 4: 2: 3[ atomic number ratio ]. In the nanobeam electron diffraction method, an electron diffraction method with a beam diameter of 1nm is performed.

As shown in fig. 31C, a plurality of spots indicating C-axis orientation were observed in the diffraction pattern of the CAAC-IGZO film.

< Structure of oxide semiconductor >

Note that when attention is paid to the crystal structure of the oxide semiconductor, the classification of the oxide semiconductor may be different from that in fig. 31A. For example, the oxide semiconductor can be classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor. Examples of the non-single crystal oxide semiconductor include CAAC-OS and nc-OS. The non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, an a-like OS (amorphous oxide semiconductor), an amorphous oxide semiconductor, and the like.

The CAAC-OS, nc-OS and a-like OS will be described in detail.

[CAAC-OS]

The CAAC-OS is an oxide semiconductor including a plurality of crystalline regions whose c-axes are oriented in a specific direction. The specific direction is a thickness direction of the CAAC-OS film, a normal direction of a surface of the CAAC-OS film on which the CAAC-OS film is formed, or a normal direction of a surface of the CAAC-OS film. Further, the crystalline region is a region having periodicity of atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region in which the lattice arrangement is uniform. The CAAC-OS has a region where a plurality of crystal regions are connected in the direction of the a-b plane, and this region may have distortion. The distortion is a portion in which the direction of the lattice arrangement changes between a region in which the lattice arrangement is aligned and another region in which the lattice arrangement is aligned, in a region in which a plurality of crystal regions are connected. In other words, CAAC-OS refers to an oxide semiconductor in which the c-axis is oriented and there is no significant orientation in the a-b plane direction.

Each of the plurality of crystal regions is composed of one or more fine crystals (crystals having a maximum diameter of less than 10 nm). When the crystal region is composed of one fine crystal, the maximum diameter of the crystal region is less than 10 nm. When the crystal region is composed of a plurality of fine crystals, the size of the crystal region may be about several tens of nm.

In addition, In the In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) including a layer In which indium (In) and oxygen are stacked (hereinafter, In layer), and a layer In which the element M, zinc (Zn), and oxygen are stacked (hereinafter, M, Zn layer). In addition, indium and the element M may be substituted for each other. Therefore, the (M, Zn) layer sometimes contains indium. In addition, the In layer may contain the element M. Note that the In layer sometimes contains Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

For example, when a CAAC-OS film is subjected to structural analysis using an XRD apparatus, a peak of c-axis orientation is detected at or near 2 θ of 31 ° in Out-of-plane XRD measurement using θ/2 θ scanning. Note that the position (2 θ value) of the peak indicating the c-axis orientation may vary depending on the kind, composition, and the like of the metal element constituting the CAAC-OS.

Further, for example, a plurality of bright spots (spots) are observed in the electron diffraction pattern of the CAAC-OS film. When the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) is taken as a center of symmetry, a certain spot and the other spots are observed at positions point-symmetric to each other.

When the crystal region is observed from the above-mentioned specific direction, the lattice arrangement in the crystal region is substantially hexagonal, but the unit lattice is not limited to regular hexagonal, and may be non-regular hexagonal. In addition, the distortion may have a lattice arrangement such as a pentagon or a heptagon. In addition, no clear grain boundary (grain boundary) was observed in the vicinity of the CAAC-OS distortion. That is, the distortion of the lattice arrangement suppresses the formation of grain boundaries. This may be because CAAC-OS can tolerate distortion that occurs due to a low density of the arrangement of oxygen atoms in the a-b plane direction or due to a change in the bonding distance between atoms due to substitution of metal atoms.

Further, it was confirmed that the crystal structure of the grain boundary was clearly defined as so-called polycrystal (crystal). Since the grain boundary becomes a recombination center and carriers are trapped, there is a possibility that the on-state current of the transistor is reduced, the field-effect mobility is reduced, or the like. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of crystalline oxides providing a semiconductor layer of a transistor with an excellent crystal structure. Note that, in order to constitute the CAAC-OS, a structure including Zn is preferable. For example, an In-Zn oxide and an In-Ga-Zn oxide are preferable because the occurrence of grain boundaries can be further suppressed as compared with an In oxide.

CAAC-OS is an oxide semiconductor having high crystallinity and no clear grain boundary is observed. Therefore, it can be said that in CAAC-OS, the decrease in electron mobility due to the grain boundary does not easily occur. Further, since crystallinity of an oxide semiconductor may be reduced by mixing of impurities, generation of defects, or the like, CAAC-OS can be said to be an oxide semiconductor with less impurities or defects (oxygen vacancies, or the like). Therefore, the oxide semiconductor including CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including CAAC-OS has high heat resistance and high reliability. The CAAC-OS is also stable against high temperature (so-called heat buildup) in the manufacturing process. Thus, the use of the CAAC-OS for the OS transistor can increase the degree of freedom in the manufacturing process.

[nc-OS]

In nc-OS, the atomic arrangement in a minute region (for example, a region of 1nm to 10nm, particularly 1nm to 3 nm) has periodicity. In other words, nc-OS has a minute crystal. The size of the fine crystal is, for example, 1nm or more and 10nm or less, particularly 1nm or more and 3nm or less, and the fine crystal is called a nanocrystal. Furthermore, no regularity in crystallographic orientation was observed for nc-OS between different nanocrystals. Therefore, orientation was not observed in the entire film. Therefore, sometimes nc-OS does not differ from a-like OS or amorphous oxide semiconductor in some analytical methods. For example, when the nc-OS film is subjected to structural analysis using an XRD device, a peak indicating crystallinity is not detected in an Out-of-plane XRD measurement using a theta/2 theta scan. Further, when electron diffraction using electron rays having a larger beam diameter than that of the nanocrystal (for example, 50nm or more) (also referred to as selective electron diffraction) is performed on the nc-OS film, a diffraction pattern similar to a halo pattern is observed. On the other hand, when electron diffraction (also referred to as nanobeam electron beam) using electron beam having a beam diameter close to or smaller than the size of nanocrystal (for example, 1nm or more and 30nm or less) is performed on the nc-OS film, an electron diffraction pattern in which a plurality of spots are observed in an annular region centered on a direct spot may be obtained.

[a-like OS]

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS contains holes or low density regions. That is, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. Further, the hydrogen concentration in the film of the a-like OS is higher than that in the films of nc-OS and CAAC-OS.

< Structure of oxide semiconductor >

Next, the details of the CAC-OS will be described. Further, CAC-OS is explained in relation to the material composition.

[CAC-OS]

CAC-OS is, for example, a structure in which elements contained in a metal oxide are unevenly distributed, and the size of a material containing unevenly distributed elements is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size. Note that a state in which one or more metal elements are unevenly distributed in a metal oxide and a region containing the metal elements is mixed is also referred to as a mosaic shape or a patch (patch) shape in the following, and the size of the region is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size.

The CAC-OS is a structure in which a material is divided into a first region and a second region to form a mosaic, and the first region is distributed in a film (hereinafter, also referred to as a cloud). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

Here, the atomic number ratios of In, Ga and Zn with respect to the metal elements of CAC-OS constituting the In-Ga-Zn oxide are each referred to as [ In ], [ Ga ] and [ Zn ]. For example, In the CAC-OS of the In-Ga-Zn oxide, the first region is a region whose [ In ] is larger than that In the composition of the CAC-OS film. Further, the second region is a region whose [ Ga ] is larger than [ Ga ] in the composition of the CAC-OS film. Further, for example, the first region is a region whose [ In ] is larger than [ In ] In the second region and whose [ Ga ] is smaller than [ Ga ] In the second region. Further, the second region is a region whose [ Ga ] is larger than [ Ga ] In the first region and whose [ In ] is smaller than [ In ] In the first region.

Specifically, the first region is a region containing indium oxide, indium zinc oxide, or the like as a main component. The second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. In other words, the first region can be referred to as a region containing In as a main component. The second region may be referred to as a region containing Ga as a main component.

Note that a clear boundary between the first region and the second region may not be observed.

For example, In CAC-OS of an In-Ga-Zn oxide, it was confirmed that the semiconductor device had a structure In which a region (first region) containing In as a main component and a region (second region) containing Ga as a main component were unevenly distributed and mixed, based on an EDX-plane analysis image (EDX-mapping) obtained by Energy Dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy).

When the CAC-OS is used for a transistor, the CAC-OS can have a switching function (a function of controlling on/off) by a complementary action of conductivity due to the first region and insulation due to the second region. In other words, it has the function of electrical conductivity in one part of the material of the CAC-OS and in another partHas an insulating function and has a semiconductor function as a whole material. By separating the conductive function and the insulating function, each function can be improved to the maximum. Therefore, by using the CAC-OS for the transistor, a high on-state current (I) can be realized_on) High field effect mobility (mu) and good switching operation.

Oxide semiconductors have various structures and various characteristics. The oxide semiconductor according to one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

< transistor with oxide semiconductor >

Here, a case where the above-described oxide semiconductor is used for a transistor will be described.

By using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Further, a transistor with high reliability can be realized.

An oxide semiconductor having a low carrier concentration is preferably used for the transistor. For example, the carrier concentration in the oxide semiconductor may be 1 × 10¹⁷cm^-3Hereinafter, it is preferably 1 × 10¹⁵cm^-3Hereinafter, more preferably 1 × 10¹³cm^-3Hereinafter, more preferably 1 × 10¹¹cm^-3Hereinafter, more preferably less than 1X 10¹⁰cm^-3And 1 × 10^-9cm^-3The above. In the case where the purpose is to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification and the like, a state where the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". In addition, an oxide semiconductor having a low carrier concentration is sometimes referred to as "a high-purity intrinsic" or "an oxide semiconductor substantially having a high-purity intrinsic".

Since the oxide semiconductor film which is intrinsic or substantially intrinsic in high purity has a lower density of defect states, it is possible to have a lower density of trap states.

Further, the electric charges trapped in the trap level of the oxide semiconductor may take a long time to disappear, and may act as fixed electric charges. Therefore, the transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electric characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. The impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

< impurities >

Here, the influence of each impurity in the oxide semiconductor is described.

When the oxide semiconductor contains silicon or carbon which is one of the group 14 elements, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor or in the vicinity of the interface of the oxide semiconductor (concentration measured by Secondary Ion Mass Spectrometry (SIMS))¹⁸atoms/cm³Hereinafter, 2 × 10 is preferable¹⁷atoms/cm³The following.

Further, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level may be formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has a normally-on characteristic. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is set to 1X 10¹⁸atoms/cm³Hereinafter, 2 × 10 is preferable ¹⁶atoms/cm³The following.

When the oxide semiconductor contains nitrogen, electrons as carriers are easily generated, and the carrier concentration is increased to make the oxide semiconductor n-type. As a result, a transistor using an oxide semiconductor containing nitrogen for a semiconductor tends to have a normally-on characteristic. Alternatively, when the oxide semiconductor contains nitrogen, a trap level may be formed. As a result, the electrical characteristics of the transistor may be unstable. Therefore, the nitrogen concentration in the oxide semiconductor to be measured by SIMSSet to be less than 5X 10¹⁹atoms/cm³Preferably 5X 10¹⁸atoms/cm³Hereinafter, more preferably 1 × 10¹⁸atoms/cm³Hereinafter, more preferably 5 × 10¹⁷atoms/cm³The following.

Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to the metal atom to generate water, and thus oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons are sometimes generated as carriers. In addition, a part of hydrogen is bonded to oxygen bonded to a metal atom, and electrons as carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing hydrogen easily has a normally-on characteristic. Thus, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by SIMS is set to be lower than 1 × 10 ²⁰atoms/cm³Preferably less than 1X 10¹⁹atoms/cm³More preferably less than 5X 10¹⁸atoms/cm³More preferably less than 1X 10¹⁸atoms/cm³。

By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

(embodiment mode 4)

In this embodiment, an electronic device including a display device using one embodiment of the present invention will be described.

Fig. 32A is an external view of the camera 8000 with the viewfinder 8100 attached. An imaging device is provided in the camera 8000. The camera 8000 may be, for example, a digital camera. In fig. 32A, the camera 8000 and the viewfinder 8100 are electronic devices that are detachable and separate from each other, but a viewfinder having a display device may be incorporated in the housing 8001 of the camera 8000.

The camera 8000 includes a housing 8001, a display portion 8002, an operation button 8003, a shutter button 8004, and the like. Further, the camera 8000 is attached with a detachable lens 8006.

Here, the camera 8000 has a structure in which the lens 8006 is detachable and exchangeable from the housing 8001, and the lens 8006 and the housing 8001 may be integrally formed.

By pressing the shutter button 8004, the camera 8000 can perform imaging. Further, the display portion 8002 is used as a touch panel, and imaging can be performed by touching the display portion 8002.

The housing 8001 of the camera 8000 includes an embedder having an electrode, and can be connected to a strobe device or the like in addition to the viewfinder 8100.

The viewfinder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like. The viewfinder 8100 may be an electronic viewfinder.

The housing 8101 includes an embedder fitted to the embedder of the camera 8000, and the finder 8100 can be attached to the camera 8000. The inserter includes an electrode, and an image or the like received from the camera 8000 using the electrode can be displayed on the display portion 8102.

The button 8103 is used as a power button. By using the button 8103, display or non-display of the display portion 8102 can be switched.

The display device according to one embodiment of the present invention can be used for the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100. Since the pixel density of the display device according to one embodiment of the present invention is extremely high, even when the display portion 8002 or the display portion 8102 is close to the user, an image with a more realistic sensation can be displayed on the display portion 8002 or the display portion 8102 without the user confirming the pixels. In particular, since the user's eyes approach the eyepiece portion and confirms an image displayed on the display portion 8102 of the viewfinder 8100, the distance between the user and the display portion 8102 is very short. Accordingly, the display portion 8102 particularly preferably uses the display device according to one embodiment of the present invention. In addition, in the case where the display portion 8102 uses the display device of one embodiment of the present invention, an image having a resolution of 4K, 5K, or higher can be displayed on the display portion 8102.

Further, the resolution of an image that can be captured by the image capturing apparatus provided on the camera 8000 is preferably equal to or higher than the resolution of an image that can be displayed by the display portion 8002 or the display portion 8102. For example, when the display portion 8102 can display an image with a resolution of 4K, it is preferable that an imaging device capable of capturing an image of 4K or more be provided in the camera 8000. When the display portion 8102 can display an image with a resolution of 5K, an imaging device capable of capturing an image of 5K or more is preferably provided in the camera 8000.

Fig. 32B is an external view of the head mounted display 8200.

The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. In addition, a battery 8206 is incorporated in the mounting portion 8201.

Power is supplied from the battery 8206 to the main body 8203 through the cable 8205. The main body 8203 includes a wireless receiver and the like, and can display an image corresponding to received image data and the like on the display portion 8204. Further, the movement of the eyeball and the eyelid of the user is captured by a camera provided in the main body 8203, and the coordinates of the line of sight of the user are calculated from the information, whereby the line of sight of the user can be used as an input method.

Further, a plurality of electrodes may be provided at positions of the mounting portion 8201 to be contacted by the user. The main body 8203 may have a function of detecting a current flowing through the electrode according to the movement of the eyeball of the user to recognize the line of sight of the user. The main body 8203 may have a function of monitoring the pulse of the user by detecting the current flowing through the electrode. The mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, or may have a function of displaying biological information of a user on the display portion 8204. The main body 8203 may detect a motion of the head of the user and change an image displayed on the display portion 8204 in synchronization with the motion of the head of the user.

A display device according to one embodiment of the present invention can be used for the display portion 8204. This makes it possible to reduce the frame width of the head mounted display 8200, and the display unit 8204 can display a high-quality image and can display an image with a high presence feeling.

Fig. 32C, 32D, and 32E are external views of the head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixing tool 8304, and a pair of lenses 8305.

The user can see the display on the display portion 8302 through the lens 8305. Preferably, the display portion 8302 is disposed in a curved shape. By bending the arrangement display portion 8302, the user can feel a high sense of realism. Note that although the configuration in which one display portion 8302 is provided is illustrated in this embodiment, the configuration is not limited to this, and for example, a configuration in which two display portions 8302 are provided may be employed. In this case, when each display unit is disposed on the side of each eye of the user, three-dimensional display using parallax or the like can be performed.

A display device according to one embodiment of the present invention can be used for the display portion 8302. Since the display device according to one embodiment of the present invention has an extremely high pixel density, a user can display an image with a higher sense of presence without seeing pixels even when the display device is enlarged by the lens 8305 as shown in fig. 32E.

Next, fig. 33A to 33G illustrate examples of electronic apparatuses different from the electronic apparatuses illustrated in fig. 32A to 32E.

The electronic apparatus shown in fig. 33A to 33G includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (which has a function of measuring a force, a displacement, a position, a velocity, acceleration, an angular velocity, a rotational speed, a distance, light, liquid, magnetism, a temperature, a chemical substance, sound, time, hardness, an electric field, a current, a voltage, electric power, radiation, a flow rate, humidity, inclination, vibration, smell, or infrared ray), a microphone 9008, and the like.

The electronic apparatus shown in fig. 33A to 33G has various functions. For example, the following functions may be provided: a function of displaying various information (still image, moving image, character image, and the like) on the display unit; a function of a touch panel; a function of displaying a calendar, date, time, or the like; a function of controlling processing by using various software (programs); a function of performing wireless communication; a function of connecting to various computer networks by using a wireless communication function; a function of transmitting or receiving various data by using a wireless communication function; a function of reading out a program or data stored in a storage medium and displaying the program or data on a display unit; and the like. Note that the functions that the electronic apparatuses shown in fig. 33A to 33G can have are not limited to the above-described functions, but can have various functions. Further, although not illustrated in fig. 33A to 33G, the electronic apparatus may include a plurality of display portions. In addition, the electronic device may be provided with a camera or the like so as to have the following functions: a function of shooting a still image; a function of shooting a moving image; a function of storing a captured image in a storage medium (an external storage medium or a storage medium built in a camera); a function of displaying the captured image on a display unit; and the like.

Next, the electronic apparatus shown in fig. 33A to 33G is explained in detail.

Fig. 33A is a perspective view showing the television set 9100. A large display portion 9001 of 50 inches or more or 100 inches or more, for example, can be attached to the television set 9100.

The display device of one embodiment of the present invention can be used for the display portion 9001 included in the television set 9100. This makes it possible to narrow the frame of the television set 9100, and the display portion 9001 can display high-quality images and can display images with a high presence.

Fig. 33B is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 has, for example, one or more functions of a telephone, an electronic notebook, an information reading apparatus, and the like. In particular, it can be used as a smartphone. The portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. Further, the portable information terminal 9101 may display text or image information on a plurality of faces thereof. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) may be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a dotted rectangle may be displayed on the other surface of the display portion 9001. Further, as an example of the information 9051, a display for prompting reception of information from an email, SNS (Social Networking Services), a telephone, or the like; titles of e-mails or SNS, etc.; a sender name of an email, SNS, or the like; a date; time; the remaining amount of the battery; and display of antenna received signal strength. Alternatively, an operation button 9050 or the like may be displayed in place of the information 9051 at the position where the information 9051 is displayed.

The display device according to one embodiment of the present invention can be used for the display portion 9001 of the portable information terminal 9101. This makes it possible to narrow the frame of the portable information terminal 9101, and the display portion 9001 can display high-quality images and images with a high presence feeling.

Fig. 33C is a perspective view showing the portable information terminal 9102. Mobile information terminal 9102 has a function of displaying information on three or more surfaces of display portion 9001. Here, an example is shown in which the information 9052, the information 9053, and the information 9054 are displayed on different surfaces. For example, the user of the portable information terminal 9102 can confirm the display (here, the information 9053) of the portable information terminal 9102 in a pocket. Specifically, the telephone number, name, or the like of the person who makes a call is displayed at a position where the information can be viewed from above the portable information terminal 9102. The user can confirm the display without taking out the portable information terminal 9102 from a pocket, and thus can determine whether to answer the call.

The display device according to one embodiment of the present invention can be used for the display portion 9001 included in the portable information terminal 9102. This makes it possible to downsize the portable information terminal 9102, and the display portion 9001 can display high-quality images and images with a high presence feeling.

Fig. 33D is a perspective view showing the wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various application programs such as mobile phones, electronic mails, reading and editing of articles, music playback, network communication, and computer games. The display surface of the display portion 9001 is curved, and display can be performed on the curved display surface. Further, the portable information terminal 9200 can perform short-range wireless communication standardized for communication. For example, hands-free calling can be performed by communicating with a headset that can perform wireless communication. Further, the portable information terminal 9200 includes a connection terminal 9006, and can directly exchange data with another information terminal through a connector. Further, charging may be performed through the connection terminal 9006. Further, the charging operation may be performed by wireless power supply without the connection terminal 9006.

The display device according to one embodiment of the present invention can be used for the display portion 9001 included in the portable information terminal 9200. This makes it possible to narrow the frame of the portable information terminal 9200, and the display portion 9001 can display high-quality images and images with a high presence feeling.

Fig. 33E to 33G are perspective views showing a foldable portable information terminal 9201. Fig. 33E is a perspective view of the portable information terminal 9201 in the unfolded state, fig. 33F is a perspective view of the portable information terminal 9201 in the middle of changing from one state to the other of the unfolded state and the folded state, and fig. 33G is a perspective view of the portable information terminal 9201 in the folded state. The portable information terminal 9201 has good portability in the folded state, and has excellent display list performance because of a large display area in which the information terminal is seamlessly connected in the unfolded state. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 to which hinges 9055 are connected. The hinge 9055 allows the two housings 9000 to be folded back and folded back reversibly from the unfolded state of the portable information terminal 9201. For example, the portable information terminal 9201 may be curved with a radius of curvature of 1mm or more and 150mm or less.

The display device according to one embodiment of the present invention can be used for the display portion 9001 included in the portable information terminal 9201. This makes it possible to narrow the frame of the portable information terminal 9201, and the display portion 9001 can display high-quality images and images with a high presence feeling.

At least a part of the configuration examples shown in this embodiment mode and the drawings corresponding to these examples can be implemented in appropriate combination with other configuration examples or drawings.

At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[ description of symbols ]

10: display device, 20: layer, 21: gate drive circuit, 21 a: gate drive circuit, 21 b: gate drive circuit, 22: data driving circuit, 22 a: data driving circuit, 22 b: data drive circuit, 23: region, 23 a: region, 23 b: region, 23 c: region, 23 d: region, 30: layer, 31: wiring, 31 a: wiring, 31 b: wiring, 32: wiring, 33: display unit, 34: pixel, 35: wiring, 35 a: wiring, 35 b: wiring, 40: circuit, 41: reception circuit, 42: serial-parallel conversion circuit, 43: buffer circuit, 44: shift register circuit, 45: latch circuit, 46: d/a conversion circuit, 46 a: potential generation circuit, 46 b: pass transistor logic circuit, 47: amplification circuit, 48: resistor, 49: transmission transistor, 51: transistor, 52: transistor, 53: transistor, 54: transistor, 55: transistor, 56: transistor, 57: transistor, 58: transistor, 59: transistor, 60: transistor, 61: transistor, 62: transistor, 63: transistor, 64: capacitor, 65: capacitor, 66: capacitor, 67: source follower circuit, 70: region, 71: transistor, 72: transistor, 73: dummy transistor, 80: layer, 81: demultiplexing circuit, 81 a: demultiplexing circuit, 81 b: demultiplexing circuit, 82: wiring, 82 a: wiring, 82 b: wiring, 83: wiring, 83 a: wiring, 83 b: wiring, 110: channel formation region, 111: source region, 112: drain region, 113: gate electrode, 114: opening, 115: wiring, 116: opening, 117: wiring, 118: opening, 119: opening, 120: opening, 121: wiring, 122: wiring, 123: wiring, 130: channel formation region, 131: source region, 132: drain region, 133: gate electrode, 134: opening, 135: wiring, 136: opening 137: wiring, 138: opening 139: opening section, 140: opening, 141: wiring, 142: wiring, 143: wiring, 151: semiconductor, 152: conductor, 200A: transistor, 200B: transistor, 200C: transistor, 205: electrical conductor, 214: insulator, 216: insulator, 222: insulator, 224: insulator, 230: metal oxide, 230 a: metal oxide, 230 b: metal oxide, 230 c: metal oxide, 240: conductor, 240 a: conductor, 240 b: conductor, 241: insulator, 241 a: insulator, 241 b: insulator, 242: conductor, 242 a: conductor, 242 b: conductor, 243 a: region, 243 b: region, 244: insulator, 250: insulator, 252: metal oxide, 254: insulator, 260: conductor, 260 a: conductor, 260 b: conductor, 270: insulator, 271: insulator, 272: insulator, 274: insulator, 280: insulator, 281: insulator, 301 a: conductor, 301 b: conductor, 305: conductor, 311: conductor, 313: electrical conductor, 317: conductor, 321: lower electrode, 323: insulator, 325: upper electrode, 331: conductor, 333: electrical conductor, 335: conductive body, 337: conductor, 341: conductor, 343: electric conductor, 347: conductor, 351: conductor, 353: conductor, 355: electrical conductor, 357: conductor, 361: insulator, 363: insulator, 403: vegetarian molecule separate layer, 405: insulator, 407: insulator, 409: insulator, 411: insulator, 413: insulator, 415: insulator, 417: insulator, 419: insulator, 421: insulator, 441: transistor, 443: conductor, 445: insulator, 447: semiconductor region, 449 a: low-resistance region, 449 b: low-resistance region, 451: conductor, 453: electrical conductor, 455: electric conductor, 457: electrical conductor, 459: conductor, 461: electrical conductor, 463: conductor, 465: electric conductor, 467: electric conductor, 469: electrical conductor, 471: conductor, 501: insulator, 503: insulator, 505: insulator, 507: insulator, 509: insulator, 550: transistor, 552: transistor, 554: transistor, 560: a capacitor, 562: capacitor, 570: liquid crystal element, 572: light-emitting element, 601: transistor, 602: transistor, 603: transistor, 613: insulator, 614: insulator, 616: insulator, 622: insulator, 624: insulator, 644: insulator, 654: insulator, 674: insulator, 680: insulator, 681: insulator, 701: substrate, 705: substrate, 712: sealant, 716: FPC, 721: hole injection layer, 722: hole transport layer, 723: light-emitting layer, 724: electron transport layer, 725: electron injection layer, 730: insulator, 732: sealing layer, 734: insulator, 736: coloring layer, 738: light-shielding layer, 760: connection electrode, 772: conductor, 774: electric conductor, 776: liquid crystal layer, 778: structure 780: anisotropic conductor, 786: EL layer, 786 a: EL layer, 786 b: EL layer, 786 c: EL layer, 788: electrical conductor, 792: charge generation layer, 800: transistor, 801 a: conductor, 801 b: conductor, 805: conductor, 811: electrical conductor, 813: electrical conductor, 814: insulator, 816: insulator, 817: conductor, 821: insulator, 822: insulator, 824: insulator, 844: insulator, 853: electrical conductor, 854: insulator, 855: electrical conductor, 874: insulator, 880: insulator, 881: insulator, 901: subpixel, 901B: subpixel, 901G: sub-pixel, 901R: sub-pixel, 902: pixel, 911: electrical conductor, 912: electrical conductor, 913: semiconductor, 914: semiconductor, 915 a: conductor, 915 b: electrical conductor, 916 a: electrical conductor, 916 b: conductor, 917: conductor, 918: electrical conductor, 919: conductor, 920: electrical conductor, 921: conductor, 922: electric conductor, 923: electrical conductor, 924: electric conductor, 925: electrical conductor, 926: electrical conductor, 927: electrical conductor, 928: electrical conductor, 929: conductor, 930: electrical conductor, 931: electrical conductor, 990: electrical conductor, 991: adhesive layer, 992: insulator, 993: colored layer, 993 a: colored layer, 993 b: colored layer, 994: adhesive layer, 995: substrate, 1021: insulator, 1022: insulator, 1023: insulator, 1024: insulator, 1025: insulator, 1026: insulator, 1027: insulator, 8000: camera, 8001: shell, 8002: display unit, 8003: operation buttons, 8004: shutter button, 8006: lens, 8100: viewfinder, 8101: outer shell, 8102: display unit, 8103: button, 8200: head-mounted display, 8201: mounting section, 8202: lens, 8203: main body, 8204: display unit, 8205: cable, 8206: battery, 8300: head-mounted display, 8301: outer shell, 8302: display unit, 8304: fixing tool, 8305: lens, 9000: housing, 9001: display portion, 9003: speaker, 9005: operation buttons, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: operation button, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9100: television apparatus, 9101: portable information terminal, 9102: portable information terminal, 9200: portable information terminal, 9201: portable information terminal