Method and system for providing network entry fairness between applications

文档序号：1958175 发布日期：2021-12-10 浏览：10次中文

阅读说明：本技术 用于在应用之间提供网络入口公平性的方法和系统 (Method and system for providing network entry fairness between applications ) 是由 A·S·科普瑟 A·M·巴塔耶纳于 2020-03-23 设计创作，主要内容包括：提供了用于促进应用之间的网络入口公平性的方法和系统。在网络的入口端口处,对提供数据通信的应用进行审查,使得可以使用仲裁过程在该入口端口处公平地分配带宽。在典型的过程中,带宽是基于流通道的数量分配的,而与这些流通道的来源和特性无关。在所述入口端口处,对提供数据通信的应用进行检查将允许更适当地分配输入带宽。(Methods and systems are provided for facilitating network entry fairness among applications. At an ingress port of the network, applications providing data communication are vetted so that bandwidth can be fairly allocated at the ingress port using an arbitration process. In a typical process, bandwidth is allocated based on the number of flow channels, regardless of the source and characteristics of the flow channels. At the ingress port, checking the application providing data communication will allow more appropriate allocation of incoming bandwidth.)

1. A switch, comprising:

an edge flow logic block to group received packet flows into application packets, wherein a respective packet flow corresponds to a packet having one or more common header fields and is identified by a flow identifier that is unique within an ingress port; and

an input stream logic block coupled to the edge stream logic block and arbitrating forwarding of a buffered packet stream based on a respective injection limit of the buffered packet stream corresponding to the application packet to which the packet stream belongs.

2. The switch of claim 1, wherein the edge flow logic block is further to map each application packet to a corresponding injection limit identifier, wherein a respective injection limit identifier indicates a set of data injection limit parameters.

3. The switch of claim 2, wherein the set of data injection limit parameters includes a unicast injection limit and a multicast injection limit.

4. The switch of claim 1, wherein the injection limit is indexed by an injection limit identifier; and is

Wherein arbitrating forwarding of the buffered packet stream, the input stream logic block further to:

performing a first level of scheduling among all of the injection limit identifiers, wherein a respective injection limit identifier is associated with one or more application packets subject to an injection limit corresponding to the injection limit identifier;

performing a second level of scheduling among all associated application packets for each injection limit identifier, wherein each application packet is associated with one or more packet flows; and

for each application packet, a third level of scheduling is performed among all packet flows belonging to the application packet.

5. The switch of claim 1, wherein the input flow logic block is further to maintain an amount of injected data for all packet flows associated with a respective injection limit.

6. The switch of claim 1, wherein a predetermined index of application packets is reserved for traffic that is not subject to injection limitations.

7. The switch of claim 1, wherein input stream logic block is further to dynamically adjust a value of each injection limit based on a number of active streams associated with the injection limit.

8. A method, comprising:

grouping the received packet flows into application packets, wherein the respective packet flows correspond to packets having one or more common header fields and are identified by a flow identifier that is unique within the input port; and

arbitrating forwarding of a buffered packet flow based on a respective injection limit of the buffered packet flow corresponding to the application packet to which the packet flow belongs.

9. The method of claim 8, further comprising mapping each application packet to a corresponding injection limit identifier, wherein a respective injection limit identifier indicates a set of data injection limit parameters.

10. The method of claim 8, wherein the set of data injection limit parameters includes a unicast injection limit and a multicast injection limit.

11. The method of claim 10, wherein the injection limit is indexed by an injection limit identifier; and is

Wherein arbitrating forwarding of the buffered packet stream further comprises:

performing a second level of scheduling among all associated application packets for each injection limit identifier, wherein each application packet is associated with one or more packet flows; and

for each application packet, a third level of scheduling is performed among all packet flows belonging to the application packet.

12. The method of claim 8, further comprising maintaining an injection data volume for all packet flows associated with a respective injection limit.

13. The method of claim 8, wherein a predetermined index of application packets is reserved for traffic that is not subject to injection limitations.

14. The method of claim 8, further comprising dynamically adjusting a value of the injection limit based on a number of active flows associated with each injection limit.

15. A network system, comprising:

a plurality of interconnected switches, the plurality of interconnected switches including at least one edge switch, the edge switch comprising:

16. The network system of claim 15, wherein the edge flow logic block is further to map each application packet to a corresponding injection limit identifier, wherein the respective injection limit identifier indicates a set of data injection limit parameters.

17. The network system of claim 16, wherein the set of data injection limiting parameters includes a unicast injection limit and a multicast injection limit.

18. The network system of claim 15, wherein the injection limit is indexed by an injection limit identifier; and is

Wherein arbitrating forwarding of the buffered packet stream, the input stream logic block further to:

performing a second level of scheduling among all associated application packets for each injection limit identifier, wherein each application packet is associated with one or more packet flows; and

for each application packet, a third level of scheduling is performed among all packet flows belonging to the application packet.

19. The network system of claim 15, wherein the input stream logic block is further to maintain an amount of injected data for all packet streams associated with a corresponding injection limit.

20. The network system of claim 15, wherein a predetermined index of application packets is reserved for traffic that is not subject to injection limitations.

21. The network system of claim 15, wherein input stream logic block is further to dynamically adjust a value of each injection limit based on a number of active streams associated with the injection limit.

Technical Field

The present disclosure relates generally to the field of network technology. More particularly, the present disclosure relates to methods and systems for facilitating network entry fairness among applications.

Prior Art

As network-enabled devices and applications become more prevalent, various types of traffic and increasing network loads continue to demand higher performance from the underlying network architecture. For example, applications such as High Performance Computing (HPC), streaming media, and internet of things (IOT) may generate different types of traffic that are well characterized. Thus, in addition to traditional network performance metrics such as bandwidth and latency, network architects continue to face scalability, versatility, and efficiency challenges.

Background

Disclosure of Invention

Methods and systems are provided for facilitating network entry fairness among applications. At an ingress port of the network, applications providing data communication are vetted so that bandwidth can be fairly allocated at the ingress port using an arbitration process. In a typical process, bandwidth is allocated based on the number of flow channels, regardless of the source and characteristics of the flow channels. At the ingress port, checking the application providing data communication will allow more appropriate allocation of incoming bandwidth.

Drawings

FIG. 1 illustrates an example network that facilitates flow channels.

Fig. 2A illustrates an example switch that facilitates a flow path.

Fig. 2B shows an example of how switches on a data path may maintain flow state information.

Fig. 3A shows an exemplary structural header of a data packet.

Fig. 3B illustrates an exemplary Acknowledgement (ACK) packet format.

FIG. 3C illustrates the relationship between different variables used to derive and maintain state information for a flow.

Fig. 4A shows an example of how a flow may be transmitted using a flow channel table.

Fig. 4B shows an example of an Edge Flow Channel Table (EFCT).

Fig. 4C shows an example of an Input Flow Channel Table (IFCT).

Fig. 4D shows an example of an Output Flow Channel Table (OFCT).

Fig. 5A illustrates an exemplary switch architecture.

Fig. 5B shows an exemplary matrix of crossbar switch tiles.

Fig. 5C illustrates an exemplary crossbar switch with virtual output queuing and crossbar queuing.

FIG. 5D illustrates an exemplary age queue for storing requests.

Fig. 6A shows an example of unfair share of link bandwidth that may occur in a network.

Fig. 6B shows an example of endpoint congestion.

Fig. 7A illustrates a flow diagram of an exemplary process of generating an explicit endpoint congestion notification ACK.

Fig. 7B illustrates an exemplary endpoint congestion management logic block.

Fig. 8 shows a flow diagram illustrating an exemplary process of generating an ACK in response to a packet being dequeued from an output buffer.

Fig. 9A shows a flow diagram of an exemplary fine-grained flow control (FGFC) process.

Fig. 9B shows an example of a network interface controller supporting FGFC.

Fig. 10 shows an example of fabric link congestion.

Fig. 11 shows a flow diagram of an example process for applying credit-based flow control over a congestion fabric link.

Fig. 12A illustrates an exemplary input queue logic block that facilitates ingress fairness.

Fig. 12B illustrates a flow diagram of an exemplary enqueue-dequeue process that enforces entry fairness.

FIG. 13 illustrates an example edge exchange system that facilitates flow channels.

FIG. 14 illustrates an exemplary intermediate exchange system that facilitates flow channels.

In the drawings, like reference numerals refer to like elements.

Detailed Description

Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The invention is thus not limited to the embodiments shown.

SUMMARY

This disclosure describes systems and methods that can facilitate network entry fairness. More specifically, packets injected into the switch network may be examined and the application of the injected data may be determined. An arbitration process may then be used to allocate bandwidth at the ingress ports on an application-by-application basis, thereby providing ingress fairness among applications.

In the present disclosure, a packet stream may also be referred to as a "packet flow" or simply a "flow". The data path through which the flow passes and its configuration information maintained by the switch may be referred to as a "flow channel". Furthermore, the terms "buffer" and "queue" are used interchangeably in this disclosure.

FIG. 1 illustrates an example network that facilitates flow channels. In this example, a network of switches 100 (which may also be referred to as a "switch fabric") may include switches 102, 104, 106, 108, and 110. Each switch may have a unique address or ID within the switch fabric 100. Various types of devices and networks may be coupled to the switch fabric. For example, storage array 112 may be coupled to switch fabric 100 via switch 110; an InfiniBand (IB) -based HPC network 114 may be coupled to the switch fabric 100 via the switches 108; a plurality of end hosts (e.g., host 116) may be coupled to switch fabric 100 via switch 104; and the IP/ethernet network 118 may be coupled to the switch fabric 100 via the switch 102. In general, a switch may have edge ports and fabric ports. The edge port may be coupled to a device external to the structure. The fabric port may be coupled to another switch within the fabric via a fabric link.

In general, traffic may be injected into the switch fabric 100 via an ingress port of an edge switch and exit the switch fabric 100 via an egress port of another (or the same) edge switch. The ingress edge switch may group the injected packets into flows, which may be identified by flow IDs. The concept of a flow is not limited to a particular protocol or layer, such as layer 2 (layer-2) or layer 3 (layer-3) in the Open System Interface (OSI) reference model. For example, a flow may be mapped to traffic having a particular source ethernet address, traffic between a source IP address and a destination IP address, traffic corresponding to a TCP or UDP port/IP 5-tuple (source and destination IP addresses, source and destination TCP or UDP port numbers, and IP protocol numbers), or traffic generated by a process or thread running on an end host. In other words, a flow may be configured to map to data between any physical or logical entities. The configuration of the mapping may be done remotely or locally on the ingress edge switch.

After receiving the injected packet, the ingress edge switch may assign a flow ID for the flow. The flow ID may be included in a special header that the ingress edge switch may use to encapsulate the injected packet. In addition, the ingress edge switch may also examine the original header field of the injected packet to determine the appropriate egress edge switch address and include that address as the destination address in the encapsulation header. It should be noted that the flow ID may be a link-specific locally valid value, and that this value may be unique only to a specific input port on the switch. When the packet is forwarded to the next hop switch, the packet enters another link and the flow ID may be updated accordingly. Since packets of a flow go through multiple links and switches, the flow ID corresponding to the flow may form a unique chain. That is, at each switch, the packet's flow ID may be updated to the flow ID used by the outgoing link before the packet leaves the switch. This upstream-to-downstream one-to-one mapping between flow IDs may begin at the ingress edge switch and end at the egress edge switch. Because the flow ID only needs to be unique within the incoming link, the switch can accommodate a large number of flows. For example, if the stream ID is 11 bits long, the input port can support up to 2048 streams. Further, the matching pattern (one or more header fields of the packet) for mapping to the stream may include more bits. For example, a 32-bit long matching pattern (which may include multiple fields in a packet header) may map 2^32 different header field patterns. If the fabric has N ingress edge ports, a total of N x 2^32 identifiable flows can be supported.

The switch may assign a separate dedicated input queue for each flow. This configuration allows the switch to monitor and manage the degree of congestion of individual flows and prevent head-of-line congestion that can occur when a shared buffer is used for multiple flows. When a packet is transmitted to a destination egress switch, the egress switch may generate an Acknowledgement (ACK) and send the acknowledgement back to the ingress edge switch along the same data path in the upstream direction. Since the ACK packet travels the same data path, the switches on that path can obtain status information associated with the transmission of the corresponding flow by monitoring the amount of outstanding, unacknowledged data. This state information can then be used to perform flow-specific traffic management to ensure overall network health and fair handling of flows. As explained in more detail below, this per-flow queuing in combination with flow-specific delivery acknowledgements may enable the switch fabric to implement efficient, fast and accurate congestion control. Further, the switch fabric can deliver traffic with significantly improved network utilization without congestion.

The flow may be established and released dynamically or "on the fly" based on demand. In particular, a flow may be established by an ingress edge switch (e.g., establishing a mapping of flow IDs to packet headers) when a data packet arrives at the switch and the packet has not previously been assigned a flow ID. As the packet traverses the network, a flow ID may be assigned along each switch through which the packet passes, and a chain of flow IDs may be established from ingress to egress. Subsequent packets belonging to the same stream may use the same stream ID along the data path. When a packet is transmitted to a destination egress switch and a switch on the data path receives an ACK packet, each switch may update its state information regarding the amount of outstanding, unacknowledged data for the flow. For this flow, when the switch's input queue is empty and there is no more unacknowledged data, the switch may release the flow ID (i.e., release the flow channel) and reuse the flow ID for other flows. Such a data-driven dynamic flow setup and teardown mechanism may eliminate the need for centralized flow management and allow the network to respond quickly to traffic pattern changes.

It should be noted that the network architecture described herein is different from Software Defined Networks (SDNs) that typically use the OpenFlow protocol. In SDN, switches are configured by a central network controller and packets are forwarded based on one or more fields in a layer 2 (data link layer, such as ethernet), layer 3 (network layer, such as IP) or layer 4 (transport layer, such as TCP or UDP) header. In SDN, such header field lookups are performed at each switch in the network and there is no flow ID based fast forwarding as done in the networks described herein. Furthermore, since OpenFlow header field lookups are done using Ternary Content Addressable Memory (TCAM), the cost of such lookups can be high. Moreover, since the header field mapping configuration is done by a central controller, the setup and teardown of each mapping is relatively slow, potentially requiring a large amount of control traffic. As a result, SDN networks may be slow to respond to various network conditions (e.g., congestion). In contrast, in the networks described herein, flows may be dynamically established and torn down based on traffic demand, and packets may be forwarded with fixed length flow IDs. In other words, flow channels may be data driven and managed (i.e., set up, monitored, and torn down) in a distributed manner without intervention by a central controller. Furthermore, flow ID based forwarding can reduce the amount of TCAM space used and can therefore accommodate a greater number of flows.

It should be noted that the above operation can be performed substantially at line speed, with little buffering and delay, when the first packet is received. Subsequent packets from the same flow may be processed by switch 110 more quickly after the first packet is processed and scheduled for transmission because the same flow ID is used. In addition, the design of the flow channels may be such that the distribution, matching and de-distribution of the flow channels may have substantially the same cost. For example, a lookup match-based conditional assignment of a flow lane and a separate, independent deallocation of another flow lane may be performed simultaneously in nearly every clock cycle. This means that the generation and control of the flow paths adds little additional overhead to the conventional forwarding of packets. On the other hand, congestion control mechanisms may improve the performance of some applications by more than three orders of magnitude.

At each switch on the data path (including switches 110, 106, and 104), a dedicated input buffer may be provided for the flow and the amount of transmitted but unacknowledged data may be tracked. When the first packet arrives at switch 104, switch 104 may determine that the destination fabric address in the fabric header of the packet matches its own address. In response, switch 104 may decapsulate the packet according to the fabric header and forward the decapsulated packet to host 116. In addition, switch 104 may generate an ACK packet and send the ACK packet back to switch 110. When the ACK packet traverses the same data path, switches 106 and 110 may each update their own state information for the flow's unacknowledged data.

Typically, congestion within the network will cause network buffers to be filled. When the network buffer is full, ideally, traffic attempting to pass through the buffer should be slowed or stopped. Otherwise, the buffer may overflow and the packet may be discarded. In conventional networks, congestion control is typically done end-to-end at the edge. The core of the network is considered to be used only as a "low energy pipe (dumb pipe)" whose main purpose is to forward traffic. Such network designs are typically slow to respond to congestion because congestion information is typically not sent to the edge devices quickly, and the resulting actions taken by the edge devices are not always effective at removing congestion. This slow response in turn limits the utilization of the network, since network operators typically need to limit the total amount of traffic injected into the network in order to keep the network free of congestion. Furthermore, end-to-end congestion control is typically only effective if the network is not congested. Once the network is heavily congested, end-to-end congestion control will not work because the congestion notification message itself may be congested (unless the congestion control message is sent using a separate control plane network than the data plane network).

In contrast, flow paths may prevent such congestion from growing within the switch fabric. When a flow is experiencing some degree of congestion, the flow path mechanism may recognize this and, in response, may slow down or stop new packets of the same flow entering the fabric. Further, these new packets may be buffered in a stream path queue on the edge port and only allowed to enter the fabric when a packet of the same stream leaves the fabric at the destination edge port. This process may limit the total buffering requirements of the stream within the fabric to an amount that does not cause the fabric buffer to become too full.

Through the stream path, the switch is able to obtain fairly accurate status information about the amount of data outstanding en route within the fabric. This status information may be aggregated for all flows on the ingress edge port. This means that the total amount of data injected through the ingress edge port can be known. Thus, the stream lane mechanism may place a limit on the amount of data in the structure. When all edge ports apply this limiting action, the amount of packet data in the entire fabric can be well controlled, which in turn can prevent the entire fabric from saturating. The flow path may also slow down the progress of a single congested flow within the fabric without slowing down other flows. This feature can keep packets away from congestion hot spots while preventing buffers from becoming full and ensuring free buffer space for irrelevant traffic.

Operation of flow channels

In general, a flow path may define a path for each communication session across the switch fabric. The paths and the amount of data belonging to each flow may be described in a set of dynamic connection flow tables associated with each link of the switch fabric. On each ingress port, edge, and fabric, a set of flow path queues may be defined. There may be one queue per flow channel. When packets arrive, they may be assigned to flow channels on the edge ports, or already assigned to flow channels on fabric ingress ports by the egress fabric ports of the link partners. The flow lane information may be used to direct the packet into the appropriate flow lane queue.

Fig. 2A illustrates an example switch that facilitates a flow path. In this example, the switch may include a crossbar switch 202. Crossbar switch 202 may have multiple input ports (e.g., input port 204) and multiple output ports (e.g., output 208). Crossbar switch 202 may forward packets from input ports to output ports. Each input port may be associated with a plurality of input queues, each queue being assigned to a different incoming stream arriving at the input port. For example, data arriving at a given port of a switch may first be segregated based on their individual flows and stored in flow-specific input queues (e.g., input queue 206). Packets stored in the input queues may be dequeued and sent to the crossbar switch 202 based on a scheduling algorithm (described in more detail in later sections) designed to control congestion. On the output side, once a packet passes through crossbar switch 202, it may be temporarily stored in an output transmit queue (e.g., output transmit queue 210), which may be shared by all flows leaving the same output port. Meanwhile, the header of the packet may be updated using the flow ID of the outgoing link before the packet is dequeued from the output transmit queue and transmitted on the outgoing link. It should be noted that this hop-by-hop (hop-by-hop) flow ID mapping may be done as the first packet in the flow traverses the network. When the packet reaches the next hop switch, the packet may again be stored in the flow-specific input queue, and the same process may be repeated. It should be noted that the flow ID is used to distinguish flows traveling on the same fabric link and may be generally assigned by the transmitter end of the link, which is the switch output port that is transmitting onto the link.

By providing a flow-specific input queue, the switch can allow each flow to move independently of all other flows. The switch can avoid the very common head of line blocking problem in the shared input buffer. The flow-specific input queues also allow packets in a single flow to maintain order. As a flow passes through the switch, flow-specific input queues may be allocated on each input port for the flow, and become linked, effectively forming one long queue across the entire fabric for the flow, and packets for the flow may remain in order.

The progress of successful delivery of packets belonging to a flow may be reported by a series of ACKs generated by the edge ports of the egress switches. The ACK packet may propagate back along the data path traversed by the data packet and may be forwarded by the switch according to forwarding information maintained in the flow table. As the ACK packets propagate upstream, these packets may be processed by the input queue manager of each switch, which may update the state information of the corresponding flow based on the information carried by the ACK packets. The ACK packet may have a type field to provide advanced information about the downstream data path, such as congestion. The switch's input queue manager may use this information to make decisions about pending packets currently buffered in its input queue, such as limiting the transmission rate or changing the forwarding path. In addition, the input queue manager may update the information carried in the ACK packet based on the buffered state information of the flow so that the upstream switch can make the appropriate decision. For example, if an input queue for a given flow is experiencing congestion (e.g., the amount of data in the queue is above a predetermined threshold), the input queue manager may update an ACK packet forwarded to the next upstream switch to include the congestion information.

If the ACK corresponds to the last packet of the flow, the switch may determine that the flow does not have any unacknowledged data. Accordingly, the switch may release the flow channel by deleting the corresponding entry in the flow table.

As described above, the input queue manager on each switch may maintain information about transmitted but unacknowledged data for a given flow. Fig. 2B shows an example of how switches on a data path may maintain flow state information. In this example, the data path taken by the flow may include switches 222, 224, and 226. The amount of transmitted but unacknowledged stream data may be indicated by a variable "flow _ extend", which may be measured in the number of fixed-length data units, such as 256 bytes. In addition, flow _ extend and other flow state information may be maintained by the switch's input queue manager, which may continuously monitor all flow-specific queues.

In the example of fig. 2B, the value of flow _ extend at the input queue manager of switch 226 is 1 because there is one data unit that has been sent out of the input queue and forwarded through the crossbar switch. It should be noted that due to the scheduling of all data packets to be transmitted via the output link, data packets sent by the input queue may be temporarily buffered in the output transmission buffer. When such a packet is buffered in the transmit buffer of the output port, the input queue may still treat the packet as transmitted in order to update the flow _ extend value.

Accordingly, since the input queue for a given flow at switch 226 has six queued data units, and two additional data units are transmitted between switches 224 and 226, the flow _ extend value at switch 224 is 9. Similarly, the flow _ extend value at switch 222 is 13 because there are three data units stored in the input queue at switch 224 and one data unit is transmitted between switches 222 and 224.

In general, a flow lane may remain assigned to a single flow until all ACKs for all packets sent on the flow lane are returned. This means that the flow channel table entry can remain active for a longer time near the fabric inlet edge port than near the outlet edge port. If a single packet is injected into the network, a flow channel may be assigned to the ingress edge port, then another flow channel may be assigned to the next fabric link through which the packet passes, and so on until the last flow channel is assigned when the packet reaches the last fabric link. Each allocation may generate a flow ID, represented as a variable "flow _ ID," to identify an entry of the flow table for the fabric link. (more details about the flow path table are provided below in connection with FIG. 4A.) the first packet may result in a different flow _ id being assigned on each fabric link through the switch fabric.

At the input queue of each switch, the flow channel table entry may indicate the state information of each flow from that point downstream to the flow's egress destination edge port, including the flow _ extend value. Packets received on the local input port may increase the flow _ extend value by the amount of incoming data, while ACKs may decrease the flow _ extend by the amount of acknowledged transmitted data.

When a packet reaches the final destination egress port, an ACK packet may be generated for the packet and returned. The ACK may be routed using the data path information stored in the corresponding entry of the flow path table of each switch on the data path. Alternatively, the ACK packet itself need not carry path information and therefore may be small and light. If no other packets are sent on the flow, the ACK may release each flow channel in reverse order. Once released, the flow paths on each switch may be assigned to different flows.

If another packet follows the first packet on the same flow, then an ACK corresponding to the second packet needs to be received before the flow path is released at the given switch. In one embodiment, the flow channel can only be released when the ACKs of all transmitted packets of the same flow have returned.

In general, various protocols may require in-order packet delivery. Even when the fabric uses adaptive routing to achieve load balancing across multiple data paths, stream lanes can be used to guarantee this delivery order. If packets between an ingress edge port and an egress edge port (possibly located in a different switch remote from the fabric) are injected at a very low rate, each injected packet may reach its destination and return an ACK to the source before injecting the next packet. In this case, each packet may be a leading packet and any path from the routing cross-fabric may be selected using the best available dynamic adaptive routing. This is possible because the first packet can define the path of the flow through the fabric.

Now assume that the packet injection rate is slightly increased to the point that the next packet of the same flow is injected before the ACK for the current packet is returned to the source. The second packet may be associated with the ACK that passed through the first packet somewhere along the data path along the stream. Beyond this transit point, the ACK will release the flow channel assigned to the first packet because the flow _ extend value associated with the first packet will return to zero when the ACK is processed by the logic of the flow channel. At the same time, the second packet can now define a new flow, since it again causes the flow channels to be allocated on each subsequent fabric link. This second packet, while causing the flow channels to be allocated after this transit point is exceeded, can still be forwarded to a different path based on dynamic adaptive routing. On the other hand, before passing through the point, the second packet may expand the pending stream created by the first packet to include the second packet. This means that the ACK for the first packet may not reduce the flow _ extend value to zero and the flow channel may remain active until the point is passed. This also means that the second packet can reach the transit point along the exact path taken by the first packet. It should be noted that when it follows the previous packet, the second packet cannot reach the egress edge port before the first packet, and thus the correct packet order can be maintained.

If the injection rate of the flow is further increased, the second packet will pass through the ACK of the first packet at a position closer to the destination edge port. Depending on the packet injection rate and packet-to-ACK round trip delay for the flow, it is also possible that a third, fourth, fifth or additional packet enters the fabric before the ACK for the first packet returns to the source edge port. The maximum packet rate depends on the size of the packet and the bandwidth of the link. The round trip delay of the data packets and ACKs may be an important parameter for the fabric implementation and may be used along with the maximum packet rate to calculate the maximum number of flow channels required per link. Ideally, the design can provide a reasonable number of unassigned flow channels regardless of the flow pattern. When a large number of packets arriving at an ingress edge port have different destinations and these packets have smaller sizes and high injection rates, the demand on the number of flow channels may be high. In the most extreme case, each packet may be assigned a different flow channel. These flow channels are released when the ACK for the packet returns. Accordingly, the number of required flow channels may be calculated as ((packet rate) × (average packet to ACK round trip delay)).

Note that the packet rate on a single flow channel is not to be confused with the packet rate on the link. If the traffic pattern is such that many small packets are sent to different destinations, consecutive packets sent onto the link may have different destinations. This means that each packet may belong to a different flow and may be the only packet that uses the corresponding flow channel. In this example, the link may experience a high packet rate, but the packet rate of each flow may be lower. Optionally, multiple ACKs (e.g., 48 ACKs) may be aggregated together to form a single ACK frame for transmission over the link and protected by a frame check sequence (e.g., 32-bit FCS). For example, each ACK may occupy 25 bits and the frame may have an overhead of 9 bytes. That is, the overhead per ACK on a full-size frame is about 9/(25/8 × 48) × 100% — 6%. The logic may optimize the number of ACKs per frame so that when ACKs arrive slowly, the ACKs do not have to wait too long to aggregate. For example, the ACK aggregation logic may manage ACK transmission based on activity of the outgoing link using three timers. These timers may be started when a new ACK arrives at the ACK aggregation logic block. If the outgoing link is idle, a first timer (which may be set to 30ns, for example) may be used to hold the ACK while waiting for additional ACKs to arrive. When the timer expires, all ACKs received within the corresponding time window may be aggregated into a frame and transmitted onto the outgoing link. If the outgoing link is busy, a second timer (which may be set to 60ns, for example) may be used to wait for additional ACKs. Using this second timer may allow more ACKs to be aggregated into a single frame, and the frame may only be transmitted when a predetermined number of ACKs are collected. It should be noted that some number of ACKs in a single frame may use less per-ACK line bandwidth than other numbers of ACKs due to ethernet framing constraints. If a significant number of ACKs are not collected and the outgoing link is still busy transmitting normal data packets, a third timer may be used, which may be set to 90ns, for example. Once the third timer expires, all collected ACKs may be aggregated in a frame and transmitted onto the link. By using these three timers, the system can significantly reduce the overhead of sending ACKs on the outgoing link.

In some examples, an ingress edge port of a switch may use a fabric header to encapsulate a received packet, which allows forwarding of the packet using a flow path. Fig. 3A shows an exemplary structural header of a data packet. The fabric header may include a flow _ id field (which may identify a flow channel) and a "data _ flow" field (which may indicate the progress of the entire flow).

At least one ACK may be generated when the data packet is transmitted to its destination. Fig. 3B shows an exemplary ACK packet format. The ACK packet may include a "flow _ id" field, an "ACK _ flow" field, an "ACK type" field, and a Cyclic Redundancy Check (CRC) field. The flow _ id field may indicate the flow to which the ACK packet belongs. The ACK _ flow field may correspond to a data _ flow value associated with the data packet acknowledged by the ACK packet. Recall that each switch can maintain a flow _ extend value that indicates the amount of data that has been transferred but not acknowledged. The value of flow _ extend may be derived as data _ flow-ack _ flow, where the data _ flow value is taken from the last transmitted packet.

The ACK type field may indicate different types of ACKs. As described above, during normal operation, when a data packet is transferred to a destination edge port, a regular ACK packet may be generated and sent back to the source. Accordingly, the ACK type field in the ACK packet may indicate a normal ACK. When congestion occurs, the ACK type field may be used to indicate various types and severity of congestion, such as new congestion on a flow, persistent congestion on a flow, severe congestion on an egress edge port, or mid-fabric local congestion that requires rerouting of flows to rebalance the load of the entire fabric. In addition, in special cases such as heavily congested fabric links, dropped packets, or link errors, ACKs may also be generated by intermediate switches that are not the final destination, and the ACK type field may be used to inform upstream switches of different types of network conditions. Other additional fields may also be included in the ACK packet.

Fig. 3C shows the relationship between different variables used to derive and maintain state information for a flow. In this example, the switch may use the variable "total _ extend" to track the total amount of unacknowledged transmitted data and data currently queued at the switch. the value of total _ extend may be equal to the sum of flow _ extend (the amount of data transmitted and not acknowledged) and queue _ extend (the amount of data stored in the input queue of the corresponding stream). The variable "ACK _ flow" may indicate the data location corresponding to the latest ACK for the flow. The variable "data _ flow" may indicate the location of the next packet to be transmitted, which also corresponds to the packet stored at the head of the input queue. The variable "next _ data _ flow" may indicate the location where the switch can expect the next packet received from an upstream switch. Note that queue _ extent is next _ data _ flow-data _ flow, and flow _ extent is data _ flow-ack _ flow.

In some examples, a flow channel table may be used to facilitate flow channels throughout the structure. A flow path table is a data structure that stores forwarding and state information for a given flow at a switch port. Fig. 4A illustrates an example of how state information associated with multiple streams may be stored using a stream channel table. This state information can be specific to each flow and efficiently stored in a table. Assume that source host 402 is sending a packet to destination host 404 via a fabric. The data path traversed by the packet may include ingress edge switch 406, intermediate switches 408 and 430, and egress edge switch 432.

When a packet arrives on an ingress edge link 403 of a switch 406, the address translation logic 410 may analyze the header of the packet. Address translation logic 410 may determine the destination fabric address of the egress switch (in this case switch 432) based on the ethernet, IP, or HPC header information of the packet. It should be noted that the address translation logic 410 may also use header information associated with other protocols or combinations of different protocols. The fabric destination address determined by the address translation logic 410 may then be used to perform a lookup in an Edge Flow Channel Table (EFCT) 412. EFCT 412 may perform a lookup operation on a packet using the packet's structural destination address and optionally additional values extracted from the packet's header (which may be referred to as a matching pattern). EFCT 412 may compare the matching pattern of packets to the stored matching patterns of all existing assigned streams. If a match is found, the packet is part of an existing flow and a previously assigned flow ID may be returned for the packet. If a match is not found, a new flow ID may be assigned to the packet and a matching pattern may be added to EFCT 412. In other words, EFCT 412 may be used to determine whether a flow channel already exists for an incoming packet or whether a new flow channel needs to be allocated. In addition to the destination fabric address, other packet header information (such as traffic classification, TCP or UDP port number, and process or thread ID) may also be used to map or assign the stream ID.

The stream ID obtained by EFCT 412 may then be used as an index to map to an entry in an input stream channel table (IFCT) 414. Each entry in IFCT 414 may be indexed by a stream ID and store state information for the corresponding stream. The entries in IFCT 414 may store the values of next _ data _ flow, and ack _ flow (see FIG. 3C) associated with the flow. In addition, the IFCT entries may store other parameters for congestion control and dynamic routing of flows.

The flow ID may also be used to identify or assign a flow-specific input queue in which incoming packets may be temporarily stored. Status information for a particular queue and parameters used to monitor and control the queue (e.g., thresholds for detecting congestion) may be stored in corresponding entries in IFCT 414. The input queue management logic may determine when a packet may be dequeued from an input queue and sent to the data crossbar switch 413 based on flow control parameters stored in entries of the IFCT 414.

When a packet is dequeued from an input queue and sent through crossbar switch 413 to an output port, the packet will be sent with the input port number at the time it arrives at switch 406. When the packet arrives at the transmission buffer of the output port, the header of the packet may be updated with a new flow ID based on the flow ID and input port number of the packet for use by the next-hop switch (i.e., switch 408) for the same flow. This is because each link may have its own set of flow channels identified by their respective flow IDs in each direction. The mapping from incoming stream ID to outgoing stream ID used on the next link can be done by looking up the outgoing stream channel table (OFCT) 416. OFCT 416 may perform a lookup using a matching pattern that is a combination of the local input port number corresponding to link 403 and the flow ID of the packet generated by EFCT 412. If a match is found, the flow has already been defined and the packet's flow ID is updated with the value corresponding to the matching pattern (this new outgoing flow ID will be used by the downstream next-hop switch 408). If no match is found, a new outgoing stream ID may be assigned to the new stream channel, which may be mapped to the input port number and the previous incoming stream ID. An entry including the outgoing flow ID, the incoming port number, and the incoming flow ID may be stored in OFCT 416.

In the case where the packet is the first packet in the flow, the lookup in OFCT 416 does not result in any mapping. In turn, OFCT 416 may assign a flow path to the packet with a flow ID to be used by the input port on switch 408 and IFCT 418. This new flow path identified by its flow ID may be added to the packet header for transmission onto link 417 and may be used by IFCT418 of the link partner (switch 408) to access the congestion information of the flow path. As previously described, if no match is found, OFCT 424 may further generate a new flow channel using its matching pattern of the immediately upstream input port number and the flow ID associated with link 417. OFCT 424 may then assign a new flow channel identified by the new flow ID. It should be noted that OFCT 416 may also be used as a forwarding table for ACKs for the flow in the upstream direction. After forwarding upstream from switch 408 to switch 406, the ACK packet may be updated with the flow ID associated with edge link 403 and forwarded to the appropriate input port on switch 406 as indicated by the corresponding entry in OFCT 416. The ACK packet may be forwarded by ACK crossbar switch 415 in the upstream direction to the input port.

Subsequently, when a packet arrives at switch 408, its flow ID may be used to identify the input queue to use and determine the entry in IFCT 418. If switch 408 has not previously allocated the flow ID of the packet, a new input queue may be provided and a new entry may be created in IFCT 418. From this point on, a similar process may be performed to forward packets across switches 408 and 430 until the packets reach egress switch 432.

When a packet arrives at switch 432, ACK generator logic block 420 may generate an ACK packet based on the packet's flow ID and input port number after the packet is forwarded by data crossbar switch 423. The ACK packet may then be forwarded in the upstream direction by ACK crossbar switch 422. Meanwhile, based on the ACK packet, the IFCT 421 may update the state information of the flow in the corresponding table entry. When the ACK packet arrives at switch 430, OFCT 419 may be looked up to determine the upstream flow ID and upstream input port to which the ACK packet is to be forwarded. The ACK packet may then update its flow ID and forward to the appropriate input port in the upstream direction. Since ACK packets traverse the data path upstream in a similar manner, each switch's IFCT may update its table entry for the flow based on the ACK.

It should be noted that the flow _ extend variable may be an important parameter because it represents the total amount of data of the downstream packet of the stream. When the flow _ extend of the entry is zero, it is considered that the stream channel can be freely reassigned to another stream. Typically, upon receiving a new packet, the input logic may request that data be sent to the output port. The selected output port may be a function of flow _ extend stored in the IFCT. If flow _ extend is zero, there are no packets downstream of the flow towards the destination egress edge port. Thus, the switch can use load-based adaptive routing to select any active path to the destination. In a multi-path network, dynamic adaptive routing can be accomplished without reordering packets. If flow _ extend is not zero and in-order delivery is required, the packet may use the same route that was used for the previous packet. The IFCT may have a field storing the previous output port number, which is loaded and may be used to ensure connection with the previously used output port when a packet request is issued to the output port.

As previously described, a flow channel may use a matching function to identify packets belonging to an existing flow. When an ethernet frame or other type of packet is received on an ingress edge port, the received frame or packet may be parsed in real time and some fields of the packet header may be used for lookup in a CAM or Ternary Content Addressable Memory (TCAM). If there is a match, the matching address may become the stream ID used to select the stream channel. When a match does not occur, the switch hardware may load the pattern of the match failure directly onto the CAM's free line, which may be done without additional delay. Thus, any subsequent packets can be matched to the new entry without extensive buffering. The selected free entry becomes the new flow ID of the new flow channel entry. It should be noted that no external software intervention is required to load the new entry. This process may be done autonomously by the switch hardware.

The de-allocation of the stream ID and corresponding CAM match line may also be performed automatically by hardware when the last ACK of the stream is returned. The deallocation can be done in hardware for new packets that potentially match, without external software intervention.

In some examples, ingress edge switch 406 may include fine-grained flow control logic 434 that may communicate with Network Interface Controller (NIC)401 on host 402 to apply flow control on a per-flow basis. More details regarding fine-grained flow control are provided below in connection with the description of congestion management.

Fig. 4B shows an example of EFCT. In this example, EFCT may include a data _ flow field 454, an ACK _ flow field 456, and optionally additional fields. EFCT may be associated with an input port and entries in EFCT may be indexed by a flow _ ID value, such as flow _ ID 452. In one embodiment, the match pattern field may reside in a match function logic block, which may comprise a CAM or TCAM. The match function logic may use the match pattern to generate a flow _ ID value, which in turn may be used as an index to a corresponding EFCT entry. From the perspective of the EFCT, flow _ extend (i.e., data _ flow-ack _ flow) may include all unacknowledged data downstream of the table, which may include the local flow _ queue plus the flow _ extend value for the corresponding IFCT.

Fig. 4C shows an example of IFCT. In this example, the IFCT may be associated with an input port and may include a follow _ port field 466, a next _ data _ flow field 468, a data _ flow field 470, an ACK _ flow field 472, an ep _ context field 474, an Upstream Metering (UM) flag field 477, a Downstream Metering (DM) flag field 478, and optionally additional fields. The flow _ ID value of an incoming packet (e.g., flow _ ID 464) may be used as an index to look up the output port number indicated by the follow _ port field 466 and the state information associated with the corresponding flow. Congestion control information associated with endpoint congestion (e.g., ep _ congestion field 474) and hop-by-hop credit based flow control (e.g., UM flag field 477 and DM flag field 478) may also be stored in the IFCT, as will be described in more detail later in this document. The IFCT may further store information about dynamic routes associated with different flows.

Fig. 4D shows an example of OFCT. In this example, the OFCT may be associated with an output port and may include an input _ port field 482, an input _ port _ flow _ ID field 484 (which corresponds to the existing flow _ ID of a packet when it arrives at the input port), a data _ flow field 486, an ACK _ flow field 488, and optionally additional fields. Data _ flow field 486 and ACK _ flow field 488 may be used to determine the value of flow _ extend from the OFCT. The combination of input _ port field 482 and input _ port _ flow _ ID field 484 (which may also be referred to as "ingress flow _ ID") may be used to determine or assign an egress flow _ ID ready for transmission to a packet on an egress link corresponding to the OFCT. In one embodiment, an outgoing flow _ ID value (e.g., flow _ ID 486) may be used as an index to look up an entry in the OFCT.

Exemplary switch architecture

In one embodiment, a switch chip supporting the above features may provide 64 network ports, each of which may operate at 100Gbps or 200Gbps with a total throughput of 12.8 Tbps. Other numbers of ports and data rates are also possible. Each network edge port may support various types of protocols such as IEEE 802.3, ethernet, optimized IP based protocols, and HPC portal protocols. The ethernet frame may be bridged based on its layer 2 address or routed based on its layer 3 (IPv4/IPv6) address. Optimized IP frames have only layer 3 (IPv4/IPv6) headers, so they are typically routed based on layer 3 addresses. The enhanced portal format frames typically use a dedicated NIC and may be mapped directly to the enhanced fabric format of the switch.

When a switch chip is connected to another switch chip, they may communicate using an enhanced fabric frame format that provides additional control fields and status fields to support a multi-chip fabric. One of the distinguishing features of the switch architecture of the present disclosure compared to ethernet switches or alternative technologies such as infiniband is that the switch of the present disclosure can provide flow path-based congestion control. An enhanced fabric frame format running between switch chips may provide forward and reverse path signaling of states for a flow.

In one embodiment, the switch chip may be implemented based on a crossbar architecture with combined virtual output queuing and crossbar queuing. Buffering and forwarding of data packets may be accomplished through credit-based request and authorization mechanisms.

Fig. 5A illustrates an exemplary switch architecture. In one embodiment, the switch chip may include a Receiver (RX) block 502 and a Transmitter (TX) block 504. When traffic is received from the RX block 502, if the switch chip is configured as an edge switch, the packet may be sent to an Ethernet Lookup (ELU) block 506. ELU block 506 may provide address translation (lookup) from the external MAC or IP address (most often, but other header fields may also be used) to an internal Fabric Address (FA). The ELU block 506 may also provide a mapping from the packet's own traffic class identifier (e.g., Ethernet traffic class) to a fabric traffic class identifier, which may be identified by a Fabric Tag (FTAG) included in the fabric header.

In one embodiment, IEEE 802.3 and optimized IP format packets may be passed through ELU block 506. ELU block 506 may extract the appropriate headers for the lookup process and return the lookup result to Ethernet Ingress Queue (EIQ) block 508, which queues the headers for flow path allocation in EFCT block 510. EIQ block 508 may also associate the packet address stored in the Input Buffer (IBUF) block 512 with its translated header. For IEEE 802.3 and optimized IP packets, ELU block 506 may perform a lookup to create a field for forwarding the packet within the fabric.

For ingress edge ports, EIQ block 508 may queue the packet header to wait for EFCT block 510 to allocate the flow channel. If EFCT block 510 runs out of flow channels, EIQ the FIFO queue in block 508 may fill and when a configurable threshold is exceeded, a pause packet may be generated. For packets received from fabric ports, these packets do not require flow path allocation and therefore their headers are not queued in EIQ block 508.

An Input Header (IHDR) block 514 coupled to the IBUF block 512 may perform modifications on the received packets and update the structural header fields of the packets. The IHDR block 514 may receive packet data, an entry timestamp, and an authorization header (which may contain modification data and instructions) from the IBUF block 512. Such modifications may include removing various ethernet layer 2 header fields and adding a fabric header. The IHDR block 514 may modify the packets "on the fly" as they are read out of the IBUF block 512 and sent to the data crossbar 516.

The IBUF block 512 may store unmodified packets as they are received by the switch chip and may support different formats. The stored packet address (i.e., the pointer denoted sop _ ptr) and the index of the packet may be sent EIQ by IBUF block 512 to block 508, which EIQ may match the packet with the results of the header lookup of ELU block 506.

At some point in time, each packet stored in IBUF block 512 is either sent to the destination port via data crossbar 516 based on the grant sent via grant crossbar 518 and input queue (INQ) block 520 (explained below), or is dropped. Both operations may be performed based on a reference to sop _ ptr. The grant may also contain other fields from ELU block 506 and EFCT 510 that may be sent with the packet to IHDR block 514. The IHDR block 514 in turn may use the control information from the authorization header to make appropriate modifications to the packet before forwarding the packet to the destination port via the data crossbar 516. When the buffers in IBUF block 512 are full, configurable thresholds may be exceeded, which may trigger various flow control and congestion management mechanisms.

EFCT 510 may assign flow lanes for packets depending on the FTAG, destination address, and Virtual Network Identifier (VNI). Matching patterns may provide separation between flows with individual ordering and priority constraints between the same source and destination fabric ports. In general, different cores on a node may run using different VNIs, and this flow separation allows for different core decouples (decouples).

If the matching value is currently unique, a new flow channel may be assigned. If the match value is the same as the match value of the existing allocated flow channel, the packet is assigned to the corresponding existing flow. The size of the packet may be used to increment the data _ flow value of the stream. In one embodiment, for edge ports, OFCT 522 may be used as EFCT. The acknowledgement returned from the downstream flow channel table is used to increase the flow's ack _ flow value. When this value catches up with the data _ flow value, the stream channel may be automatically deallocated and its matching pattern may be invalidated.

The INQ block 520 may receive header requests from EIQ block 508 and, for ingress edge ports, may also receive header requests from EFCT 510. The INQ block 520 may store the lookup result header in its header RAM. A pointer to each header may be stored in one of a set of queues based on the corresponding flow channel of the header. At the edge port, the packet headers may be arbitrated in a fair manner for routing by application packets (APPGs) that may be used to group applications into different traffic classes. At a fabric port, the header may be arbitrated based on its flow path. When the header is considered for routing, it may be forwarded to Fabric Routing Function (FRF) block 524 and then also to IFCT 526.

FRF block 524 may perform routing functions based on the network topology and select output ports to which packets are to be forwarded (or ports for multicast). The routing results may be passed to IFCT 526 where they are combined with the rest of the header and IFCT 526 may use the results from FRF block 524 or select a previous route using the given flow if it is important to maintain packet order. IFCT 526 may then pass the forwarding result (i.e., output port information for the given packet) back to INQ block 520 as a new request. The request may then be used to schedule the packet for transmission through the data crossbar 516 toward the desired output port.

The request may then be placed in a request queue (or queues) in INQ block 520 based on a shaping function corresponding to the flow channel, Virtual Channel (VC) identifier, and output port. (note that to avoid deadlock, the physical link may be divided into multiple virtual link groups using VCs.) after arbitration, a request may be sent through request crossbar 528 to age queue (AGEQ) block 530. Later, the corresponding grant may be returned via the grant crossbar 518. When a grant is returned, the INQ block 520 may take the corresponding header and return it to the IBUF block 512 where it is recombined with its payload and then forwarded to the IHDR block 514 and subsequent data crossbar 516.

As previously described, IFCT 526 may measure the amount of flow data buffered in the local flow queue. It may also measure the amount of unacknowledged data downstream in the flow. IFCT 526 may also store the returned acknowledgement code value in its table and use the flow-specific state information and configuration information indexed by the packet's FTAG value to determine whether the header of the packet it receives is to be forwarded, discarded, or waiting (master to wait) longer. The "waiting" condition may be achieved by not dequeuing headers from the flow queue. The headers may eventually be dequeued and the decision to forward, discard or wait may be made again. In one embodiment, IFCT 516 may have a "drop" interface to IBUF block 512, which allows the sop _ ptr value to be passed to IBUF block 512 when a packet is to be dropped. In response, the header of the packet may be discarded before being added to the request queue. IFCT 516 may further increment the corresponding statistics of the dropped packets.

FRF block 524 may receive route requests from INQ block 520 for each received packet and may return a route response to IFCT 526 for each route request. The routing response may indicate to which port or ports the packet should be forwarded and on which VC. For non-multicast requests, the response may indicate a preferred port and a set of acceptable ports to which the packet may be forwarded, allowing IFCT 526 to use the preferred port for new flows or rerouted flows, or to maintain the current path for existing flows via a port that may not be the currently preferred choice of FRF block 524. In case of an error, the FRF may also indicate to the IFCT the legitimate port to which no packet can be forwarded. When this occurs, the packet is dropped.

The routing decision of FRF block 524 may be based on a combination of: rules based on software configurable tables, dynamic load information and pseudo-random selection. Factors that a rule may consider include the destination of a packet, the location of the packet on its path (e.g., source packet, intermediate packet, destination switch), the VC on which the packet is received, and the type of port (edge, local, or global) on which the packet is received. The AGEQ block 530 may provide the FRF block 524 with the current load present on the output side of the port associated with the given FRF instance. Each FRF instance may communicate with every other FRF instance within the switch core to know the current load at each output port, and the link up/down status of each port. The FRF instance may also communicate with FRF instances in neighboring switch chips to obtain load-related status of neighboring devices. In one embodiment, FRF block 524 may be configured to support multiple network topologies.

The AGEQ block 530 may accept requests from all input ports via request crossbar 528, buffer the requests, arbitrate among the requests by traffic classification using a traffic shaper, and pass the requests to OFCT block 522 to be granted by grant crossbar 518. The buffering of requests within the AGEQ block 530 may be managed to allow each input sufficient space to send a request while also allowing inputs with multiple streams targeting a given output to take up more space. The AGEQ block 530 may also be responsible for managing access to the links using either credit-based flow control for IBUF blocks of adjacent switch chips or pause-based flow control for unstructured links. When a packet is released by the AGEQ block 530 (i.e., a corresponding grant is issued for the packet waiting in the IBUF block 512), the packet will be placed on the outgoing link. Additionally, the AGEQ block 530 may have a path that allows packets originating on a given port, such as maintenance or reduction packets, to arbitrate for resources on the port.

The OFCT 522 can be programmed to operate as an EFCT for an egress edge port, or as an OFCT for a fabric port. For egress edge port operations, when the block is programmed as EFCT, the header received from the AGEQ block 530 may be passed through EFCT to the authorization crossbar 518 and remain largely unchanged. EFCT may also receive a new ACK from an Output Buffer (OBUF) block 532 to acknowledge packets leaving the structure. These ACKs may be returned to ACK crossbar 534 and will be ACKs that close the flow in the upstream flow table. EFCT may also generate a congestion notification message when the agrq block 530 reports congestion. This congestion on the egress edge port typically represents an incast formation and is used to slow down the flow returning on the ingress edge port.

For fabric port operations, OFCT 522 may manage the flow path allocation for the next hop switch on the outgoing link. It may work in tandem with the IFCTs of the fabric link partners and create extensions for flows that may be used by the IFCTs of the link partners to manage packet forwarding progress.

OFCT 522 may also manage ACKs received from fabric links and return those ACKs upstream through ACK crossbar 534. After the existing flow has been created or extended, OFCT 522 may generate flow _ ID and data _ flow values that may be added to the next hop structure header by IHDR block 514 and add these values to the grant that is returned to grant crossbar 518 along with other header values.

An Output Buffer (OBUF) block 532 may capture packets that have been sent to a corresponding output port through the data crossbar 516. The packets may arrive on, for example, four different column buses, enqueued on, for example, four separate FIFO queues (explained in more detail in connection with fig. 5B). The OBUF block 532 may arbitrate among these FIFO queues to check whether each packet is a data reduction packet (reduction packet). Any data reduction packets that match descriptors in Reduction Engine (RED) block 534 may be consumed by RED block 534. All other packets may be enqueued in the elastic FIFO queue waiting to be transmitted to the outgoing link. OBUF block 532 may include an output arbiter that may select packets from the elastic FIFO queues, full reduction packets from RED block 534, control packets from control packet transmitter (CFTX) block 536, and injected packets from the management interface for transmission to the outgoing link.

If the AGEQ block 530 starts to fill or drop ACKs, the OBUF block 532 may also generate an ACK value to indicate intermediate fabric congestion if the AGEQ block 530 has dropped packets.

In one embodiment, a control packet receiver (CFRX) block 538 may process all control-related packets that may be extracted from the IBUF block 512. These control related packets may include congestion signaling packets, flow control credit issue packets, and flow channel ACKs, among others. Congestion signaling information may be sent to FRF block 524 and used to make routing decisions. Credit-based flow control information may be sent to the AGEQ block 530 for scheduling packets for forwarding to downstream switches. The ACK may be sent to OFCT 522 (which in turn may identify the input port to which the ACK is to be forwarded) and then to ACK crossbar 534.

Accordingly, CFTX block 536 may send an ACK (based on IFCT 526), a credit-based flow control packet (based on the state of IBUF block 512), and a congestion signaling packet to the corresponding output port.

The OBUF block 532 may also generate credit feedback to the AGEQ block 530 indicating the landing space (mapping space) available for outgoing packets (note that the credit is for crossbar scheduling between the crossbar's inputs and outputs and is different than the credit for inter-switch flow control). The credit information is passed by the AGEQ block 530 to the INQ block 520, optionally via credit crossbar 540, which uses the credit information to schedule packet extraction from the IBUF block 512.

As described above, there may be five crossbars in a switch chip: request crossbar 528, grant crossbar 518, credit crossbar 540, ACK crossbar 534, and data crossbar 516.

Request crossbar 528 may send requests from the inputs to the target output AGEQ block. The credit protocol may be used to ensure that there is a requested landing space at the output. Each request may contain a pointer (sop _ ptr) to the storage location of the packet in IBUF block 512.

The authorization crossbar 518 may return authorization to the input that satisfies the request. The grant may return a pointer (sop _ ptr). A grant is returned only if there is room for the corresponding packet in the OBUF block 532. Authorization may also optionally return credits for the requested space in OBUF block 532.

Credit crossbar 540 may return credits for the request space in OBUF block 532. ACK crossbar 534 may propagate ACK packets from output ports to input ports based on OFCT 522. The data crossbar 516 may move authorized packets from the IBUF block 512 to the target OBUF block 532. Authorization is returned only when there is guaranteed package landing space at the output, so the package is not blocked.

Fig. 5B shows an exemplary cross switch. In this example, a crossbar tile matrix 550 may be used to forward data, ACKs, requests, grants, and credits. The data crossbar may move multi-clock packets with headers and data payloads, while the other four crossbars move only single-clock packet headers. All five crossbars may use the same basic architecture. As shown in fig. 5B, the crossbar tile matrix 550 may be a 64 x 64 device made up of an 8 x 4 matrix of 32 crossbar tiles. Each tile may be a 16 x8 crossbar switch with 16 inputs (one for each port in its corresponding row (e.g., row 552) and 8 outputs (one for each port in its corresponding column (e.g., column 554)).

FIG. 5C illustrates an exemplary architecture of a crossbar tile. In this example, crossbar tile 570 may have 16 input ports and 8 output ports. The input buffer for a corresponding input port (e.g., input 0) may be partitioned into separate virtual output queues, such as queue 572. Each virtual output queue corresponds to a respective output port. The virtual output queue arrangement may avoid input head of line blocking. Additionally, at each crossbar switch point there is a crossbar queue, such as queue 574, that can absorb packets sent by a respective input on the row bus to the corresponding column bus. The crossbar queues may avoid blocking on the output (column) bus and allow the column bus to be more fully utilized. During operation, the transfer of packets from input to output is accomplished through a request-grant mechanism. In a first round of arbitration, each virtual output queue may request to send its stored packets (if any). The transmission of requests from all virtual output queues of an input is accomplished by an input arbiter, such as arbiter 576. Once these requests are made, the output scheduler issues the corresponding grants. After the input port receives the grant, the corresponding packet is dequeued from the virtual output queue and forwarded by the crossbar switch. The packet is then temporarily stored in the crossbar queue of the appropriate output (column) bus. A second arbiter (e.g., arbiter 578) may be used to schedule the extraction of packets from the plurality of crossbar queues corresponding to a given column bus.

Returning now to FIG. 5B, each row may have 16 row buses (e.g., row bus 553) that feed input data to all of the tiles in the row. Each column may have 8 column buses (e.g., column bus 555) that transmit forwarded data to corresponding output ports. The row bus can be driven from each source in a row to all 8 crossbar tiles in that row. Each row may have the same connections, a single row with a pair of all (one-to-all) row bus connections. Arbitration may occur at a crossbar from the 16 row buses of the row to the 8 column buses in a given column. Buffering is provided on each 16 x8 crossbar tile of each row bus to absorb packets during the time when the column buses are contended. In one embodiment, non-jumbo packets are not placed on the row bus unless there is room for the entire packet in the input buffer of the target crossbar. To save chip area (real estate), even if there is not enough space, it is allowed to place the jumbo packet on the row bus, which is blocked until the packet wins arbitration and frees up space when it moves onto the column bus (i.e., the input buffer size can only be used to accept non-jumbo packets). The column bus may be driven from a given crossbar to each destination port within a column. Each destination port performs another level of arbitration between the column buses from 4 rows. The 16 row buses drive 8 crossbars, each of which feeds 8 column buses, with 4 times acceleration between rows and columns possible.

In one embodiment, both the row and column buses may use a credit-based protocol to determine when they are able to transmit (see arbiters 576 and 578 in FIG. 5C). In the case of a row bus, the source port may maintain a credit count for the input buffer of the in-row crossbar. For a data crossbar, when a packet is allowed to enter the row bus depends on the queue configuration and state. If the grants for the input buffers of a particular crossbar all pass through a single queue, there needs to be room for the packet at the head of the queue before starting the packet transmission. If grants are distributed among multiple queues, packet transfer will not begin unless there is room in the buffer for the entire maximum size packet in order to prevent small packets from locking out large packets. In this way, once a packet transfer on the row bus begins, it does not stop until the entire packet is transferred. Accordingly, the crossbar input buffer is large enough to handle the maximum packet size and has additional space to cover the worst-case round trip (from packet send to credit return). However, this may not be the case for jumbo bags. For jumbo packets, to save the buffer, the input buffer of the crossbar may be set to just have enough space to handle non-jumbo sized maximum transmission unit (MTU, e.g., approximately 1500 bytes) packets, where the jumbo packet is allowed to block the row bus while waiting to gain access to the target column bus.

For a column bus, each crossbar tile may maintain a credit count for the input buffer at each destination port in the column. Unlike the row bus, there is no requirement that a credit be available for the largest size packet before the packet begins to be transmitted on the column bus. When credit becomes available, individual words of the packet may be moved. Thus, the input buffer at the destination of each column bus need only be large enough to cover the worst-case round trip (e.g., from packet transmission to credit return).

As shown in FIGS. 5B and 5C, each crossbar tile may have 16 row bus input buffers and 8 possible destinations. Round-robin arbitration may be used between 16 sources per destination. For a data crossbar, once the source wins arbitration, it may retain control of the destination column bus until the entire packet has been sent.

In one embodiment, the output control block may be responsible for accepting requests from all input ports via the request crossbar, buffering the requests, and passing the requests to the OFCT for authorization via the authorization crossbar. The AGEQ space may be managed by an output control block to allow a single input with multiple streams targeting a given output to move its request to the AGEQ. The output control block may also be responsible for managing the use of space in the input buffers and allocation of stream lanes on downstream neighboring switches (i.e., link partners corresponding to the output ports). In addition, the output control block may have a path that allows packets (e.g., maintenance or reduction packets) originating on a given port to be arbitrated for resources on the port.

Requests may enter the output control block from each row of the matrix via the column bus. Each column bus may feed a separate FIFO queue, where space in the FIFO queue is managed via credits. The size of these FIFOs may be deep enough to cover the maximum round trip delay plus some additional space to allow requests to be moved out of the crossbar and prevent head-of-line blocking. The request may be checked for a valid Error Check Code (ECC) before being written to the FIFO queue. If an error is detected, the packet may be discarded and the error marked.

In one embodiment, Least Recently Used (LRU) arbitration may be used between column bus FIFO queues to select which FIFO queue is selected and forward the corresponding request to the AGEQ block. When a request is removed from each FIFO queue, credits may be returned to the corresponding crossbar.

The output buffer may issue a request to the output control block to send the reduction and maintenance packets on the corresponding outgoing link. These requests may be given higher priority. In one embodiment, the reduction package does not use flow channels and the maintenance package can use loopback (loopback) to create flows, thus there is no need to check flow channel availability or use OFCT to create authorizations. They also do not use space in the output buffer and therefore do not need examination space.

The size of the next request to be processed from the output buffer may be checked against the maximum packet size. If it exceeds this value, the request is not processed and an error flag may be set. This may cause the output buffer request path to be blocked until a warm reset is performed.

In one embodiment, each input port may be allocated a fixed amount of AGEQ space, denoted fixed alloc. This space may be large enough to accommodate each traffic class associated with the corresponding input port, and have enough additional space to cover request-credit round trips. The allocation of the fixed space between different traffic classes within the same input port is configurable. Traffic classification may be identified by a combination of a Shaping Queue (SQ) identifier and a Virtual Channel (VC) identifier. In one embodiment, the AGEQ may have 8k positions, each position corresponding to a unit of flow. The fixed allocated space total may be (64 fixed alloc) and the remaining space may be 8k-64 fixed alloc. This remaining space may be shared between all inputs.

The shared space may be managed by the output. If there is space in the shared space, the incoming request may move from the static space to the shared space as it arrives, but limited by each input. When a request is moved to shared space, credits may be returned immediately via a credit crossbar and the request marked as being in shared space in the AGEQ. When a request is granted, the shared space is credited if it is marked as using the shared space. If the request is not marked as using shared space, it is considered to use static space and credit is returned to the input along with the authorization.

Credits may not be sent every clock cycle due to collisions in the credit crossbar. The FIFO queue may be used to provide buffering for these transient interrupts. In one embodiment, requests from the request crossbar may be accepted only if there is space in the FIFO queue. For example, a FIFO queue with a depth of 32 positions may be used to limit the likelihood of its backup into the request crossbar.

Shared space in the AGEQ may limit the amount of space that any single input may occupy. These limits may be set as a percentage of the available space. For example, if the limit is set to 50%, and if an input is active, then the input may access 50% of the shared space. In the case of two active inputs, each input has access to 37.5% of the shared space, calculated as (space _ used _ by _ l + space _ left 0.5)/2 ═ 37.5% (50% + 50% × 0.5)/2 ═ 37.5%. With three active inputs, each input has access to 29.2% of the shared space, calculated as (space _ used _ by _2+ space _ left 0.5)/3 ═ 75% + 25% × 0.5)/2 ═ 29.2%, and so on. The total amount of total shared space that can be used by all activity inputs is limited, 50%, 75%, and 87.5% in these three examples, respectively. With this configuration, the shared space allocated to each input may be dynamically changed based on the number of inputs currently active. Additional activity inputs may cause other activity inputs to relinquish their shared space, which is then allocated to the new input.

Given that the cost of implementing partitioning in hardware can be high, such a dynamic allocation function of shared AGEQ space can be implemented as a lookup table with, for example, 64 entries, where each entry corresponds to a certain number of active input ports. The number of active input ports may be used as an index to the table. The values in the table may be a limit to the shared space that any input can access and the total space that they can consume in their entirety. Software-based functionality may be used to program the values in the table according to the total amount of shared space and the percentage of usage allowed for each input. As more inputs become active, less and less space is allowed per input and the total space available increases. Incoming requests from inputs that exceed this limit or total amounts that exceed the total space limit may not be allowed to take up more shared space.

To track the number of active inputs in an AGEQ, a set of 64 counters (one for each input) may be used. These counters may count up when a request is placed in an AGEQ and count down when it is fetched (authorized). A second counter that counts the number of non-zero counts can be used to index into the lookup table for shared space allocation. Additionally, to manage the shared space, an additional set of 64 counters may be used to track the current usage of the shared space by each input. A single counter may also be used to track overall shared space usage. These counters may be compared to the current quota to determine whether to allow the request to use the shared space. In one embodiment, all counters may be 13 bits wide, which is sufficient to cover, for example, 8K positions in the AGEQ.

Fig. 5D illustrates an exemplary embodiment of an age queue. In this example, the age queue may use a request RAM 580 having, for example, 8K locations. These positions may be dynamically assigned to a number of individual queues 582, which may correspond to the total number of traffic class (identified by SQ value) and virtual lane (identified by VC value) combinations. In one embodiment, one physical link may be divided into four VCs and the system may support 8 traffic classes. Accordingly, there are a total of 32 (i.e., 4 x 8) separate queues, each for a unique SQ/VC combination. Each queue may be a linked list of locations within a storage ram. This enables each SQ/VC combination to take up more space as required.

As shown in fig. 5D, each queue may include a front pointer to the front of the chain table. Each entry in the linked list also includes a pointer to the next entry in the linked list. In one embodiment, a pointer to the next entry may be stored in the next pointer RAM. The last position in the queue may be pointed to by a backward pointer. Each location in the respective queue can accommodate a request. Requests may be dequeued from the front of the queue and inserted to the back of the queue.

In addition to the linked list data structure, each queue may also have a FIFO queue at its head, such as the FIFO queue 584 of requests. These FIFO queues may be used to ensure that the queue can maintain each clock of requests with a multi-clock read access time from the request RAM. When a new request arrives, if the head FIFO queue of the queue is not full, the request can be written directly to the head FIFO queue bypassing the request RAM. Once a request for a given queue is written to the request RAM, subsequent requests are also written to the request RAM to maintain order. The bypass path may be used again as soon as there are no more requests for the queue in the request RAM and there is space in the corresponding head FIFO.

When a request is read from the head FIFO queue, and there is a corresponding request queued in the request RAM, a dequeue operation may be initiated. Since only one head FIFO queue is read at a time, only one dequeue operation can be initiated per clock cycle. Logic may be included to handle various race conditions between an ongoing or imminent enqueue operation and the head FIFO queue being read.

The free list RAM may be a simple FIFO queue that is initialized with pointers to all entries (e.g., 8k entries) whenever a reset is completed. A count may be kept to track how many entries in the free list RAM are valid. When an entry is fetched, the entry is popped from the front of the FIFO and used. When an entry is returned, the entry is pushed to the back of the FIFO queue 585. Multiple entries (e.g., 3) of the free list RAM header may be saved in the trigger so that they can be accessed quickly.

To support the full performance of a packet, the age queue needs to support enqueue and dequeue operations each clock cycle. The following gives the operation on the data structure for enqueue operations. These operations differ depending on whether the queue being written is empty or not. In most cases, simultaneous enqueuing and dequeuing of a particular queue can be handled because they use and update different fields. One special case is where a dequeue operation clears a queue. To handle this situation, logically a dequeue operation may be performed first, followed by an enqueue operation. This may be accomplished by using an empty flag for the queue that may be set when the queue is emptied by a dequeue operation and then cleared based on an enqueue operation.

Arbitration may occur between requests that are granted subject to input buffer management, output buffer management, and stream channel quotas. Arbitration may also be stopped if the OFCT input FIFO queue has no credits. In one embodiment, arbitration may be performed in two stages, one between SQs and one between VCs. Traffic shaping arbitration may be used to arbitrate between SQs. Deficit round-robin (default round-robin) arbitration may be used to arbitrate between VCs within a given SQ.

In one embodiment, traffic shaping arbitration may use a series of token buckets (token buckets) to control the bandwidth of each SQ. For example, if there are 8 SQs, there may be 8 leaf buckets (one for each SQ), 4 branch buckets, and one head bucket. Arbitration may be divided into three packets, packet 1 having the highest priority, followed by packet 2, and then packet 3. Arbitration may occur in the same manner between eligible SQs for both packet 1 and packet 2. For each of these 8 priorities, x8 round-robin arbitration (8 parallel round-robin arbitration operations) may be performed between SQs. A fixed arbitration between the priorities can be performed. Packet 3 arbitration has no priority and may be a single x8 round robin arbitration. For packet 1 arbitration, the priority of each arbitration comes from the settings in the leaf bucket. For packet 2 arbitration, the priority comes from the setting in the branch bucket. In all cases, if the request wins arbitration, the bucket that is checked as eligible for the packet is also the bucket from which the packet size token is obtained.

Packets may be classified to select the SQ to which their request is to be forwarded. This allows traffic associated with an application to form a different shape than traffic from a different application or a different traffic class. This feature is particularly important on edge ports connected to NICs, as applications are typically configured to use resource sharing on nodes, and similarly they are granted a certain proportion of network bandwidth. In one embodiment, this classification may be performed by tagging packets with the FTAG and VNI as they enter the fabric. The FTAG and VNI are then used to select shaping queues when packets leave the fabric. Configuration registers may be used to map the FTAG to the SQ.

In one embodiment, an AGEQ may have multiple shaping queues addressed by { SQ, VC }. For example, if there are 8 SQs and 4 VCs, there may be 32 independent shaping queues in total. The corresponding 3-bit SQ index may be a shaping function, and the VC value maps to one of four queues (corresponding to 4 VCs) within the shaping function. For ethernet egress (edge) ports, no VC is needed to avoid deadlock, so all 32 shaping queues are available.

Congestion management

As described above, each flow on a given switch may have its own dedicated packet queue. This configuration facilitates separate flow control for each flow. Thus, the network can remain largely lossless and one flow using a link can be blocked without blocking any other flow using the same link. Unlike conventional packet-switched networks, congestion in a certain part of the network can only affect the flows that cause the congestion. For example, in a conventional network, the buffer before the congested link may soon be filled with packets that cause congestion. This in turn may force a switch to issue a pause command or use some other flow control method to prevent neighboring switches from sending packets to the congested link. Thus, packets that cause congestion may be stopped or slowed down, and all other packets that may not be destined for the congested link may also be stopped or slowed down. Thus, from a topological point of view, congestion may spread laterally and increase the size of the saturation tree.

In contrast, a flow path may reduce the load on the link causing congestion corresponding to the flow causing congestion. This load reduction may allow other flows sharing these links to use more link bandwidth and transmit their payloads faster, while only packets that cause congested links are slowed down.

In general, conventional networks can operate properly as long as the network load is not at or near full capacity. This is most often the case for small and medium size networks. However, for large or very large networks running multiple high bandwidth applications, a portion of the network may be saturated with traffic load at any point in time. In these cases, unfair packet delivery may occur even if the individual switches implement fairness policies locally.

Fig. 6A shows an example of an unfair share of link bandwidth that may occur in a network. In this example, each of sources a through K attempts to send a packet stream to destination L, forming an incast scenario where multiple sources send packets to a single destination. Source nodes A, B and C are coupled to switch 602; source nodes D, E and F are coupled to switch 604; source nodes G, H and I are coupled to switch 606; and the source node and J and K, and destination node L are coupled to switch 608. It is assumed that each switch employs a fair arbitration policy, i.e., an equal number of packets are selected from each of its input ports to any particular output port. However, as shown in fig. 6A, sources closer to the destination may obtain a higher proportion of the final link bandwidth than sources whose traffic needs to pass through more switching stages. Switch 608 has three incoming data sources from node J, K and switch 606, and may divide the bandwidth on the outgoing link to node L equally between each source. Thus, nodes J, K may each occupy 33.3% of the bandwidth on the outgoing link to destination node L.

The same may be true for the next closest switch (i.e., switch 606), and so on. In this example, there are only four levels of switches, there are only three or four inputs per level, and only a total of 11 inputs are intended to be sent to the destination node L, the bandwidth occupied by the three input sources (nodes A, B and C) on the outgoing link to the destination node L being only 1/48 for the two other input sources (nodes J and K). Thus, even with a locally fair arbitration policy, nodes far from the destination are subject to very unfair processing. A more realistic network topology may involve more switching stages, more switching inputs, and more sources attempting to transmit to a single destination. A medium-sized incast may result in six orders of magnitude difference between the transmission bandwidths of different sources.

The unfairness problem described above is often caused by the fact that: the arbitration policy implemented by the switch is based on the input port. That is, bandwidth limiting is done at a per-port granularity. In contrast, by facilitating flow channels and enforcing flow-specific restrictions, the network can significantly reduce the degree of unfairness between different flows. For example, in the scenario shown in fig. 6A, when the switch implements a per-flow fair bandwidth allocation policy, all eight source nodes may share the bandwidth of the edge link between the switch 608 and the destination node L substantially equally. The extreme tail-out delay of a single packet can also be greatly reduced by providing a more fair flow-based arbitration policy. For large system installations, the maximum latency in the control network is often a major concern for architects. Typically, this can only be achieved by limiting the incoming bandwidth into the network to a fraction of the peak bandwidth. For example, an input bandwidth limit of 20% of peak bandwidth may be typical for a large data center. By contrast, with flow channels and appropriate control mechanisms, it is now possible to build networks that do not impose such restrictions.

In addition to fairness, another challenge faced by network architects is congestion. In general, two types of congestion may occur in a network. The first type is endpoint congestion, where egress edge links coupled to a destination device are congested. The second type is fabric link congestion, i.e., intermediate fabric link congestion.

Fig. 6B shows an example of endpoint congestion. In this example, two source hosts 612 and 614 are sending data to a destination host 616. Traffic from source hosts 612 and 614 converges at edge switch 620 and the egress edge link 618 between switch 620 and host 616 may become congested. Such a congestion scenario typically occurs in incast, where multiple sources send traffic to a single destination. Congestion may occur when the egress edge link reaches its full data rate capacity, or when the destination host 616 is unable to process all incoming packets at a fast enough rate. In any event, when endpoint congestion occurs, the outgoing transport buffer on switch 620 coupled to link 618 may experience an increase in its amount of stored data.

The switch may detect and relieve endpoint congestion by monitoring the output buffers on the egress edge links and by sending ACKs with congestion information to upstream switches and source nodes. More specifically, an output buffer coupled to an egress edge link may monitor the status of the buffer and detect congestion when certain criteria are met. When a packet arrives or leaves the output buffer, the output buffer may calculate three congestion detection parameters, such as: (1) the amount of data stored in the buffer, (2) the number of packets stored in the buffer, and (3) the rate of change of the buffer depth (the amount of data stored in the buffer). Three thresholds may be set for the three monitoring parameters, respectively, but more or fewer thresholds may be set. When at least one of these parameters exceeds a corresponding threshold, congestion is considered to be present.

When congestion is detected, the switch may generate and transmit an endpoint congestion notification ACK corresponding to the packet that just entered the output buffer. The ACK may include a value indicating the severity of congestion. It should be noted that the endpoint congestion notification ACK is not intended to inform upstream switches of the successful delivery of packets, but rather the existence and extent of congestion on their egress edge links. (in fact, when the endpoint congestion notification ACK is sent, packets may still be stored in the output buffer waiting to be transmitted onto the egress edge link.) this fast, explicit congestion notification mechanism allows the switch to quickly take action on the particular flow that caused the congestion.

In addition, the output buffer may update the congestion detection parameters as packets are dequeued and transmitted to the egress edge link. If there is no congestion, a regular ACK is generated and sent, which may clear any previous congestion notifications received by the upstream switch operating on the corresponding flow. If there is congestion, the ACK may be tagged with a flag that allows the ACK to inform the switch of continued congestion on the egress edge link and successful delivery of the packet.

Fig. 7A illustrates a flow diagram of an exemplary process of generating an explicit endpoint congestion notification ACK. During operation, the system may continuously monitor the output buffer of the egress edge link. The system may then receive a packet at an output buffer (operation 702). Upon receiving the packets, the system may calculate the three congestion parameters (total amount of data, total number of packets, and rate of buffer depth change) for the output buffer (operation 704). The system may further determine whether any of these parameters exceed corresponding thresholds (operation 706). If at least one parameter exceeds a threshold, congestion is deemed to be present. Accordingly, the system may generate and send an explicit endpoint congestion notification ACK packet corresponding to the flow of packets to the upstream switch (operation 708). If congestion is not detected, the system may resume normal operation.

Fig. 7B illustrates an exemplary endpoint congestion management logic block. In this example, the endpoint congestion management logic block 730 may include an output buffer monitor 732, a congestion parameter calculation logic block 734, and an endpoint congestion notification ACK generation logic block 736. During operation, the output buffer monitor 732 may monitor the status of the output buffers associated with the egress edge links. Based on the status of the monitored output buffers, the congestion parameter calculation logic block 734 may calculate the three congestion parameters (see operation 704 in the flow chart in fig. 7A). When one of these parameters exceeds the corresponding threshold, the endpoint congestion notification ACK generation logic 736 may generate an endpoint congestion notification ACK and send the ACK to the upstream switch.

Fig. 8 shows a flow diagram of an exemplary process of generating an ACK in response to a packet being dequeued from an output buffer. In this example, the system first dequeues the packet from the output buffer (operation 802). The system may then calculate the three congestion parameters (total amount of data, total number of packets, and rate of buffer depth change) for the output buffer (operation 804). The system may determine whether any of these parameters exceed corresponding thresholds (operation 806). If at least one parameter exceeds a threshold, congestion is deemed to be present. Accordingly, the system may generate an ACK packet with a flag indicating persistent congestion (operation 808). If congestion is not detected, the system may generate a regular ACK packet (operation 809). The system may then send the ACK packet to the upstream switch (operation 810) and transmit the dequeued data packet onto the egress edge link (operation 812).

It should be noted that the endpoint congestion management logic shown in fig. 7B may also perform the operations described in the flowchart shown in fig. 8. In other words, the endpoint congestion management logic 730 may potentially generalize the endpoint congestion notification ACK when packets arrive at the output buffer and packets depart from the output buffer.

When an endpoint congestion notification ACK traverses the fabric, the IFCT of the switch on the path may apply a bandwidth limitation to the flow corresponding to the ACK. In fact, the fabric may slow the delivery speed of the flow in a distributed manner at each switch on the data path. When the endpoint congestion notification ACK passes the IFCT, its value may be stored in the table entry of the flow as an ep _ constraint value, which may be used to select the maximum bandwidth desired for the flow. Each value of ep _ containment may have a corresponding set of high water level value, target water level value, and discard water level value. For high levels of congestion, when ep _ congestion has a higher value, the water level value may have a lower value so that congestion may be more aggressively alleviated. For low levels of congestion, when ep _ containment has a lower value, a different set of larger high, target and drop water level values for higher streaming bandwidth may be used. For example, a table indexed by the ep _ constraint value may be used. For each ep _ containment value, the table may indicate a corresponding set of high, target, and discard water level values. The entries of the table may be predetermined such that when an endpoint congestion notification ACK is received, the switch may perform a lookup in the table using the ep _ congestion value and apply the three corresponding water level values to the identified flow.

In some cases, if the sources greedy inject data, simply slowing down the forwarding speed inside the network may not be enough to completely eliminate the congestion. To address this issue, the ingress edge switch may be configured to instruct the source device (which typically resides outside the fabric) to limit data injection in a fine-grained, flow-by-flow manner. This switch-to-host flow control mechanism may be referred to as fine-grained flow control (FGFC).

In particular, especially in an HPC environment, an end host or compute node may have a large number of cores running a large number of threads, processes, or virtual machines, where each core may inject its own data stream into the network through a common physical Network Interface Controller (NIC). When congestion is present, port-by-port based flow control can only limit the overall data rate of a single port on the NIC, which can be 40Gb/s or higher. Extrapolating back the total data rate across the entire port may result in unfairness to the flows that do not cause congestion. FGFC can extend the concept of individual flows or associated flow packets to their ultimate source, which can be a single thread executing on one of the cores.

To slow down the injection of data from the source, the FGFC logic block on the ingress edge switch (e.g., FGFC logic block 434 in edge switch 406 in fig. 4A) may use a pause-credit mixing approach to restrict incoming data associated with a particular flow or flow packet. Pause-based methods typically involve the receiving end issuing a pause command to the transmitter end, in response to which the transmitter end may stop transmission until further notice. For a credit-based approach, the receiving end may send transmission credits to the transmitting end, which allows the transmitter to send more data, but at most only the amount specified by the credit value. This mechanism allows the receiving end to more accurately control its input buffer depth to avoid overflow while allowing transmission to continue. FGFC may use a hybrid approach, where upon detecting congestion, the ingress edge switch may issue FGFC packets with set timer values for one or more flows to an end host NIC (e.g., NIC 401 on end host 402 in fig. 4A). After receiving the FGFC packet, the ingress edge switch may turn on a credit-based flow control mode. In response, the NIC may limit the transmission data rate of the corresponding stream(s) based on the received credits, while allowing other streams to transmit at normal data rates. After the expiration of the predetermined timer, the end host NIC may resume normal transmission of the restricted stream(s) unless another pause command is received. It should be noted that the restricted flow may be identified by any field derived from the packet. The restricted flow may be specific to a single process or thread executing on the end host.

FGFC can implement control communications between the edge switch and the end host NIC using ethernet frames with an Organization Unique Identifier (OUI) extended ethertype field. The frames may indicate one or more of: (1) the protocol used by the controlled flow; (2) an identifier indicating a source (e.g., an application, process, or thread) that generates a packet that needs to be restricted; (3) a pause time value for which flow control is to continue (which may prevent locking if a subsequent FGFC frame is lost due to an error), and (4) a credit value, which may be zero, indicating the number of frames or amount of data that may be sent during the pause.

It should be noted that the identifier used to indicate the source stream subject to flow control may differ based on the protocol associated with the stream. For layer 2 ethernet Virtual Local Area Network (VLAN) traffic, the identifier may include a VLAN number. For IPv4 traffic, the identifier may include a source/destination IP address pair, a UDP or TCP/IP5 tuple containing a UDP or TCP port number, or an optional flow label. For IPv6 traffic, the identifier may include one or more IPv6 addresses or IPv6 flow tags. For proprietary HPC protocol traffic, the identifier may comprise a process or thread ID. Typically, this identifier is also stored in the EFCT of the edge switch, as it is used to map the corresponding traffic to the flow ID.

To trigger FGFC, the IFCT of the ingress edge switch may monitor its flow-specific input queues. For each queue, the corresponding IFCT entry may indicate three water level values: high, target, and discard, which may be used to measure queue depth. In some examples, these water level values may be included as additional fields in the IFCT as shown in fig. 4C, or may be stored in a separate table and linked by fields in the IFCT. When the queue depth is less than the target value, FGFC is not required. When the queue depth reaches the target water level value, the IFCT may communicate with the FGFC logic block to initiate FGFC with the NIC of the end host. When the queue depth falls below the drop water level value, the FGFC may be stopped and normal transmission of the stream resumed.

Fig. 9A shows a flow chart of an exemplary FGFC process. During operation, at the ingress edge switch, the system may monitor the flow-specific input queues (operation 902). The system may further determine whether the FGFC is currently on for the corresponding flow (operation 904). If FGFC is currently turned on for the flow, the system may determine whether the queue depth is below the drop water level (operation 906). If the queue depth has not dropped below the drop level, the system may continue credit-based transmission in FGFC mode (operation 912). If the queue depth has decreased below the drop water level, the system may revert to normal transmission of the stream (operation 914). Returning to operation 904, if the FGFC is not currently on, the system may determine whether the queue depth is greater than the target water level (operation 908). If so, the system may initiate FGFC for the stream (operation 910). The FGFC logic block in the edge switch may obtain flow identification information (e.g., VLAN tag, TCP/IP 5-tuple, thread ID, etc.) from the EFCT entry corresponding to the flow and send the FGFC ethernet frame to the NIC on the end host. Subsequently, the system may continue to monitor the input queue (operation 902). If the queue depth is not greater than the target level, the system may continue with regular data transfer (operation 914).

To facilitate FGFC, the NIC may be configured to process FGFC ethernet frames so that the NIC may communicate with an application or process on the end host that is generating data. The parsing of the FGFC ethernet frames and the communication with the application or process may be done in software, hardware, or a combination of both. Fig. 9B shows an example of a FGFC-enabled NIC. In this example, the NIC 930 may include a processor 932, a memory 934, a transmitter 936, a receiver 938, an FGFC logic block 940, and a communications logic block 942. During operation, the transmitter 936 and the receiver 938 may perform communication with the edge switch via the edge link. The communication logic 942 may communicate with a central processing unit of an end host where the NIC 930 is located via a data bus, such as a peripheral component interconnect express (PCIe) bus. Processor 932 and memory 934 internal to NIC 930 may perform local processing of data. During operation, FGFC logic block 940 may work with edge switches to apply FGFC in a flow-by-flow manner. Additionally, the FGFC logic block 940 may communicate with the central processing unit of the end host via the communication logic block 942 to limit data injection by a single application or process corresponding to a particular flow subject to FGFC, thereby controlling the amount of data injected into the fabric.

As described above, two types of congestion may occur in the network. The first type is end point congestion and the second type is fabric link congestion. Fig. 10 shows an example of fabric link congestion. In this example, two intermediate switches 1002 and 1006 communicate via fabric link 1004. Multiple source/destination pairs may send traffic via fabric link 1004. Thus, fabric link 1004 may experience congestion, but links to and from fabric link 1004 may not be congested. When such congestion occurs, the fabric link 1004 may appear to be a "hot spot".

To alleviate fabric link congestion, the switch may apply dynamic flow control based on flow-by-flow credits. At the switch, if the input queue begins to fill up and the queue _ extend value for the flow reaches a predetermined threshold, the switch may generate a special ACK to notify the IFCT of the upstream switch of the congestion. This special hop-by-hop ACK may be referred to as a "headroom ACK". Upon receipt of the Headroom ACK, the IFCT of the upstream switch may initiate credit-based flow control with the downstream switch. In the downstream IFCT entry, a flag Upstream Metering (UM) may be set to indicate that data transmissions from the upstream switch are now metered on a credit basis. The Headroom ACK packet may also include a credit value.

When the upstream switch receives the Headroom ACK, a flag called Downstream Metering (DM) may be set in the corresponding entry of the IFCT. The IFCT may also store a headroom field (headroom field) for the symbol in the IFCT entry with a credit value carried by the headroom ack (i.e., the headroom value indicates the number of credits). The headroom field may represent the amount of data that may be forwarded to the downstream switch. This establishes credit-based flow control for the corresponding flow. If the Headroom ACK is received if the DM flag in the flow entry has been set, the credit value carried by the Headroom ACK may be added to the existing headroom value.

If the headroom value is not greater than zero (i.e., no credit available), new packets received by the upstream IFCT may be blocked. These packets may fill the input queue for the flow and may in turn cause the IFCT to initiate flow control on its upstream IFCT on a flow credit-by-flow basis, and so on. If the headroom value is greater than zero, the packets stored in the input queues may be dequeued and forwarded to the downstream switch, and the headroom value may be decremented by the size of the forwarded packets, which may cause the headroom value to become zero or negative.

Since the flow is restricted from sending new packets to the downstream IFCT, the input queue of the downstream IFCT may begin to be consumed at some rate, depending on its downstream congestion. As described above, the input queue for each flow may have three queue depth water level values, i.e., high, target, and drop, which may be used to manage credit-based flow control. The target water level may be approximated to the ideal queue depth for the desired stream bandwidth. Which means that there is sufficient buffering available to transmit data downstream. When congestion occurs, the credit-based flow control mechanism may attempt to keep the queue _ extend value of the flow near the target water level.

If the queue _ extend value is between the high and drop levels and greater than the target level, then a credit slightly smaller than the packet size may be returned to the upstream switch along with the Headroom ACK when forwarding the packet. If the value of queue _ extend does not exceed the target level, a credit slightly larger than the packet size may be returned to the upstream switch along with the Headroom ACK when forwarding the packet.

If the queue _ extend depth is greater than the high water level, no credit is returned when forwarding the packet. This mechanism can lower the queue _ extend value more quickly and is typically used when congestion is first detected. The input queue for a flow may become empty more quickly if the congestion clears. Credit-based flow control may be turned off when the queue depth is less than the drop water level. This may be done by clearing the UM flag in the IFCT entry and returning the headroom ack with the largest credit value to the upstream switch. When received by the upstream IFCT, the Headroom ACK will clear the DM flag of the entry and turn off flow control for the headroom value.

It should be noted that in a typical network topology, there may be multiple switches and multiple data paths between two endpoints. In a multi-path network, various methods may be used to control fabric link congestion. For example, injection limits described later in this document may control the maximum amount of data in the overall structure. This means that if a particular fabric link is overloaded, the flow may use a different data path that does not pass through the congested link. An overloaded link may be detected and a "reroute" ACK generated for a group of flows. Rerouting ACKs may temporarily block a flow in an upstream switch, and when all ACKs for that flow are returned, the flow may be unblocked and may be free to use a different path on the fabric. The load-based dynamic adaptive routing mechanism may then direct the leading packet to use a different non-congested fabric link. Furthermore, the load on the entire structure may become more balanced.

Fig. 11 shows a flow diagram of an example process for applying credit-based flow control over a congestion fabric link. During operation, the switch system may monitor its flow-specific input queues (operation 1102). The system may determine whether an entry in its IFCT has the UM flag set (operation 1104). If the UM flag is set, which means that credit-based flow control is on, the system may further determine whether the queue _ extend value is less than the discard water level value (operation 1106). If the queue _ extend value is less than the discard water level value, the system may clear the UM flag, turn off credit-based flow control, and resume normal data transfer (operation 1014). If the queue _ extend value is greater than the discard water level value, the system may continue credit-based flow control (operation 1106). Returning to operation 1104, if the UM flag is not set, which means that the system is in a normal transmission mode, the system may determine whether the queue _ extend value is greater than the target water level value (operation 1108). If so, the system may initiate credit-based flow control and send a Headroom ACK to the upstream switch (operation 1110). If the queue _ extent value is not greater than the target water level value, the system may continue with the normal data transfer (operation 1112).

In general, a flow path switch may use a combination of several congestion detection and control mechanisms. For example, different degrees of endpoint congestion may be reported using endpoint congestion notification ACKs that may be returned from the final fabric egress edge ports. The ACK type may be used to manage the bandwidth of flows flowing into heavily congested egress edge ports. The system may also manage fabric link congestion using hop-by-hop credit based flow control. Such hop-by-hop congestion management mechanisms may effectively cope with low to moderate levels of congestion, as the response time may be much shorter than the network-level round trip delay.

The system may also apply per-flow injection limits if congestion is severe, which may be caused by a large range of incasts. The injection limit for the flow may be determined based on the ep _ constraint value. The injection limit may be compared to the flow _ extend value in all IFCTs traversed by the flow. If flow _ extend is greater than the limit, then IFCT may block packets for the flow from being forwarded from the input queue. This mechanism can reduce the packet forwarding rate over the entire flow to as few as a single packet.

The system can also protect irrelevant traffic from extreme congestion due to incasts of a large number of contributors. In this case, the ep _ containment value may be set to a higher value, and the average data amount of the stream may be reduced to a small portion of the packet. This can be achieved by releasing the next packet of a single flow into the fabric from the IFCT of the ingress edge port only after a programmable delay since the ACK of the previous packet was received.

In addition to the flow-by-flow injection limits, the system may also measure the amount of data injected into the fabric on a flow-by-flow port basis, and set the injection limits to impose an upper limit on the total amount of data that a port can inject into the fabric. Since each ingress port can apply the injection limit, the system can control the maximum amount of data allowed within the fabric. Limiting the amount of data entering the structure ensures that no buffer depletion occurs in the event of bandwidth scarcity. Thus, traffic that does not use the reduced bandwidth path is not affected.

To facilitate port-by-port injection limiting, the IFCT may maintain a total flow count. The total count is incremented each time a packet is injected into the fabric from an edge port. When an ACK is returned for a flow, the total flow count may be decremented. Once all ACKs for all flows for the ingress port are returned (i.e., when the sum of the flow _ extend values for all flows becomes zero), the total traffic count may be set to zero.

Ingress fairness

In some embodiments, the INQ block may include a set of application packet (APPG) queues, a set of stream pipe queues (FCQ), and a set of Request Queues (RQ). The APPG queue may be used to provide fairness between applications at the ingress port. On fabric ports, normal traffic is assigned a default value (e.g., APPG ═ 0) so that arbitration can occur between the flow channels by polling.

The flow channel queue may ensure that frames from each flow are transmitted in order without blocking any other flow. The request queue can ensure that frames destined for a particular output/SQ/VC are delivered in order without blocking other frames.

When a new header arrives at the INQ block of an ingress edge port, its application packet (APPG) may be provided over the EFCT interface. If the EFCT does not provide APPG, APPG may be set to a default value, such as 0. This may be the case for normal traffic arriving on a fabric link. The APPG queue is intended to provide fairness between applications on edge ports, particularly when one or more applications use few flow channels while another uses many flow channels. If the FC of the new header is not enqueued on its APPG queue as indicated by the FC _ queued mask, it will be enqueued there. Each APPG may map to an injection limit id (ilid). In one embodiment, the predetermined APPG value (e.g., 127, where there may be 128 APPGs total) may be an application specific grouping assigned to an ILID that is not subject to injection limitations (e.g., an ILID value of 8, where there may be 8 ILIDs total). Each other ILID is subject to injection limitations managed by the IFCT. The ifct _ inq. injection _ ok value provides an ILID mask that can be dequeued. Hierarchical arbitration allows frame fairness among ILIDs. The 8:1 polling arbiter may select the ILID. Within each ILID, the 128:1 polling arbiter may select from those APPGs that have that ILID. Each ILID maintains its own priority pointer. If the IFCT determines that the dequeue request will exceed the injection limit, it may assert the abort il flag. In this case, not only is the dequeue process aborted, but the priority pointer for the ILID is also reset to the aborted APPG.

On the fabric link, normal traffic arrives with use _ effect ═ 0, and these headers are put into APPG 0. Sniffing, SFLOW, and some loopback traffic may arrive at the fabric link with use _ effect ═ 1. Like the edge links, the fabric links are subject to injection constraints, but the IFCT together with the appropriate APPG to ILID mapping ensures that the injection _ ok flag of APPG 0 remains set.

Once an APPG is selected, the FC at the head of the APPG queue will be sent to the FC queue for dequeuing. The FC dequeues from the APPG queue waits until the FC dequeues are complete before the FC eventually completes. If FC dequeue is aborted due to a violation of an injection limit, the FC's APPG dequeue may be cancelled; in this case, the suspended FC remains at the head of the APPQ queue. If dequeuing from the APPG queue is successful or aborted due to violating the flow restrictions, the FC dequeuing from the APPG is complete; in these cases, the FC will re-enqueue to the back of the APPG queue as long as the FC queue is not empty. In addition to FC, each APPG queue entry contains a bit (wa _ abort) indicating whether FC dequeuing was aborted due to violating the flow constraint (abort _ FC _ queue). If the bit is set, after selecting the FC for another dequeue attempt, although it is in the FC dequeue pipeline, it is speculatively retried with a lower priority.

When the FC enqueues on the APPG queue, the corresponding bit of the FC _ queued mask is set. When the dequeue of the APPG queue is complete, if FC is not re-enqueued, the corresponding bit FC _ queued is cleared.

In this way, the system may have three levels of arbitration. First, the system selects the ILID. The system then selects the APPG and finally selects the FC from the APPG.

No flow frame: a special value of APPG, e.g., 127, may be reserved for "no-flow" frames. These frames with flow _ id ═ 0 do not belong to a flow and are not injection limited. For injected traffic on edge and fabric links (use _ effect ═ 1), EFCT may be configured such that "no flow" frames are assigned to APPG 127. In addition to assigning this APPG to ILID 8, the INQ need not treat it differently from other APPGs. In one embodiment, only three bits of the ILID are present on the ifct _ inq interface, so for these headers the value of fc _ dq _ ILID is 0. It should be noted that normal traffic on a fabric link (use _ effect ═ 0) can always be assigned to APPG 0. This applies to "no-flow" frames, since IFCT ensures that the ILID corresponding to APPG 0 is not injection-limited.

Speculative retry selection: since the FC dequeue pipeline may be long (e.g., 21 cycles), and the FC may only appear once in its APPG queue, while its dequeue from the APPG queue may not end up until the FC dequeue pipeline ends, few flow channels are active at this time, and generally nothing may be dequeued from the APPG queue. In this case, the system may select the FC in the FC dequeue pipeline to retry. If FCQ in the pipeline is not currently empty, the flow channel in the pipeline is eligible for retries. If the last dequeue attempt of a flow channel is aborted due to a flow restriction, its priority is lower than other flow channels. From the prioritized set of eligible flow channels, the least recently selected flow channel is selected for retry.

Unlike the flow path and request queues, sometimes the system may enqueue two flow paths (FCs) in the APPG queue — one from the new header and one from the end of the FC dequeue pipeline. If the linked list supports only a single enqueue, the system may maintain an enqueue cache, which in one embodiment may have 32 entries. New headers whose FCs are not in the APPG queue may be enqueued first. The FC in the enqueue buffer may have a second priority and enqueue when the FC of the new header does not need to be enqueued. The FC from the end of the FC dequeue pipeline may have the lowest priority and write it to the enqueue cache if it cannot be enqueued immediately. To initiate the FC dequeue operation, the system may use the credits in the enqueue cache. The credit is returned if the system does not require enqueuing at the end of the pipe (abort il, or successful dequeue but FCQ empty) or when an entry in the cache is enqueued on the APPG queue. If many FCs are active and backed up due to flow restrictions (abort _ FC _ queue), the system may halt the FC dequeue pipeline for a period of time. However, this can only be created when the APPG queue fills the FC. Once all active FCs are in the APPG, the new header does not create an enqueue request.

In one embodiment, there may be 8 injection limits, and these limits are identified by a 3-bit ILID. The ILID is created from a mapping in the INQ block indexed from the 7-bit APPG value. The ILID is passed with the header and is used to select the rejected _ data value for each ILID, which is the sum of all the rejected _ data values of the stream and the rejection _ limit _ id that matches the ILID. Each ILID has a unicast injected _ data value and a multicast mcast _ injected _ data value. Each ILID may also have a unicast limit and another limit for multicast. These limits are compared to the corresponding imported _ data _ sum values. The abort _ il signal may be asserted with abort _ fq _ request if the imported _ data value exceeds the limit when the header is processed. When abort il is asserted, the state of the INQ arbiter may return to its value prior to the dequeue of the header so that it is the next frame appearing in the IFCT of the ILID.

These eight injection _ ok [7:0] signals (one for each ILID) may only be asserted if the corresponding limit is greater than or equal to the injected _ data values for both unicast and multicast. The INQ uses these signals to decide which APPG queues should actively dequeue frames from FCQ. In one embodiment, the injection _ ok [0] may be set to "T" (true) even when the unicast or multicast injected _ data value exceeds its injection limit. The IFCT may still use the abort il signal to abort the header and thus the header will not be forwarded, but the INQ block will not stop trying to dequeue the header belonging to ILID-0. This can accommodate lossy ethernet frames and packets because IFCT will discard the header if the FQ depth or PCP depth reaches the water level, which makes it necessary to do so. It will perform this conditional discard function only if the INQ dequeues headers that it may need to discard. IFCT does not discard lossless traffic. By preventing unnecessary dequeues of headers that may be aborted by the abort il signal, the system may free up pipelines for other ILIDs that are still below their injection limit.

These eight multicast restrictions may be in RTFIFCTCFGMCASTINTINJENTIONLIMIT

- - - - __. When the ILID exceeds the value of mcast _ injection _ limit, it can block mcast _ injected _ data.

In some embodiments, the system may provide more sophisticated injection control for unicast traffic. As with multicast, each unicast ILID may have its own injected data value. They may function in units of, for example, 24 bytes to match the injected data values from stream to stream. The limits to which they are compared may be dynamic, depending on which ILIDs are active. This allows limiting the maximum data contribution of a single node to the overall structure, but also allows a single application running on that node to be able to get a larger share of the data limit when running independently or the only application using the structure.

There may be a NODE _ LIMIT value that is an absolute LIMIT of all unicast data from the fabric entry edge. The sum of the active ILID LIMITs may be equal to the NODE _ LIMIT value. There may also be a set of RATIO registers, one for each ILID. One of which may be set to a maximum value. Other registers may be set proportionally against the maximum ILID to its expected injection data compared to the maximum value. These RATIO registers can then be compared to each other. At any given point in time, only some of the ILIDs are active (active ILIDs have non-zero injected _ data values). A set of injection LIMITs may be generated by logic for only the active ILID, which add up to the NODE _ LIMIT. Non-active injection limits may be excluded from the sum. The values of these active injection limits will have the same relative RATIOs as defined by their RATIO CSR.

Each ILID also has an absolute limit that can be used on high priority data to protect low priority data. It can also be used for scavenger traffic classification, again to protect other classifications. Each ILID will be limited by the lower of the absolute LIMIT and the dynamic LIMIT generated by the RATIO and NODE LIMIT CSR.

If a flow exceeds its injection limit, frames may still be dropped if necessary for any drop condition. If the frame is dropped, the over _ injection _ lim signal should be ignored.

FORCE _ INJECTION _ OK _0 has been added to the register of IFCT to prevent blocking frames dequeued from FCQ with ILID-0. This may typically be set in the IFCT registers of the fabric links to disable any injection limit control for any frame that has been checked against the IFCT injection limits of its ingress edge link.

As previously described, APPG queue allocation may be performed in EFCT. When multiple applications share a node and their use of stream queues is very different, an APPG queue may be provided to improve fairness of access to the fabric. From the 7-bit index, 128 APPG queues may be selected. This may be generated using FTAG. Each FTAG may be configured to access multiple APPG queues. The 7-bit APPG index may be generated by adding the APPG _ BASE component of the FTAG to another index obtained from the vni _ ext input. For portal frames, this may be a 16-bit VNI value. For an L2 bridge frame, this may be a 12-bit VLAN value; and for IPv4 and IPv6 this may be a flow label. CRC hash values may be used against FTAG for L2, IPV4, and IPV6 packets from L2_ VLAN _ USE _ CRC, IPV4_ USE _ CRC, and FLOW _ idle _ USE _ CRC settings, respectively.

The APPG _ INDEX _ SIZE value may be used to decide how many lower bits to add to APPG _ BASE. The APPG queues of different FTAGs can be prevented by software from overlapping each other, but this is not prohibited and may provide a more fair arbitration between FCs depending on the application.

In one embodiment, the APPG queue index 127 may be reserved for "no _ flow" frames. These are frames using FTAG with DISABLE _ FLOW _ CHANNELS set in the R _ TF _ OFCT _ CFG _ FTAG [16] register. If the frame is dropped due to the DISCARD _ FTAG set or the HIGH _ RATE _ PUT set in the R _ TF _ OFCT _ CFG _ FTAG [16] register and a non-portal frame arrives, the APPG is also forced to 127 and a no _ flow _ id is generated.

If the newly computed APPG queue index happens to be 127, but the flow _ id is not no _ flow, then the APPG queue index may be forced 126. This is done to ensure that the APPG queue 127 can exclusively contain a no _ flow _ id header.

A single Flow Queue (FQ) should not typically be assigned to more than one APPG queue. However, reconfiguration of the control registers may result in the match logic directing a single flow to more than one APPG queue. To prevent this from happening, the following procedure may be used when making changes to the switch that is actively receiving frames from the link. The procedure for changing the APPG configuration for a particular FTAG is as follows.

DISCARD _ FTA is set in R _ TF _ OFCT _ CFG _ FTAG [16] to mark all frames arriving at the changed FTAG as dropped while they are marked as no _ flow frames. Any new frame that arrives will not allocate or match a flow and will be marked as dropped and therefore will not be forwarded in the IFCT. Its header FTAG value is not changed.

Next, the system may use the "Table _ Test" function in OFCT to wait for all old FTAG values to disappear from the flow Table. This may take some time to shut down all old flows.

The system may then change the APPG _ BASE or APPG _ INDEX _ SIZE of the FTAG to the new value.

Finally, the DISCARD _ FTAG is cleared when all control registers are updated.

Fig. 12A illustrates an exemplary input queue logic block that facilitates ingress fairness. In this example, an input queue (INQ) logic block 1206 may be coupled to an EFCT logic block 1202 and an IFCT logic block 1204 (see, e.g., the architecture in FIG. 5A). When EFCT logic block 1202 receives a packet, it may map the packet to a flow channel and map the flow channel to an APPG. The header of the packet may then be enqueued in the INQ logic block 1206. In one embodiment, the queuing and arbitration in the INQ logic block 1206 are arranged as a three-level hierarchy. As shown in this example, packets belonging to a flow channel are buffered in a flow-by-flow queue 1203. Flows of the same APPG are grouped together under the APPG, which belongs to a group of APPGs 1205. Since each APPG maps to an ILID, the highest and first level of the hierarchy is ILID 1207. When performing arbitration, the IFCT logic 1204 may perform a first level of scheduling among all the ILIDs 1207 (8 ILIDs in this example). Servicing of each ILID may be done in a manner that conforms to the injection limits corresponding to each ILID. In one embodiment, the system may perform round-robin scheduling among all ILIDs 1207. Next, within each ILID, the system may perform a second level of scheduling between APPGs 1205 (128 APPGs in this example) that are subject to injection limits corresponding to that ILID. The system may then perform a third level of scheduling between all the flow channels queued in a single APPG. This three-level hierarchical arbitration process can ensure ingress fairness between applications and processes that generate the stream. Once the header of the packet is dequeued, the system may generate a corresponding request that forwards the data payload of the packet to the output buffer, and the request is sent to a request queue 1208, where the request may be granted.

Fig. 12B illustrates a flow diagram of an exemplary enqueue-dequeue process that enforces entry fairness. During operation, the system receives a packet at the EFCT (operation 1220). The EFCT may then determine the flow channel and APPG of the packet (operation 1222). In one embodiment, the APPG may be determined by the FTAG and VNI associated with the flow channel. The system may further map the APPG to an ILID that points to a set of injection limits that apply to the APPG (operation 1224). Next, the system may enqueue the header of the packet in the corresponding flow channel queue (operation 1226). The system may then perform three levels of hierarchical arbitration, starting with the ILID, to the APPG and then to the stream pipe, and dequeue the header and buffered packets (operation 1228). The system may then forward the packet to the crossbar switch (operation 1230).

Fig. 12 illustrates an example edge switching system that facilitates flow paths (which may correspond to switch 406 in fig. 4A, for example). In this example, switch 1202 may include a plurality of communication ports, such as port 1220. Each port may include a transmitter and a receiver. Switch 1202 may also include processor 1204, storage 1206, and stream channel switching logic 1208. The stream lane switch module 1208 may be coupled to all communication ports and may further include a crossbar switch 1210, an EFCT logic block 1212, an IFCT logic block 1214, and an OFCT logic block 1216.

Crossbar switch 1210 may include one or more crossbar switch chips that may be configured to forward data packets and control packets (e.g., ACK packets) between communication ports. EFCT logic block 1212 may process packets received from the edge link and map the received packets to corresponding flows based on one or more header fields in the packets. Additionally, the EFCT logic block 1212 may assemble FGFC ethernet frames that may be transmitted to the end host to control the amount of data injected by the various processes or threads. IFCT logic 1214 may include IFCTs and perform various flow control methods in response to control packets, such as end point congestion notification ACKs and structural link credit based flow control ACKs. The OFCT logic 1216 may comprise a memory unit that stores OFCTs, and communicates with the IFCT logic of another switch to update the flow ID of the packet as it is forwarded to the next hop switch.

Fig. 13 illustrates an example intermediate switch system that facilitates flow channels (which may correspond to switches 408 and 430 in fig. 4A, for example). In this example, switch 1302 may include a plurality of communication ports, such as port 1320. Each port may include a transmitter and a receiver. Switch 1302 may also include a processor 1304, a storage device 1306, and stream channel switching logic 1308. The flow channel switch module 1308 may be coupled to all communication ports and may further include a crossbar switch 1310, an EFCT logic block 1312, an IFCT logic block 1314, and an OFCT logic block 1316.

Crossbar switch 1310 may include one or more crossbar switch chips that may be configured to forward data packets and control packets (e.g., ACK packets) between communication ports. EFCT logic block 1312 may process packets received from the edge links and map the received packets to corresponding flows based on one or more header fields in the packets. Additionally, the EFCT logic block 1312 may assemble FGFC ethernet frames that may be transmitted to the end host to control the amount of data injected by the various processes or threads. The IFCT logic 1314 may include IFCT and perform various flow control methods in response to control packets (e.g., endpoint congestion notification ACKs and structural link credit based flow control ACKs). The OFCT logic 1316 may include a memory unit that stores OFCTs and communicates with the IFCT logic of another switch to update the flow ID of the packet as it is forwarded to the next hop switch.

In summary, the present disclosure describes a data-driven intelligent networking system that can adapt to dynamic traffic through fast, efficient congestion control. The system may maintain state information for individual packet flows, which may be dynamically established or released based on injected data. The packet stream may be mapped to its layer 2, layer 3, or other protocol specific header information. Upon arrival at the switch, a flow-specific input queue may be provided for each flow. Packets of the corresponding stream are acknowledged upon reaching an egress point of the network, and the acknowledged packets are sent back along the same data path to the ingress point of the backward stream. Thus, each switch can obtain state information of each flow and perform flow control in a flow-by-flow manner. Such flow control allows better utilization of the network while providing versatile traffic engineering and congestion control capabilities.

The methods and processes described above may be performed by hardware logic blocks, modules, or devices. A hardware logic block, module or apparatus may include, but is not limited to, an Application Specific Integrated Circuit (ASIC) chip, a Field Programmable Gate Array (FPGA), a dedicated or shared processor that executes code at a particular time, and other programmable logic devices now known or later developed. When activated, the hardware logic blocks, modules, or devices perform the methods and processes included therein.

The methods and processes described herein may also be embodied as code or data, which may be stored in a storage device or computer-readable storage medium. The methods and processes may be performed by a processor when the stored code or data is read and executed by the processor.

The foregoing descriptions of embodiments of the present invention have been presented only for purposes of illustration and description. The description is not intended to be exhaustive or to limit the invention to the precise form disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the invention is defined by the appended claims.

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