Communication method and device

文档序号：212352 发布日期：2021-11-05 浏览：9次中文

阅读说明：本技术 一种通信方法及装置 (Communication method and device ) 是由黄科超马会肖梁伟光于 2020-05-04 设计创作，主要内容包括：本申请提供了一种通信方法及装置,所述方法包括：对待传输的第一比特序列进行编码,得到第一矩阵,第一矩阵包含多个尺寸相同的比特方阵,各个比特方阵包含多个比特数据；然后按照第一映射关系,对第一矩阵中的各个比特方阵的比特数据,均进行在各自比特方阵范围内的位置变换,得到位置变化后的第二矩阵；进而对第二矩阵进行比特数据在各个比特方阵之间的位置变换,得到第三矩阵,根据第三矩阵调制待发送的第一符号序列。第一映射关系中的行变换映射关系指示比特数据在比特方阵范围内位置变换前后的行标识映射关系。行变换映射关系可以通过全局偏移约束因子、至少两个局部偏移约束因子进行约束。可以提高信息传输的抗突发能力。(The application provides a communication method and a communication device, wherein the method comprises the following steps: coding a first bit sequence to be transmitted to obtain a first matrix, wherein the first matrix comprises a plurality of bit square matrixes with the same size, and each bit square matrix comprises a plurality of bit data; then according to the first mapping relation, the bit data of each bit square matrix in the first matrix is subjected to position transformation within the range of each bit square matrix to obtain a second matrix after the position transformation; and then carrying out position conversion of bit data among the bit square matrixes on the second matrix to obtain a third matrix, and modulating a first symbol sequence to be transmitted according to the third matrix. The row transformation mapping relation in the first mapping relation indicates a row identification mapping relation before and after the position of the bit data is transformed in the range of the bit square matrix. The row transformation mapping relation may be constrained by a global offset constraint factor, at least two local offset constraint factors. The burst resistance of information transmission can be improved.)

1. A method of communication, comprising:

coding a first bit sequence to be transmitted to obtain a first matrix, wherein the first matrix comprises a plurality of bit square matrixes with the same size, and each bit square matrix comprises a plurality of bit data;

according to a first mapping relation, performing position transformation on bit data of each bit square matrix in the first matrix within the range of the respective bit square matrix to obtain a second matrix, wherein the first mapping relation is used for indicating the position mapping relation of each bit data before and after the position transformation within the range of the bit square matrix, the first mapping relation comprises a row transformation mapping relation, the row transformation mapping relation is constrained by a global offset constraint factor and at least two local offset constraint factors, the global offset constraint factor is used for constraining the position offset of each bit data row transformation in the bit square matrix, and the local offset constraint factor is used for constraining the position offset of bit data rows transformation in a part of bit rows in the bit square matrix;

performing position transformation of bit data among the bit square matrixes on the second matrix to obtain a third matrix;

and modulating a first symbol sequence to be transmitted according to the third matrix.

2. The method of claim 1, wherein the row transformation mapping relationship is further constrained by a start offset parameter for constraining a start position of the bit data in the bit matrix for position transformation by a position offset amount.

3. The method according to claim 2, wherein said local offset constraint factor comprises m-1, where m is an integer greater than 3, in the case where said first matrix comprises a square matrix of bits having a number of rows and columns of 2 Λ m;

the global offset constraint factor, the local offset constraint factor, and the start offset parameter constrain the row transformation mapping relationship by the following equation:

wherein r is₀Identifying a corresponding row of first bit data in the bit square matrix before position conversion in the bit square matrix range, wherein the first bit data is any bit data in the bit square matrix, and r₁For the corresponding row identification after the position transformation of the first bit data within the bit matrix, c₁Corresponding column identification after the position of the first bit data is transformed in the range of the bit square matrix, g is the global offset constraint factor, beta is the local offset constraint factor, and alpha isAnd g, beta and alpha of the initial offset parameter are preset integers, k is an index mark of beta, the value of g is determined according to 2 Λ p, and p is an integer greater than 1.

4. A method according to claim 3, characterized in that in case of m-4, g { -8, -4,4}, β ∈ { -8, -4,4}, β {₂∈{-7,-5,-3,-1,1,3,5,7}；

Wherein, in the case of g ═ 8, β₀And beta₁Is taken from one of the following combinations: { beta ]₀＝-6、β₁＝-8}、{β₀＝-6、β₁＝0}、{β₀＝-4、β₁＝-6}、{β₀＝-4、β₁＝-2}、{β₀＝-4、β₁＝2}、{β₀＝-4、β₁＝6}、{β₀＝-2、β₁＝-8}、{β₀＝-2、β₁＝0}、{β₀＝2、β₁＝-8}、{β₀＝2、β₁＝0}、{β₀＝4、β₁＝-6}、{β₀＝4、β₁＝-2}、{β₀＝4、β₁＝2}、{β₀＝4、β₁＝6}、{β₀＝6、β₁＝-8}、{β₀＝6、β₁＝0}；

In the case of g-4 or g-4, β₀And beta₁Is taken from one of the following combinations: { beta ]₀＝-6、β₁＝4}、{β₀＝-2、β₁＝-4}、{β₀＝0、β₁＝-6}、{β₀＝0、β₁＝-2}、{β₀＝0、β₁＝2}、{β₀＝0、β₁＝6}、{β₀＝2、β₁＝4}、{β₀＝6、β₁＝-4}。

5. The method of claim 3 or 4, wherein the first mapping further comprises a column transformation mapping, the column transformation mapping constrained by the following formula:

wherein, c₀Column identification corresponding to the first bit data before position conversion in the bit square matrix range, r1 row identification corresponding to the first bit data after position conversion in the bit square matrix range, c₁And h, gamma and theta are preset integers and w is an index mark of gamma, which are corresponding to the first bit data after the position of the first bit data is changed in the range of the bit square matrix.

6. The method of claim 5, wherein in the case that m has a value of 4, g has a value of-4, β₀Is 0, beta₁Has a value of-2, beta₂Is 3, alpha is 0, h is-2, gamma₀Is 0, gamma₁Is taken as 7, gamma₂Is-7 and theta is 0.

7. The method of claim 6, wherein the first mapping relationship is indicated by a first mapping table, and wherein the first mapping table is:

(0,0) (1,1) (2,2) (3,3) (4,4) (5,5) (6,6) (7,7) (8,8) (9,9) (10,10) (11,11) (12,12) (13,13) (14,14) (15,15) (12,14) (13,15) (14,0) (15,1) (0,2) (1,3) (2,4) (3,5) (4,6) (5,7) (6,8) (7,9) (8,10) (9,11) (10,12) (11,13) (8,12) (9,13) (10,14) (11,15) (12,0) (13,1) (14,2) (15,3) (0,4) (1,5) (2,6) (3,7) (4,8) (5,9) (6,10) (7,11) (4,10) (5,11) (6,12) (7,13) (8,14) (9,15) (10,0) (11,1) (12,2) (13,3) (14,4) (15,5) (0,6) (1,7) (2,8) (3,9) (14,15) (15,0) (0,1) (1,2) (2,3) (3,4) (4,5) (5,6) (6,7) (7,8) (8,9) (9,10) (10,11) (11,12) (12,13) (13,14) (10,13) (11,14) (12,15) (13,0) (14,1) (15,2) (0,3) (1,4) (2,5) (3,6) (4,7) (5,8) (6,9) (7,10) (8,11) (9,12) (6,11) (7,12) (8,13) (9,14) (10,15) (11,0) (12,1) (13,2) (14,3) (15,4) (0,5) (1,6) (2,7) (3,8) (4,9) (5,10) (2,9) (3,10) (4,11) (5,12) (6,13) (7,14) (8,15) (9,0) (10,1) (11,2) (12,3) (13,4) (14,5) (15,6) (0,7) (1,8) (15,7) (0,8) (1,9) (2,10) (3,11) (4,12) (5,13) (6,14) (7,15) (8,0) (9,1) (10,2) (11,3) (12,4) (13,5) (14,6) (11,5) (12,6) (13,7) (14,8) (15,9) (0,10) (1,11) (2,12) (3,13) (4,14) (5,15) (6,0) (7,1) (8,2) (9,3) (10,4) (7,3) (8,4) (9,5) (10,6) (11,7) (12,8) (13,9) (14,10) (15,11) (0,12) (1,13) (2,14) (3,15) (4,0) (5,1) (6,2) (3,1) (4,2) (5,3) (6,4) (7,5) (8,6) (9,7) (10,8) (11,9) (12,10) (13,11) (14,12) (15,13) (0,14) (1,15) (2,0) (13,6) (14,7) (15,8) (0,9) (1,10) (2,11) (3,12) (4,13) (5,14) (6,15) (7,0) (8,1) (9,2) (10,3) (11,4) (12,5) (9,4) (10,5) (11,6) (12,7) (13,8) (14,9) (15,10) (0,11) (1,12) (2,13) (3,14) (4,15) (5,0) (6,1) (7,2) (8,3) (5,2) (6,3) (7,4) (8,5) (9,6) (10,7) (11,8) (12,9) (13,10) (14,11) (15,12) (0,13) (1,14) (2,15) (3,0) (4,1) (1,0) (2,1) (3,2) (4,3) (5,4) (6,5) (7,6) (8,7) (9,8) (10,9) (11,10) (12,11) (13,12) (14,13) (15,14) (0,15)

the first mapping table comprises 256 table units, and each table unit has corresponding mapping position data; the first table unit is a table unit in the first mapping table, and mapping position data in the first table unit is (s, t), where s and t are integers greater than or equal to 0 and less than 16, and (s, t) is used to indicate a position of bit data stored in the first table unit before position transformation in a bit square matrix range.

8. The method according to any of claims 1-7, wherein modulating the first symbol sequence to be transmitted according to the third matrix comprises:

determining a first bit sequence to be modulated according to the third matrix;

determining each adjacent four-bit data in the first bit sequence as a first modulation mapping unit according to a sequence from front to back, wherein the bit data in each first modulation mapping unit is used for modulating the same modulation symbol;

mapping the first two bits of data in the first target modulation mapping unit into a component of the first modulation symbol in the X polarization direction, and mapping the last two bits of data in the first target modulation mapping unit into a component of the first modulation symbol in the Y polarization direction; the first target modulation mapping unit is any one of the first modulation mapping units;

modulating the first modulation symbol according to the component of the first modulation symbol in the X polarization direction and the component of the first modulation symbol in the Y polarization direction.

9. The method according to any of claims 1-7, wherein modulating the first symbol sequence to be transmitted according to the third matrix comprises:

determining a second bit sequence to be modulated according to the third matrix;

determining each adjacent eight-bit data in the second bit sequence as a second modulation mapping unit according to the sequence from front to back, wherein the bit data in each second modulation mapping unit is used for modulating two modulation symbols;

mapping first two bits of bit data in a second target modulation mapping unit to a component of a second modulation symbol in the X polarization direction, mapping third bits of bit data and fourth bits of bit data in the second target modulation unit to a component of a third modulation symbol in the X polarization direction, mapping fifth bits of bit data and sixth bits of bit data in the second target modulation unit to a component of the second modulation symbol in the Y polarization direction, and mapping seventh bits of bit data and eighth bits of bit data in the second target modulation unit to a component of the third modulation symbol in the Y polarization direction; the second target modulation mapping unit is any one of the second modulation mapping units;

modulating the second modulation symbol according to a component of the second modulation symbol in an X polarization direction and a component of the second modulation symbol in a Y polarization direction;

and modulating the third modulation symbol according to the component of the third modulation symbol in the X polarization direction and the component of the third modulation symbol in the Y polarization direction.

10. A method of communication, comprising:

demodulating a received first symbol sequence to obtain a first matrix, wherein the first matrix comprises a plurality of bit square matrixes with the same size, and each bit square matrix comprises a plurality of bit data;

carrying out position transformation of bit data among bit square matrixes on the first matrix to obtain a second matrix;

according to a first mapping relation, performing position transformation on bit data of each bit square matrix in the second matrix in the direction of the bit square matrix to obtain a transformed third matrix, wherein the first mapping relation is used for indicating the position mapping relation of the bit data before and after the position transformation in the range of the bit square matrix, the first mapping relation comprises a row transformation mapping relation, the row transformation mapping relation is constrained by a global offset constraint factor and at least two local offset constraint factors, the global offset constraint factor is used for constraining the position offset of the row transformation of the bit data in the bit square matrix, and the local offset constraint factor is used for constraining the position offset of the row transformation of the bit data in a part of bit rows in the bit square matrix;

and decoding to obtain a first bit sequence according to the third matrix.

11. The method of claim 10, wherein the row transform mapping relationship is further constrained by a start offset parameter for constraining a start position of the bit data in the bit matrix for position transformation by a position offset amount.

12. The method according to claim 11, wherein said local offset constraint factor comprises m-1, where m is an integer greater than 3, in the case where said first matrix comprises a square matrix of bits having a number of rows and columns of 2 Λ m;

the global offset constraint factor, the local offset constraint factor, and the start offset parameter constrain the row transformation mapping relationship by the following equation:

wherein r is₀Identifying a corresponding row of first bit data in the bit square matrix after position transformation within the bit square matrix range, wherein the first bit data is any bit data in the bit square matrix, and r₁For the corresponding row identification before the position change of the first bit data in the range of the bit matrix, c₁Corresponding column identification before the position of the first bit data is changed in a bit square matrix range, g is the global offset constraint factor, beta is the local offset constraint factor, alpha is the initial offset parameter, g, beta and alpha are all preset integers, k is index identification of beta, and the value of g is determined according to 2 ^ pAnd p is an integer greater than 1.

13. Method according to claim 12, characterized in that in case of m-4, g { -8, -4,4}, β ∈ { -8, -4,4}, β {₂∈{-7,-5,-3,-1,1,3,5,7}；

14. The method of claim 12 or 13, wherein the first mapping further comprises a column transformation mapping, the column transformation mapping constrained by the following formula:

wherein, c₀Column identification corresponding to the first bit data after position conversion within the bit square matrix range, r1 row identification corresponding to the first bit data before position conversion within the bit square matrix range, c₁And h, gamma and theta are preset integers, and w is an index mark of gamma, which is corresponding to the first bit data before position transformation in the bit square matrix range.

15. The method of claim 14, wherein in the case that m is 4, g is-4, β₀Is 0, beta₁Has a value of-2, beta₂Is 3, alpha is 0, h is-2, gamma₀Is 0, gamma₁Is taken as 7, gamma₂Is-7 and theta is 0.

16. The method of claim 15, wherein the first mapping relationship is indicated by a first mapping table, and wherein the first mapping table is:

the first mapping table comprises 256 table units, and each table unit has corresponding mapping position data; the first table unit is a table unit in the first mapping table, and mapping position data in the first table unit is (s, t), where s and t are integers greater than or equal to 0 and less than 16, and (s, t) is used to indicate a position of the bit data stored in the first table unit after position transformation in a bit square matrix range.

17. The method of any of claims 10-16, wherein demodulating the received first sequence of symbols to obtain a first matrix comprises:

demodulating a first modulation symbol to obtain two-bit second bit data and two-bit third bit data corresponding to the first modulation symbol, where the second bit data is bit data corresponding to a component of the first modulation symbol in an X polarization direction, the third bit data is bit data corresponding to a component of the first modulation symbol in a Y polarization direction, and the first modulation symbol is any one modulation symbol in the first symbol sequence;

arranging the two second bit data adjacently in the same column in the first matrix, and arranging the two third bit data adjacently below the second bit data.

18. The method of any of claims 10-16, wherein demodulating the received first sequence of symbols to obtain a first matrix comprises:

demodulating a second modulation symbol to obtain two-bit fourth bit data and two-bit fifth bit data corresponding to the second modulation symbol, where the fourth bit data is bit data corresponding to a component of the second modulation symbol in an X polarization direction, the fifth bit data is bit data corresponding to a component of the second modulation symbol in a Y polarization direction, and the second modulation symbol is any modulation symbol except for a last modulation symbol in the first symbol sequence;

demodulating a third modulation symbol to obtain two-bit sixth bit data and two-bit seventh bit data corresponding to the third modulation symbol, where the sixth bit data is bit data corresponding to a component of the third modulation symbol in an X polarization direction, the seventh bit data is bit data corresponding to a component of the third modulation symbol in a Y polarization direction, and the third modulation symbol is a modulation symbol adjacent to and behind the second modulation symbol in the first symbol sequence;

adjacently arranging the two fourth bit data in the same column in the first matrix, adjacently arranging the two sixth bit data below the fourth bit data, adjacently arranging the two fifth bit data below the fourth bit data, and adjacently arranging the two seventh bit data below the fifth bit data.

19. A communications apparatus, comprising:

the device comprises a first processing module, a second processing module and a transmission module, wherein the first processing module is used for coding a first bit sequence to be transmitted to obtain a first matrix, the first matrix comprises a plurality of bit square matrixes with the same size, and each bit square matrix comprises a plurality of bit data;

a second processing module, configured to perform, according to a first mapping relationship, position transformation in a respective bit matrix range for bit data of each bit matrix in the first matrix, to obtain a second matrix, where the first mapping relationship is used to indicate a position mapping relationship before and after the position transformation of each bit data in the bit matrix range, the first mapping relationship includes a row transformation mapping relationship, the row transformation mapping relationship is constrained by a global offset constraint factor and at least two local offset constraint factors, the global offset constraint factor is used to constrain a position offset of each bit data row transformation in the bit matrix, and the local offset constraint factor is used to constrain a position offset of a bit data row transformation in a part of bit rows in the bit matrix;

the third processing module is used for carrying out position transformation on bit data among the bit square matrixes on the second matrix to obtain a second bit sequence;

and a fourth processing module, configured to modulate the first symbol sequence to be transmitted according to the second bit sequence.

20. The apparatus of claim 19, wherein the row transform mapping relationship is further constrained by a start offset parameter for constraining a start position of the bit data in the bit matrix for position transformation by a position offset amount.

21. The apparatus according to claim 20, wherein said local offset constraint factor comprises m-1, where m is an integer greater than 3, in the case where said first matrix comprises a square matrix of bits having a number of rows and columns of 2 Λ m;

the global offset constraint factor, the local offset constraint factor, and the start offset parameter constrain the row transformation mapping relationship by the following equation:

wherein r is₀Identifying a corresponding row of first bit data in the bit square matrix before position conversion in the bit square matrix range, wherein the first bit data is any bit data in the bit square matrix, and r₁For the corresponding row identification after the position transformation of the first bit data within the bit matrix, c₁The method comprises the steps of obtaining a first bit data, obtaining a first initial offset parameter, obtaining a first column identifier corresponding to the first bit data after position transformation in a bit matrix range, obtaining a global offset constraint factor, obtaining a local offset constraint factor, obtaining an initial offset parameter, obtaining a column identifier corresponding to the first bit data after position transformation in the bit matrix range, obtaining an index identifier of beta, and determining the value of g according to 2 lambada p, wherein p is an integer larger than 1.

22. The apparatus of claim 21, wherein in case of m-4, g e-8, -4, β₂∈{-7,-5,-3,-1,1,3,5,7}；

23. The apparatus of claim 21 or 22, wherein the first mapping relationship further comprises a column transformation mapping relationship, the column transformation mapping relationship constrained by the following formula:

24. The apparatus of claim 23, wherein in the case that m has a value of 4, g has a value of-4, β₀Is 0, beta₁Has a value of-2, beta₂Is 3, alpha is 0, h is-2, gamma₀Is 0, gamma₁Is taken as 7, gamma₂Is-7 and theta is 0.

25. The apparatus of claim 24, wherein the first mapping relationship is indicated by a first mapping table, and wherein the first mapping table is:

26. The device according to any of claims 19 to 25, wherein the fourth processing module is specifically configured to:

determining a first bit sequence to be modulated according to the third matrix;

27. The device according to any of claims 19 to 25, wherein the fourth processing module is specifically configured to:

determining a second bit sequence to be modulated according to the third matrix;

28. A communications apparatus, comprising:

the first processing module is used for demodulating a received first symbol sequence to obtain a first matrix, wherein the first matrix comprises a plurality of bit square matrixes with the same size, and each bit square matrix comprises a plurality of bit data;

the second processing module is used for carrying out position transformation on bit data among the bit square matrixes on the first matrix to obtain a second matrix;

a third processing module, configured to perform, according to a first mapping relationship, position transformation in the bit matrix direction of each bit matrix in the second matrix, to obtain a transformed third matrix, where the first mapping relationship is used to indicate a position mapping relationship before and after the position transformation of each bit data in a bit matrix range, the first mapping relationship includes a row transformation mapping relationship, the row transformation mapping relationship is constrained by a global offset constraint factor and at least two local offset constraint factors, the global offset constraint factor is used to constrain a position offset amount of row transformation of each bit data in the bit matrix, and the local offset constraint factor is used to constrain a position offset amount of row transformation of bit data in a partial bit row in the bit matrix;

and the fourth processing module is used for decoding to obtain a first bit sequence according to the third matrix.

29. The apparatus of claim 28, wherein the row transform mapping relationship is further constrained by a start offset parameter for constraining a start position of the bit data in the bit matrix for position transformation by a position offset amount.

30. The apparatus according to claim 29, wherein said local offset constraint factor comprises m-1, where m is an integer greater than 3, in the case where said first matrix comprises a square matrix of bits having a number of rows and columns of 2 Λ m;

the global offset constraint factor, the local offset constraint factor, and the start offset parameter constrain the row transformation mapping relationship by the following equation:

wherein r is₀Identifying a corresponding row of first bit data in the bit square matrix after position transformation within the bit square matrix range, wherein the first bit data is any bit data in the bit square matrix, and r₁For the corresponding row identification before the position change of the first bit data in the range of the bit matrix, c₁The method comprises the steps that corresponding column identification is carried out on first bit data before position transformation in a bit square matrix range, g is a global offset constraint factor, beta is a local offset constraint factor, alpha is an initial offset parameter, g, beta and alpha are preset integers, k is an index identification of beta, the value of g is determined according to 2 ^ p, and p is an integer larger than 1.

31. The apparatus of claim 30, wherein in case of m-4, g e-8, -4, β₂∈{-7,-5,-3,-1,1,3,5,7}；

32. The apparatus of claim 30 or 31, wherein the first mapping further comprises a column transformation mapping, the column transformation mapping constrained by the following equation:

33. The apparatus of claim 32, wherein in the case that m is 4, g is-4, β₀Is 0, beta₁Has a value of-2, beta₂Is 3, alpha is 0, h is-2, gamma₀Is gotA value of 0, gamma₁Is taken as 7, gamma₂Is-7 and theta is 0.

34. The apparatus of claim 33, wherein the first mapping relationship is indicated by a first mapping table, and wherein the first mapping table is:

the first mapping table comprises 256 table units, and each table unit has corresponding mapping position data; the first table unit is a table unit in the first mapping table, and mapping position data in the first table unit is (s, t), where s and t are integers greater than or equal to 0 and less than 16, and (s, t) is used to indicate a position of the bit data stored in the first table unit after position transformation in a bit square matrix range.

35. The device according to any one of claims 28 to 34, wherein the first processing module is specifically configured to:

arranging the two second bit data adjacently in the same column in the first matrix, and arranging the two third bit data adjacently below the second bit data.

36. The device according to any one of claims 28 to 34, wherein the first processing module is specifically configured to:

37. A communication apparatus comprising a processor, a memory, and a communication interface, the processor being configured to invoke a program stored in the memory to perform the communication method of any one of claims 1-9, or to perform the communication method of any one of claims 10-18.

38. A computer storage medium having stored thereon instructions that, when executed on a processor, cause the processor to perform the communication method of any one of claims 1-9 or the communication method of any one of claims 10-18.

Technical Field

The present application relates to the field of communications technologies, and in particular, to a communication method and apparatus.

Background

At present, high-speed optical transmission networks are developing towards high-capacity, packetized and intelligent. High-speed optical transmission networks need to use efficient Forward Error Correction (FEC) codes to combat optical impairments (such as uncompensated chromatic dispersion, polarization mode dispersion, nonlinear effects, etc.) during optical transmission, so as to keep the bit Error rate sufficiently low for long-distance transmission. In the prior art, a modulator may be connected behind an FEC encoder, that is, after information to be transmitted is encoded to obtain a corresponding bit sequence, the bit sequence is modulated to generate a corresponding symbol sequence, the generated symbol sequence is transmitted to a receiving end through an optical transmission network, and after the receiving end demodulates and decodes the received symbol sequence, information transmitted by a transmitting end may be obtained. If the transmission link is affected by the burst factor in the transmission process of the symbol sequence, which causes errors in a plurality of continuous symbols in the symbol sequence, the receiving end corrects the errors by the FEC code in the decoding process after receiving the symbol sequence affected by the burst factor.

Disclosure of Invention

The application provides a communication method and a communication device, which can improve the burst resistance of information transmission and reduce the error rate of the information transmission.

The first aspect of the present application provides a communication method, which may be applied to a sending end device of a communication network, to implement adjustment of a structure of information to be sent, and improve an anti-burst capability of information transmission. In the method, a first bit sequence to be transmitted is input and coded, and a first matrix is determined according to a coded result, wherein the first matrix comprises a plurality of bit square matrixes with the same size, and each bit square matrix comprises a plurality of bit data; then according to the first mapping relation, the bit data of each bit square matrix in the first matrix is subjected to position transformation within the range of each bit square matrix to obtain a second matrix after the position transformation; and then carrying out position conversion of bit data among the bit square matrixes on the second matrix to obtain a third matrix, and modulating a first symbol sequence to be transmitted according to the third matrix.

The first mapping relation may be used to indicate a position mapping relation of each bit data before and after position conversion in the bit matrix range, and includes a row conversion mapping relation, and the row conversion mapping relation may indicate a row identifier mapping relation of the bit data before and after position conversion in the bit matrix range. The line transformation mapping relation can be restrained by a global offset restraining factor and at least two local offset restraining factors, the global offset restraining factor is used for restraining the position offset of each bit data line transformation in the bit square matrix, the local offset restraining factor is used for restraining the position offset of the bit data line transformation in a part of bit rows in the bit square matrix, and the position offset of the bit data line transformation in different bit rows is restrained in a targeted and diversified mode through the global offset restraining factor and the at least two local offset restraining factors, so that the bit data in the first matrix are subjected to position transformation more discretely and more uniformly, and the burst resistance of information transmission is improved.

In an alternative implementation, the row transformation mapping relationship is further constrained by a start offset parameter, and the start offset parameter may constrain a start position of the bit data in the bit matrix for position transformation according to the position offset. The setting of the initial offset parameter can make the bit square matrix generate translation transformation, and further realize the position transformation of the bit data.

In an alternative implementation, the number of local offset constraint factors is related to the size of the bit square matrix, the first matrix is divided into a plurality of bit square matrices with the number of rows and columns being 2 Λ m, then the local offset constraint factors may comprise m-1, where m is an integer greater than 3; the global offset constraint factor, the local offset constraint factor, and the start offset parameter constrain the row transform mapping relationship by the following formulas:

wherein r is₀Identifying a corresponding row of first bit data in the bit square matrix before position conversion within the bit square matrix, wherein the first bit data isThe data being any bit of data in a square matrix of bits, r₁For the corresponding row identification after the position conversion of the first bit data within the bit matrix, c₁The method comprises the steps that corresponding column identifiers are corresponding to first bit data after position transformation in a bit square matrix range, g is a global offset constraint factor, beta is a local offset constraint factor, alpha is an initial offset parameter, g, beta and alpha are all preset integers, k is an index identifier of beta, the value of g is determined according to 2 lambada p, and p is an integer larger than 1.

Wherein the m-1 local offset constraint factors include local offset constraint factors that constrain from the 2 ^ (f-1) th bit line to the 2 ^ m th bit line, f being an integer greater than 0 and less than m. It should be noted that m-1 local offset constraint factors herein may include 0, and the number of local offset constraint factors other than 0 is not less than 2.

When the bit data of the same row is converted to other rows before conversion, a certain column offset needs to be corresponded, when a plurality of bit data of the same row are converted to different bit rows, the corresponding column offsets are also different, and the column offsets when the bit data of the same row is converted to other rows before conversion are subjected to targeted and diversified constraint through a global offset constraint factor for constraining all rows and m-1 local offset constraint factors for constraining part of the rows, so that the dispersion and uniformity of bit data position conversion within a bit square array range are improved.

In an alternative implementation, in the case of m { -4, g ∈ { -8, -4,4}, β { -4 { (4) } is equal to₂∈{-7,-5,-3,-1,1,3,5,7}；

In an alternative implementation, the first mapping relationship further includes a column transformation mapping relationship, the column transformation mapping relationship being constrained by the following formula:

wherein, c₀Column identification corresponding to the first bit data before position conversion in the bit square matrix range, r1 row identification corresponding to the first bit data after position conversion in the bit square matrix range, c₁And h, gamma and theta are preset integers, and w is an index mark of gamma, which is corresponding to the first bit data after the position of the first bit data is changed in the range of the bit square matrix.

When the bit data of the same column before column conversion is converted into other columns, a certain column offset is required to be corresponded, when a plurality of bit data of the same column are converted into different bit columns, the corresponding column offset is also different, and the column offset when the bit data of the same column before conversion is converted into other columns is subjected to targeted and diversified constraint through the formula, so that the dispersion and uniformity of bit data position conversion in the range of a bit square matrix are improved.

In some alternativesIn an implementation mode, under the condition that the value of m is 4, the value of g is-4, beta₀Is 0, beta₁Has a value of-2, beta₂Is 3, alpha is 0, h is-2, gamma₀Is 0, gamma₁Is taken as 7, gamma₂Is-7 and theta is 0.

In some alternative implementations, the first mapping relationship may be indicated by a first mapping table, the first mapping table containing 256 table units, mapping position data in each table unit; for any first table unit in the first mapping table, mapping position data in the first table unit is (s, t), and both s and t are integers which are greater than or equal to 0 and less than 16, wherein (s, t) is used for indicating the position of bit data stored in the first table unit before position transformation in a bit square matrix range;

the first mapping table is:

(0,0)	(1,1)	(2,2)	(3,3)	(4,4)	(5,5)	(6,6)	(7,7)	(8,8)	(9,9)	(10,10)	(11,11)	(12,12)	(13,13)	(14,14)	(15,15)
																(12,14)	(13,15)	(14,0)	(15,1)	(0,2)	(1,3)	(2,4)	(3,5)	(4,6)	(5,7)	(6,8)	(7,9)	(8,10)	(9,11)	(10,12)	(11,13)
(8,12)	(9,13)	(10,14)	(11,15)	(12,0)	(13,1)	(14,2)	(15,3)	(0,4)	(1,5)	(2,6)	(3,7)	(4,8)	(5,9)	(6,10)	(7,11)
																(4,10)	(5,11)	(6,12)	(7,13)	(8,14)	(9,15)	(10,0)	(11,1)	(12,2)	(13,3)	(14,4)	(15,5)	(0,6)	(1,7)	(2,8)	(3,9)
(14,15)	(15,0)	(0,1)	(1,2)	(2,3)	(3,4)	(4,5)	(5,6)	(6,7)	(7,8)	(8,9)	(9,10)	(10,11)	(11,12)	(12,13)	(13,14)
																(10,13)	(11,14)	(12,15)	(13,0)	(14,1)	(15,2)	(0,3)	(1,4)	(2,5)	(3,6)	(4,7)	(5,8)	(6,9)	(7,10)	(8,11)	(9,12)
(6,11)	(7,12)	(8,13)	(9,14)	(10,15)	(11,0)	(12,1)	(13,2)	(14,3)	(15,4)	(0,5)	(1,6)	(2,7)	(3,8)	(4,9)	(5,10)
																(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,0)	(10,1)	(11,2)	(12,3)	(13,4)	(14,5)	(15,6)	(0,7)	(1,8)
(15,7)	(0,8)	(1,9)	(2,10)	(3,11)	(4,12)	(5,13)	(6,14)	(7,15)	(8,0)	(9,1)	(10,2)	(11,3)	(12,4)	(13,5)	(14,6)
																(11,5)	(12,6)	(13,7)	(14,8)	(15,9)	(0,10)	(1,11)	(2,12)	(3,13)	(4,14)	(5,15)	(6,0)	(7,1)	(8,2)	(9,3)	(10,4)
(7,3)	(8,4)	(9,5)	(10,6)	(11,7)	(12,8)	(13,9)	(14,10)	(15,11)	(0,12)	(1,13)	(2,14)	(3,15)	(4,0)	(5,1)	(6,2)
																(3,1)	(4,2)	(5,3)	(6,4)	(7,5)	(8,6)	(9,7)	(10,8)	(11,9)	(12,10)	(13,11)	(14,12)	(15,13)	(0,14)	(1,15)	(2,0)
(13,6)	(14,7)	(15,8)	(0,9)	(1,10)	(2,11)	(3,12)	(4,13)	(5,14)	(6,15)	(7,0)	(8,1)	(9,2)	(10,3)	(11,4)	(12,5)
																(9,4)	(10,5)	(11,6)	(12,7)	(13,8)	(14,9)	(15,10)	(0,11)	(1,12)	(2,13)	(3,14)	(4,15)	(5,0)	(6,1)	(7,2)	(8,3)
(5,2)	(6,3)	(7,4)	(8,5)	(9,6)	(10,7)	(11,8)	(12,9)	(13,10)	(14,11)	(15,12)	(0,13)	(1,14)	(2,15)	(3,0)	(4,1)
																(1,0)	(2,1)	(3,2)	(4,3)	(5,4)	(6,5)	(7,6)	(8,7)	(9,8)	(10,9)	(11,10)	(12,11)	(13,12)	(14,13)	(15,14)	(0,15)

for example, in the table unit of 2 rows and 5 columns in the above table, the mapping position data contained therein is (13,1), which indicates that in the position conversion process in the range of the bit square matrix, the bit data located in 13 rows and 1 columns is converted to the position located in 2 rows and 5 columns in the bit square matrix.

In an alternative implementation, the first symbol sequence to be transmitted is modulated by means of dual-polarization quadrature amplitude modulation.

In an alternative implementation, the first sequence of symbols to be transmitted is modulated by means of dual-polarization quadrature phase shift keying.

In an alternative implementation manner, if a first symbol sequence to be transmitted is modulated in a dual-polarization quadrature phase shift keying manner, a first bit sequence to be modulated may be determined according to a third matrix, and each adjacent four-bit data in the first bit sequence is determined as a first modulation mapping unit according to a sequence from front to back, where the bit data in the first modulation mapping unit is used to modulate the same modulation symbol; for any one first target modulation mapping unit in the first modulation mapping units, mapping the first two bits of data in the first target modulation mapping unit to be a component of the first modulation symbol in the X polarization direction, and mapping the last two bits of data in the first target modulation mapping unit to be a component of the first modulation symbol in the Y polarization direction; and modulating the first modulation symbol according to the component of the first modulation symbol in the X polarization direction and the component of the first modulation symbol in the Y polarization direction. In this way, each successive four-bit in the first bit sequence is modulated into a modulation symbol.

In an alternative implementation, if the first symbol sequence to be transmitted is modulated by a dual-polarization quadrature phase shift keying method, the second bit sequence to be modulated may be determined according to the third matrix; then according to the sequence from front to back, determining every adjacent eight-bit data in the second bit sequence as a second modulation mapping unit, wherein the bit data in each second modulation mapping unit is used for modulating two modulation symbols; aiming at any one second target modulation mapping unit in the second modulation mapping unit, mapping the first two bit data in the second target modulation mapping unit into a component of a second modulation symbol in the X polarization direction, mapping the third bit data and the fourth bit data in the second target modulation unit into a component of a third modulation symbol in the X polarization direction, mapping the fifth bit data and the sixth bit data in the second target modulation unit into a component of the second modulation symbol in the Y polarization direction, mapping the seventh bit data and the eighth bit data in the second target modulation unit into a component of the third modulation symbol in the Y polarization direction, further modulating the second modulation symbol according to the component of the second modulation symbol in the X polarization direction and the component of the second modulation symbol in the Y polarization direction, and modulating the component of the third modulation symbol in the X polarization direction and the component of the third modulation symbol in the Y polarization direction, and modulating the third modulation symbol. In this way, each successive eight-bit data in the first bit sequence is modulated crosswise into two modulation symbols.

The second aspect of the present application provides another communication method, which may be applied to a receiving end device of a communication network, to recover a structure of received information and reduce an error rate of information transmission. Demodulating a received first symbol sequence, and determining a first matrix according to a demodulated result, wherein the first matrix comprises a plurality of bit square matrixes with the same size, and each bit square matrix comprises a plurality of bit data; then, carrying out position transformation of bit data among the bit square matrixes on the first matrix to obtain a second matrix; and then, according to the first mapping relation, carrying out position transformation in the azimuth of each bit square matrix aiming at the bit data of each bit square matrix in the second matrix to obtain a transformed third matrix, and decoding according to the third matrix to obtain a first bit sequence.

The first mapping relation is constrained by a global offset constraint factor and at least two local offset constraint factors, and information data which originally belongs to the same matrix row (namely, the information data which belongs to the same matrix row before the position of bit data in a bit square matrix is transformed by the sending end equipment) and is scattered at different rows in the matrix (the information data which is scattered to different rows in the matrix after the position of the bit data in the bit square matrix is transformed by the sending end equipment) is recovered into the same matrix row.

In an alternative implementation, the row transformation mapping relationship is further constrained by a start offset parameter, and the start offset parameter is used for constraining a start position of the bit data in the bit matrix to perform position transformation according to the position offset. The setting of the initial offset parameter can make the bit square matrix generate translation transformation, and further realize the position transformation of the bit data.

wherein r is₀Identifying corresponding row identification after the position of first bit data in the bit square matrix is changed in the range of the bit square matrix, wherein the first bit data is any bit data in the bit square matrix, and r₁For the corresponding row identification of the first bit data before the position change within the bit matrix, c₁The method comprises the steps that corresponding column identification is carried out on first bit data before position transformation in a bit square matrix range, g is a global offset constraint factor, beta is a local offset constraint factor, alpha is an initial offset parameter, g, beta and alpha are all preset integers, k is index identification of beta, the value of g is determined according to 2 lambada p, and p is an integer larger than 1.

When the bit data of different rows before conversion is converted into other rows, the bit data need to correspond to a certain column offset, when a plurality of bit data of different rows are converted into the same row, the corresponding column offsets are also different, through a global offset constraint factor for constraining all rows and m-1 local offset constraint factors for constraining part of the rows, the column offsets of the plurality of bit data of different rows before conversion when the plurality of bit data of different rows are converted into the same row are subjected to targeted and diversified constraints, and the dispersion and uniformity of bit data position conversion within the range of a bit square matrix are improved.

In an alternative implementation, in the case of m { -4, g ∈ { -8, -4,4}, β { -4 { (4) } is equal to₂∈{-7,-5,-3,-1,1,3,5,7}；

wherein, c₀Column identification corresponding to the first bit data after position conversion in the bit matrix range, r1 row identification corresponding to the first bit data before position conversion in the bit matrix range, c₁Identifying corresponding column before the position of the first bit data is changed in the range of the bit square matrix, wherein h, gamma and theta are preset integers, and w is a cord of gammaAnd (5) guiding identification.

When the bit data of different columns before the column transformation is transformed to other columns, the bit data of different columns need to correspond to a certain column offset, when the bit data of different columns are transformed to the same column, the corresponding column offset is also different, the column offset of the bit data of different columns before the transformation is transformed to the same column is subjected to targeted and diversified constraints through the formula, and the dispersion and uniformity of bit data position transformation in the range of a bit square matrix are improved.

In some alternative implementations, g has a value of-4, β, where m has a value of 4₀Is 0, beta₁Has a value of-2, beta₂Is 3, alpha is 0, h is-2, gamma₀Is 0, gamma₁Is taken as 7, gamma₂Is-7 and theta is 0.

In some alternative implementations, the first mapping relationship may be indicated by a first mapping table, the first mapping table containing 256 table units, mapping position data in each table unit; for any first table unit in the first mapping table, mapping position data in the first table unit is (s, t), and both s and t are integers which are greater than or equal to 0 and less than 16, wherein (s, t) is used for indicating the position of bit data stored in the first table unit after position transformation in a bit matrix range;

the first mapping table is:

(0,0)	(1,1)	(2,2)	(3,3)	(4,4)	(5,5)	(6,6)	(7,7)	(8,8)	(9,9)	(10,10)	(11,11)	(12,12)	(13,13)	(14,14)	(15,15)
																(12,14)	(13,15)	(14,0)	(15,1)	(0,2)	(1,3)	(2,4)	(3,5)	(4,6)	(5,7)	(6,8)	(7,9)	(8,10)	(9,11)	(10,12)	(11,13)
(8,12)	(9,13)	(10,14)	(11,15)	(12,0)	(13,1)	(14,2)	(15,3)	(0,4)	(1,5)	(2,6)	(3,7)	(4,8)	(5,9)	(6,10)	(7,11)
																(4,10)	(5,11)	(6,12)	(7,13)	(8,14)	(9,15)	(10,0)	(11,1)	(12,2)	(13,3)	(14,4)	(15,5)	(0,6)	(1,7)	(2,8)	(3,9)
(14,15)	(15,0)	(0,1)	(1,2)	(2,3)	(3,4)	(4,5)	(5,6)	(6,7)	(7,8)	(8,9)	(9,10)	(10,11)	(11,12)	(12,13)	(13,14)
																(10,13)	(11,14)	(12,15)	(13,0)	(14,1)	(15,2)	(0,3)	(1,4)	(2,5)	(3,6)	(4,7)	(5,8)	(6,9)	(7,10)	(8,11)	(9,12)
(6,11)	(7,12)	(8,13)	(9,14)	(10,15)	(11,0)	(12,1)	(13,2)	(14,3)	(15,4)	(0,5)	(1,6)	(2,7)	(3,8)	(4,9)	(5,10)
																(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,0)	(10,1)	(11,2)	(12,3)	(13,4)	(14,5)	(15,6)	(0,7)	(1,8)
(15,7)	(0,8)	(1,9)	(2,10)	(3,11)	(4,12)	(5,13)	(6,14)	(7,15)	(8,0)	(9,1)	(10,2)	(11,3)	(12,4)	(13,5)	(14,6)
																(11,5)	(12,6)	(13,7)	(14,8)	(15,9)	(0,10)	(1,11)	(2,12)	(3,13)	(4,14)	(5,15)	(6,0)	(7,1)	(8,2)	(9,3)	(10,4)
(7,3)	(8,4)	(9,5)	(10,6)	(11,7)	(12,8)	(13,9)	(14,10)	(15,11)	(0,12)	(1,13)	(2,14)	(3,15)	(4,0)	(5,1)	(6,2)
																(3,1)	(4,2)	(5,3)	(6,4)	(7,5)	(8,6)	(9,7)	(10,8)	(11,9)	(12,10)	(13,11)	(14,12)	(15,13)	(0,14)	(1,15)	(2,0)
(13,6)	(14,7)	(15,8)	(0,9)	(1,10)	(2,11)	(3,12)	(4,13)	(5,14)	(6,15)	(7,0)	(8,1)	(9,2)	(10,3)	(11,4)	(12,5)
																(9,4)	(10,5)	(11,6)	(12,7)	(13,8)	(14,9)	(15,10)	(0,11)	(1,12)	(2,13)	(3,14)	(4,15)	(5,0)	(6,1)	(7,2)	(8,3)
(5,2)	(6,3)	(7,4)	(8,5)	(9,6)	(10,7)	(11,8)	(12,9)	(13,10)	(14,11)	(15,12)	(0,13)	(1,14)	(2,15)	(3,0)	(4,1)
																(1,0)	(2,1)	(3,2)	(4,3)	(5,4)	(6,5)	(7,6)	(8,7)	(9,8)	(10,9)	(11,10)	(12,11)	(13,12)	(14,13)	(15,14)	(0,15)

in an alternative implementation, the received first symbol sequence is demodulated by dual-polarization quadrature amplitude modulation.

In an alternative implementation, the received first symbol sequence is demodulated by dual-polarization quadrature phase shift keying.

In an alternative implementation manner, if the received first symbol sequence is demodulated in a dual-polarization quadrature phase shift keying manner, for any first modulation symbol in the first symbol sequence, the first modulation symbol is demodulated to obtain two-bit second bit data corresponding to a component of the first modulation symbol in the X polarization direction and two-bit third bit data corresponding to a component of the first modulation symbol in the Y polarization direction; two bits of second bit data are adjacently arranged in the same column in the first matrix, and two bits of third bit data are adjacently arranged below the second bit data.

In an alternative implementation manner, if the received first symbol sequence is demodulated through a dual-polarization quadrature phase shift keying manner, the second modulation symbol is demodulated with respect to any second modulation symbol in the first symbol sequence, so as to obtain two-bit fourth bit data and two-bit fifth bit data corresponding to the second modulation symbol, where the fourth bit data is bit data corresponding to a component of the second modulation symbol in the X polarization direction, the fifth bit data is bit data corresponding to a component of the second modulation symbol in the Y polarization direction, and the second modulation symbol is any modulation symbol other than the last modulation symbol in the first symbol sequence.

And demodulating the third modulation symbol aiming at a third modulation symbol adjacent to the second modulation symbol in the first symbol sequence to obtain two-bit sixth bit data and two-bit seventh bit data corresponding to the third modulation symbol, wherein the sixth bit data is bit data corresponding to a component of the third modulation symbol in the X polarization direction, and the seventh bit data is bit data corresponding to a component of the third modulation symbol in the Y polarization direction.

Two bits of fourth bit data are adjacently arranged in the same column in the first matrix, two bits of sixth bit data are adjacently arranged below the fourth bit data, two bits of fifth bit data are adjacently arranged below the fourth bit data, and two bits of seventh bit data are adjacently arranged below the fifth bit data.

A third aspect of the present application provides a communication apparatus, which may be a sending end device or a part of a sending end device in a communication network, and includes a first processing module, a second processing module, a third processing module, and a fourth processing module, where: the first processing module is used for coding a first bit sequence to be transmitted to obtain a first matrix, the first matrix comprises a plurality of bit square matrixes with the same size, and each bit square matrix comprises a plurality of bit data; the second processing module is used for carrying out position transformation in the range of each bit square matrix aiming at the bit data of each bit square matrix in the first matrix according to the first mapping relation to obtain a second matrix; the third processing module is used for carrying out position transformation on bit data among the bit square matrixes on the second matrix to obtain a second bit sequence; and a fourth processing module, configured to modulate the first symbol sequence to be transmitted according to the second bit sequence.

wherein r is₀Identifying a corresponding row of first bit data in the bit square matrix before position transformation in the bit square matrix range, wherein the first bit data is any bit data in the bit square matrix, and r₁For the corresponding row identification after the position conversion of the first bit data within the bit matrix, c₁The method comprises the steps that corresponding column identifiers are corresponding to first bit data after position transformation in a bit square matrix range, g is a global offset constraint factor, beta is a local offset constraint factor, alpha is an initial offset parameter, g, beta and alpha are all preset integers, k is an index identifier of beta, the value of g is determined according to 2 lambada p, and p is an integer larger than 1.

In an alternative implementation form of the method of the invention,in the case where m is 4, g ∈ { -8, -4,4}, β₂∈{-7,-5,-3,-1,1,3,5,7}；

wherein, c₀Column identification corresponding to the first bit data before position conversion in the bit square matrix range, r1 row identification corresponding to the first bit data after position conversion in the bit square matrix range, c₁Is firstAnd h, gamma and theta are all preset integers, and w is an index mark of gamma.

the first mapping table is:

In an alternative implementation, the fourth processing module is specifically configured to modulate the first symbol sequence to be transmitted by a dual-polarization quadrature amplitude modulation scheme.

In an alternative implementation, the fourth processing module is specifically configured to modulate the first sequence of symbols to be transmitted by means of dual-polarization quadrature phase shift keying.

In an alternative implementation manner, if the fourth processing module modulates the first symbol sequence to be transmitted in a dual-polarization quadrature phase shift keying manner, the first bit sequence to be modulated may be specifically determined according to the third matrix, and each adjacent four-bit data in the first bit sequence is determined as a first modulation mapping unit according to a sequence from front to back, where the bit data in the first modulation mapping unit is used to modulate the same modulation symbol; for any one first target modulation mapping unit in the first modulation mapping units, mapping the first two bits of data in the first target modulation mapping unit to be a component of the first modulation symbol in the X polarization direction, and mapping the last two bits of data in the first target modulation mapping unit to be a component of the first modulation symbol in the Y polarization direction; and modulating the first modulation symbol according to the component of the first modulation symbol in the X polarization direction and the component of the first modulation symbol in the Y polarization direction. In this way, each successive four-bit in the first bit sequence is modulated into a modulation symbol.

In an alternative implementation manner, if the fourth processing module modulates the first symbol sequence to be transmitted in a dual-polarization quadrature phase shift keying manner, the fourth processing module may specifically determine the second bit sequence to be modulated according to the third matrix; then according to the sequence from front to back, determining every adjacent eight-bit data in the second bit sequence as a second modulation mapping unit, wherein the bit data in each second modulation mapping unit is used for modulating two modulation symbols; aiming at any one second target modulation mapping unit in the second modulation mapping unit, mapping the first two bit data in the second target modulation mapping unit into a component of a second modulation symbol in the X polarization direction, mapping the third bit data and the fourth bit data in the second target modulation unit into a component of a third modulation symbol in the X polarization direction, mapping the fifth bit data and the sixth bit data in the second target modulation unit into a component of the second modulation symbol in the Y polarization direction, mapping the seventh bit data and the eighth bit data in the second target modulation unit into a component of the third modulation symbol in the Y polarization direction, further modulating the second modulation symbol according to the component of the second modulation symbol in the X polarization direction and the component of the second modulation symbol in the Y polarization direction, and modulating the component of the third modulation symbol in the X polarization direction and the component of the third modulation symbol in the Y polarization direction, and modulating the third modulation symbol. In this way, each successive eight-bit data in the first bit sequence is modulated crosswise into two modulation symbols.

The fourth aspect of the present application further provides another communication apparatus, which may be a receiving end device of a communication network, or a part of the receiving end device, to recover a structure of received information and reduce an error rate of information transmission. The device comprises a first processing module, a second processing module, a third processing module and a fourth processing module, wherein: the first processing module is used for demodulating the received first symbol sequence to obtain a first matrix, wherein the first matrix comprises a plurality of bit square matrixes with the same size, and each bit square matrix comprises a plurality of bit data; the second processing module is used for carrying out position transformation on bit data among the bit square matrixes on the first matrix to obtain a second matrix; the third processing module is used for carrying out position transformation in the azimuth of each bit square matrix aiming at the bit data of each bit square matrix in the second matrix according to the first mapping relation to obtain a transformed third matrix; and the fourth processing module is used for decoding to obtain a first bit sequence according to the third matrix.

wherein r is₀Identifying corresponding row identification after the position of first bit data in the bit square matrix is changed in the range of the bit square matrix, wherein the first bit data is any bit data in the bit square matrix, and r₁For the corresponding row identification of the first bit data before the position change within the bit matrix, c₁Corresponding column identification before position conversion of first bit data in a bit square matrix range, g being a global offset constraint factor, beta being a local offset constraint factor, alpha being an initial offset parameter, g, beta, alpha all being preset integers, k being an index identification of beta, the value of g being determined according to 2 Λ p, p beingAn integer greater than 1.

In an alternative implementation, in the case of m { -4, g ∈ { -8, -4,4}, β { -4 { (4) } is equal to₂∈{-7,-5,-3,-1,1,3,5,7}；

In the case of g-4 or g-4, β₀And beta₁Is taken asOne of the column combinations: { beta ]₀＝-6、β₁＝4}、{β₀＝-2、β₁＝-4}、{β₀＝0、β₁＝-6}、{β₀＝0、β₁＝-2}、{β₀＝0、β₁＝2}、{β₀＝0、β₁＝6}、{β₀＝2、β₁＝4}、{β₀＝6、β₁＝-4}。

wherein, c₀Column identification corresponding to the first bit data after position conversion in the bit matrix range, r1 row identification corresponding to the first bit data before position conversion in the bit matrix range, c₁And h, gamma and theta are preset integers, and w is an index mark of gamma, wherein the corresponding column mark is the corresponding column mark before the position of the first bit data is changed in the range of the bit square matrix.

In some alternative implementations, the first mapping relationship may be indicated by a first mapping table, the first mapping table containing 256 table units, mapping position data in each table unit; for any first table unit in the first mapping table, mapping position data in the first table unit is (s, t), and both s and t are integers which are greater than or equal to 0 and less than 16, wherein (s, t) is used for indicating the position of bit data stored in the first table unit after position transformation in a bit matrix range;

the first mapping table is:

(0,0)	(1,1)	(2,2)	(3,3)	(4,4)	(5,5)	(6,6)	(7,7)	(8,8)	(9,9)	(10,10)	(11,11)	(12,12)	(13,13)	(14,14)	(15,15)
																(12,14)	(13,15)	(14,0)	(15,1)	(0,2)	(1,3)	(2,4)	(3,5)	(4,6)	(5,7)	(6,8)	(7,9)	(8,10)	(9,11)	(10,12)	(11,13)
(8,12)	(9,13)	(10,14)	(11,15)	(12,0)	(13,1)	(14,2)	(15,3)	(0,4)	(1,5)	(2,6)	(3,7)	(4,8)	(5,9)	(6,10)	(7,11)
																(4,10)	(5,11)	(6,12)	(7,13)	(8,14)	(9,15)	(10,0)	(11,1)	(12,2)	(13,3)	(14,4)	(15,5)	(0,6)	(1,7)	(2,8)	(3,9)
(14,15)	(15,0)	(0,1)	(1,2)	(2,3)	(3,4)	(4,5)	(5,6)	(6,7)	(7,8)	(8,9)	(9,10)	(10,11)	(11,12)	(12,13)	(13,14)
																(10,13)	(11,14)	(12,15)	(13,0)	(14,1)	(15,2)	(0,3)	(1,4)	(2,5)	(3,6)	(4,7)	(5,8)	(6,9)	(7,10)	(8,11)	(9,12)
(6,11)	(7,12)	(8,13)	(9,14)	(10,15)	(11,0)	(12,1)	(13,2)	(14,3)	(15,4)	(0,5)	(1,6)	(2,7)	(3,8)	(4,9)	(5,10)
																(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,0)	(10,1)	(11,2)	(12,3)	(13,4)	(14,5)	(15,6)	(0,7)	(1,8)
(15,7)	(0,8)	(1,9)	(2,10)	(3,11)	(4,12)	(5,13)	(6,14)	(7,15)	(8,0)	(9,1)	(10,2)	(11,3)	(12,4)	(13,5)	(14,6)
																(11,5)	(12,6)	(13,7)	(14,8)	(15,9)	(0,10)	(1,11)	(2,12)	(3,13)	(4,14)	(5,15)	(6,0)	(7,1)	(8,2)	(9,3)	(10,4)
(7,3)	(8,4)	(9,5)	(10,6)	(11,7)	(12,8)	(13,9)	(14,10)	(15,11)	(0,12)	(1,13)	(2,14)	(3,15)	(4,0)	(5,1)	(6,2)
																(3,1)	(4,2)	(5,3)	(6,4)	(7,5)	(8,6)	(9,7)	(10,8)	(11,9)	(12,10)	(13,11)	(14,12)	(15,13)	(0,14)	(1,15)	(2,0)
(13,6)	(14,7)	(15,8)	(0,9)	(1,10)	(2,11)	(3,12)	(4,13)	(5,14)	(6,15)	(7,0)	(8,1)	(9,2)	(10,3)	(11,4)	(12,5)
																(9,4)	(10,5)	(11,6)	(12,7)	(13,8)	(14,9)	(15,10)	(0,11)	(1,12)	(2,13)	(3,14)	(4,15)	(5,0)	(6,1)	(7,2)	(8,3)
(5,2)	(6,3)	(7,4)	(8,5)	(9,6)	(10,7)	(11,8)	(12,9)	(13,10)	(14,11)	(15,12)	(0,13)	(1,14)	(2,15)	(3,0)	(4,1)
																(1,0)	(2,1)	(3,2)	(4,3)	(5,4)	(6,5)	(7,6)	(8,7)	(9,8)	(10,9)	(11,10)	(12,11)	(13,12)	(14,13)	(15,14)	(0,15)
(1,0)	(2,1)	(3,2)	(4,3)	(5,4)	(6,5)	(7,6)	(8,7)	(9,8)	(10,9)	(11,10)	(12,11)	(13,12)	(14,13)	(15,14)	(0,15)

in an alternative implementation, the first processing module is specifically configured to demodulate the received first symbol sequence by means of dual-polarization quadrature amplitude modulation.

In an alternative implementation, the first processing module is specifically configured to demodulate the received first symbol sequence by means of dual-polarization quadrature phase shift keying.

In an alternative implementation manner, if the first processing module demodulates the received first symbol sequence in a dual-polarization quadrature phase shift keying manner, for any first modulation symbol in the first symbol sequence, the first processing module demodulates the first modulation symbol to obtain two-bit second bit data corresponding to a component of the first modulation symbol in the X polarization direction and two-bit third bit data corresponding to a component of the first modulation symbol in the Y polarization direction; two bits of second bit data are adjacently arranged in the same column in the first matrix, and two bits of third bit data are adjacently arranged below the second bit data.

In an alternative implementation manner, if the first processing module demodulates the received first symbol sequence in a dual-polarization quadrature phase shift keying manner, for any second modulation symbol in the first symbol sequence, the first processing module demodulates the second modulation symbol to obtain two-bit fourth bit data and two-bit fifth bit data corresponding to the second modulation symbol, where the fourth bit data is bit data corresponding to a component of the second modulation symbol in the X polarization direction, the fifth bit data is bit data corresponding to a component of the second modulation symbol in the Y polarization direction, and the second modulation symbol is any modulation symbol other than the last modulation symbol in the first symbol sequence.

A fifth aspect of the present application provides another communication apparatus, which may be a sending end device or a receiving end device in a communication network, and may also be a part of the sending end device or a part of the receiving end device (such as a circuit or a chip), and includes a processor, a memory, and a communication interface, where the processor, the memory, and the communication interface are connected to each other, where the communication interface is used to receive and send data, the memory is used to store the above program, and the processor is used to call the program stored in the memory, and when the program is executed by a computer, the computer executes the communication method in the first aspect and any one of the possible implementations of the first aspect, or executes the communication method in the second aspect and any one of the possible implementations of the second aspect. The processor and the memory may be physically separate units, or the memory may be integrated with the processor.

A sixth aspect of the present application provides a computer-readable medium storing instructions that, when executed on a computer, cause the computer to perform the communication method of the first aspect and any one of its possible implementations, or the communication method of the second aspect and any one of its possible implementations.

A seventh aspect of the present application provides a computer program product comprising: computer program code for causing a computer to perform the method of the first aspect and any one of its possible implementations or the communication method of the second aspect and any one of its possible implementations when the computer program code runs on a computer.

An eighth aspect of the present application provides a chip, where the chip includes a processor and a communication interface, and the processor is coupled to the communication interface, and is configured to implement the communication method provided in the first aspect or any optional implementation manner, or implement the communication method in the second aspect and any possible implementation manner thereof.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic architecture diagram of a communication system according to an embodiment of the present application;

fig. 2 is a flowchart illustrating a communication method according to an embodiment of the present application;

fig. 3 is a schematic diagram illustrating a matrix representation of a bit sequence according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a set of square matrices for inter-block interleaving according to the present application;

fig. 5 is a constellation diagram of 16QAM according to an embodiment of the present application;

fig. 6 is a QPSK constellation provided in an embodiment of the present application;

fig. 7 is a schematic diagram of a bit sequence provided in an embodiment of the present application;

fig. 8 is a schematic flow chart of another communication method provided in the embodiments of the present application;

fig. 9 is a schematic flowchart of another communication method provided in an embodiment of the present application;

fig. 10 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of another communication device provided in an embodiment of the present application;

fig. 12 is a schematic structural diagram of another communication device provided in an embodiment of the present application;

fig. 13 is a schematic structural diagram of another communication device according to an embodiment of the present application;

fig. 14 is a schematic structural diagram of a communication chip according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

First, some operation symbols appearing in the formulas referred to in the embodiments of the present application will be describedOperation, meaning that a is rounded down, e.g.The operation of b% c in the embodiments of the present application means that b modulo c, and when b is a non-negative number, the remainder of b divided by c is taken as the value of b% c, for example, 8% 3 is 2, 2% 3 is 3, and when b is a negative number, the value of b% c is obtained by adding an integer multiple of a to b to a positive integer, and then performing the operation of modulo, for example, -9% 16 is 7, and-10% 3 is 2.

Next, a system architecture on which the communication method according to the embodiment of the present application is based is described, referring to fig. 1, fig. 1 is a schematic architecture diagram of a communication system according to the embodiment of the present application, as shown in fig. 1, the communication system includes a sending end device 10 and a receiving end device 20.

The transmitting end device 10 has a function of encoding an input bit sequence to be transmitted; the sending-end device 10 further has an information structure changing function, which includes a function of performing bit data position conversion within a bit matrix range on a bit matrix in a matrix carrying transmission information according to the first mapping relationship, and a function of performing bit data position conversion between bit matrixes on a bit matrix in a matrix carrying transmission information; the transmitting-end device 10 also has a function of modulating and outputting information after the structural change. The sending-end device 10 may be one entity device integrating all the functions described above, or may include a plurality of entity devices respectively having different functions described above.

The receiving-end device 20 has a function of demodulating the received information; the receiving-end device 20 further has a function of performing structure recovery on the demodulated information, including a function of performing bit data position conversion between bit matrixes (i.e., inverse conversion of bit data position conversion between bit matrixes by the transmitting-end device) on bit matrixes within a matrix carrying transmission information, and a function of performing bit data position conversion between bit matrixes (i.e., inverse conversion of bit data position conversion within a range of bit matrixes by the transmitting-end device) on bit matrixes within a matrix carrying transmission information according to the first mapping relationship; the receiving-end device 20 also has a function of decoding the information after the structure is restored. The receiving end device 20 may be a single entity device integrating all the functions described above, or may include a plurality of entity devices respectively having different functions described above.

In one implementation, the transmitting-end device 10 may include an encoder 01, an interleaver 02, and a modulator 03, and the receiving-end device 20 may include a demodulator 04, a deinterleaver 05, and a decoder 06. Wherein:

the encoder 01 is configured to receive a bit sequence carrying information to be transmitted, where the bit sequence carrying the information to be transmitted includes multiple bit data, and the bit data carries the information to be transmitted; the encoder 01 also serves to encode the received bit sequence, convert it into a signal form that can be used for transmission or storage, etc., and transmit the encoded bit sequence to the interleaver 02. In one implementation, encoder 01 may be an FEC encoder.

Further, the encoder 01 may include a serial-to-parallel conversion means 011, a first sub-encoding means 012, and a second sub-encoding means 013. The serial-to-parallel conversion device 011 can be configured to perform serial-to-parallel conversion on a bit sequence to be transmitted, convert the bit sequence to be transmitted into two bit sequences capable of performing parallel processing, and transmit the two bit sequences obtained after the serial-to-parallel conversion to the first sub-encoding device 012 and the second sub-encoding device 013 respectively; the first sub-coding device 012 and the second sub-coding device 013 are configured to code the received bit sequence and transmit the coded bit sequence to the interleaver 02.

The interleaver 02 is configured to perform position transformation on bit data in a received bit sequence, so that the structure of the bit sequence is changed, and the content is not changed; the interleaver 02 is also arranged to send the position transformed bit sequence to the modulator 03. In one implementation, interleaver 02 may be an FEC interleaver. Specifically, the interleaver 02 may process the received bit sequence in a matrix form, and implement position conversion of bit data in the bit sequence by changing the position of each bit in the matrix. Further, the matrix is a matrix that can be divided into a plurality of bit matrixes of the same size, and the number of bit rows and bit columns in the bit matrixes is equal.

Further, the interleaver 02 may include an intra-block interleaving means 021 and an inter-block interleaving means 022. If the interleaver 02 processes the received bit sequence in the form of a matrix, the intra-block interleaving device 021 is configured to perform position transformation inside the bit square matrix on the bit data in each bit square matrix, and the inter-block interleaving device 022 is configured to perform position transformation between the bit data square matrices in each bit square matrix, and send the transformed matrix to the modulator 03.

The modulator 03 is configured to perform modulation processing on the received bit sequence, and modulate the bit sequence into a symbol sequence form suitable for transmission in a channel; the modulator 03 is further configured to output the modulated symbol sequence into a transmission channel. Optionally, the modulator 03 may be a device that performs Modulation by using a DP-QAM (Dual-polarization Quadrature Amplitude Modulation), a device that performs Modulation by using a DP-QPSK (Dual-polarization Quadrature Phase Shift Keying), or the like. In one implementation, the modulator 03 may map bit data in the bit sequence to a component of the modulation symbol in the complex plane, and then perform modulation according to the component of the complex plane, so as to implement modulation of a plurality of bit data to generate one modulation symbol.

The demodulator 04 is configured to demodulate a received transmission signal, and recover information to be transmitted therefrom, where the transmission signal includes a modulation symbol sequence, and is recovered to a bit sequence form through demodulation processing; the demodulator 04 is also configured to transmit the demodulated bit sequence to the deinterleaver 05. Optionally, the demodulator 04 may adopt a demodulation mode corresponding to DP-QAM, a demodulation mode corresponding to DP-QPSK, or the like. The demodulator 04 may demodulate the modulation symbol sequence to obtain components of each modulation symbol in the complex plane, and then determine corresponding bit data according to the components of the complex plane, where the number of bit data corresponding to one modulation symbol is different in different modulation modes. The demodulator 04 may use a demodulation method corresponding to the modulation method used by the modulator on the transmission signal side.

The deinterleaver 05 is configured to receive the bit sequence demodulated by the demodulator 04, and perform position conversion on bit data in the bit sequence to convert the structure of the bit sequence without changing the content; the deinterleaver 05 is also used to send the position-transformed bit sequence to the decoder 06. In one implementation, the deinterleaver may be an FEC deinterleaver. Specifically, the deinterleaver 05 may process the received bit sequence in the form of a matrix, and by changing the position of bit data, recover the message.

Further, the deinterleaver 05 may include an inter deinterleaving means 051 and an intra deinterleaving means 052. The inter-block deinterleaving means 051 performs position conversion between bit matrixes for the bit data of each bit matrix, and the intra-block deinterleaving means 052 performs position conversion within the bit matrix range for the bit data of each bit matrix. The intra-block deinterleaving device 052 converts the matrix into a bit sequence, and then transmits the two bit sequences to the decoder 06.

The decoder 06 is configured to receive the bit sequence sent by the deinterleaver 05, decode the received bit sequence, recover the information to be transmitted therefrom, and transmit the obtained information to a destination receiving device of the information. In one implementation, the decoder 06 may be an FEC decoder.

Further, the decoder 06 may comprise a first sub-decoding device 061, a second sub-decoding device 062, and a parallel-to-serial conversion device 061, wherein the second sub-decoding device 061 and the second sub-decoding device 062 are respectively configured to decode the two bit sequences output by the deinterleaver, and respectively output the decoded bit sequences. The parallel-to-serial conversion means 061 is configured to convert the received decoded bit sequence into a serial processed bit sequence and output the serial processed bit sequence.

Based on the system architecture, the embodiment of the present application provides a communication method, which may adjust a coded matrix at a sending end of a communication network according to a first mapping relationship information structure, modulate and send information after structure adjustment, and constrain a row transformation mapping relationship in the first mapping relationship by a global offset constraint factor and at least two local offset constraint factors, so that information data in a same matrix row is uniformly and discretely adjusted to positions of different rows in the matrix, and the adjusted information has higher anti-burst capability in a transmission process; correspondingly, the receiving end of the communication network recovers the structure of the received information according to the first mapping relation, and recovers the information data which originally belongs to the same matrix row (namely, belongs to the same matrix row before the information structure adjustment is carried out by the sending end) and is dispersed at the position of different rows in the matrix (namely, the position of the different rows dispersed to the different rows in the matrix before the information structure adjustment is carried out by the sending end), so that not only is the recovery of the information realized, but also the sudden errors which possibly occur in the information transmission process are uniformly dispersed and converted into random errors, and the error rate of the information transmission is reduced.

Referring to fig. 2, fig. 2 is a flowchart illustrating a communication method provided in this embodiment of the present application, where the method includes, but is not limited to, steps S201 to S209, and in one implementation, steps S201 to S205 may be executed by the sending end device 10 in the system architecture shown in fig. 1, and steps S206 to S209 may be executed by the receiving end device 20 in the system architecture shown in fig. 1.

S201, the sending end equipment encodes a first bit sequence to be transmitted to obtain a first matrix.

In one implementation, the first bit sequence may be a bit sequence to be transmitted with a certain length received by the sending end device within a certain time unit, for example, the length of the bit sequence that the sending end device may receive within the time unit is 149184 × Z (Z may be a positive integer, such as 4, 6, or 8, etc.) bits, and the length of the bit sequence that the sending end device may receive within the certain time unit is 149184 × Z bits as the first bit sequence.

Specifically, the sending end device may perform serial-to-parallel conversion on the first bit sequence to obtain two parallel bit sequences, encode the two parallel bit sequences to obtain two encoded bit sequences, and further convert the two encoded bit sequences into a matrix form to obtain two first matrices, that is, matrices into which the two encoded bit sequences are converted, which are both to be used as the first matrices, and perform the following operations related to the first matrices.

For example, the first bit sequence received by the transmitting device has a length of 149184 × Z bits, and may be converted into two parallel bit sequences having a length of 74592 × Z bits, and then encoded to obtain two parallel bit sequences having a length of 86016 × Z bits, and the two parallel bit sequences having a length of 86016 × Z bits are converted into matrices including 672 × Z bit rows and 128 bit columns, respectively.

The first matrix may be divided into a plurality of bit matrixes of the same size, for example, into a plurality of bit matrixes of 16 bit rows and bit columns, or into a plurality of bit matrixes of 32 bit rows and bit columns, or into a plurality of bit matrixes of 64 bit rows and bit columns, and so on. In the process of converting the coded bit sequence into the matrix, the bit data can be filled by taking the bit square matrix as a unit, so that the conversion of the matrix form is realized.

For example, if the sender apparatus obtains a coded bit sequence with a length of 86016 × Z bits, and converts the coded bit sequence into a first matrix containing 672 × Z bit rows and 128 bit columns, the first matrix is divided into a plurality of bit square matrixes of 16 bit rows and 16 bit columns, that is, the first matrix contains 42 × Z square matrix rows and 8 square matrixes, and the position of each bit data in the coded bit sequence is represented as {0,1,2,3,4,5,6, … …,86 × Z-3,86016 × Z-2,86016 × Z-1}, for example, the position of the first bit data in the coded bit sequence is represented as 0, the position of the second bit data in the coded bit sequence is represented as 1, and the position of the 86016 × Z bit data in the coded bit sequence is represented as 86016 × Z-1, referring to fig. 3, which is a schematic diagram of a matrix representation of a bit sequence provided by this embodiment of the present application, as shown in FIG. 3, the sending-end device can put the bit data at 0-15 position in the coded bit sequence into the position of the first bit row in the first bit square matrix of the 0 square matrix and the 0 square matrix in sequence, put the bit data at 16-31 position into the position of the second bit row in the first bit square matrix in sequence, and so on, the bit data at 0-255 position in the coded bit sequence are put in the first bit square matrix, the bit data at 256-511 position in the coded bit sequence are put in the second bit square matrix of the 1 square matrix and the 0 square matrix in the same way, the bit data at 512-7 position in the coded bit sequence are put in the third bit square matrix of the 0 square matrix and the 1 square matrix, the bit data at 768-1023 position in the coded bit sequence are put in the fourth bit square matrix of the 1 square matrix and the 1 square matrix, according to the method, bit matrixes of 0 square matrix row and 1 square matrix row are filled, then bit matrixes in 2 square matrix row and 3 square matrix row are filled in the same way, and the like, every two square matrix rows are filled, when the two square matrix rows are filled, the square matrixes are filled, when the bit matrixes are filled according to the square arrays, the bit matrixes in the bit square matrixes are filled sequentially according to the bit rows in the bit square matrixes, and all bit data in the coding bit sequence are put into the matrixes according to the method, so that the bit sequence represented by the matrixes, namely the first matrix, is obtained. After the padding is completed, each bit square matrix of the first matrix contains a plurality of bits of data.

S202, the sending end equipment carries out position transformation in the bit square array directions of the bit data of each bit square array in the first matrix according to the first mapping relation to obtain a second matrix.

Here, the first mapping relation is used to indicate a position mapping relation before and after the position conversion of each bit data in the bit matrix range, and the first mapping relation includes a line conversion mapping relation, which may indicate a line identification mapping relation before and after the position conversion of the bit data in the bit matrix range.

The line transformation mapping relation is constrained by a global migration constraint factor and at least two local migration constraint factors, the global migration constraint factor is used for constraining the position migration amount of each bit data line transformation in the bit matrix, and the local migration constraint factor is used for constraining the position migration amount of the bit data line transformation in a part of bit lines in the bit matrix. In a specific implementation, if the bit square of the first matrix has 2 Λ m bit rows, the local offset constraint factors may have m-1, where the m-1 local offset constraint factors include local offset constraint factors that constrain from the 2 Λ (f-1) th bit row to the 2 Λ m th bit row, where f is an integer greater than 0 and less than m. It should be noted that m-1 local offset constraint factors herein may include 0, and the number of local offset constraint factors other than 0 is not less than 2.

For example, in the case where the bit square matrix of the first matrix has 16 bit rows, that is, the bit square matrix is a 16 × 16 bit square matrix, 3 local offset constraint factors (which may be factor 1, factor 2, and factor 3, respectively) may be set, the factor 1 may be a local offset constraint factor that constrains rows 2 to 16, the factor 2 may be a local offset constraint factor that constrains rows 4 to 16, and the factor 3 may be a local offset constraint factor that constrains rows 8 to 16.

When bit data position conversion is carried out within the range of the bit square matrix, for line conversion, bit data in the same line before conversion can be dispersed into different lines after conversion, and meanwhile, in adjacent bit lines after conversion, the column spacing of the bit data from the same line before conversion is larger, so that the bit data in the same line before conversion can be uniformly and discretely dispersed in the bit square matrix after conversion. When the bit data of the same row is converted to other rows before conversion, the bit data of the same row needs to correspond to a certain column offset, when a plurality of bit data of the same row are converted to different bit rows, the corresponding column offsets are different, and the column offsets when the bit data of the same row is converted to other rows before conversion are subjected to targeted and diversified constraint through a global offset constraint factor for constraining all the rows and at least two local offset constraint factors for constraining part of the rows, so that the dispersion and uniformity of bit data position conversion within a bit square matrix range are improved.

Optionally, the line transformation mapping relationship of the bit data in the bit matrix may also be constrained by a start offset parameter, where the start offset parameter is used to constrain a start position of the bit data in the bit matrix for performing position transformation according to the position offset. The setting of the initial offset parameter can make the bit square matrix generate translation transformation, and further realize the position transformation of the bit data.

As a further alternative, for any first bit data in a bit square matrix with both row and column numbers of 2 ^ m (m is an integer greater than 3), the global offset constraint factor and the local offset constraint factor may constrain their row transformation mapping relationship by the following equation (1):

wherein r is₀For the row identification, r, corresponding to the first bit data in the bit matrix before the position change within the bit matrix₁For the corresponding row identification after the position conversion of the first bit data within the bit matrix, c₁The method comprises the steps that corresponding column identifiers are corresponding to first bit data after position transformation in a bit square matrix range, g is a global offset constraint factor, beta is a local offset constraint factor, alpha is an initial offset parameter, g, beta and alpha are all preset integers, k is an index identifier of beta, the value of g is determined according to 2 lambada p, and p is an integer larger than 1. It should be noted that the formula (1) is only a constraint form of the line transformation mapping relationship, and the formula corresponding to other modified formulas also belongs to the protection scope of the present application, for example, the formula (1) can be modified intoIn another example, can be deformed intoAnd so on.

In a specific implementation manner, in the case that m is 4, g can be any one of { -8, -4,4}, beta₂May be any one of { -7, -5, -3, -1,1,3,5,7}, wherein, in the case where g { -8, β is present₀And beta₁The values of (a) may be any one of the combinations in table 1:

β₀	-6	-6	-4	-4	-4	-4	-2	-2	2	2	4	4	4	4	6	6
																	β₁	-8	0	-6	-2	2	6	-8	0	-8	0	-6	-2	2	6	-8	0

TABLE 1

In the case of g-4 or g-4, β₀And beta₁The values of (a) may be any one of the combinations in table 2:

β₀	-6	-2	0	0	0	0	2	6
									β₁	4	-4	-6	-2	2	6	4	-4

TABLE 2

Optionally, the first mapping relationship further includes a column transformation mapping relationship, and the column transformation mapping relationship may indicate a column identifier mapping relationship before and after position transformation of the bit data in the bit square matrix range. In one implementation, for any first bit data in a bit matrix with both rows and columns of 2 ^ m (m is an integer greater than 3), its column transformation mapping relationship may be constrained by the following equation (2):

wherein, c₀Is a first bitColumn identification corresponding to data before position conversion in the range of bit square matrix, r1 is row identification corresponding to first bit data after position conversion in the range of bit square matrix, c₁And h, gamma and theta are preset integers, and w is an index mark of gamma, which is corresponding to the first bit data after the position of the first bit data is changed in the range of the bit square matrix. It should be noted that formula (2) is only a constraint form of the above column transformation mapping relationship, and the formula corresponding to other modified formulas also falls within the scope of the present application, for example, formula (2) may be modified as follows:

wherein v is an integer; as another example, it can be modified to:

when bit data position conversion is performed within the range of the bit square matrix, for column conversion, bit data in the same column before conversion may be dispersed into different columns after conversion, and at the same time, in adjacent bit columns after conversion, the column pitch of bit data from the same column before conversion is made larger, so that bit data in the same column before conversion may be uniformly and discretely dispersed in the bit square matrix after conversion. When the bit data in the same column before transformation is transformed to other columns, a certain column offset needs to be corresponded, when a plurality of bit data in the same column are transformed to different bit columns, the corresponding column offsets are also different, and the column offsets when the bit data in the same column before transformation is transformed to other columns are subjected to targeted and diversified constraints through a formula (2), so that the dispersion and uniformity of bit data position transformation in a bit square matrix range are improved.

In a first alternative implementation, the first matrix is divided into a bit square matrix including 16 bit rows and 16 bit columns, and the value of g in formula (1) is set to-4, β₀Is set to 0, beta₁Is set to-2, beta₂Setting the value of (a) to 3 and the value of α to 0 to obtain the formula (3):

the value of h in the formula (2) is set as-2, gamma₀Is set to 0, gamma₁Is set to be 7, gamma₂Setting the value of (a) to-7 and the value of θ to 0 to obtain the formula (4):

r in formula (3) and formula (4)₁For the corresponding row identification after the position conversion of the bit data within the bit matrix, c₁For the corresponding column identification, r, of the bit data after a position change within the bit matrix₀For the corresponding row identification before the position change of the bit data within the bit matrix, c₀The corresponding column before the position of the bit data is transformed in the range of the bit square matrix is identified. A first mapping relationship can be determined by using formula (3) and formula (4), where formula (3) constrains row transformation mapping relationships of a bit square matrix, formula (4) constrains column transformation mapping relationships of the bit square matrix, and the first mapping relationship corresponding to formula (3) and formula (4) can be represented by a first mapping table of 16 rows × 16 columns, and the first mapping table is represented by table 3:

(0,0)	(1,1)	(2,2)	(3,3)	(4,4)	(5,5)	(6,6)	(7,7)	(8,8)	(9,9)	(10,10)	(11,11)	(12,12)	(13,13)	(14,14)	(15,15)
																(12,14)	(13,15)	(14,0)	(15,1)	(0,2)	(1,3)	(2,4)	(3,5)	(4,6)	(5,7)	(6,8)	(7,9)	(8,10)	(9,11)	(10,12)	(11,13)
(8,12)	(9,13)	(10,14)	(11,15)	(12,0)	(13,1)	(14,2)	(15,3)	(0,4)	(1,5)	(2,6)	(3,7)	(4,8)	(5,9)	(6,10)	(7,11)
																(4,10)	(5,11)	(6,12)	(7,13)	(8,14)	(9,15)	(10,0)	(11,1)	(12,2)	(13,3)	(14,4)	(15,5)	(0,6)	(1,7)	(2,8)	(3,9)
(14,15)	(15,0)	(0,1)	(1,2)	(2,3)	(3,4)	(4,5)	(5,6)	(6,7)	(7,8)	(8,9)	(9,10)	(10,11)	(11,12)	(12,13)	(13,14)
																(10,13)	(11,14)	(12,15)	(13,0)	(14,1)	(15,2)	(0,3)	(1,4)	(2,5)	(3,6)	(4,7)	(5,8)	(6,9)	(7,10)	(8,11)	(9,12)
(6,11)	(7,12)	(8,13)	(9,14)	(10,15)	(11,0)	(12,1)	(13,2)	(14,3)	(15,4)	(0,5)	(1,6)	(2,7)	(3,8)	(4,9)	(5,10)
																(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,0)	(10,1)	(11,2)	(12,3)	(13,4)	(14,5)	(15,6)	(0,7)	(1,8)
(15,7)	(0,8)	(1,9)	(2,10)	(3,11)	(4,12)	(5,13)	(6,14)	(7,15)	(8,0)	(9,1)	(10,2)	(11,3)	(12,4)	(13,5)	(14,6)
																(11,5)	(12,6)	(13,7)	(14,8)	(15,9)	(0,10)	(1,11)	(2,12)	(3,13)	(4,14)	(5,15)	(6,0)	(7,1)	(8,2)	(9,3)	(10,4)
(7,3)	(8,4)	(9,5)	(10,6)	(11,7)	(12,8)	(13,9)	(14,10)	(15,11)	(0,12)	(1,13)	(2,14)	(3,15)	(4,0)	(5,1)	(6,2)
																(3,1)	(4,2)	(5,3)	(6,4)	(7,5)	(8,6)	(9,7)	(10,8)	(11,9)	(12,10)	(13,11)	(14,12)	(15,13)	(0,14)	(1,15)	(2,0)
(13,6)	(14,7)	(15,8)	(0,9)	(1,10)	(2,11)	(3,12)	(4,13)	(5,14)	(6,15)	(7,0)	(8,1)	(9,2)	(10,3)	(11,4)	(12,5)
																(9,4)	(10,5)	(11,6)	(12,7)	(13,8)	(14,9)	(15,10)	(0,11)	(1,12)	(2,13)	(3,14)	(4,15)	(5,0)	(6,1)	(7,2)	(8,3)
(5,2)	(6,3)	(7,4)	(8,5)	(9,6)	(10,7)	(11,8)	(12,9)	(13,10)	(14,11)	(15,12)	(0,13)	(1,14)	(2,15)	(3,0)	(4,1)
																(1,0)	(2,1)	(3,2)	(4,3)	(5,4)	(6,5)	(7,6)	(8,7)	(9,8)	(10,9)	(11,10)	(12,11)	(13,12)	(14,13)	(15,14)	(0,15)

TABLE 3

Table 3 has 16 rows (0 row to 15 rows from left to right in sequence) and 16 columns (0 column to 15 columns from top to bottom in sequence), and contains 256 table cells, each table cell has corresponding mapping position data, and for any first table cell in table 3, the mapping position data contained therein is represented by (s, t), and s and t are integers greater than or equal to 0 and less than 16, and (s, t) is used to indicate the position of the bit data stored in the first table cell before position conversion in the bit square matrix range. For example, in table 3, the table cell of 2 rows and 5 columns of positions, which contains mapping position data of (13,1), indicates that in the process of position conversion within the range of the bit square matrix, the bit data located in 13 rows and 1 columns are converted to the positions located in 2 rows and 5 columns of the bit square matrix.

In a second alternative implementation, the first matrix is divided into a bit square matrix including 32 bit rows and 32 bit columns, and the value of g in formula (1) is set to-4, β₀Is set to 0, beta₁Is set to 14, beta₂Is set to-12, beta₃Setting the value of-1 and the value of alpha to 0 to obtain the formula (5):

the value of h in the formula (2) is set as-2, gamma₀Is set to 0, gamma₁Is set to be 7, gamma₂Is set to-7, gamma₃Setting the value of (a) to 0, and setting the value of θ to 0, to obtain formula (6):

r in formula (5) and formula (6)₁For the corresponding row identification after the position conversion of the bit data within the bit matrix, c₁For the corresponding column identification, r, of the bit data after a position change within the bit matrix₀For the corresponding row identification before the position change of the bit data within the bit matrix, c₀The corresponding column before the position of the bit data is transformed in the range of the bit square matrix is identified. A first mapping relation can be determined through a formula (5) and a formula (6), the formula (5) restrains the row transformation mapping relation of the bit square matrix, the formula (6) restrains the column transformation mapping relation of the bit square matrix, and the first mapping relation corresponding to the formula (5) and the formula (6) can pass through a second mapping relation of 32 rows multiplied by 32 columnsTable representation, wherein columns 1 through 16 of the second mapping table may be represented by table 4 and columns 17 through 32 of the second mapping table by table 5 (tables 4 and 5 are shown below).

It should be noted that, here, the second mapping table is shown by the two tables of table 4 and table 5 only for clearly showing the second mapping table constrained by the formula (5) and the formula (6), and in actual use, for example, when the mapping table is stored in the transmitting end device, the mapping table is a single integral table, and the data in table 5 is adjacently arranged on the right side of the data in table 4, so as to form the second mapping table with 32 rows × 32 columns.

In a third optional implementation manner, the first matrix is divided into a bit square matrix including 64 bit rows and 64 bit columns, and the value of g in the formula (1) is set to-4, β₀Is set to 0, beta₁Is set to 14, beta₂Is set to-12, beta₃Is set to 0, beta₄The value of (a) is set to-1, and the value of α is set to 0, to obtain formula (7):

the value of h in the formula (2) is set as-2, gamma₀Is set to 0, gamma₁Is set to be 7, gamma₂Is set to-7, gamma₃Is set to 0, gamma₄Setting the value of (a) to 0, and setting the value of θ to 0, to obtain formula (8):

r in formula (7) and formula (8)₁For the corresponding row identification after the position conversion of the bit data within the bit matrix, c₁For the corresponding column identification, r, of the bit data after a position change within the bit matrix₀For the corresponding row identification before the position change of the bit data within the bit matrix, c₀The corresponding column before the position of the bit data is transformed in the range of the bit square matrix is identified. By the formula(7) And equation (8) may determine a first mapping relationship, equation (7) constrains a row transformation mapping relationship of the bit square matrix, equation (8) constrains a column transformation mapping relationship of the bit square matrix, and the first mapping relationship corresponding to equations (7) and (8) may be represented by a third mapping table of 64 rows × 64 columns, where columns 1 to 16 of the third mapping table may be represented by table 6, columns 17 to 32 of the third mapping table may be represented by table 7, columns 33 to 48 of the third mapping table may be represented by table 8, and columns 48 to 64 of the third mapping table may be represented by table 9. Fig. 4 to 9 are as follows.

(0,0)	(1,1)	(2,2)	(3,3)	(4,4)	(5,5)	(6,6)	(7,7)	(8,8)	(9,9)	(10,10)	(11,11)	(12,12)	(13,13)	(14,14)	(15,15)
																(28,30)	(29,31)	(30,0)	(31,1)	(0,2)	(1,3)	(2,4)	(3,5)	(4,6)	(5,7)	(6,8)	(7,9)	(8,10)	(9,11)	(10,12)	(11,13)
(24,28)	(25,29)	(26,30)	(27,31)	(28,0)	(29,1)	(30,2)	(31,3)	(0,4)	(1,5)	(2,6)	(3,7)	(4,8)	(5,9)	(6,10)	(7,11)
																(20,26)	(21,27)	(22,28)	(23,29)	(24,30)	(25,31)	(26,0)	(27,1)	(28,2)	(29,3)	(30,4)	(31,5)	(0,6)	(1,7)	(2,8)	(3,9)
(30,31)	(31,0)	(0,1)	(1,2)	(2,3)	(3,4)	(4,5)	(5,6)	(6,7)	(7,8)	(8,9)	(9,10)	(10,11)	(11,12)	(12,13)	(13,14)
																(26,29)	(27,30)	(28,31)	(29,0)	(30,1)	(31,2)	(0,3)	(1,4)	(2,5)	(3,6)	(4,7)	(5,8)	(6,9)	(7,10)	(8,11)	(9,12)
(22,27)	(23,28)	(24,29)	(25,30)	(26,31)	(27,0)	(28,1)	(29,2)	(30,3)	(31,4)	(0,5)	(1,6)	(2,7)	(3,8)	(4,9)	(5,10)
																(18,25)	(19,26)	(20,27)	(21,28)	(22,29)	(23,30)	(24,31)	(25,0)	(26,1)	(27,2)	(28,3)	(29,4)	(30,5)	(31,6)	(0,7)	(1,8)
(16,23)	(17,24)	(18,25)	(19,26)	(20,27)	(21,28)	(22,29)	(23,30)	(24,31)	(25,0)	(26,1)	(27,2)	(28,3)	(29,4)	(30,5)	(31,6)
																(12,21)	(13,22)	(14,23)	(15,24)	(16,25)	(17,26)	(18,27)	(19,28)	(20,29)	(21,30)	(22,31)	(23,0)	(24,1)	(25,2)	(26,3)	(27,4)
(8,19)	(9,20)	(10,21)	(11,22)	(12,23)	(13,24)	(14,25)	(15,26)	(16,27)	(17,28)	(18,29)	(19,30)	(20,31)	(21,0)	(22,1)	(23,2)
																(4,17)	(5,18)	(6,19)	(7,20)	(8,21)	(9,22)	(10,23)	(11,24)	(12,25)	(13,26)	(14,27)	(15,28)	(16,29)	(17,30)	(18,31)	(19,0)
(14,22)	(15,23)	(16,24)	(17,25)	(18,26)	(19,27)	(20,28)	(21,29)	(22,30)	(23,31)	(24,0)	(25,1)	(26,2)	(27,3)	(28,4)	(29,5)
																(10,20)	(11,21)	(12,22)	(13,23)	(14,24)	(15,25)	(16,26)	(17,27)	(18,28)	(19,29)	(20,30)	(21,31)	(22,0)	(23,1)	(24,2)	(25,3)
(6,18)	(7,19)	(8,20)	(9,21)	(10,22)	(11,23)	(12,24)	(13,25)	(14,26)	(15,27)	(16,28)	(17,29)	(18,30)	(19,31)	(20,0)	(21,1)
																(2,16)	(3,17)	(4,18)	(5,19)	(6,20)	(7,21)	(8,22)	(9,23)	(10,24)	(11,25)	(12,26)	(13,27)	(14,28)	(15,29)	(16,30)	(17,31)
(31,14)	(0,15)	(1,16)	(2,17)	(3,18)	(4,19)	(5,20)	(6,21)	(7,22)	(8,23)	(9,24)	(10,25)	(11,26)	(12,27)	(13,28)	(14,29)
																(27,12)	(28,13)	(29,14)	(30,15)	(31,16)	(0,17)	(1,18)	(2,19)	(3,20)	(4,21)	(5,22)	(6,23)	(7,24)	(8,25)	(9,26)	(10,27)
(23,10)	(24,11)	(25,12)	(26,13)	(27,14)	(28,15)	(29,16)	(30,17)	(31,18)	(0,19)	(1,20)	(2,21)	(3,22)	(4,23)	(5,24)	(6,25)
																(19,8)	(20,9)	(21,10)	(22,11)	(23,12)	(24,13)	(25,14)	(26,15)	(27,16)	(28,17)	(29,18)	(30,19)	(31,20)	(0,21)	(1,22)	(2,23)
(29,13)	(30,14)	(31,15)	(0,16)	(1,17)	(2,18)	(3,19)	(4,20)	(5,21)	(6,22)	(7,23)	(8,24)	(9,25)	(10,26)	(11,27)	(12,28)
																(25,11)	(26,12)	(27,13)	(28,14)	(29,15)	(30,16)	(31,17)	(0,18)	(1,19)	(2,20)	(3,21)	(4,22)	(5,23)	(6,24)	(7,25)	(8,26)
(21,9)	(22,10)	(23,11)	(24,12)	(25,13)	(26,14)	(27,15)	(28,16)	(29,17)	(30,18)	(31,19)	(0,20)	(1,21)	(2,22)	(3,23)	(4,24)
																(17,7)	(18,8)	(19,9)	(20,10)	(21,11)	(22,12)	(23,13)	(24,14)	(25,15)	(26,16)	(27,17)	(28,18)	(29,19)	(30,20)	(31,21)	(0,22)
(15,5)	(16,6)	(17,7)	(18,8)	(19,9)	(20,10)	(21,11)	(22,12)	(23,13)	(24,14)	(25,15)	(26,16)	(27,17)	(28,18)	(29,19)	(30,20)
																(11,3)	(12,4)	(13,5)	(14,6)	(15,7)	(16,8)	(17,9)	(18,10)	(19,11)	(20,12)	(21,13)	(22,14)	(23,15)	(24,16)	(25,17)	(26,18)
(7,1)	(8,2)	(9,3)	(10,4)	(11,5)	(12,6)	(13,7)	(14,8)	(15,9)	(16,10)	(17,11)	(18,12)	(19,13)	(20,14)	(21,15)	(22,16)
																(3,31)	(4,0)	(5,1)	(6,2)	(7,3)	(8,4)	(9,5)	(10,6)	(11,7)	(12,8)	(13,9)	(14,10)	(15,11)	(16,12)	(17,13)	(18,14)
(13,4)	(14,5)	(15,6)	(16,7)	(17,8)	(18,9)	(19,10)	(20,11)	(21,12)	(22,13)	(23,14)	(24,15)	(25,16)	(26,17)	(27,18)	(28,19)
																(9,2)	(10,3)	(11,4)	(12,5)	(13,6)	(14,7)	(15,8)	(16,9)	(17,10)	(18,11)	(19,12)	(20,13)	(21,14)	(22,15)	(23,16)	(24,17)
(5,0)	(6,1)	(7,2)	(8,3)	(9,4)	(10,5)	(11,6)	(12,7)	(13,8)	(14,9)	(15,10)	(16,11)	(17,12)	(18,13)	(19,14)	(20,15)
																(1,30)	(2,31)	(3,0)	(4,1)	(5,2)	(6,3)	(7,4)	(8,5)	(9,6)	(10,7)	(11,8)	(12,9)	(13,10)	(14,11)	(15,12)	(16,13)

TABLE 4

(16,16)	(17,17)	(18,18)	(19,19)	(20,20)	(21,21)	(22,22)	(23,23)	(24,24)	(25,25)	(26,26)	(27,27)	(28,28)	(29,29)	(30,30)	(31,31)
																(12,14)	(13,15)	(14,16)	(15,17)	(16,18)	(17,19)	(18,20)	(19,21)	(20,22)	(21,23)	(22,24)	(23,25)	(24,26)	(25,27)	(26,28)	(27,29)
(8,12)	(9,13)	(10,14)	(11,15)	(12,16)	(13,17)	(14,18)	(15,19)	(16,20)	(17,21)	(18,22)	(19,23)	(20,24)	(21,25)	(22,26)	(23,27)
																(4,10)	(5,11)	(6,12)	(7,13)	(8,14)	(9,15)	(10,16)	(11,17)	(12,18)	(13,19)	(14,20)	(15,21)	(16,22)	(17,23)	(18,24)	(19,25)
(14,15)	(15,16)	(16,17)	(17,18)	(18,19)	(19,20)	(20,21)	(21,22)	(22,23)	(23,24)	(24,25)	(25,26)	(26,27)	(27,28)	(28,29)	(29,30)
																(10,13)	(11,14)	(12,15)	(13,16)	(14,17)	(15,18)	(16,19)	(17,20)	(18,21)	(19,22)	(20,23)	(21,24)	(22,25)	(23,26)	(24,27)	(25,28)
(6,11)	(7,12)	(8,13)	(9,14)	(10,15)	(11,16)	(12,17)	(13,18)	(14,19)	(15,20)	(16,21)	(17,22)	(18,23)	(19,24)	(20,25)	(21,26)
																(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,16)	(10,17)	(11,18)	(12,19)	(13,20)	(14,21)	(15,22)	(16,23)	(17,24)
(0,7)	(1,8)	(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,16)	(10,17)	(11,18)	(12,19)	(13,20)	(14,21)	(15,22)
																(28,5)	(29,6)	(30,7)	(31,8)	(0,9)	(1,10)	(2,11)	(3,12)	(4,13)	(5,14)	(6,15)	(7,16)	(8,17)	(9,18)	(10,19)	(11,20)
(24,3)	(25,4)	(26,5)	(27,6)	(28,7)	(29,8)	(30,9)	(31,10)	(0,11)	(1,12)	(2,13)	(3,14)	(4,15)	(5,16)	(6,17)	(7,18)
																(20,1)	(21,2)	(22,3)	(23,4)	(24,5)	(25,6)	(26,7)	(27,8)	(28,9)	(29,10)	(30,11)	(31,12)	(0,13)	(1,14)	(2,15)	(3,16)
(30,6)	(31,7)	(0,8)	(1,9)	(2,10)	(3,11)	(4,12)	(5,13)	(6,14)	(7,15)	(8,16)	(9,17)	(10,18)	(11,19)	(12,20)	(13,21)
																(26,4)	(27,5)	(28,6)	(29,7)	(30,8)	(31,9)	(0,10)	(1,11)	(2,12)	(3,13)	(4,14)	(5,15)	(6,16)	(7,17)	(8,18)	(9,19)
(22,2)	(23,3)	(24,4)	(25,5)	(26,6)	(27,7)	(28,8)	(29,9)	(30,10)	(31,11)	(0,12)	(1,13)	(2,14)	(3,15)	(4,16)	(5,17)
																(18,0)	(19,1)	(20,2)	(21,3)	(22,4)	(23,5)	(24,6)	(25,7)	(26,8)	(27,9)	(28,10)	(29,11)	(30,12)	(31,13)	(0,14)	(1,15)
(15,30)	(16,31)	(17,0)	(18,1)	(19,2)	(20,3)	(21,4)	(22,5)	(23,6)	(24,7)	(25,8)	(26,9)	(27,10)	(28,11)	(29,12)	(30,13)
																(11,28)	(12,29)	(13,30)	(14,31)	(15,0)	(16,1)	(17,2)	(18,3)	(19,4)	(20,5)	(21,6)	(22,7)	(23,8)	(24,9)	(25,10)	(26,11)
(7,26)	(8,27)	(9,28)	(10,29)	(11,30)	(12,31)	(13,0)	(14,1)	(15,2)	(16,3)	(17,4)	(18,5)	(19,6)	(20,7)	(21,8)	(22,9)
																(3,24)	(4,25)	(5,26)	(6,27)	(7,28)	(8,29)	(9,30)	(10,31)	(11,0)	(12,1)	(13,2)	(14,3)	(15,4)	(16,5)	(17,6)	(18,7)
(13,29)	(14,30)	(15,31)	(16,0)	(17,1)	(18,2)	(19,3)	(20,4)	(21,5)	(22,6)	(23,7)	(24,8)	(25,9)	(26,10)	(27,11)	(28,12)
																(9,27)	(10,28)	(11,29)	(12,30)	(13,31)	(14,0)	(15,1)	(16,2)	(17,3)	(18,4)	(19,5)	(20,6)	(21,7)	(22,8)	(23,9)	(24,10)
(5,25)	(6,26)	(7,27)	(8,28)	(9,29)	(10,30)	(11,31)	(12,0)	(13,1)	(14,2)	(15,3)	(16,4)	(17,5)	(18,6)	(19,7)	(20,8)
																(1,23)	(2,24)	(3,25)	(4,26)	(5,27)	(6,28)	(7,29)	(8,30)	(9,31)	(10,0)	(11,1)	(12,2)	(13,3)	(14,4)	(15,5)	(16,6)
(31,21)	(0,22)	(1,23)	(2,24)	(3,25)	(4,26)	(5,27)	(6,28)	(7,29)	(8,30)	(9,31)	(10,0)	(11,1)	(12,2)	(13,3)	(14,4)
																(27,19)	(28,20)	(29,21)	(30,22)	(31,23)	(0,24)	(1,25)	(2,26)	(3,27)	(4,28)	(5,29)	(6,30)	(7,31)	(8,0)	(9,1)	(10,2)
(23,17)	(24,18)	(25,19)	(26,20)	(27,21)	(28,22)	(29,23)	(30,24)	(31,25)	(0,26)	(1,27)	(2,28)	(3,29)	(4,30)	(5,31)	(6,0)
																(19,15)	(20,16)	(21,17)	(22,18)	(23,19)	(24,20)	(25,21)	(26,22)	(27,23)	(28,24)	(29,25)	(30,26)	(31,27)	(0,28)	(1,29)	(2,30)
(29,20)	(30,21)	(31,22)	(0,23)	(1,24)	(2,25)	(3,26)	(4,27)	(5,28)	(6,29)	(7,30)	(8,31)	(9,0)	(10,1)	(11,2)	(12,3)
																(25,18)	(26,19)	(27,20)	(28,21)	(29,22)	(30,23)	(31,24)	(0,25)	(1,26)	(2,27)	(3,28)	(4,29)	(5,30)	(6,31)	(7,0)	(8,1)
(21,16)	(22,17)	(23,18)	(24,19)	(25,20)	(26,21)	(27,22)	(28,23)	(29,24)	(30,25)	(31,26)	(0,27)	(1,28)	(2,29)	(3,30)	(4,31)
																(17,14)	(18,15)	(19,16)	(20,17)	(21,18)	(22,19)	(23,20)	(24,21)	(25,22)	(26,23)	(27,24)	(28,25)	(29,26)	(30,27)	(31,28)	(0,29)

TABLE 5

(0,0)	(1,1)	(2,2)	(3,3)	(4,4)	(5,5)	(6,6)	(7,7)	(8,8)	(9,9)	(10,10)	(11,11)	(12,12)	(13,13)	(14,14)	(15,15)
																(60,62)	(61,63)	(62,0)	(63,1)	(0,2)	(1,3)	(2,4)	(3,5)	(4,6)	(5,7)	(6,8)	(7,9)	(8,10)	(9,11)	(10,12)	(11,13)
(56,60)	(57,61)	(58,62)	(59,63)	(60,0)	(61,1)	(62,2)	(63,3)	(0,4)	(1,5)	(2,6)	(3,7)	(4,8)	(5,9)	(6,10)	(7,11)
																(52,58)	(53,59)	(54,60)	(55,61)	(56,62)	(57,63)	(58,0)	(59,1)	(60,2)	(61,3)	(62,4)	(63,5)	(0,6)	(1,7)	(2,8)	(3,9)
(62,63)	(63,0)	(0,1)	(1,2)	(2,3)	(3,4)	(4,5)	(5,6)	(6,7)	(7,8)	(8,9)	(9,10)	(10,11)	(11,12)	(12,13)	(13,14)
																(58,61)	(59,62)	(60,63)	(61,0)	(62,1)	(63,2)	(0,3)	(1,4)	(2,5)	(3,6)	(4,7)	(5,8)	(6,9)	(7,10)	(8,11)	(9,12)
(54,59)	(55,60)	(56,61)	(57,62)	(58,63)	(59,0)	(60,1)	(61,2)	(62,3)	(63,4)	(0,5)	(1,6)	(2,7)	(3,8)	(4,9)	(5,10)
																(50,57)	(51,58)	(52,59)	(53,60)	(54,61)	(55,62)	(56,63)	(57,0)	(58,1)	(59,2)	(60,3)	(61,4)	(62,5)	(63,6)	(0,7)	(1,8)
(48,55)	(49,56)	(50,57)	(51,58)	(52,59)	(53,60)	(54,61)	(55,62)	(56,63)	(57,0)	(58,1)	(59,2)	(60,3)	(61,4)	(62,5)	(63,6)
																(44,53)	(45,54)	(46,55)	(47,56)	(48,57)	(49,58)	(50,59)	(51,60)	(52,61)	(53,62)	(54,63)	(55,0)	(56,1)	(57,2)	(58,3)	(59,4)
(40,51)	(41,52)	(42,53)	(43,54)	(44,55)	(45,56)	(46,57)	(47,58)	(48,59)	(49,60)	(50,61)	(51,62)	(52,63)	(53,0)	(54,1)	(55,2)
																(36,49)	(37,50)	(38,51)	(39,52)	(40,53)	(41,54)	(42,55)	(43,56)	(44,57)	(45,58)	(46,59)	(47,60)	(48,61)	(49,62)	(50,63)	(51,0)
(46,54)	(47,55)	(48,56)	(49,57)	(50,58)	(51,59)	(52,60)	(53,61)	(54,62)	(55,63)	(56,0)	(57,1)	(58,2)	(59,3)	(60,4)	(61,5)
																(42,52)	(43,53)	(44,54)	(45,55)	(46,56)	(47,57)	(48,58)	(49,59)	(50,60)	(51,61)	(52,62)	(53,63)	(54,0)	(55,1)	(56,2)	(57,3)
(38,50)	(39,51)	(40,52)	(41,53)	(42,54)	(43,55)	(44,56)	(45,57)	(46,58)	(47,59)	(48,60)	(49,61)	(50,62)	(51,63)	(52,0)	(53,1)
																(34,48)	(35,49)	(36,50)	(37,51)	(38,52)	(39,53)	(40,54)	(41,55)	(42,56)	(43,57)	(44,58)	(45,59)	(46,60)	(47,61)	(48,62)	(49,63)
(32,46)	(33,47)	(34,48)	(35,49)	(36,50)	(37,51)	(38,52)	(39,53)	(40,54)	(41,55)	(42,56)	(43,57)	(44,58)	(45,59)	(46,60)	(47,61)
																(28,44)	(29,45)	(30,46)	(31,47)	(32,48)	(33,49)	(34,50)	(35,51)	(36,52)	(37,53)	(38,54)	(39,55)	(40,56)	(41,57)	(42,58)	(43,59)
(24,42)	(25,43)	(26,44)	(27,45)	(28,46)	(29,47)	(30,48)	(31,49)	(32,50)	(33,51)	(34,52)	(35,53)	(36,54)	(37,55)	(38,56)	(39,57)
																(20,40)	(21,41)	(22,42)	(23,43)	(24,44)	(25,45)	(26,46)	(27,47)	(28,48)	(29,49)	(30,50)	(31,51)	(32,52)	(33,53)	(34,54)	(35,55)
(30,45)	(31,46)	(32,47)	(33,48)	(34,49)	(35,50)	(36,51)	(37,52)	(38,53)	(39,54)	(40,55)	(41,56)	(42,57)	(43,58)	(44,59)	(45,60)
																(26,43)	(27,44)	(28,45)	(29,46)	(30,47)	(31,48)	(32,49)	(33,50)	(34,51)	(35,52)	(36,53)	(37,54)	(38,55)	(39,56)	(40,57)	(41,58)
(22,41)	(23,42)	(24,43)	(25,44)	(26,45)	(27,46)	(28,47)	(29,48)	(30,49)	(31,50)	(32,51)	(33,52)	(34,53)	(35,54)	(36,55)	(37,56)
																(18,39)	(19,40)	(20,41)	(21,42)	(22,43)	(23,44)	(24,45)	(25,46)	(26,47)	(27,48)	(28,49)	(29,50)	(30,51)	(31,52)	(32,53)	(33,54)
(16,37)	(17,38)	(18,39)	(19,40)	(20,41)	(21,42)	(22,43)	(23,44)	(24,45)	(25,46)	(26,47)	(27,48)	(28,49)	(29,50)	(30,51)	(31,52)
																(12,35)	(13,36)	(14,37)	(15,38)	(16,39)	(17,40)	(18,41)	(19,42)	(20,43)	(21,44)	(22,45)	(23,46)	(24,47)	(25,48)	(26,49)	(27,50)
(8,33)	(9,34)	(10,35)	(11,36)	(12,37)	(13,38)	(14,39)	(15,40)	(16,41)	(17,42)	(18,43)	(19,44)	(20,45)	(21,46)	(22,47)	(23,48)
																(4,31)	(5,32)	(6,33)	(7,34)	(8,35)	(9,36)	(10,37)	(11,38)	(12,39)	(13,40)	(14,41)	(15,42)	(16,43)	(17,44)	(18,45)	(19,46)
(14,36)	(15,37)	(16,38)	(17,39)	(18,40)	(19,41)	(20,42)	(21,43)	(22,44)	(23,45)	(24,46)	(25,47)	(26,48)	(27,49)	(28,50)	(29,51)
																(10,34)	(11,35)	(12,36)	(13,37)	(14,38)	(15,39)	(16,40)	(17,41)	(18,42)	(19,43)	(20,44)	(21,45)	(22,46)	(23,47)	(24,48)	(25,49)
(6,32)	(7,33)	(8,34)	(9,35)	(10,36)	(11,37)	(12,38)	(13,39)	(14,40)	(15,41)	(16,42)	(17,43)	(18,44)	(19,45)	(20,46)	(21,47)
																(2,30)	(3,31)	(4,32)	(5,33)	(6,34)	(7,35)	(8,36)	(9,37)	(10,38)	(11,39)	(12,40)	(13,41)	(14,42)	(15,43)	(16,44)	(17,45)
(63,28)	(0,29)	(1,30)	(2,31)	(3,32)	(4,33)	(5,34)	(6,35)	(7,36)	(8,37)	(9,38)	(10,39)	(11,40)	(12,41)	(13,42)	(14,43)
																(59,26)	(60,27)	(61,28)	(62,29)	(63,30)	(0,31)	(1,32)	(2,33)	(3,34)	(4,35)	(5,36)	(6,37)	(7,38)	(8,39)	(9,40)	(10,41)
(55,24)	(56,25)	(57,26)	(58,27)	(59,28)	(60,29)	(61,30)	(62,31)	(63,32)	(0,33)	(1,34)	(2,35)	(3,36)	(4,37)	(5,38)	(6,39)
																(51,22)	(52,23)	(53,24)	(54,25)	(55,26)	(56,27)	(57,28)	(58,29)	(59,30)	(60,31)	(61,32)	(62,33)	(63,34)	(0,35)	(1,36)	(2,37)
(61,27)	(62,28)	(63,29)	(0,30)	(1,31)	(2,32)	(3,33)	(4,34)	(5,35)	(6,36)	(7,37)	(8,38)	(9,39)	(10,40)	(11,41)	(12,42)
																(57,25)	(58,26)	(59,27)	(60,28)	(61,29)	(62,30)	(63,31)	(0,32)	(1,33)	(2,34)	(3,35)	(4,36)	(5,37)	(6,38)	(7,39)	(8,40)
(53,23)	(54,24)	(55,25)	(56,26)	(57,27)	(58,28)	(59,29)	(60,30)	(61,31)	(62,32)	(63,33)	(0,34)	(1,35)	(2,36)	(3,37)	(4,38)
																(49,21)	(50,22)	(51,23)	(52,24)	(53,25)	(54,26)	(55,27)	(56,28)	(57,29)	(58,30)	(59,31)	(60,32)	(61,33)	(62,34)	(63,35)	(0,36)
(47,19)	(48,20)	(49,21)	(50,22)	(51,23)	(52,24)	(53,25)	(54,26)	(55,27)	(56,28)	(57,29)	(58,30)	(59,31)	(60,32)	(61,33)	(62,34)
																(43,17)	(44,18)	(45,19)	(46,20)	(47,21)	(48,22)	(49,23)	(50,24)	(51,25)	(52,26)	(53,27)	(54,28)	(55,29)	(56,30)	(57,31)	(58,32)
(39,15)	(40,16)	(41,17)	(42,18)	(43,19)	(44,20)	(45,21)	(46,22)	(47,23)	(48,24)	(49,25)	(50,26)	(51,27)	(52,28)	(53,29)	(54,30)
																(35,13)	(36,14)	(37,15)	(38,16)	(39,17)	(40,18)	(41,19)	(42,20)	(43,21)	(44,22)	(45,23)	(46,24)	(47,25)	(48,26)	(49,27)	(50,28)
(45,18)	(46,19)	(47,20)	(48,21)	(49,22)	(50,23)	(51,24)	(52,25)	(53,26)	(54,27)	(55,28)	(56,29)	(57,30)	(58,31)	(59,32)	(60,33)
																(41,16)	(42,17)	(43,18)	(44,19)	(45,20)	(46,21)	(47,22)	(48,23)	(49,24)	(50,25)	(51,26)	(52,27)	(53,28)	(54,29)	(55,30)	(56,31)
(37,14)	(38,15)	(39,16)	(40,17)	(41,18)	(42,19)	(43,20)	(44,21)	(45,22)	(46,23)	(47,24)	(48,25)	(49,26)	(50,27)	(51,28)	(52,29)
																(33,12)	(34,13)	(35,14)	(36,15)	(37,16)	(38,17)	(39,18)	(40,19)	(41,20)	(42,21)	(43,22)	(44,23)	(45,24)	(46,25)	(47,26)	(48,27)
(31,10)	(32,11)	(33,12)	(34,13)	(35,14)	(36,15)	(37,16)	(38,17)	(39,18)	(40,19)	(41,20)	(42,21)	(43,22)	(44,23)	(45,24)	(46,25)
																(27,8)	(28,9)	(29,10)	(30,11)	(31,12)	(32,13)	(33,14)	(34,15)	(35,16)	(36,17)	(37,18)	(38,19)	(39,20)	(40,21)	(41,22)	(42,23)
(23,6)	(24,7)	(25,8)	(26,9)	(27,10)	(28,11)	(29,12)	(30,13)	(31,14)	(32,15)	(33,16)	(34,17)	(35,18)	(36,19)	(37,20)	(38,21)
																(19,4)	(20,5)	(21,6)	(22,7)	(23,8)	(24,9)	(25,10)	(26,11)	(27,12)	(28,13)	(29,14)	(30,15)	(31,16)	(32,17)	(33,18)	(34,19)
(29,9)	(30,10)	(31,11)	(32,12)	(33,13)	(34,14)	(35,15)	(36,16)	(37,17)	(38,18)	(39,19)	(40,20)	(41,21)	(42,22)	(43,23)	(44,24)
																(25,7)	(26,8)	(27,9)	(28,10)	(29,11)	(30,12)	(31,13)	(32,14)	(33,15)	(34,16)	(35,17)	(36,18)	(37,19)	(38,20)	(39,21)	(40,22)
(21,5)	(22,6)	(23,7)	(24,8)	(25,9)	(26,10)	(27,11)	(28,12)	(29,13)	(30,14)	(31,15)	(32,16)	(33,17)	(34,18)	(35,19)	(36,20)
																(17,3)	(18,4)	(19,5)	(20,6)	(21,7)	(22,8)	(23,9)	(24,10)	(25,11)	(26,12)	(27,13)	(28,14)	(29,15)	(30,16)	(31,17)	(32,18)
(15,1)	(16,2)	(17,3)	(18,4)	(19,5)	(20,6)	(21,7)	(22,8)	(23,9)	(24,10)	(25,11)	(26,12)	(27,13)	(28,14)	(29,15)	(30,16)
																(11,63)	(12,0)	(13,1)	(14,2)	(15,3)	(16,4)	(17,5)	(18,6)	(19,7)	(20,8)	(21,9)	(22,10)	(23,11)	(24,12)	(25,13)	(26,14)
(7,61)	(8,62)	(9,63)	(10,0)	(11,1)	(12,2)	(13,3)	(14,4)	(15,5)	(16,6)	(17,7)	(18,8)	(19,9)	(20,10)	(21,11)	(22,12)
																(3,59)	(4,60)	(5,61)	(6,62)	(7,63)	(8,0)	(9,1)	(10,2)	(11,3)	(12,4)	(13,5)	(14,6)	(15,7)	(16,8)	(17,9)	(18,10)
(13,0)	(14,1)	(15,2)	(16,3)	(17,4)	(18,5)	(19,6)	(20,7)	(21,8)	(22,9)	(23,10)	(24,11)	(25,12)	(26,13)	(27,14)	(28,15)
																(9,62)	(10,63)	(11,0)	(12,1)	(13,2)	(14,3)	(15,4)	(16,5)	(17,6)	(18,7)	(19,8)	(20,9)	(21,10)	(22,11)	(23,12)	(24,13)
(5,60)	(6,61)	(7,62)	(8,63)	(9,0)	(10,1)	(11,2)	(12,3)	(13,4)	(14,5)	(15,6)	(16,7)	(17,8)	(18,9)	(19,10)	(20,11)
																(1,58)	(2,59)	(3,60)	(4,61)	(5,62)	(6,63)	(7,0)	(8,1)	(9,2)	(10,3)	(11,4)	(12,5)	(13,6)	(14,7)	(15,8)	(16,9)

TABLE 6

(16,16)	(17,17)	(18,18)	(19,19)	(20,20)	(21,21)	(22,22)	(23,23)	(24,24)	(25,25)	(26,26)	(27,27)	(28,28)	(29,29)	(30,30)	(31,31)
																(12,14)	(13,15)	(14,16)	(15,17)	(16,18)	(17,19)	(18,20)	(19,21)	(20,22)	(21,23)	(22,24)	(23,25)	(24,26)	(25,27)	(26,28)	(27,29)
(8,12)	(9,13)	(10,14)	(11,15)	(12,16)	(13,17)	(14,18)	(15,19)	(16,20)	(17,21)	(18,22)	(19,23)	(20,24)	(21,25)	(22,26)	(23,27)
																(4,10)	(5,11)	(6,12)	(7,13)	(8,14)	(9,15)	(10,16)	(11,17)	(12,18)	(13,19)	(14,20)	(15,21)	(16,22)	(17,23)	(18,24)	(19,25)
(14,15)	(15,16)	(16,17)	(17,18)	(18,19)	(19,20)	(20,21)	(21,22)	(22,23)	(23,24)	(24,25)	(25,26)	(26,27)	(27,28)	(28,29)	(29,30)
																(10,13)	(11,14)	(12,15)	(13,16)	(14,17)	(15,18)	(16,19)	(17,20)	(18,21)	(19,22)	(20,23)	(21,24)	(22,25)	(23,26)	(24,27)	(25,28)
(6,11)	(7,12)	(8,13)	(9,14)	(10,15)	(11,16)	(12,17)	(13,18)	(14,19)	(15,20)	(16,21)	(17,22)	(18,23)	(19,24)	(20,25)	(21,26)
																(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,16)	(10,17)	(11,18)	(12,19)	(13,20)	(14,21)	(15,22)	(16,23)	(17,24)
(0,7)	(1,8)	(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,16)	(10,17)	(11,18)	(12,19)	(13,20)	(14,21)	(15,22)
																(60,5)	(61,6)	(62,7)	(63,8)	(0,9)	(1,10)	(2,11)	(3,12)	(4,13)	(5,14)	(6,15)	(7,16)	(8,17)	(9,18)	(10,19)	(11,20)
(56,3)	(57,4)	(58,5)	(59,6)	(60,7)	(61,8)	(62,9)	(63,10)	(0,11)	(1,12)	(2,13)	(3,14)	(4,15)	(5,16)	(6,17)	(7,18)
																(52,1)	(53,2)	(54,3)	(55,4)	(56,5)	(57,6)	(58,7)	(59,8)	(60,9)	(61,10)	(62,11)	(63,12)	(0,13)	(1,14)	(2,15)	(3,16)
(62,6)	(63,7)	(0,8)	(1,9)	(2,10)	(3,11)	(4,12)	(5,13)	(6,14)	(7,15)	(8,16)	(9,17)	(10,18)	(11,19)	(12,20)	(13,21)
																(58,4)	(59,5)	(60,6)	(61,7)	(62,8)	(63,9)	(0,10)	(1,11)	(2,12)	(3,13)	(4,14)	(5,15)	(6,16)	(7,17)	(8,18)	(9,19)
(54,2)	(55,3)	(56,4)	(57,5)	(58,6)	(59,7)	(60,8)	(61,9)	(62,10)	(63,11)	(0,12)	(1,13)	(2,14)	(3,15)	(4,16)	(5,17)
																(50,0)	(51,1)	(52,2)	(53,3)	(54,4)	(55,5)	(56,6)	(57,7)	(58,8)	(59,9)	(60,10)	(61,11)	(62,12)	(63,13)	(0,14)	(1,15)
(48,62)	(49,63)	(50,0)	(51,1)	(52,2)	(53,3)	(54,4)	(55,5)	(56,6)	(57,7)	(58,8)	(59,9)	(60,10)	(61,11)	(62,12)	(63,13)
																(44,60)	(45,61)	(46,62)	(47,63)	(48,0)	(49,1)	(50,2)	(51,3)	(52,4)	(53,5)	(54,6)	(55,7)	(56,8)	(57,9)	(58,10)	(59,11)
(40,58)	(41,59)	(42,60)	(43,61)	(44,62)	(45,63)	(46,0)	(47,1)	(48,2)	(49,3)	(50,4)	(51,5)	(52,6)	(53,7)	(54,8)	(55,9)
																(36,56)	(37,57)	(38,58)	(39,59)	(40,60)	(41,61)	(42,62)	(43,63)	(44,0)	(45,1)	(46,2)	(47,3)	(48,4)	(49,5)	(50,6)	(51,7)
(46,61)	(47,62)	(48,63)	(49,0)	(50,1)	(51,2)	(52,3)	(53,4)	(54,5)	(55,6)	(56,7)	(57,8)	(58,9)	(59,10)	(60,11)	(61,12)
																(42,59)	(43,60)	(44,61)	(45,62)	(46,63)	(47,0)	(48,1)	(49,2)	(50,3)	(51,4)	(52,5)	(53,6)	(54,7)	(55,8)	(56,9)	(57,10)
(38,57)	(39,58)	(40,59)	(41,60)	(42,61)	(43,62)	(44,63)	(45,0)	(46,1)	(47,2)	(48,3)	(49,4)	(50,5)	(51,6)	(52,7)	(53,8)
																(34,55)	(35,56)	(36,57)	(37,58)	(38,59)	(39,60)	(40,61)	(41,62)	(42,63)	(43,0)	(44,1)	(45,2)	(46,3)	(47,4)	(48,5)	(49,6)
(32,53)	(33,54)	(34,55)	(35,56)	(36,57)	(37,58)	(38,59)	(39,60)	(40,61)	(41,62)	(42,63)	(43,0)	(44,1)	(45,2)	(46,3)	(47,4)
																(28,51)	(29,52)	(30,53)	(31,54)	(32,55)	(33,56)	(34,57)	(35,58)	(36,59)	(37,60)	(38,61)	(39,62)	(40,63)	(41,0)	(42,1)	(43,2)
(24,49)	(25,50)	(26,51)	(27,52)	(28,53)	(29,54)	(30,55)	(31,56)	(32,57)	(33,58)	(34,59)	(35,60)	(36,61)	(37,62)	(38,63)	(39,0)
																(20,47)	(21,48)	(22,49)	(23,50)	(24,51)	(25,52)	(26,53)	(27,54)	(28,55)	(29,56)	(30,57)	(31,58)	(32,59)	(33,60)	(34,61)	(35,62)
(30,52)	(31,53)	(32,54)	(33,55)	(34,56)	(35,57)	(36,58)	(37,59)	(38,60)	(39,61)	(40,62)	(41,63)	(42,0)	(43,1)	(44,2)	(45,3)
																(26,50)	(27,51)	(28,52)	(29,53)	(30,54)	(31,55)	(32,56)	(33,57)	(34,58)	(35,59)	(36,60)	(37,61)	(38,62)	(39,63)	(40,0)	(41,1)
(22,48)	(23,49)	(24,50)	(25,51)	(26,52)	(27,53)	(28,54)	(29,55)	(30,56)	(31,57)	(32,58)	(33,59)	(34,60)	(35,61)	(36,62)	(37,63)
																(18,46)	(19,47)	(20,48)	(21,49)	(22,50)	(23,51)	(24,52)	(25,53)	(26,54)	(27,55)	(28,56)	(29,57)	(30,58)	(31,59)	(32,60)	(33,61)
(15,44)	(16,45)	(17,46)	(18,47)	(19,48)	(20,49)	(21,50)	(22,51)	(23,52)	(24,53)	(25,54)	(26,55)	(27,56)	(28,57)	(29,58)	(30,59)
																(11,42)	(12,43)	(13,44)	(14,45)	(15,46)	(16,47)	(17,48)	(18,49)	(19,50)	(20,51)	(21,52)	(22,53)	(23,54)	(24,55)	(25,56)	(26,57)
(7,40)	(8,41)	(9,42)	(10,43)	(11,44)	(12,45)	(13,46)	(14,47)	(15,48)	(16,49)	(17,50)	(18,51)	(19,52)	(20,53)	(21,54)	(22,55)
																(3,38)	(4,39)	(5,40)	(6,41)	(7,42)	(8,43)	(9,44)	(10,45)	(11,46)	(12,47)	(13,48)	(14,49)	(15,50)	(16,51)	(17,52)	(18,53)
(13,43)	(14,44)	(15,45)	(16,46)	(17,47)	(18,48)	(19,49)	(20,50)	(21,51)	(22,52)	(23,53)	(24,54)	(25,55)	(26,56)	(27,57)	(28,58)
																(9,41)	(10,42)	(11,43)	(12,44)	(13,45)	(14,46)	(15,47)	(16,48)	(17,49)	(18,50)	(19,51)	(20,52)	(21,53)	(22,54)	(23,55)	(24,56)
(5,39)	(6,40)	(7,41)	(8,42)	(9,43)	(10,44)	(11,45)	(12,46)	(13,47)	(14,48)	(15,49)	(16,50)	(17,51)	(18,52)	(19,53)	(20,54)
																(1,37)	(2,38)	(3,39)	(4,40)	(5,41)	(6,42)	(7,43)	(8,44)	(9,45)	(10,46)	(11,47)	(12,48)	(13,49)	(14,50)	(15,51)	(16,52)
(63,35)	(0,36)	(1,37)	(2,38)	(3,39)	(4,40)	(5,41)	(6,42)	(7,43)	(8,44)	(9,45)	(10,46)	(11,47)	(12,48)	(13,49)	(14,50)
																(59,33)	(60,34)	(61,35)	(62,36)	(63,37)	(0,38)	(1,39)	(2,40)	(3,41)	(4,42)	(5,43)	(6,44)	(7,45)	(8,46)	(9,47)	(10,48)
(55,31)	(56,32)	(57,33)	(58,34)	(59,35)	(60,36)	(61,37)	(62,38)	(63,39)	(0,40)	(1,41)	(2,42)	(3,43)	(4,44)	(5,45)	(6,46)
																(51,29)	(52,30)	(53,31)	(54,32)	(55,33)	(56,34)	(57,35)	(58,36)	(59,37)	(60,38)	(61,39)	(62,40)	(63,41)	(0,42)	(1,43)	(2,44)
(61,34)	(62,35)	(63,36)	(0,37)	(1,38)	(2,39)	(3,40)	(4,41)	(5,42)	(6,43)	(7,44)	(8,45)	(9,46)	(10,47)	(11,48)	(12,49)
																(57,32)	(58,33)	(59,34)	(60,35)	(61,36)	(62,37)	(63,38)	(0,39)	(1,40)	(2,41)	(3,42)	(4,43)	(5,44)	(6,45)	(7,46)	(8,47)
(53,30)	(54,31)	(55,32)	(56,33)	(57,34)	(58,35)	(59,36)	(60,37)	(61,38)	(62,39)	(63,40)	(0,41)	(1,42)	(2,43)	(3,44)	(4,45)
																(49,28)	(50,29)	(51,30)	(52,31)	(53,32)	(54,33)	(55,34)	(56,35)	(57,36)	(58,37)	(59,38)	(60,39)	(61,40)	(62,41)	(63,42)	(0,43)
(47,26)	(48,27)	(49,28)	(50,29)	(51,30)	(52,31)	(53,32)	(54,33)	(55,34)	(56,35)	(57,36)	(58,37)	(59,38)	(60,39)	(61,40)	(62,41)
																(43,24)	(44,25)	(45,26)	(46,27)	(47,28)	(48,29)	(49,30)	(50,31)	(51,32)	(52,33)	(53,34)	(54,35)	(55,36)	(56,37)	(57,38)	(58,39)
(39,22)	(40,23)	(41,24)	(42,25)	(43,26)	(44,27)	(45,28)	(46,29)	(47,30)	(48,31)	(49,32)	(50,33)	(51,34)	(52,35)	(53,36)	(54,37)
																(35,20)	(36,21)	(37,22)	(38,23)	(39,24)	(40,25)	(41,26)	(42,27)	(43,28)	(44,29)	(45,30)	(46,31)	(47,32)	(48,33)	(49,34)	(50,35)
(45,25)	(46,26)	(47,27)	(48,28)	(49,29)	(50,30)	(51,31)	(52,32)	(53,33)	(54,34)	(55,35)	(56,36)	(57,37)	(58,38)	(59,39)	(60,40)
																(41,23)	(42,24)	(43,25)	(44,26)	(45,27)	(46,28)	(47,29)	(48,30)	(49,31)	(50,32)	(51,33)	(52,34)	(53,35)	(54,36)	(55,37)	(56,38)
(37,21)	(38,22)	(39,23)	(40,24)	(41,25)	(42,26)	(43,27)	(44,28)	(45,29)	(46,30)	(47,31)	(48,32)	(49,33)	(50,34)	(51,35)	(52,36)
																(33,19)	(34,20)	(35,21)	(36,22)	(37,23)	(38,24)	(39,25)	(40,26)	(41,27)	(42,28)	(43,29)	(44,30)	(45,31)	(46,32)	(47,33)	(48,34)
(31,17)	(32,18)	(33,19)	(34,20)	(35,21)	(36,22)	(37,23)	(38,24)	(39,25)	(40,26)	(41,27)	(42,28)	(43,29)	(44,30)	(45,31)	(46,32)
																(27,15)	(28,16)	(29,17)	(30,18)	(31,19)	(32,20)	(33,21)	(34,22)	(35,23)	(36,24)	(37,25)	(38,26)	(39,27)	(40,28)	(41,29)	(42,30)
(23,13)	(24,14)	(25,15)	(26,16)	(27,17)	(28,18)	(29,19)	(30,20)	(31,21)	(32,22)	(33,23)	(34,24)	(35,25)	(36,26)	(37,27)	(38,28)
																(19,11)	(20,12)	(21,13)	(22,14)	(23,15)	(24,16)	(25,17)	(26,18)	(27,19)	(28,20)	(29,21)	(30,22)	(31,23)	(32,24)	(33,25)	(34,26)
(29,16)	(30,17)	(31,18)	(32,19)	(33,20)	(34,21)	(35,22)	(36,23)	(37,24)	(38,25)	(39,26)	(40,27)	(41,28)	(42,29)	(43,30)	(44,31)
																(25,14)	(26,15)	(27,16)	(28,17)	(29,18)	(30,19)	(31,20)	(32,21)	(33,22)	(34,23)	(35,24)	(36,25)	(37,26)	(38,27)	(39,28)	(40,29)
(21,12)	(22,13)	(23,14)	(24,15)	(25,16)	(26,17)	(27,18)	(28,19)	(29,20)	(30,21)	(31,22)	(32,23)	(33,24)	(34,25)	(35,26)	(36,27)
																(17,10)	(18,11)	(19,12)	(20,13)	(21,14)	(22,15)	(23,16)	(24,17)	(25,18)	(26,19)	(27,20)	(28,21)	(29,22)	(30,23)	(31,24)	(32,25)

TABLE 7

(32,32)	(33,33)	(34,34)	(35,35)	(36,36)	(37,37)	(38,38)	(39,39)	(40,40)	(41,41)	(42,42)	(43,43)	(44,44)	(45,45)	(46,46)	(47,47)
																(28,30)	(29,31)	(30,32)	(31,33)	(32,34)	(33,35)	(34,36)	(35,37)	(36,38)	(37,39)	(38,40)	(39,41)	(40,42)	(41,43)	(42,44)	(43,45)
(24,28)	(25,29)	(26,30)	(27,31)	(28,32)	(29,33)	(30,34)	(31,35)	(32,36)	(33,37)	(34,38)	(35,39)	(36,40)	(37,41)	(38,42)	(39,43)
																(20,26)	(21,27)	(22,28)	(23,29)	(24,30)	(25,31)	(26,32)	(27,33)	(28,34)	(29,35)	(30,36)	(31,37)	(32,38)	(33,39)	(34,40)	(35,41)
(30,31)	(31,32)	(32,33)	(33,34)	(34,35)	(35,36)	(36,37)	(37,38)	(38,39)	(39,40)	(40,41)	(41,42)	(42,43)	(43,44)	(44,45)	(45,46)
																(26,29)	(27,30)	(28,31)	(29,32)	(30,33)	(31,34)	(32,35)	(33,36)	(34,37)	(35,38)	(36,39)	(37,40)	(38,41)	(39,42)	(40,43)	(41,44)
(22,27)	(23,28)	(24,29)	(25,30)	(26,31)	(27,32)	(28,33)	(29,34)	(30,35)	(31,36)	(32,37)	(33,38)	(34,39)	(35,40)	(36,41)	(37,42)
																(18,25)	(19,26)	(20,27)	(21,28)	(22,29)	(23,30)	(24,31)	(25,32)	(26,33)	(27,34)	(28,35)	(29,36)	(30,37)	(31,38)	(32,39)	(33,40)
(16,23)	(17,24)	(18,25)	(19,26)	(20,27)	(21,28)	(22,29)	(23,30)	(24,31)	(25,32)	(26,33)	(27,34)	(28,35)	(29,36)	(30,37)	(31,38)
																(12,21)	(13,22)	(14,23)	(15,24)	(16,25)	(17,26)	(18,27)	(19,28)	(20,29)	(21,30)	(22,31)	(23,32)	(24,33)	(25,34)	(26,35)	(27,36)
(8,19)	(9,20)	(10,21)	(11,22)	(12,23)	(13,24)	(14,25)	(15,26)	(16,27)	(17,28)	(18,29)	(19,30)	(20,31)	(21,32)	(22,33)	(23,34)
																(4,17)	(5,18)	(6,19)	(7,20)	(8,21)	(9,22)	(10,23)	(11,24)	(12,25)	(13,26)	(14,27)	(15,28)	(16,29)	(17,30)	(18,31)	(19,32)
(14,22)	(15,23)	(16,24)	(17,25)	(18,26)	(19,27)	(20,28)	(21,29)	(22,30)	(23,31)	(24,32)	(25,33)	(26,34)	(27,35)	(28,36)	(29,37)
																(10,20)	(11,21)	(12,22)	(13,23)	(14,24)	(15,25)	(16,26)	(17,27)	(18,28)	(19,29)	(20,30)	(21,31)	(22,32)	(23,33)	(24,34)	(25,35)
(6,18)	(7,19)	(8,20)	(9,21)	(10,22)	(11,23)	(12,24)	(13,25)	(14,26)	(15,27)	(16,28)	(17,29)	(18,30)	(19,31)	(20,32)	(21,33)
																(2,16)	(3,17)	(4,18)	(5,19)	(6,20)	(7,21)	(8,22)	(9,23)	(10,24)	(11,25)	(12,26)	(13,27)	(14,28)	(15,29)	(16,30)	(17,31)
(0,14)	(1,15)	(2,16)	(3,17)	(4,18)	(5,19)	(6,20)	(7,21)	(8,22)	(9,23)	(10,24)	(11,25)	(12,26)	(13,27)	(14,28)	(15,29)
																(60,12)	(61,13)	(62,14)	(63,15)	(0,16)	(1,17)	(2,18)	(3,19)	(4,20)	(5,21)	(6,22)	(7,23)	(8,24)	(9,25)	(10,26)	(11,27)
(56,10)	(57,11)	(58,12)	(59,13)	(60,14)	(61,15)	(62,16)	(63,17)	(0,18)	(1,19)	(2,20)	(3,21)	(4,22)	(5,23)	(6,24)	(7,25)
																(52,8)	(53,9)	(54,10)	(55,11)	(56,12)	(57,13)	(58,14)	(59,15)	(60,16)	(61,17)	(62,18)	(63,19)	(0,20)	(1,21)	(2,22)	(3,23)
(62,13)	(63,14)	(0,15)	(1,16)	(2,17)	(3,18)	(4,19)	(5,20)	(6,21)	(7,22)	(8,23)	(9,24)	(10,25)	(11,26)	(12,27)	(13,28)
																(58,11)	(59,12)	(60,13)	(61,14)	(62,15)	(63,16)	(0,17)	(1,18)	(2,19)	(3,20)	(4,21)	(5,22)	(6,23)	(7,24)	(8,25)	(9,26)
(54,9)	(55,10)	(56,11)	(57,12)	(58,13)	(59,14)	(60,15)	(61,16)	(62,17)	(63,18)	(0,19)	(1,20)	(2,21)	(3,22)	(4,23)	(5,24)
																(50,7)	(51,8)	(52,9)	(53,10)	(54,11)	(55,12)	(56,13)	(57,14)	(58,15)	(59,16)	(60,17)	(61,18)	(62,19)	(63,20)	(0,21)	(1,22)
(48,5)	(49,6)	(50,7)	(51,8)	(52,9)	(53,10)	(54,11)	(55,12)	(56,13)	(57,14)	(58,15)	(59,16)	(60,17)	(61,18)	(62,19)	(63,20)
																(44,3)	(45,4)	(46,5)	(47,6)	(48,7)	(49,8)	(50,9)	(51,10)	(52,11)	(53,12)	(54,13)	(55,14)	(56,15)	(57,16)	(58,17)	(59,18)
(40,1)	(41,2)	(42,3)	(43,4)	(44,5)	(45,6)	(46,7)	(47,8)	(48,9)	(49,10)	(50,11)	(51,12)	(52,13)	(53,14)	(54,15)	(55,16)
																(36,63)	(37,0)	(38,1)	(39,2)	(40,3)	(41,4)	(42,5)	(43,6)	(44,7)	(45,8)	(46,9)	(47,10)	(48,11)	(49,12)	(50,13)	(51,14)
(46,4)	(47,5)	(48,6)	(49,7)	(50,8)	(51,9)	(52,10)	(53,11)	(54,12)	(55,13)	(56,14)	(57,15)	(58,16)	(59,17)	(60,18)	(61,19)
																(42,2)	(43,3)	(44,4)	(45,5)	(46,6)	(47,7)	(48,8)	(49,9)	(50,10)	(51,11)	(52,12)	(53,13)	(54,14)	(55,15)	(56,16)	(57,17)
(38,0)	(39,1)	(40,2)	(41,3)	(42,4)	(43,5)	(44,6)	(45,7)	(46,8)	(47,9)	(48,10)	(49,11)	(50,12)	(51,13)	(52,14)	(53,15)
																(34,62)	(35,63)	(36,0)	(37,1)	(38,2)	(39,3)	(40,4)	(41,5)	(42,6)	(43,7)	(44,8)	(45,9)	(46,10)	(47,11)	(48,12)	(49,13)
(31,60)	(32,61)	(33,62)	(34,63)	(35,0)	(36,1)	(37,2)	(38,3)	(39,4)	(40,5)	(41,6)	(42,7)	(43,8)	(44,9)	(45,10)	(46,11)
																(27,58)	(28,59)	(29,60)	(30,61)	(31,62)	(32,63)	(33,0)	(34,1)	(35,2)	(36,3)	(37,4)	(38,5)	(39,6)	(40,7)	(41,8)	(42,9)
(23,56)	(24,57)	(25,58)	(26,59)	(27,60)	(28,61)	(29,62)	(30,63)	(31,0)	(32,1)	(33,2)	(34,3)	(35,4)	(36,5)	(37,6)	(38,7)
																(19,54)	(20,55)	(21,56)	(22,57)	(23,58)	(24,59)	(25,60)	(26,61)	(27,62)	(28,63)	(29,0)	(30,1)	(31,2)	(32,3)	(33,4)	(34,5)
(29,59)	(30,60)	(31,61)	(32,62)	(33,63)	(34,0)	(35,1)	(36,2)	(37,3)	(38,4)	(39,5)	(40,6)	(41,7)	(42,8)	(43,9)	(44,10)
																(25,57)	(26,58)	(27,59)	(28,60)	(29,61)	(30,62)	(31,63)	(32,0)	(33,1)	(34,2)	(35,3)	(36,4)	(37,5)	(38,6)	(39,7)	(40,8)
(21,55)	(22,56)	(23,57)	(24,58)	(25,59)	(26,60)	(27,61)	(28,62)	(29,63)	(30,0)	(31,1)	(32,2)	(33,3)	(34,4)	(35,5)	(36,6)
																(17,53)	(18,54)	(19,55)	(20,56)	(21,57)	(22,58)	(23,59)	(24,60)	(25,61)	(26,62)	(27,63)	(28,0)	(29,1)	(30,2)	(31,3)	(32,4)
(15,51)	(16,52)	(17,53)	(18,54)	(19,55)	(20,56)	(21,57)	(22,58)	(23,59)	(24,60)	(25,61)	(26,62)	(27,63)	(28,0)	(29,1)	(30,2)
																(11,49)	(12,50)	(13,51)	(14,52)	(15,53)	(16,54)	(17,55)	(18,56)	(19,57)	(20,58)	(21,59)	(22,60)	(23,61)	(24,62)	(25,63)	(26,0)
(7,47)	(8,48)	(9,49)	(10,50)	(11,51)	(12,52)	(13,53)	(14,54)	(15,55)	(16,56)	(17,57)	(18,58)	(19,59)	(20,60)	(21,61)	(22,62)
																(3,45)	(4,46)	(5,47)	(6,48)	(7,49)	(8,50)	(9,51)	(10,52)	(11,53)	(12,54)	(13,55)	(14,56)	(15,57)	(16,58)	(17,59)	(18,60)
(13,50)	(14,51)	(15,52)	(16,53)	(17,54)	(18,55)	(19,56)	(20,57)	(21,58)	(22,59)	(23,60)	(24,61)	(25,62)	(26,63)	(27,0)	(28,1)
																(9,48)	(10,49)	(11,50)	(12,51)	(13,52)	(14,53)	(15,54)	(16,55)	(17,56)	(18,57)	(19,58)	(20,59)	(21,60)	(22,61)	(23,62)	(24,63)
(5,46)	(6,47)	(7,48)	(8,49)	(9,50)	(10,51)	(11,52)	(12,53)	(13,54)	(14,55)	(15,56)	(16,57)	(17,58)	(18,59)	(19,60)	(20,61)
																(1,44)	(2,45)	(3,46)	(4,47)	(5,48)	(6,49)	(7,50)	(8,51)	(9,52)	(10,53)	(11,54)	(12,55)	(13,56)	(14,57)	(15,58)	(16,59)
(63,42)	(0,43)	(1,44)	(2,45)	(3,46)	(4,47)	(5,48)	(6,49)	(7,50)	(8,51)	(9,52)	(10,53)	(11,54)	(12,55)	(13,56)	(14,57)
																(59,40)	(60,41)	(61,42)	(62,43)	(63,44)	(0,45)	(1,46)	(2,47)	(3,48)	(4,49)	(5,50)	(6,51)	(7,52)	(8,53)	(9,54)	(10,55)
(55,38)	(56,39)	(57,40)	(58,41)	(59,42)	(60,43)	(61,44)	(62,45)	(63,46)	(0,47)	(1,48)	(2,49)	(3,50)	(4,51)	(5,52)	(6,53)
																(51,36)	(52,37)	(53,38)	(54,39)	(55,40)	(56,41)	(57,42)	(58,43)	(59,44)	(60,45)	(61,46)	(62,47)	(63,48)	(0,49)	(1,50)	(2,51)
(61,41)	(62,42)	(63,43)	(0,44)	(1,45)	(2,46)	(3,47)	(4,48)	(5,49)	(6,50)	(7,51)	(8,52)	(9,53)	(10,54)	(11,55)	(12,56)
																(57,39)	(58,40)	(59,41)	(60,42)	(61,43)	(62,44)	(63,45)	(0,46)	(1,47)	(2,48)	(3,49)	(4,50)	(5,51)	(6,52)	(7,53)	(8,54)
(53,37)	(54,38)	(55,39)	(56,40)	(57,41)	(58,42)	(59,43)	(60,44)	(61,45)	(62,46)	(63,47)	(0,48)	(1,49)	(2,50)	(3,51)	(4,52)
																(49,35)	(50,36)	(51,37)	(52,38)	(53,39)	(54,40)	(55,41)	(56,42)	(57,43)	(58,44)	(59,45)	(60,46)	(61,47)	(62,48)	(63,49)	(0,50)
(47,33)	(48,34)	(49,35)	(50,36)	(51,37)	(52,38)	(53,39)	(54,40)	(55,41)	(56,42)	(57,43)	(58,44)	(59,45)	(60,46)	(61,47)	(62,48)
																(43,31)	(44,32)	(45,33)	(46,34)	(47,35)	(48,36)	(49,37)	(50,38)	(51,39)	(52,40)	(53,41)	(54,42)	(55,43)	(56,44)	(57,45)	(58,46)
(39,29)	(40,30)	(41,31)	(42,32)	(43,33)	(44,34)	(45,35)	(46,36)	(47,37)	(48,38)	(49,39)	(50,40)	(51,41)	(52,42)	(53,43)	(54,44)
																(35,27)	(36,28)	(37,29)	(38,30)	(39,31)	(40,32)	(41,33)	(42,34)	(43,35)	(44,36)	(45,37)	(46,38)	(47,39)	(48,40)	(49,41)	(50,42)
(45,32)	(46,33)	(47,34)	(48,35)	(49,36)	(50,37)	(51,38)	(52,39)	(53,40)	(54,41)	(55,42)	(56,43)	(57,44)	(58,45)	(59,46)	(60,47)
																(41,30)	(42,31)	(43,32)	(44,33)	(45,34)	(46,35)	(47,36)	(48,37)	(49,38)	(50,39)	(51,40)	(52,41)	(53,42)	(54,43)	(55,44)	(56,45)
(37,28)	(38,29)	(39,30)	(40,31)	(41,32)	(42,33)	(43,34)	(44,35)	(45,36)	(46,37)	(47,38)	(48,39)	(49,40)	(50,41)	(51,42)	(52,43)
																(33,26)	(34,27)	(35,28)	(36,29)	(37,30)	(38,31)	(39,32)	(40,33)	(41,34)	(42,35)	(43,36)	(44,37)	(45,38)	(46,39)	(47,40)	(48,41)

TABLE 8

(48,48)	(49,49)	(50,50)	(51,51)	(52,52)	(53,53)	(54,54)	(55,55)	(56,56)	(57,57)	(58,58)	(59,59)	(60,60)	(61,61)	(62,62)	(63,63)
																(44,46)	(45,47)	(46,48)	(47,49)	(48,50)	(49,51)	(50,52)	(51,53)	(52,54)	(53,55)	(54,56)	(55,57)	(56,58)	(57,59)	(58,60)	(59,61)
(40,44)	(41,45)	(42,46)	(43,47)	(44,48)	(45,49)	(46,50)	(47,51)	(48,52)	(49,53)	(50,54)	(51,55)	(52,56)	(53,57)	(54,58)	(55,59)
																(36,42)	(37,43)	(38,44)	(39,45)	(40,46)	(41,47)	(42,48)	(43,49)	(44,50)	(45,51)	(46,52)	(47,53)	(48,54)	(49,55)	(50,56)	(51,57)
(46,47)	(47,48)	(48,49)	(49,50)	(50,51)	(51,52)	(52,53)	(53,54)	(54,55)	(55,56)	(56,57)	(57,58)	(58,59)	(59,60)	(60,61)	(61,62)
																(42,45)	(43,46)	(44,47)	(45,48)	(46,49)	(47,50)	(48,51)	(49,52)	(50,53)	(51,54)	(52,55)	(53,56)	(54,57)	(55,58)	(56,59)	(57,60)
(38,43)	(39,44)	(40,45)	(41,46)	(42,47)	(43,48)	(44,49)	(45,50)	(46,51)	(47,52)	(48,53)	(49,54)	(50,55)	(51,56)	(52,57)	(53,58)
																(34,41)	(35,42)	(36,43)	(37,44)	(38,45)	(39,46)	(40,47)	(41,48)	(42,49)	(43,50)	(44,51)	(45,52)	(46,53)	(47,54)	(48,55)	(49,56)
(32,39)	(33,40)	(34,41)	(35,42)	(36,43)	(37,44)	(38,45)	(39,46)	(40,47)	(41,48)	(42,49)	(43,50)	(44,51)	(45,52)	(46,53)	(47,54)
																(28,37)	(29,38)	(30,39)	(31,40)	(32,41)	(33,42)	(34,43)	(35,44)	(36,45)	(37,46)	(38,47)	(39,48)	(40,49)	(41,50)	(42,51)	(43,52)
(24,35)	(25,36)	(26,37)	(27,38)	(28,39)	(29,40)	(30,41)	(31,42)	(32,43)	(33,44)	(34,45)	(35,46)	(36,47)	(37,48)	(38,49)	(39,50)
																(20,33)	(21,34)	(22,35)	(23,36)	(24,37)	(25,38)	(26,39)	(27,40)	(28,41)	(29,42)	(30,43)	(31,44)	(32,45)	(33,46)	(34,47)	(35,48)
(30,38)	(31,39)	(32,40)	(33,41)	(34,42)	(35,43)	(36,44)	(37,45)	(38,46)	(39,47)	(40,48)	(41,49)	(42,50)	(43,51)	(44,52)	(45,53)
																(26,36)	(27,37)	(28,38)	(29,39)	(30,40)	(31,41)	(32,42)	(33,43)	(34,44)	(35,45)	(36,46)	(37,47)	(38,48)	(39,49)	(40,50)	(41,51)
(22,34)	(23,35)	(24,36)	(25,37)	(26,38)	(27,39)	(28,40)	(29,41)	(30,42)	(31,43)	(32,44)	(33,45)	(34,46)	(35,47)	(36,48)	(37,49)
																(18,32)	(19,33)	(20,34)	(21,35)	(22,36)	(23,37)	(24,38)	(25,39)	(26,40)	(27,41)	(28,42)	(29,43)	(30,44)	(31,45)	(32,46)	(33,47)
(16,30)	(17,31)	(18,32)	(19,33)	(20,34)	(21,35)	(22,36)	(23,37)	(24,38)	(25,39)	(26,40)	(27,41)	(28,42)	(29,43)	(30,44)	(31,45)
																(12,28)	(13,29)	(14,30)	(15,31)	(16,32)	(17,33)	(18,34)	(19,35)	(20,36)	(21,37)	(22,38)	(23,39)	(24,40)	(25,41)	(26,42)	(27,43)
(8,26)	(9,27)	(10,28)	(11,29)	(12,30)	(13,31)	(14,32)	(15,33)	(16,34)	(17,35)	(18,36)	(19,37)	(20,38)	(21,39)	(22,40)	(23,41)
																(4,24)	(5,25)	(6,26)	(7,27)	(8,28)	(9,29)	(10,30)	(11,31)	(12,32)	(13,33)	(14,34)	(15,35)	(16,36)	(17,37)	(18,38)	(19,39)
(14,29)	(15,30)	(16,31)	(17,32)	(18,33)	(19,34)	(20,35)	(21,36)	(22,37)	(23,38)	(24,39)	(25,40)	(26,41)	(27,42)	(28,43)	(29,44)
																(10,27)	(11,28)	(12,29)	(13,30)	(14,31)	(15,32)	(16,33)	(17,34)	(18,35)	(19,36)	(20,37)	(21,38)	(22,39)	(23,40)	(24,41)	(25,42)
(6,25)	(7,26)	(8,27)	(9,28)	(10,29)	(11,30)	(12,31)	(13,32)	(14,33)	(15,34)	(16,35)	(17,36)	(18,37)	(19,38)	(20,39)	(21,40)
																(2,23)	(3,24)	(4,25)	(5,26)	(6,27)	(7,28)	(8,29)	(9,30)	(10,31)	(11,32)	(12,33)	(13,34)	(14,35)	(15,36)	(16,37)	(17,38)
(0,21)	(1,22)	(2,23)	(3,24)	(4,25)	(5,26)	(6,27)	(7,28)	(8,29)	(9,30)	(10,31)	(11,32)	(12,33)	(13,34)	(14,35)	(15,36)
																(60,19)	(61,20)	(62,21)	(63,22)	(0,23)	(1,24)	(2,25)	(3,26)	(4,27)	(5,28)	(6,29)	(7,30)	(8,31)	(9,32)	(10,33)	(11,34)
(56,17)	(57,18)	(58,19)	(59,20)	(60,21)	(61,22)	(62,23)	(63,24)	(0,25)	(1,26)	(2,27)	(3,28)	(4,29)	(5,30)	(6,31)	(7,32)
																(52,15)	(53,16)	(54,17)	(55,18)	(56,19)	(57,20)	(58,21)	(59,22)	(60,23)	(61,24)	(62,25)	(63,26)	(0,27)	(1,28)	(2,29)	(3,30)
(62,20)	(63,21)	(0,22)	(1,23)	(2,24)	(3,25)	(4,26)	(5,27)	(6,28)	(7,29)	(8,30)	(9,31)	(10,32)	(11,33)	(12,34)	(13,35)
																(58,18)	(59,19)	(60,20)	(61,21)	(62,22)	(63,23)	(0,24)	(1,25)	(2,26)	(3,27)	(4,28)	(5,29)	(6,30)	(7,31)	(8,32)	(9,33)
(54,16)	(55,17)	(56,18)	(57,19)	(58,20)	(59,21)	(60,22)	(61,23)	(62,24)	(63,25)	(0,26)	(1,27)	(2,28)	(3,29)	(4,30)	(5,31)
																(50,14)	(51,15)	(52,16)	(53,17)	(54,18)	(55,19)	(56,20)	(57,21)	(58,22)	(59,23)	(60,24)	(61,25)	(62,26)	(63,27)	(0,28)	(1,29)
(47,12)	(48,13)	(49,14)	(50,15)	(51,16)	(52,17)	(53,18)	(54,19)	(55,20)	(56,21)	(57,22)	(58,23)	(59,24)	(60,25)	(61,26)	(62,27)
																(43,10)	(44,11)	(45,12)	(46,13)	(47,14)	(48,15)	(49,16)	(50,17)	(51,18)	(52,19)	(53,20)	(54,21)	(55,22)	(56,23)	(57,24)	(58,25)
(39,8)	(40,9)	(41,10)	(42,11)	(43,12)	(44,13)	(45,14)	(46,15)	(47,16)	(48,17)	(49,18)	(50,19)	(51,20)	(52,21)	(53,22)	(54,23)
																(35,6)	(36,7)	(37,8)	(38,9)	(39,10)	(40,11)	(41,12)	(42,13)	(43,14)	(44,15)	(45,16)	(46,17)	(47,18)	(48,19)	(49,20)	(50,21)
(45,11)	(46,12)	(47,13)	(48,14)	(49,15)	(50,16)	(51,17)	(52,18)	(53,19)	(54,20)	(55,21)	(56,22)	(57,23)	(58,24)	(59,25)	(60,26)
																(41,9)	(42,10)	(43,11)	(44,12)	(45,13)	(46,14)	(47,15)	(48,16)	(49,17)	(50,18)	(51,19)	(52,20)	(53,21)	(54,22)	(55,23)	(56,24)
(37,7)	(38,8)	(39,9)	(40,10)	(41,11)	(42,12)	(43,13)	(44,14)	(45,15)	(46,16)	(47,17)	(48,18)	(49,19)	(50,20)	(51,21)	(52,22)
																(33,5)	(34,6)	(35,7)	(36,8)	(37,9)	(38,10)	(39,11)	(40,12)	(41,13)	(42,14)	(43,15)	(44,16)	(45,17)	(46,18)	(47,19)	(48,20)
(31,3)	(32,4)	(33,5)	(34,6)	(35,7)	(36,8)	(37,9)	(38,10)	(39,11)	(40,12)	(41,13)	(42,14)	(43,15)	(44,16)	(45,17)	(46,18)
																(27,1)	(28,2)	(29,3)	(30,4)	(31,5)	(32,6)	(33,7)	(34,8)	(35,9)	(36,10)	(37,11)	(38,12)	(39,13)	(40,14)	(41,15)	(42,16)
(23,63)	(24,0)	(25,1)	(26,2)	(27,3)	(28,4)	(29,5)	(30,6)	(31,7)	(32,8)	(33,9)	(34,10)	(35,11)	(36,12)	(37,13)	(38,14)
																(19,61)	(20,62)	(21,63)	(22,0)	(23,1)	(24,2)	(25,3)	(26,4)	(27,5)	(28,6)	(29,7)	(30,8)	(31,9)	(32,10)	(33,11)	(34,12)
(29,2)	(30,3)	(31,4)	(32,5)	(33,6)	(34,7)	(35,8)	(36,9)	(37,10)	(38,11)	(39,12)	(40,13)	(41,14)	(42,15)	(43,16)	(44,17)
																(25,0)	(26,1)	(27,2)	(28,3)	(29,4)	(30,5)	(31,6)	(32,7)	(33,8)	(34,9)	(35,10)	(36,11)	(37,12)	(38,13)	(39,14)	(40,15)
(21,62)	(22,63)	(23,0)	(24,1)	(25,2)	(26,3)	(27,4)	(28,5)	(29,6)	(30,7)	(31,8)	(32,9)	(33,10)	(34,11)	(35,12)	(36,13)
																(17,60)	(18,61)	(19,62)	(20,63)	(21,0)	(22,1)	(23,2)	(24,3)	(25,4)	(26,5)	(27,6)	(28,7)	(29,8)	(30,9)	(31,10)	(32,11)
(15,58)	(16,59)	(17,60)	(18,61)	(19,62)	(20,63)	(21,0)	(22,1)	(23,2)	(24,3)	(25,4)	(26,5)	(27,6)	(28,7)	(29,8)	(30,9)
																(11,56)	(12,57)	(13,58)	(14,59)	(15,60)	(16,61)	(17,62)	(18,63)	(19,0)	(20,1)	(21,2)	(22,3)	(23,4)	(24,5)	(25,6)	(26,7)
(7,54)	(8,55)	(9,56)	(10,57)	(11,58)	(12,59)	(13,60)	(14,61)	(15,62)	(16,63)	(17,0)	(18,1)	(19,2)	(20,3)	(21,4)	(22,5)
																(3,52)	(4,53)	(5,54)	(6,55)	(7,56)	(8,57)	(9,58)	(10,59)	(11,60)	(12,61)	(13,62)	(14,63)	(15,0)	(16,1)	(17,2)	(18,3)
(13,57)	(14,58)	(15,59)	(16,60)	(17,61)	(18,62)	(19,63)	(20,0)	(21,1)	(22,2)	(23,3)	(24,4)	(25,5)	(26,6)	(27,7)	(28,8)
																(9,55)	(10,56)	(11,57)	(12,58)	(13,59)	(14,60)	(15,61)	(16,62)	(17,63)	(18,0)	(19,1)	(20,2)	(21,3)	(22,4)	(23,5)	(24,6)
(5,53)	(6,54)	(7,55)	(8,56)	(9,57)	(10,58)	(11,59)	(12,60)	(13,61)	(14,62)	(15,63)	(16,0)	(17,1)	(18,2)	(19,3)	(20,4)
																(1,51)	(2,52)	(3,53)	(4,54)	(5,55)	(6,56)	(7,57)	(8,58)	(9,59)	(10,60)	(11,61)	(12,62)	(13,63)	(14,0)	(15,1)	(16,2)
(63,49)	(0,50)	(1,51)	(2,52)	(3,53)	(4,54)	(5,55)	(6,56)	(7,57)	(8,58)	(9,59)	(10,60)	(11,61)	(12,62)	(13,63)	(14,0)
																(59,47)	(60,48)	(61,49)	(62,50)	(63,51)	(0,52)	(1,53)	(2,54)	(3,55)	(4,56)	(5,57)	(6,58)	(7,59)	(8,60)	(9,61)	(10,62)
(55,45)	(56,46)	(57,47)	(58,48)	(59,49)	(60,50)	(61,51)	(62,52)	(63,53)	(0,54)	(1,55)	(2,56)	(3,57)	(4,58)	(5,59)	(6,60)
																(51,43)	(52,44)	(53,45)	(54,46)	(55,47)	(56,48)	(57,49)	(58,50)	(59,51)	(60,52)	(61,53)	(62,54)	(63,55)	(0,56)	(1,57)	(2,58)
(61,48)	(62,49)	(63,50)	(0,51)	(1,52)	(2,53)	(3,54)	(4,55)	(5,56)	(6,57)	(7,58)	(8,59)	(9,60)	(10,61)	(11,62)	(12,63)
																(57,46)	(58,47)	(59,48)	(60,49)	(61,50)	(62,51)	(63,52)	(0,53)	(1,54)	(2,55)	(3,56)	(4,57)	(5,58)	(6,59)	(7,60)	(8,61)
(53,44)	(54,45)	(55,46)	(56,47)	(57,48)	(58,49)	(59,50)	(60,51)	(61,52)	(62,53)	(63,54)	(0,55)	(1,56)	(2,57)	(3,58)	(4,59)
																(49,42)	(50,43)	(51,44)	(52,45)	(53,46)	(54,47)	(55,48)	(56,49)	(57,50)	(58,51)	(59,52)	(60,53)	(61,54)	(62,55)	(63,56)	(0,57)

TABLE 9

It should be noted that, here, only for clearly showing the third mapping table constrained by the formula (7) and the formula (8), the third mapping table is shown by the four tables of the above table 6, table 7, table 8 and table 9, and in actual use, for example, when the mapping table is stored in the sending-end device, the mapping table is an integral table, and the table 6, table 7, table 8 and table 9 are arranged in the manner shown in table 10, so as to form the third mapping table with 64 rows × 64 columns:

TABLE 6

TABLE 7

TABLE 8

TABLE 9

Watch 10

And after the position of each bit square matrix in the first matrix is transformed in the range of the bit square matrix according to the first mapping relation, a second matrix after the position transformation is obtained. The second matrix is the same size as the first matrix and comprises a plurality of bit squares of the same size as the bit squares of the first matrix. In step S202, the two first matrices obtained in step S201 are processed to obtain second matrices corresponding to the two first matrices, where the two second matrices have the same size, and for convenience of description below, the two second matrices may be respectively denoted as I0 and I1.

And S203, the sending end equipment performs position transformation of bit data among the bit square matrixes on the second matrix to obtain a third matrix.

The sending end device divides I0 and I1 into a plurality of grouping matrixes with the same size respectively in the process of carrying out bit data position conversion between bit square matrixes on the second matrix, obtains one matrix grouping of I0 and I1 respectively each time and carries out processing at the same time, executes Z times and carries out all processing on each grouping matrix. For example, if the second matrix is a matrix of 672 × Z bit rows and 128 bit columns, each of the second matrices may be divided into Z grouped matrices including 672 bit rows and 128 bit columns. Optionally, since I0 and I1 are the same in size, when the grouping matrices are obtained from I0 and I1, the position of the grouping matrix obtained from I0 in I0 is the same as the position of the grouping matrix obtained from I1 in I1.

Specifically, the sending end device includes an inter-block interleaving buffer matrix, the number of bit rows included in the inter-block interleaving buffer matrix is twice the number of bit rows included in the grouping matrix of the second matrix, and the number of bit columns included in the inter-block interleaving buffer matrix is the same as the number of bit columns of the second matrix. The inter-block interleaving buffer matrix may be divided into a plurality of bit squares of the same size as the bit square of the second matrix. For example, if the second matrix comprises 672 xZ bit rows and 128 bit columns, the inter-block interleaving buffer matrix comprises 1344 bit rows and 128 bit columns.

Taking an inter-block interleaving buffer matrix with the size of 1344 bit rows × 128 bit columns as an example, a sending end device performs position transformation between bit square arrays on bit data in a second matrix with the size of 672 × Z bit rows × 128 bit columns, the inter-block interleaving buffer matrix can be divided into a plurality of bit square arrays including 16 bit rows and 16 bit columns, the sending end device obtains one packet matrix from each of I0 and I1, places each square array row of the packet matrix obtained from I0 in sequence in an even-numbered square array row of the inter-block interleaving buffer matrix, places each square array row of the packet matrix obtained from I1 in sequence in an odd-numbered square array row of the inter-block interleaving buffer matrix, and obtains a third position transformation matrix of the bit data between the bit square arrays, and the above process is performed Z times.

And S204, the sending end equipment modulates the first symbol sequence to be sent according to the third matrix.

After the third matrix is determined, the sending end device reads the bit data from the inter-block interleaving buffer matrix according to a preset reading rule, and sequentially arranges the read bit data to obtain a second bit sequence. Before reading bit data from the inter-block interleaving buffer matrix, the bit square matrix in the inter-block interleaving buffer matrix may be divided into different square matrix sets, specifically, see fig. 4, where fig. 4 is a schematic diagram of a square matrix set of inter-block interleaving provided in the present application, and as shown in fig. 4, the square matrix rows of the inter-block interleaving buffer matrix may be divided into a 0 th square matrix set, a 1 st square matrix set, a 2 nd square matrix set, and a 3 rd square matrix set, where the 0 th square matrix set includes 2r square matrix rows in the inter-block interleaving buffer matrix, r is a non-negative integer less than 21, the 1 st square matrix set includes 2x +1 square matrix rows in the inter-block interleaving buffer matrix, x is a non-negative integer less than 21, the 2 nd square matrix set includes 2y square matrix rows in the inter-block interleaving buffer matrix, y is an integer greater than 20 and less than 42, and the 3 rd square matrix set includes 2e square matrix rows in the inter-block interleaving buffer matrix, e is an integer greater than 20 and less than 42.

128 columns are shared in the interleaving buffer matrix, each column has 1344-bit data, when the sending end device reads the bit data from the inter-block interleaving buffer matrix according to the preset reading rule, the sending end device can read according to the bit columns of the inter-block interleaving buffer matrix, the bit data in each bit column is sequentially read from the inter-block interleaving buffer matrix from left to right, and when the bit data of one bit column is read, the bit data are continuously read from the adjacent bit column on the right side until all the bit data in the inter-block interleaving buffer matrix are read. The specific process of reading the bit data in each bit column is as follows: reading the first 8 bits of bit data belonging to a 0-square array row from the bit array, sequentially reading the first 8 bits of bit data belonging to a 1-square array row from the bit array, sequentially reading the first 8 bits of bit data belonging to a 42-square array row from the bit array, and sequentially reading the first 8 bits of bit data belonging to a 43-square array row from the bit array; sequentially reading the last 8 bits of bit data belonging to the 0-square array row from the bit array, sequentially reading the last 8 bits of bit data belonging to the 1-square array row from the bit array, sequentially reading the last 8 bits of bit data belonging to the 42-square array row from the bit array, and sequentially reading the last 8 bits of bit data belonging to the 43-square array row from the bit array; and analogizing in sequence, cyclically reading 8 bits of bit data from the bit array according to the sequence of the 0 th square array set, the 1 st square array set, the 2 nd square array set and the 3 rd square array set, and reading the 8 bits of bit data of the square array set which is the top 8 bits of the bit data which is not read in the bit array every time when the 8 bits of bit data are read from the square array set until all the bit data in the bit array are read.

Here, a specified number of bits of data in the second bit sequence may be modulated into one modulation symbol, and consecutive modulation symbols constitute the first symbol sequence. The first symbol sequence may be modulated using a QAM modulation scheme, or modulated using a QPSK modulation scheme, etc. In different modulation schemes, the number of bit data corresponding to one modulation symbol is different.

For example, 16QAM is a QAM modulation scheme including 16 symbols, in a dual-polarization 16QAM modulation scheme (i.e., DP-16QAM modulation), there are 16 symbols in any polarization direction, and the 16 symbols are represented by two bit pairs, one bit pair represents an I component (in-phase component) in a complex plane, and the other bit pair represents a Q component (quadrature component) in the complex plane, see fig. 5, fig. 5 is a constellation diagram of a 16QAM provided in an embodiment of the present application, and the 16 symbols respectively correspond to different points in the complex plane and are mapped to points corresponding to different symbols in the complex plane by different values of the two bit pairs, and fig. 5 shows corresponding points of the 16 symbols in any polarization direction in the complex plane. In one mode, the correspondence between binary bit pairs and symbol amplitudes may be: (0,0) → -3, (0,1) → -1, (1,1) → 1, (1,0) → 3, and if an I component and a Q component of a certain symbol in a certain polarization direction are (1,1) and (0,1), the symbol corresponds to a point 1 in fig. 5 in the polarization direction, and the symbol phase and amplitude are determined from the point 1. In another way, the correspondence between binary bit pairs and symbol amplitudes may be: (0,0) → 3, (0,1) → 1, (1,1) → -1, (1,0) → -3, and if the I component and the Q component of a certain symbol in a certain polarization direction are (1,1) and (0,1), the symbol corresponds to a point 2 in fig. 5 in the polarization direction, and the phase and the amplitude of the symbol are determined from the point 2.

For another example, QPSK is a modulation scheme for representing an input digital signal by using four different phase differences of a carrier, and defines four carrier phases, and in order to match a quaternary carrier phase, binary data needs to be converted into quaternary data, and the quaternary data is represented by 4 corresponding symbols. In a dual-polarization QPSK modulation scheme (i.e., DP-QPSK modulation), there are 4 symbols in any polarization direction, where the 4 symbols are determined by different values of a bit pair, one bit in the bit pair represents an I component in a complex plane, and the other bit represents a Q component in the complex plane, see fig. 6, where fig. 6 is a constellation diagram of QPSK provided in an embodiment of the present application, where the 4 symbols respectively correspond to different points in the complex plane, and are mapped to points corresponding to different symbols in the complex plane through different values of the bit pair, and fig. 6 shows corresponding points of the 4 symbols in any polarization direction in the complex plane. In one mode, the binary bit-to-symbol amplitude correspondence may be: (0) → 1, (1) → 1, if the I component and the Q component of a symbol in a polarization direction are (1) and (0), the symbol corresponds to point 3 in fig. 6 in the polarization direction, and the phase of the symbol is determined according to point 3. In another way, the binary bit-to-symbol amplitude correspondence may be: (0) → 1, (1) → -1, if the I component and the Q component of a symbol in a polarization direction are (1) and (0), the symbol corresponds to the point 4 in fig. 6 in the polarization direction, and the phase of the symbol is determined according to the point 4.

In the process of mapping the bit data in the second bit sequence to the modulation symbol, the bit data needs to be obtained from the second bit sequence first, and is determined as the component of the modulation symbol in the complex plane. In one mode, when the modulation mode is modulation in the dual polarization direction, a specified number of adjacent bit data in the second bit sequence may be determined as components of the same modulation symbol in the same polarization direction. In another mode, when the modulation mode is modulation in the dual polarization direction, a specified number of bit data spaced in the second bit sequence may be determined as components of the same modulation symbol in the same polarization direction.

For example, referring to fig. 7, fig. 7 is a schematic diagram of a bit sequence provided in this embodiment of the present application, as shown in fig. 7, b0 to b7 are first eight bits of data of a second bit sequence, and if the modulation scheme employs 16QAM modulation in two polarization directions, namely, the X direction and the Y direction, each polarization direction requires 4 bits of data for mapping, the bit pair (b0, b1) may be determined as an I component of a symbol 0 in the X polarization direction, the bit pair (b2, b3) may be determined as a Q component of the symbol 0 in the X polarization direction, the bit pair (b4, b5) may be determined as an I component of the symbol 0 in the Y polarization direction, the bit pair (b6, b7) may be determined as a Q component of the symbol 0 in the Y polarization direction, and so on, and components corresponding to each symbol are sequentially obtained from the bit sequence. If the modulation scheme adopts QPSK modulation in both the X and Y directions, and each polarization direction requires 2 bits of bit data for mapping, (b0) may be determined as an I component of symbol 0 in the X polarization direction, (b1) may be determined as a Q component of symbol 0 in the X polarization direction, (b2) may be determined as an I component of symbol 0 in the Y polarization direction, and (b3) may be determined as a Q component of symbol 0 in the Y polarization direction; determining (b4) as an I component of the symbol 1 in the X polarization direction, (b5) as a Q component of the symbol 1 in the X polarization direction, (b6) as an I component of the symbol 1 in the Y polarization direction, and (b7) as a Q component of the symbol 1 in the Y polarization direction; and by analogy, obtaining the components corresponding to the symbols from the second bit sequence in sequence.

It is easy to see that, if the sending end device adopts a mode of determining the specified number of bit data at intervals in the second bit sequence as the components of the same modulation symbol in the same polarization direction, the bit data in the bit sequence can be further dispersed on the basis of performing the position conversion of the bit data, so that a certain anti-burst capability can be improved, and if the sending end device adopts a mode of determining the specified number of bit data adjacent to each other in the second bit sequence as the components of the same modulation symbol in the same polarization direction, because the continuous bit data are mapped into the components of the same symbol, the mode has higher performance requirements on the dispersion degree and the uniformity degree of the position conversion of the bit data performed by the sending end device.

In the process of modulating the second bit sequence, in an optional implementation, a specified number of adjacent bit data in the second bit sequence may be determined as components of the same modulation symbol in the same polarization direction.

In an optional implementation manner, the second bit sequence may be modulated in a dual-polarization quadrature amplitude modulation manner, and may also be modulated in a dual-polarization quadrature phase shift keying manner.

In an optional specific implementation, in the process of modulating the second bit sequence by the dual-polarization quadrature phase shift keying manner, each adjacent four-bit data in the second bit sequence may be determined as one first modulation mapping unit according to a sequence from front to back, and the bit data in each first modulation mapping unit is used for modulating the same modulation symbol. For any first target modulation mapping unit in the first modulation mapping units, the first two bits of data in the first target modulation mapping unit may be mapped to be a component of the first modulation symbol in the X polarization direction, the last two bits of data in the first target modulation unit may be mapped to be a component of the first modulation symbol in the Y polarization direction, and the first modulation symbol may be modulated according to the component of the first modulation symbol in the X polarization direction and the component of the first modulation symbol in the Y polarization direction.

For example, if the second bit sequence is C_t，C_tIs 172032 × 4 bits, C_t＝{c_0,0,c_0,1,c_0,2,c_0,3,c_1,0,c_1,1,c_1,2,c_1,3,…,c₁₇₂₀₃₁,0_,172031,1,c_172031,2,c_172031,3In the order from front to back, C_tEvery adjacent four bits of data in the sequence are determined as a first modulation mapping unit to obtain C_t＝{{c_0,0,c_0,1,c_0,2,c_0,3},{c_1,0,c_1,1,c_1,2,c_1,3},…,{c_{172031,0,172031,1},c_172031,2,c_172031,3}, such as { c }_0,0,c_0,1,c_0,2,c_0,3Is a first modulation unit, { c_1,0,c_1,1,c_1,2,c_1,3Is a first modulation unit, { c_{172031,0,172031,1},c_172031,2,c_172031,3Is a first modulation unit. Optionally, an arrangement order of the bit data in the first modulation unit is the same as an arrangement order of the bit data in the second bit sequence. The bit data in the second bit sequence can be modulated to obtain a modulation symbol sequence S_t，S_t＝{s₀,s₁,…,s₁₇₂₀₃₁}。

For any one first modulation unit c_i＝{c_i,0,c_i,1,c_i,2,c_i,3B, the bit data contained therein can be correspondingly modulated into a modulation symbol s_iWhere i is a non-negative integer less than 172032, (c) may be_i,0,c_i,1) Determined as a modulation symbol s_iComponent in the X polarization direction will be (c)_i,2,c_i,3) Determined as a modulation symbol s_iThe component in the Y polarization direction, specifically, (c) may be_i,0) Determined as a modulation symbol s_iThe I component in the X polarization direction will be (c)_i,1) Determined as a modulation symbol s_iThe Q component in the X polarization direction will be (c)_i,2) Determined as a modulation symbol s_iI component in Y polarization directionIs prepared from (c)_i,3) Determined as a modulation symbol s_iThe Q component in the Y polarization direction. And then according to the modulation symbol s_iModulation symbol s of I component in X polarization direction, Q component in X polarization direction, I component in Y polarization direction, and Q component in Y polarization direction_i。

In another optional specific implementation, in the process of modulating the second bit sequence by the dual-polarization quadrature phase shift keying manner, each adjacent eight-bit data in the second bit sequence may be determined as one second modulation mapping unit according to a front-to-back order, and the bit data in each second modulation mapping unit is used for modulating two modulation symbols. For any one of the second target modulation mapping units, the first two bits of bit data in the second target modulation mapping unit may be mapped to a component of the second modulation symbol in the X polarization direction, the third and fourth bits of bit data in the second target modulation unit may be mapped to a component of the third modulation symbol in the X polarization direction, the fifth and sixth bits of bit data in the second target modulation unit may be mapped to a component of the second modulation symbol in the Y polarization direction, and the seventh and eighth bits of bit data in the second target modulation unit may be mapped to a component of the third modulation symbol in the Y polarization direction. And modulating the second modulation symbol according to the component of the second modulation symbol in the X polarization direction and the component of the second modulation symbol in the Y polarization direction, and modulating the third modulation symbol according to the component of the third modulation symbol in the X polarization direction and the component of the third modulation symbol in the Y polarization direction.

For example, if the second bit sequence is C_t，C_tIs 172032 × 4 bits, C_t＝{c_0,0,c_0,1,…,c_0,7,c_1,0,c_1,1,c_1,2,…,c_1,7,…,c_86015,0,c_86015,1,…,c_86015,7In the order from front to back, C_tEvery adjacent eight-bit data is determined as a second modulation mapping unit to obtain C_t＝{{c_0,0,c_0,1,…,c_0,7},{c_1,0,c_1,1,…,c_1,7},…,{c_86015,0,c_86015,1,…,c_86015,7}, such as { c }_0,0,c_0,1,…,c_0,7Is a second modulation unit, { c_1,0,c_1,1,…,c_1,7Is a second modulation unit, { c_86015,0,c_86015,1,…,c_86015,7Is a second modulation unit. Optionally, the arrangement order of the bit data in the second modulation unit is the same as the arrangement order of the bit data in the second bit sequence. The bit data in the second bit sequence can be modulated to obtain a modulation symbol sequence S_t，S_t＝{s₀,s₁,…,s₁₇₂₀₃₁}。

For any one second modulation unit c_i＝{c_i,0,c_i,1,c_i,2,c_i,3,c_i,4,c_i,5,c_i,6,c_i,7B, the bit data contained therein can be correspondingly modulated into two modulation symbols s_2iAnd s_2i+1Wherein i is a non-negative integer less than 86016, or (c)_i,0,c_i,1) Determined as a modulation symbol s_2iComponent in the X polarization direction will be (c)_i,2,c_i,3) Determined as a modulation symbol s_2i+1Component in the X polarization direction will be (c)_i,4,c_i,5) Determined as a modulation symbol s_2iComponent in the Y polarization direction will be (c)_i,6,c_i,7) Determined as a modulation symbol s_2i+1The component in the Y polarization direction. Specifically, (c) can be_i,0) Determined as a modulation symbol s_2iThe I component in the X polarization direction will be (c)_i,1) Determined as a modulation symbol s_2iThe Q component in the X polarization direction will be (c)_i,2) Determined as a modulation symbol s_2i+1The I component in the X polarization direction will be (c)_i,3) Determined as a modulation symbol s_2i+1The Q component in the X polarization direction will be (c)_i,4) Determined as a modulation symbol s_2iThe I component in the Y polarization direction will be (c)_i,5) Determined as a modulation symbol s_2iThe Q component in the Y polarization direction will be (c)_i,6) Determined as a modulation symbol s_2i+1The I component in the Y polarization direction will be (c)_i,7) Determined as a modulation symbol s_2i+1The Q component in the Y polarization direction. And then according to the modulation symbol s_2iModulation symbol s of I component in X polarization direction, Q component in X polarization direction, I component in Y polarization direction, and Q component in Y polarization direction_2iAccording to the modulation symbol s_2i+1Modulation symbol s of I component in X polarization direction, Q component in X polarization direction, I component in Y polarization direction, and Q component in Y polarization direction_2i+1。

In yet another alternative specific implementation, in the process of modulating the second bit sequence by the dual-polarization quadrature amplitude modulation method, each adjacent eight-bit data in the second bit sequence may be determined as one third modulation mapping unit in the order from front to back, and the bit data in each third modulation mapping unit is used for modulating the same modulation symbol. For any third target modulation unit in the third modulation mapping unit, mapping the first four bits of bit data in the third target modulation mapping unit to a component of the fourth modulation symbol in the X polarization direction, mapping the second four bits of bit data in the third target modulation mapping unit to a component of the fourth modulation symbol in the Y polarization direction, specifically, mapping the first two bits of bit data in the first four bits of bit data to an I component of the fourth modulation symbol in the X polarization direction, mapping the second two bits of bit data in the first four bits of bit data to a Q component of the fourth modulation symbol in the X polarization direction, determining the first two bits of bit data in the second four bits of bit data to an I component of the fourth modulation symbol in the Y direction, and determining the second two bits of bit data in the second four bits of bit data to a Q component of the fourth modulation symbol in the Y direction. And modulating the fourth modulation symbol according to the component of the fourth modulation symbol in the X polarization direction and the component of the fourth modulation symbol in the Y polarization direction.

For example, if the second bit sequence is C_t，C_tIs 172032 × 8 bits, C_t＝{c_0,0,c_0,1,…,c_0,7,c_1,0,c_1,1,…c_1,7,…,c_172031,0,c_172031,1,…,c_172031,7In the order from front to back, C_tEvery adjacent eight-bit data is determined as a third modulation mapping unit to obtain C_t＝{{c_0,0,c_0,1,…,c_0,7},{c_1,0,c_1,1,…,c_1,7},…,{c_172031,0,c_172031,1,…c_172031,7}, such as { c }_0,0,c_0,1,…,c_0,7Is a third modulation unit, { c }_1,0,c_1,1,…,c_1,7Is a third modulation unit, { c }_172031,0,c_172031,1,…c_172031,7Is a third modulation unit. Optionally, the arrangement order of the bit data in the third modulation unit is the same as the arrangement order of the bit data in the second bit sequence. The bit data in the second bit sequence can be modulated to obtain a modulation symbol sequence S_t，S_t＝{s₀,s₁,…,s₁₇₂₀₃₁}。

For any one third modulation unit c_i＝{c_i,0,c_i,1,c_i,2,c_i,3,c_i,4,c_i,5,c_i,6,c_i,7B, the bit data contained therein can be correspondingly modulated into a modulation symbol s_iWhere i is a non-negative integer less than 172032, (c) may be_i,0,c_i,1,c_i,2,c_i,3) Determined as a modulation symbol s_iComponent in the X polarization direction will be (c)_i,4,c_i,5,c_i,6,c_i,7) Determined as a modulation symbol s_iThe component in the Y polarization direction. Specifically, (c) can be_i,0,c_i,1) Determined as a modulation symbol s_iThe I component in the X polarization direction will be (c)_i,2,c_i,3) Determined as a modulation symbol s_iThe Q component in the X polarization direction will be (c)_i,4,c_i,5) Determined as a modulation symbol s_iThe I component in the Y polarization direction will be (c)_i,6,c_i,7) Determined as a modulation symbol s_iThe Q component in the Y polarization direction. And then according to the modulation symbol s_iAt XModulation symbol s of I component in polarization direction, Q component in X polarization direction, I component in Y polarization direction, and Q component in Y polarization direction_i。

Through steps S201 to S204, the sending end device encodes the input first bit sequence to obtain a first matrix, performs position transformation in the bit matrix direction of each bit matrix in the first matrix according to the first mapping relationship to obtain a second matrix, performs position transformation of bit data between each bit matrix in the second matrix to determine a second bit sequence, and modulates the first symbol sequence to be sent according to the second bit sequence. The first mapping relation is used for indicating the position mapping relation of each bit data before position conversion and after position change in the range of the bit square matrix, and comprises a row conversion mapping relation and a column conversion mapping relation. The line transformation mapping relation is constrained by a global migration constraint factor and at least two local migration constraint factors, the global migration constraint factor is used for constraining the position migration amount of each bit data line transformation in the bit matrix, and the local migration constraint factor is used for constraining the position migration amount of the bit data line transformation in a part of bit lines in the bit matrix. The position offset of the bit data row transformation in different bit rows is subjected to targeted and diversified constraint through the global offset constraint factor and the at least two local offset constraint factors, so that the bit data in the first matrix is subjected to position transformation more discretely and more uniformly, and the burst resistance of information transmission is improved.

S205, the sending end device sends the first symbol sequence to the receiving end device.

Specifically, the receiving end device may send the first symbol sequence to the receiving end device through an optical network transmission channel.

And S206, the receiving end equipment demodulates the first symbol sequence to obtain a fourth matrix.

The receiving end device demodulates the received first symbol sequence in a demodulation manner corresponding to a modulation manner adopted by the transmitting end to modulate the first symbol sequence, for example, if the transmitting end device modulates the first symbol sequence in a QAM modulation manner, the receiving end device also demodulates the received first symbol sequence in a QAM demodulation manner, and if the transmitting end device modulates the first symbol sequence in a QPSK modulation manner, the receiving end device also demodulates the received first symbol sequence in a QPSK demodulation manner.

The first symbol sequence comprises a plurality of modulation symbols, the receiving end device demodulates each modulation symbol to obtain a component of each modulation symbol corresponding to the complex plane, and further determines corresponding bit data according to the component of the complex plane, wherein the number of the bit data corresponding to one modulation symbol is different in different modulation modes.

For example, if the demodulation mode is a QAM demodulation mode, the receiving end device determines, for any modulation symbol, a corresponding point in the complex plane according to the corresponding phase and amplitude, and further determines an I component and a Q component of the point in the complex plane, and determines, according to the amplitude of the I component and a mapping relationship between a preset amplitude and a binary bit pair, a bit pair corresponding to the I component, and similarly determines a bit pair corresponding to the Q component, where the bit pair corresponding to each of the I component and the Q component is four bit data corresponding to the symbol. The preset mapping relationship between the amplitude and the binary bit pair is the same as the mapping relationship between the amplitude and the binary bit pair adopted by the sending end device when modulating the first symbol sequence.

For another example, if the demodulation method is QPSK, the receiving end device determines, for an arbitrary modulation symbol, a corresponding point in the complex plane according to the corresponding phase, and further determines an I component and a Q component of the point in the complex plane, and determines, according to the amplitude of the I component and a mapping relationship between a preset amplitude and a binary bit, bit data corresponding to the I component, and similarly determines bit data corresponding to the Q component, where bits corresponding to each of the I component and the Q component are two bit data corresponding to the symbol. The preset mapping relationship between the amplitude and the binary bit is the same as the mapping relationship between the amplitude and the binary bit adopted by the sending end device when modulating the first symbol sequence.

After the bit data corresponding to the modulation symbols are determined, the receiving end device needs to place the bit data corresponding to each modulation symbol in a demodulation bit sequence, where there are many different placement modes. For example, when the demodulation scheme is demodulation in dual polarization directions, in one scheme, components of the same modulation symbol in the same polarization direction may be placed at adjacent positions in the demodulated bit sequence, and in another scheme, components of the same modulation symbol in the same polarization direction may be placed at spaced positions in the demodulated bit sequence.

Specifically, the receiving end device includes an inter-block de-interleaving buffer matrix with the same size as the inter-block interleaving matrix of the sending end device, the inter-block de-interleaving buffer matrix has the same bit square matrix dividing mode as the inter-block interleaving buffer matrix, and the inter-block de-interleaving matrix can be divided into bit square matrices with the same size. The receiving end device can divide the demodulated bit sequence into different groups according to the number of the bit data contained in the inter-block de-interleaving buffer matrix, and the different groups are sequentially placed in the de-interleaving matrix buffer matrix for processing. For example, the length of the demodulated bit sequence is 172032 × Z, the inter-block deinterleaving matrix can accommodate a data amount of 17032 bits, and can be divided into Z packets, and bit data of 172032 bits is processed in each packet, and the processing is performed Z times cyclically for one demodulated bit sequence.

Taking an inter-block de-interleaving buffer matrix with the size of 1344 bit rows × 128 bit columns as an example, a determination manner of the receiving end device for a fourth matrix corresponding to each packet in the demodulated bit sequence is introduced, the inter-block de-interleaving buffer matrix may be pre-divided into a 0 th square matrix set, a 1 st square matrix set, a 2 nd square matrix set and a 3 rd square matrix set, the 0 th square matrix set comprises 2a square matrix rows in the inter-block de-interleaving cache matrix, a is a non-negative integer smaller than 21, the 1 st square matrix set comprises 2b +1 square matrix rows in the inter-block de-interleaving cache matrix, b is a non-negative integer smaller than 21, the 2 nd square matrix set comprises 2c square matrix rows in the inter-block de-interleaving cache matrix, c is an integer larger than 20 and smaller than 42, the 3 rd square matrix set comprises 2d square matrix rows in the inter-block de-interleaving cache matrix, and d is an integer larger than 20 and smaller than 42. The way of dividing the inter-block de-interleaving buffer matrix into the square matrix set is similar to the way of dividing the inter-block de-interleaving buffer matrix into the square matrix set, and the matrix in fig. 4 can also be regarded as the inter-block de-interleaving buffer matrix after the square matrix set is divided.

And bit data filling in columns is carried out on the inter-block de-interleaving buffer matrix, bit columns are sequentially filled in the inter-block de-interleaving buffer matrix from left to right, and when one bit column is filled, the bit column adjacent to the right side is continuously filled until all the bit columns in the inter-block de-interleaving buffer matrix are filled.

The specific process of filling the bit data in each bit column may be: acquiring first 8 bits of bit data from a bit sequence, sequentially filling 0 square matrix lines in the 8 bit lines at the top of the bit sequence, acquiring 9 th to 16 th bits of bit data from the bit sequence, sequentially filling 1 square matrix lines in the 8 bit lines at the top of the bit sequence, acquiring 17 th to 24 th bits of bit data from the bit sequence, sequentially filling 42 square matrix lines in the 8 bit lines at the top of the bit sequence, acquiring 25 th to 32 th bits of bit data from the bit sequence, and sequentially filling 43 square matrix lines in the 8 bit lines at the top of the bit sequence; acquiring 33 th bit to 40 th bit data from a bit sequence, sequentially filling a 0 th square matrix row in the 8 lowest bit rows of the bit sequence, acquiring 41 th bit to 48 th bit data from the bit sequence, sequentially filling a 1 st square matrix row in the 8 lowest bit rows of the bit sequence, acquiring 49 th bit to 56 th bit data from the bit sequence, sequentially filling a 42 th square matrix row in the 8 lowest bit rows of the bit sequence, acquiring 57 th bit to 64 th bit data from the bit sequence, and sequentially filling a 43 th square matrix row in the 8 lowest bit rows of the bit sequence; and analogizing in sequence, filling 8 bits of data sequentially obtained from the bit sequence circularly according to the sequence of a 0 th square matrix set, a 1 st square matrix set, a 2 nd square matrix set and a 3 rd square matrix set, filling 8 bits of data in bit rows of the square matrix sets which are not filled in the bit array and the 8 most upper bit rows each time 8 bits of data are filled in each square matrix set until the inter-block de-interleaving cache matrix is filled, and obtaining a fourth matrix corresponding to the group.

And S207, the receiving terminal equipment performs position transformation of bit data among the bit square matrixes on the fourth matrix to obtain a fifth matrix.

The sending terminal equipment also comprises two intra-block de-interleaving buffer matrixes (marked as I '0 and I' 1), the intra-block de-interleaving buffer matrixes can also be divided into bit square matrixes with the same size as the inter-block de-interleaving buffer matrixes, the number of square matrix rows in the intra-block de-interleaving buffer matrixes is z/2 times of the number of square matrix rows in the inter-block de-interleaving buffer matrixes, and the number of bit columns in the intra-block de-interleaving buffer matrixes is the same as the number of bit columns in the inter-block de-interleaving buffer matrixes. After the sending end equipment determines a fourth matrix of any one group of the demodulation coding matrix, bit data of an even number square matrix row in the fourth matrix are sequentially filled in an upper square matrix row in an unfilled square matrix row in I '0, bit data of an odd number square matrix row in the fourth matrix are sequentially filled in an upper square matrix row in an unfilled square matrix row in I' 1 until a Z-time filling process of the inter-block de-interleaving cache matrix is executed, the I '0 and the I' 1 are respectively filled, position conversion between bit square matrixes of the bit data of each bit square matrix in the fourth matrix is completed, and the filled I '0 and I' 1 are the obtained fifth matrix.

And S208, the receiving end equipment carries out position transformation in the direction of each bit square matrix aiming at the bit data of each bit square matrix in the fifth matrix according to the second mapping relation to obtain a transformed sixth matrix.

And for any one fifth matrix, the receiving end equipment acquires any one bit square matrix, and performs position transformation of bit data in the range of the bit square matrix by taking the bit square matrix as a unit to obtain a sixth matrix after the position transformation of the bit data of each bit square matrix in the bit square matrix. In a specific implementation, the receiving end device may perform position transformation of the bit data within the bit matrix range according to a preset second mapping relationship. The second mapping relationship may be the same as the first mapping relationship used when the transmitting-end device performs the position conversion of the bit data within the bit matrix range, or may be a mapping relationship opposite to the first mapping relationship used when the transmitting-end device performs the position conversion of the bit data within the bit matrix range.

For example, if the second mapping relationship is the same as the first mapping relationship used when the transmitting-side device performs the position conversion of the bit data within the bit matrix range, and if the first mapping relationship is used to instruct the transmitting-side device to convert the bit data located at the positions of 0 bit row and 2 bit column to the positions of 1 bit row and 4 bit column in the bit matrix, the second mapping relationship (also referred to as the first mapping relationship) in the receiving-side device is used to instruct the receiving-side device to convert the bit data located at the positions of 1 bit row and 4 bit column in the bit matrix to the positions of 0 bit row and 2 bit column. If the second mapping relationship is a mapping relationship opposite to the first mapping relationship used when the transmitting-end device performs the position conversion of the bit data within the range of the bit square array, if the first mapping relationship includes the instruction information for converting the bit data located at the positions of the 0-bit row and the 2-bit column to the positions of the 1-bit row and the 4-bit column in the bit square array, the second mapping relationship inevitably includes the instruction information for converting the bit data located at the positions of the 1-bit row and the 4-bit column in the bit square array to the positions of the 0-bit row and the 2-bit column in the bit square array.

That is, the row transformation mapping relationship in the second mapping relationship may also be constrained by the global offset constraint factor and the at least two local offset constraint factors, and in an optional manner, may also be constrained by the start offset parameter. It can be understood that, in the second mapping relationship, values of the constraint parameters are equal to values of the first mapping relationship of the sending-end device.

In an optional manner, the global offset constraint factor, the local offset constraint factor, and the start offset parameter constrain the row transformation mapping relationship of the second mapping relationship by the following formula:

wherein r is₀Identifying corresponding row identification after the position of the first bit data in the bit square matrix is changed in the range of the bit square matrix, wherein the first bit data is any bit data in the bit square matrix of the fifth matrix, r₁For the corresponding row identification of the first bit data before the position change within the bit matrix, c₁The method comprises the steps that corresponding column identification is carried out on first bit data before position transformation in a bit square matrix range, g is a global offset constraint factor, beta is a local offset constraint factor, alpha is an initial offset parameter, g, beta and alpha are all preset integers, k is index identification of beta, the value of g is determined according to 2 lambada p, and p is an integer larger than 1.

Optionally, the first mapping relationship further includes a column transformation mapping relationship, and the column transformation mapping relationship is constrained by the following formula:

wherein, c₀Column identification corresponding to the first bit data after position conversion in the bit matrix range, r1 row identification corresponding to the first bit data before position conversion in the bit matrix range, c₁And h, gamma and theta are preset integers, and w is an index mark of gamma, wherein the corresponding column mark is the corresponding column mark before the position of the first bit data is changed in the range of the bit square matrix.

The values of the parameters in the formula (9) and the formula (10) are the same as the value ranges in the formula constraining the first mapping relationship in the sending end device, for example, the value of β in the formula (9) may also satisfy the corresponding descriptions in table 1 and table 2, and details are not repeated here. Furthermore, the formula (9) and the formula (10) are only a constraint form of the row transformation mapping relationship and the column transformation mapping relationship in the second mapping relationship, respectively, and the formula corresponding to other modified formulas also belongs to the protection scope of the present application

And S209, the receiving end equipment decodes the sixth matrix to obtain a third bit sequence.

And after the sixth matrix corresponding to any one fifth matrix is determined, processing the sixth matrix into a form of a decoding bit sequence for decoding. Specifically, for the sixth matrix, bit data is read every two square matrix rows, when the bit data of the two square matrix rows is read, the bit data is read according to the square array, when the bit square matrix in the square pin array is read, the bit data is sequentially read according to the bit rows in the bit square array, and all the bit data in the obtained sixth matrix is sequentially read according to the method to obtain a corresponding third bit sequence.

Referring to fig. 2, the matrix shown in fig. 2 can be regarded as a sixth matrix of the receiving end device, and the labels of the matrices in fig. 2 can be regarded as the order of the bit sequences after the bit data at the corresponding positions are read, for example, the bit square matrix located in 0 square matrix row and 0 square array in fig. 2, the bit data in the first bit row is read and then sequentially placed at the positions of 0 to 15 bits in the decoded bit sequence (where 0 bit represents the first bit in the bit sequence), the bit data in the second bit row is read and then sequentially placed at the positions of 16 to 31 bits in the decoded bit sequence, and then sequentially read downwards until the bit data in the sixteenth bit row is read and then sequentially placed at the positions of 240 to 255 bits in the decoded bit sequence, bit data in the bit square matrix of the 0 square matrix row and the 0 square matrix are all read; and further reading the bit data in the bit square matrix of the 1 square matrix row and the 0 square matrix (the bit data in the bit square matrix is placed at the position of 256-511 in the bit sequence) in the same manner, reading the bit data in the bit square matrix of the 0 square matrix row and the 1 square matrix (the bit data in the bit square matrix is placed at the position of 512-767 in the decoded bit sequence), and repeating the steps until the bit data in the bit square matrix of the 1 square matrix row and the 7 square matrix are read, placing the bit data at the position of 3840-4095 in the decoded bit sequence, reading every two square matrix rows by one unit in the same manner until all the bit data in the matrix are read, and obtaining a third bit sequence.

After the third bit sequence is determined, the receiving end equipment decodes the third bit sequence, and recovers the information to be transmitted by the sending end equipment, wherein the decoding mode of the information is matched with the encoding mode of the sending end equipment.

Through steps S206 to S209, the receiving end device demodulates the received first symbol sequence, determines a fourth matrix according to the demodulated bit sequence, performs position transformation of bit data between bit square matrices on the fourth matrix to obtain a fifth matrix, further performs position transformation in the bit square matrix orientation of each bit square matrix in the fifth matrix according to the second mapping relationship to obtain a transformed sixth matrix, and decodes according to the sixth matrix to obtain a third bit sequence. The second mapping relationship may be the same as the first mapping relationship used when the sending-end device performs the position conversion of the bit data within the bit matrix range, or may be the opposite mapping relationship to the first mapping relationship used when the sending-end device performs the position conversion of the bit data within the bit matrix range. The second mapping relation is constrained by a global offset constraint factor and at least two local offset constraint factors, and information data which originally belongs to the same matrix row (namely, the information data which belongs to the same matrix row before the position of bit data in the bit square matrix is transformed by the sending end equipment) and is scattered at different rows in the matrix (the information data which is scattered to different rows in the matrix after the position of the bit data in the bit square matrix is transformed by the sending end equipment) is recovered into the same matrix row.

Referring to fig. 8, fig. 8 is a flowchart illustrating another communication method provided in this embodiment, where the communication method may be executed by a sending end device in a communication network, and as shown in fig. 8, the method may include steps S801 to S804.

S801, coding a first bit sequence to be transmitted to obtain a first matrix.

The first matrix includes a plurality of bit squares of the same size, each bit square including a plurality of bit data.

Optionally, the first bit sequence to be transmitted is encoded to obtain two parallel bit sequences, and the parallel bit sequences are converted into a matrix form to obtain a first matrix. The specific implementation manner may refer to the specific implementation manner in step S201 in the embodiment corresponding to fig. 2, and is not described herein again.

In one implementation, the merging bit sequence may be obtained by an encoder in the sending end device, and the first matrix may be obtained by an interleaver in the sending end device.

S802, according to the first mapping relation, aiming at the bit data of each bit square matrix in the first matrix, position transformation in the range of each bit square matrix is carried out to obtain a second matrix.

The first mapping relation is used for indicating the position mapping relation of each bit data before and after position transformation in the range of the bit square matrix, the first mapping relation comprises a row transformation mapping relation, the row transformation mapping relation is restrained by a global offset restraining factor and at least two local offset restraining factors, the global offset restraining factor is used for restraining the position offset of each bit data row transformation in the bit square matrix, and the local offset restraining factor is used for restraining the position offset of the bit data row transformation in a part of bit rows in the bit square matrix.

The specific implementation manner may refer to the specific implementation manner in step S202 in the embodiment corresponding to fig. 2, and is not described herein again.

In one implementation, the second matrix may be obtained by an interleaver in the transmitting end device.

S803, the position of the bit data between the bit square matrices is transformed for the second matrix, and a third matrix is obtained.

The specific implementation manner may refer to a specific implementation manner in step S203 in the embodiment corresponding to fig. 2, and is not described herein again. In one implementation, the second matrix may be obtained by an interleaver in the transmitting end device.

And S804, modulating the first symbol sequence to be transmitted according to the third matrix.

Optionally, after the third matrix is obtained, the third matrix is converted into a form of a bit sequence to obtain a second bit sequence, and then modulation is performed according to the second bit sequence to obtain the first symbol sequence. The specific implementation manner may refer to the specific implementation manner in step S204 in the embodiment corresponding to fig. 2, and is not described herein again.

In one implementation, the second bit sequence may be obtained by an interleaver in the sending end device, and the first symbol sequence may be obtained by a modulator in the sending end device.

In this embodiment, after encoding an input first bit sequence, a sending end device obtains a first matrix, performs position transformation in the bit matrix direction of each bit square matrix in the first matrix according to a first mapping relationship to obtain a second matrix, performs position transformation of bit data between each bit square matrix in the second matrix to determine a second bit sequence, and modulates a first symbol sequence to be sent according to the second bit sequence. The first mapping relation is used for indicating the position mapping relation of each bit data before position conversion and after position change in the range of the bit square matrix, and comprises a row conversion mapping relation and a column conversion mapping relation. The line transformation mapping relation is constrained by a global migration constraint factor and at least two local migration constraint factors, the global migration constraint factor is used for constraining the position migration amount of each bit data line transformation in the bit matrix, and the local migration constraint factor is used for constraining the position migration amount of the bit data line transformation in a part of bit lines in the bit matrix. The position offset of the bit data row transformation in different bit rows is subjected to targeted and diversified constraint through the global offset constraint factor and the at least two local offset constraint factors, so that the bit data in the first matrix is subjected to position transformation more discretely and more uniformly, and the burst resistance of information transmission is improved.

Referring to fig. 9, fig. 9 is a flowchart illustrating another communication method provided in this embodiment, which may be executed by a receiving end device in a communication network, as shown in fig. 9, the method may include steps S901 to S904.

S901 demodulates the received first symbol sequence to obtain a first matrix.

The first matrix includes a plurality of bit squares of the same size, each bit square including a plurality of bit data.

The receiving end device demodulates the first symbol sequence to obtain a demodulated bit sequence, and then converts the demodulated bit sequence into a matrix form to obtain a first matrix. The specific implementation manner of demodulating the first symbol in step S206 to obtain the fourth matrix in the embodiment corresponding to fig. 2 may be referred to, and details are not described here.

In one implementation, the first matrix may be obtained by a demodulator in the receiving end device.

S902, carrying out position transformation of bit data among the bit square matrixes on the first matrix to obtain a second matrix.

The specific implementation manner may refer to the specific implementation manner of performing position transformation on bit data between each bit square matrix on the fourth matrix in step S207 in the embodiment corresponding to fig. 2 to obtain the fifth matrix, which is not described herein again. In one implementation, the second matrix may be obtained by a deinterleaver in the receiving end device.

And S903, according to the first mapping relation, carrying out position transformation in the bit square matrix direction of each bit data of each bit square matrix in the second matrix to obtain a transformed third matrix.

The first mapping relation is used for indicating the position mapping relation of each bit data before and after position transformation in the range of the bit square matrix, the first mapping relation comprises a row transformation mapping relation, the row transformation mapping relation is restrained by a global offset restraining factor and at least two local offset restraining factors, the global offset restraining factor is used for restraining the position offset of each bit data row transformation in the bit square matrix, and the local offset restraining factor is used for restraining the position offset of bit data row transformation in a part of bit rows in the bit square matrix.

For a specific implementation manner, referring to the second mapping relationship in step S208 in the embodiment corresponding to fig. 2, for the bit data of each bit square matrix in the fifth matrix, position transformation in the direction of each bit square matrix is performed to obtain a specific implementation manner of the transformed sixth matrix, which is not described herein again.

In one implementation, the second matrix may be obtained by a deinterleaver in the transmitting-end device.

And S904, decoding to obtain a first bit sequence according to the third matrix.

And converting the third matrix into a form of a bit sequence to obtain a decoded bit sequence, and further decoding the decoded bit sequence to obtain a first bit sequence. The specific implementation manner may refer to the specific implementation manner of decoding the third bit sequence according to the sixth matrix in step S209 in the embodiment corresponding to fig. 2, which is not described herein again.

In one implementation, the decoded bit sequence may be obtained by a deinterleaver in the transmitting-end device, and the first bit sequence may be obtained by a decoder in the transmitting-end device.

In this embodiment, after demodulating the received first symbol sequence, the receiving end device determines a fourth matrix according to the demodulated bit sequence, performs position transformation of bit data between bit square arrays on the fourth matrix to obtain a fifth matrix, further performs position transformation in the bit square array directions of the bit square arrays according to the second mapping relationship, to the bit data of the bit square arrays in the fifth matrix to obtain a transformed sixth matrix, and decodes the sixth matrix to obtain a third bit sequence. The second mapping relationship may be the same as the first mapping relationship used when the sending-end device performs the position conversion of the bit data within the bit matrix range, or may be the opposite mapping relationship to the first mapping relationship used when the sending-end device performs the position conversion of the bit data within the bit matrix range. The second mapping relation is constrained by a global offset constraint factor and at least two local offset constraint factors, and information data which originally belongs to the same matrix row (namely, the information data which belongs to the same matrix row before the position of bit data in the bit square matrix is transformed by the sending end equipment) and is scattered at different rows in the matrix (the information data which is scattered to different rows in the matrix after the position of the bit data in the bit square matrix is transformed by the sending end equipment) is recovered into the same matrix row.

An embodiment of the present application provides a communication apparatus, which may be a sending end device or a component that may be used in a sending end device, where the communication apparatus may include a module or a unit, so as to implement steps S201 to S205 in fig. 2 or implement the communication method in fig. 8. In a possible manner, the communication method may be implemented by a first processing unit, a second processing unit, a third processing unit, and a fourth processing unit, where the first processing module, the second processing module, the third processing module, and the fourth processing module may be physically independent modules from each other, or may be the same module integrated together. The first processing unit, the second processing unit, the third processing unit, and the fourth processing unit may be logic modules divided according to functions, or corresponding hardware modules, respectively, and when all of them are logic modules, referring to fig. 10, fig. 10 is a schematic structural diagram of a communication device provided in an embodiment of the present application, as shown in fig. 10, the communication device 100 includes a first processing module 1001, a second processing module 1002, a third processing module 1003, and a fourth processing module 1004, where:

a first processing module 1001, configured to encode a first bit sequence to be transmitted to obtain a first matrix, where the first matrix includes a plurality of bit square matrices with the same size, and each bit square matrix includes a plurality of bit data;

a second processing module 1002, configured to perform, according to a first mapping relationship, position transformation in a respective bit matrix range for bit data of each bit matrix in the first matrix, to obtain a second matrix, where the first mapping relationship is used to indicate a position mapping relationship before and after the position transformation of each bit data in the bit matrix range, the first mapping relationship includes a row transformation mapping relationship, the row transformation mapping relationship is constrained by a global offset constraint factor and at least two local offset constraint factors, the global offset constraint factor is used to constrain a position offset amount of each bit data row transformation in the bit matrix, and the local offset constraint factor is used to constrain a position offset amount of a bit data row transformation in a part of bit rows in the bit matrix;

a third processing module 1003, configured to perform position transformation on bit data between bit square matrices on the second matrix to obtain a second bit sequence;

a fourth processing module 1004, configured to modulate the first symbol sequence to be transmitted according to the second bit sequence.

In an optional manner, the line transformation mapping relationship is further constrained by a start offset parameter, where the start offset parameter is used to constrain a start position of the bit data in the bit matrix for performing position transformation according to a position offset.

In an alternative way, in the case where the number of rows and the number of columns of the square matrix of bits comprised by the first matrix is 2 ^ m, the local offset constraint factor comprises m-1, where m is an integer greater than 3;

the global offset constraint factor, the local offset constraint factor, and the start offset parameter constrain the row transformation mapping relationship by the following equation:

wherein r is₀Identifying a corresponding row of first bit data in the bit square matrix before position conversion in the bit square matrix range, wherein the first bit data is any bit data in the bit square matrix, and r₁For the corresponding row identification after the position transformation of the first bit data within the bit matrix, c₁Corresponding column identification after the position of the first bit data is transformed in the range of a bit square matrix, g is the global offset constraint factor, beta is the local offset constraint factor, and alpha is the initial offset parameterG, beta and alpha are all preset integers, k is an index mark of beta, the value of g is determined according to 2 lambada p, and p is an integer larger than 1.

In an alternative, in the case where m is 4, g ∈ { -8, -4,4}, β₂∈{-7,-5,-3,-1,1,3,5,7}；

In an alternative, the first mapping relationship further includes a column transformation mapping relationship, and the column transformation mapping relationship is constrained by the following formula:

wherein, c₀Is that it isColumn identification corresponding to first bit data before position conversion in a bit square matrix range, r1 is row identification corresponding to the first bit data after position conversion in the bit square matrix range, c₁And h, gamma and theta are preset integers and w is an index mark of gamma, which are corresponding to the first bit data after the position of the first bit data is changed in the range of the bit square matrix.

In an optional mode, when m is 4, g is-4, β₀Is 0, beta₁Has a value of-2, beta₂Is 3, alpha is 0, h is-2, gamma₀Is 0, gamma₁Is taken as 7, gamma₂Is-7 and theta is 0.

In an optional manner, the fourth processing module 1004 is specifically configured to:

determining a first bit sequence to be modulated according to the third matrix;

In an optional manner, the fourth processing module 1004 is specifically configured to:

determining a second bit sequence to be modulated according to the third matrix;

In an optional manner, the first mapping relationship is indicated by a first mapping table, where the first mapping table includes 256 table units, and each table unit has corresponding mapping position data; a first table unit is a table unit in the first mapping table, mapping position data in the first table unit is (s, t), wherein s and t are integers which are greater than or equal to 0 and less than 16, and the (s, t) is used for indicating the position of bit data stored in the first table unit before position transformation in a bit square matrix range;

the first mapping table is:

(0,0)	(1,1)	(2,2)	(3,3)	(4,4)	(5,5)	(6,6)	(7,7)	(8,8)	(9,9)	(10,10)	(11,11)	(12,12)	(13,13)	(14,14)	(15,15)
																(12,14)	(13,15)	(14,0)	(15,1)	(0,2)	(1,3)	(2,4)	(3,5)	(4,6)	(5,7)	(6,8)	(7,9)	(8,10)	(9,11)	(10,12)	(11,13)
(8,12)	(9,13)	(10,14)	(11,15)	(12,0)	(13,1)	(14,2)	(15,3)	(0,4)	(1,5)	(2,6)	(3,7)	(4,8)	(5,9)	(6,10)	(7,11)
																(4,10)	(5,11)	(6,12)	(7,13)	(8,14)	(9,15)	(10,0)	(11,1)	(12,2)	(13,3)	(14,4)	(15,5)	(0,6)	(1,7)	(2,8)	(3,9)
(14,15)	(15,0)	(0,1)	(1,2)	(2,3)	(3,4)	(4,5)	(5,6)	(6,7)	(7,8)	(8,9)	(9,10)	(10,11)	(11,12)	(12,13)	(13,14)
																(10,13)	(11,14)	(12,15)	(13,0)	(14,1)	(15,2)	(0,3)	(1,4)	(2,5)	(3,6)	(4,7)	(5,8)	(6,9)	(7,10)	(8,11)	(9,12)
(6,11)	(7,12)	(8,13)	(9,14)	(10,15)	(11,0)	(12,1)	(13,2)	(14,3)	(15,4)	(0,5)	(1,6)	(2,7)	(3,8)	(4,9)	(5,10)
																(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,0)	(10,1)	(11,2)	(12,3)	(13,4)	(14,5)	(15,6)	(0,7)	(1,8)
(15,7)	(0,8)	(1,9)	(2,10)	(3,11)	(4,12)	(5,13)	(6,14)	(7,15)	(8,0)	(9,1)	(10,2)	(11,3)	(12,4)	(13,5)	(14,6)
																(11,5)	(12,6)	(13,7)	(14,8)	(15,9)	(0,10)	(1,11)	(2,12)	(3,13)	(4,14)	(5,15)	(6,0)	(7,1)	(8,2)	(9,3)	(10,4)
(7,3)	(8,4)	(9,5)	(10,6)	(11,7)	(12,8)	(13,9)	(14,10)	(15,11)	(0,12)	(1,13)	(2,14)	(3,15)	(4,0)	(5,1)	(6,2)
																(3,1)	(4,2)	(5,3)	(6,4)	(7,5)	(8,6)	(9,7)	(10,8)	(11,9)	(12,10)	(13,11)	(14,12)	(15,13)	(0,14)	(1,15)	(2,0)
(13,6)	(14,7)	(15,8)	(0,9)	(1,10)	(2,11)	(3,12)	(4,13)	(5,14)	(6,15)	(7,0)	(8,1)	(9,2)	(10,3)	(11,4)	(12,5)
																(9,4)	(10,5)	(11,6)	(12,7)	(13,8)	(14,9)	(15,10)	(0,11)	(1,12)	(2,13)	(3,14)	(4,15)	(5,0)	(6,1)	(7,2)	(8,3)
(5,2)	(6,3)	(7,4)	(8,5)	(9,6)	(10,7)	(11,8)	(12,9)	(13,10)	(14,11)	(15,12)	(0,13)	(1,14)	(2,15)	(3,0)	(4,1)
																(1,0)	(2,1)	(3,2)	(4,3)	(5,4)	(6,5)	(7,6)	(8,7)	(9,8)	(10,9)	(11,10)	(12,11)	(13,12)	(14,13)	(15,14)	(0,15)

alternatively, fig. 11 shows one possible structure of the communication apparatus.

Referring to fig. 11, fig. 11 is a schematic structural diagram of another communication device according to an embodiment of the present application, and as shown in fig. 11, the communication device 110 may include: one or more processors 1101, memory 1102, and a communication interface 1103. These components may be connected by a bus 1104 or otherwise, as illustrated in FIG. 11 by a bus. Wherein:

the processor 1101 may be a general purpose processor, such as a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present application. The processor 1101 may process data received via the communication interface 1103. The processor 1101 may also process signals or data to be sent to the communication interface 1103.

The memory 1102 may be coupled to the processor 1101 via the bus 1104 or an input-output port, and the memory 1102 may be integrated with the processor 1101. The memory 1102 is used to store various software programs and/or sets of instructions. In particular, the memory 1102 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. The memory 1102 may also store a network communication program that may be used to communicate with one or more additional devices, one or more terminals, and one or more network devices.

The communication interface 1103 can be used for receiving signals or data input to the communication device 110, and can also be used for outputting signals or data processed by the processor 1101. The number of communication interfaces 1103 can be one or more.

The processor 1101 may be used to read and execute computer readable instructions. Specifically, the processor 1101 may be configured to invoke a program stored in the memory 1102, for example, an implementation program of the communication method provided in one or more embodiments of the present application in the transmitting device, and execute instructions included in the program to implement the method related to the subsequent embodiments.

Wherein, the processor 1101 may be configured to:

performing position transformation of bit data among the bit square matrixes on the second matrix to obtain a third matrix;

and modulating a first symbol sequence to be transmitted according to the third matrix.

It should be noted that the communication device 110 shown in fig. 11 is only one implementation manner of the embodiment of the present application, and in practical applications, it may also include more or less components, and is not limited herein.

It is understood that the communication device in the embodiment of the present application may implement steps S201 to S205 in the embodiment shown in fig. 1 or implement the embodiment corresponding to fig. 8, and as to the specific implementation manner of the functional components included in the communication device of fig. 10 and the corresponding advantageous effects, reference may be made to the detailed description of the embodiment of fig. 1 or fig. 8 described above.

The present embodiment provides a communication apparatus, which may be a receiving end device or a component that may be used for the receiving end device, and the communication apparatus may include a module or a unit, so as to implement steps S206 to S209 in fig. 2 or implement the communication method in fig. 9. In a possible manner, the communication method may be implemented by a first processing unit, a second processing unit, a third processing unit, and a fourth processing unit, where the first processing module, the second processing module, the third processing module, and the fourth processing module may be physically independent modules from each other, or may be the same module integrated together. The first processing unit, the second processing unit, the third processing unit and the fourth processing unit may be respectively logic modules divided according to functions or respectively corresponding hardware modules. When all of them are logic modules, referring to fig. 12, fig. 12 is a schematic structural diagram of another communication apparatus provided in the embodiment of the present application, and as shown in fig. 12, the communication apparatus 120 includes a first processing module 1201, a second processing module 1202, a third processing module 1203, and a fourth processing module 1204, where:

a first processing module 1201, configured to demodulate a received first symbol sequence to obtain a first matrix, where the first matrix includes a plurality of bit square matrices with the same size, and each bit square matrix includes a plurality of bit data;

a second processing module 1202, configured to perform position transformation on bit data between bit square matrices on the first matrix to obtain a second matrix;

a third processing module 1203, configured to perform, according to a first mapping relationship, position transformation in the bit matrix direction of each bit matrix in the second matrix, to obtain a transformed third matrix, where the first mapping relationship is used to indicate a position mapping relationship before and after the position transformation of each bit data in a bit matrix range, the first mapping relationship includes a row transformation mapping relationship, the row transformation mapping relationship is constrained by a global offset constraint factor and at least two local offset constraint factors, the global offset constraint factor is used to constrain a position offset amount of the row transformation of each bit data in the bit matrix, and the local offset constraint factor is used to constrain a position offset amount of the row transformation of bit data in a part of bit rows in the bit matrix;

a fourth processing module 1204, configured to decode to obtain a first bit sequence according to the third matrix.

the global offset constraint factor, the local offset constraint factor, and the start offset parameter constrain the row transformation mapping relationship by the following equation:

wherein r is₀Identifying a corresponding row of first bit data in the bit square matrix after position transformation within the bit square matrix range, wherein the first bit data is any bit data in the bit square matrix, and r₁For the corresponding row identification before the position change of the first bit data in the range of the bit matrix, c₁The method comprises the steps that corresponding column identification is carried out on first bit data before position transformation in a bit square matrix range, g is a global offset constraint factor, beta is a local offset constraint factor, alpha is an initial offset parameter, g, beta and alpha are preset integers, k is an index identification of beta, the value of g is determined according to 2 ^ p, and p is an integer larger than 1.

In an alternative, in the case where m is 4, g ∈ { -8, -4,4}, β₂∈{-7,-5,-3,-1,1,3,5,7}；

In an optional mode, when m is 4, g is-4, β₀Is 0, beta₁Has a value of-2, beta₂Is 3, alpha is 0, h is-2, gamma₀Is 0, gamma₁Is taken as 7, gamma₂Is-7 and theta is 0.

the first mapping table is:

(0,0)	(1,1)	(2,2)	(3,3)	(4,4)	(5,5)	(6,6)	(7,7)	(8,8)	(9,9)	(10,10)	(11,11)	(12,12)	(13,13)	(14,14)	(15,15)
																(12,14)	(13,15)	(14,0)	(15,1)	(0,2)	(1,3)	(2,4)	(3,5)	(4,6)	(5,7)	(6,8)	(7,9)	(8,10)	(9,11)	(10,12)	(11,13)
(8,12)	(9,13)	(10,14)	(11,15)	(12,0)	(13,1)	(14,2)	(15,3)	(0,4)	(1,5)	(2,6)	(3,7)	(4,8)	(5,9)	(6,10)	(7,11)
																(4,10)	(5,11)	(6,12)	(7,13)	(8,14)	(9,15)	(10,0)	(11,1)	(12,2)	(13,3)	(14,4)	(15,5)	(0,6)	(1,7)	(2,8)	(3,9)
(14,15)	(15,0)	(0,1)	(1,2)	(2,3)	(3,4)	(4,5)	(5,6)	(6,7)	(7,8)	(8,9)	(9,10)	(10,11)	(11,12)	(12,13)	(13,14)
																(10,13)	(11,14)	(12,15)	(13,0)	(14,1)	(15,2)	(0,3)	(1,4)	(2,5)	(3,6)	(4,7)	(5,8)	(6,9)	(7,10)	(8,11)	(9,12)
(6,11)	(7,12)	(8,13)	(9,14)	(10,15)	(11,0)	(12,1)	(13,2)	(14,3)	(15,4)	(0,5)	(1,6)	(2,7)	(3,8)	(4,9)	(5,10)
																(2,9)	(3,10)	(4,11)	(5,12)	(6,13)	(7,14)	(8,15)	(9,0)	(10,1)	(11,2)	(12,3)	(13,4)	(14,5)	(15,6)	(0,7)	(1,8)
(15,7)	(0,8)	(1,9)	(2,10)	(3,11)	(4,12)	(5,13)	(6,14)	(7,15)	(8,0)	(9,1)	(10,2)	(11,3)	(12,4)	(13,5)	(14,6)
																(11,5)	(12,6)	(13,7)	(14,8)	(15,9)	(0,10)	(1,11)	(2,12)	(3,13)	(4,14)	(5,15)	(6,0)	(7,1)	(8,2)	(9,3)	(10,4)
(7,3)	(8,4)	(9,5)	(10,6)	(11,7)	(12,8)	(13,9)	(14,10)	(15,11)	(0,12)	(1,13)	(2,14)	(3,15)	(4,0)	(5,1)	(6,2)
																(3,1)	(4,2)	(5,3)	(6,4)	(7,5)	(8,6)	(9,7)	(10,8)	(11,9)	(12,10)	(13,11)	(14,12)	(15,13)	(0,14)	(1,15)	(2,0)
(13,6)	(14,7)	(15,8)	(0,9)	(1,10)	(2,11)	(3,12)	(4,13)	(5,14)	(6,15)	(7,0)	(8,1)	(9,2)	(10,3)	(11,4)	(12,5)
																(9,4)	(10,5)	(11,6)	(12,7)	(13,8)	(14,9)	(15,10)	(0,11)	(1,12)	(2,13)	(3,14)	(4,15)	(5,0)	(6,1)	(7,2)	(8,3)
(5,2)	(6,3)	(7,4)	(8,5)	(9,6)	(10,7)	(11,8)	(12,9)	(13,10)	(14,11)	(15,12)	(0,13)	(1,14)	(2,15)	(3,0)	(4,1)
																(1,0)	(2,1)	(3,2)	(4,3)	(5,4)	(6,5)	(7,6)	(8,7)	(9,8)	(10,9)	(11,10)	(12,11)	(13,12)	(14,13)	(15,14)	(0,15)

in an optional manner, the first processing module 1201 is specifically configured to:

arranging the two second bit data adjacently in the same column in the first matrix, and arranging the two third bit data adjacently below the second bit data.

In an optional manner, the first processing module 1201 is specifically configured to:

Alternatively, fig. 13 shows one possible structure of the communication apparatus.

Referring to fig. 13, fig. 13 is a schematic structural diagram of another communication device according to an embodiment of the present application, and as shown in fig. 13, the communication device 130 may include: one or more processors 1301, memory 1302, and a communications interface 1303. These components may be connected by a bus 1304 or otherwise, as illustrated in FIG. 13 by a bus. Wherein:

the processor 1301 may be a general-purpose processor, such as a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present application. Processor 1301 may process data received through communications interface 1303. The processor 1801 may also process signals or data to be transmitted to the communication interface 1303.

The memory 1302 may be coupled to the processor 1301 via a bus 1304 or an input/output port, and the memory 1302 may be integrated with the processor 1301. The memory 1302 is used to store various software programs and/or sets of instructions. In particular, memory 1302 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic disk storage devices, flash memory devices, or other non-volatile solid state storage devices. The memory 1302 may also store a network communication program that may be used to communicate with one or more additional devices, one or more terminals, one or more network devices.

The communication interface 1303 may be used for receiving signals or data input to the communication device 130, and may also be used for outputting signals or data processed by the processor 1301. The number of the communication interfaces 1303 may be one or more.

Processor 1301 may be used to read and execute computer readable instructions. Specifically, the processor 1301 may be configured to invoke a program stored in the memory 1302, for example, an implementation program implemented in the receiving device in the communication method provided in one or more embodiments of the present application, and execute instructions included in the program to implement the method related to the subsequent embodiments.

The processor 1301 may be configured to:

carrying out position transformation of bit data among bit square matrixes on the first matrix to obtain a second matrix;

and decoding to obtain a first bit sequence according to the third matrix.

It should be noted that the communication device 130 shown in fig. 13 is only one implementation manner of the embodiment of the present application, and in practical applications, it may also include more or less components, and is not limited herein.

It is understood that the communication device in the embodiment of the present application may implement steps S204 to S209 in the embodiment shown in fig. 1, or execute the embodiment corresponding to fig. 9. With regard to the specific implementation of the functional components included in the communication device of fig. 12 and the corresponding advantages, reference may be made to the specific description of the embodiments of fig. 1 or 9.

Referring to fig. 14, fig. 14 is a schematic structural diagram of a communication chip provided in an embodiment of the present application. As shown in fig. 14, the communication chip 140 may include: a processor 1401, and one or more communication interfaces 1402 coupled to processor 1401. Wherein:

processor 1401 is operable to read and execute computer readable instructions. In particular implementations, processor 1401 may include primarily a controller, an operator, and registers. The controller is mainly responsible for instruction decoding and sending out control signals for operations corresponding to the instructions. The arithmetic unit is mainly responsible for executing fixed-point or floating-point arithmetic operation, shift operation, logic operation and the like, and can also execute address operation and conversion. The register is mainly responsible for storing register operands, intermediate operation results and the like temporarily stored in the instruction execution process. In a specific implementation, the hardware architecture of the processor 1401 may be an Application Specific Integrated Circuit (ASIC) architecture, an MIPS architecture, an ARM architecture, an NP architecture, or the like. The processor 1401 may be single core or multi-core.

The interface 1402 may be used to input signals or data to be processed to the processor 1401, and may output the processing result of the processor 1401 to the outside. For example, the communication interface 1402 may be a General Purpose Input Output (GPIO) interface, and may be connected to a plurality of peripheral devices (e.g., a display (LCD), a camera (camara), a Radio Frequency (RF) module, etc.). The communication interface 1402 is connected to the processor 1401 via a bus 1403.

In this application, the processor 1401 may be configured to invoke, from the memory, an implementation program of the communication method provided in one or more embodiments of the present application on the sending-end device side, and execute instructions included in the implementation program; or the method is used for calling the implementation program of the communication method provided by one or more embodiments of the present application on the receiving end device side from the memory, and executing the instructions contained in the program; the communication interface 1402 may be used to output the results of execution by the processor 1401. In this application, the communication interface 1402 may specifically be configured to output the first symbol sequence obtained by modulation by the processor 1401, or output the first bit sequence obtained by decoding by the processor 1401. For the communication method provided by one or more embodiments of the present application, reference may be made to the foregoing embodiments shown in fig. 1, fig. 8, or fig. 9, which are not described herein again.

It should be noted that the functions of the processor 1401 and the communication interface 1402 may be implemented by hardware design, software design, or a combination of hardware and software, which is not limited herein.

In another embodiment of the present application, a communication system is further provided, where the communication system includes a sending end device and a receiving end device. By way of example, the sending end device may be the communication apparatus provided in fig. 10 or fig. 11, or include the communication apparatus provided in fig. 10 or fig. 11, and is configured to perform steps S201 to S205 in the communication method provided in fig. 2, or perform the communication method provided in fig. 8; and/or, the receiving end device may be the communication apparatus provided in fig. 12 or fig. 13, or include the communication apparatus provided in fig. 12 or fig. 13, and is configured to perform steps S206-S209 in the communication method provided in fig. 2, or perform the communication method provided in fig. 9.

In another embodiment of the present application, a readable storage medium is further provided, where a computer executing instruction is stored in the readable storage medium, and when a device (which may be a single chip microcomputer, a chip, or the like) or a processor invokes the computer executing instruction stored in the readable storage medium, steps executed by a sending end device or a receiving end device in the communication method provided in each embodiment shown in fig. 2, fig. 8, or fig. 9 are implemented. The aforementioned readable storage medium may include: u disk, removable hard disk, read only memory, random access memory, magnetic or optical disk, etc. for storing program codes.

In another embodiment of the present application, there is also provided a computer program product comprising computer executable instructions stored in a computer readable storage medium; the at least one processor of the device may read the computer-readable storage medium to execute the computer-executable instructions to implement the steps performed by the sending end device or the receiving end device in the communication method provided by the various embodiments shown in fig. 2, fig. 8, or fig. 9.

The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

Finally, it should be noted that: the above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

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