阅读说明：本技术 一种被用于无线通信的用户、基站中的方法和设备 (Method and equipment used in user and base station of wireless communication ) 是由 吴克颖 于 2017-08-07 设计创作，主要内容包括：本申请公开了一种被用于无线通信的用户、基站中的方法和设备。第一节点首先生成第一比特块,执行信道编码,然后发送第一无线信号。其中,所述第一比特块被用于所述信道编码的输入,所述信道编码的输出被用于生成所述第一无线信号；所述第一比特块包括第二比特块中所有的比特和第三比特块中所有的比特；第四比特块的循环冗余校验比特块被用于生成所述第三比特块；所述第四比特块包括所述第二比特块中所有的比特和第五比特块中所有的比特,所述第五比特块中的比特的值是固定的,所述第五比特块由K个比特组成,所述K是正整数；所述K和所述第二比特块中的比特的数目相关。利用本申请中所述的方法,可以有效提高循环冗余校验的差错校验性能。(The application discloses a method and a device in a user, a base station used for wireless communication. The first node first generates a first bit block, performs channel coding, and then transmits a first wireless signal. Wherein the first block of bits is used for the input of the channel coding and the output of the channel coding is used for generating the first wireless signal; the first bit block comprises all bits in the second bit block and all bits in the third bit block; a block of cyclic redundancy check bits of a fourth block of bits is used to generate the third block of bits; the fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the values of the bits in the fifth bit block are fixed, the fifth bit block consists of K bits, the K is a positive integer; the K is related to the number of bits in the second block of bits. By using the method disclosed by the application, the error checking performance of the cyclic redundancy check can be effectively improved.)

1. An apparatus in a first node for wireless communication, comprising:

the first processing module generates a first bit block and executes channel coding;

wherein the first block of bits is used for the channel coded input; the first bit block comprises all bits in the second bit block and all bits in the third bit block; a block of cyclic redundancy check bits of a fourth block of bits is used to generate the third block of bits; the fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the fifth bit block consists of K bits, the K is a positive integer; the K is related to the number of bits in the second block of bits.

2. The arrangement in the first node according to claim 1, characterised in that all bits in the fifth bit block are 1.

3. An arrangement in the first node according to claim 1 or 2, characterized in that the position of all bits in the fifth bit block in the fourth bit block is fixed for a given number of bits in the second bit block.

4. An arrangement in a first node according to any of claims 1-3, characterised in that the position of any bit in the fifth block of bits in the fourth block of bits is before any bit in the second block of bits.

5. The device in the first node according to any of claims 1-4, wherein the position of at least two bits in the fifth bit block in the fourth bit block is discontinuous.

6. The device according to any of claims 1 to 5, wherein at least two bits of said second bit block are discontinuous in said first bit block, and wherein at least two bits of said third bit block are discontinuous in their position in said first bit block; for any given bit in the third block of bits, the position of all bits in the second block of bits associated with the given bit in the first block of bits precedes the given bit.

7. The apparatus in a first node according to any of claims 1 to 6, wherein the first node is a base station and the second bit block comprises downlink control information; or the first node is a user equipment, and the second bit block includes uplink control information.

8. An apparatus in a second node for wireless communication, comprising:

a second processing module for executing channel decoding and recovering the first bit block;

wherein the first block of bits is used for the channel coding corresponding channel coded input; the first bit block comprises all bits in the second bit block and all bits in the third bit block; a block of cyclic redundancy check bits of a fourth block of bits is used to generate the third block of bits; the fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the fifth bit block consists of K bits, the K is a positive integer; the K is related to the number of bits in the second block of bits.

9. A method in a first node used for wireless communication, comprising:

-generating a first block of bits;

-performing channel coding;

wherein the first block of bits is used for the channel coded input; the first bit block comprises all bits in the second bit block and all bits in the third bit block; a block of cyclic redundancy check bits of a fourth block of bits is used to generate the third block of bits; the fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the fifth bit block consists of K bits, the K is a positive integer; the K is related to the number of bits in the second block of bits.

10. A method in a second node used for wireless communication, comprising:

-performing channel decoding;

-recovering the first bit block;

wherein the first block of bits is used for the channel coding corresponding channel coded input; the first bit block comprises all bits in the second bit block and all bits in the third bit block; a block of cyclic redundancy check bits of a fourth block of bits is used to generate the third block of bits; the fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the fifth bit block consists of K bits, the K is a positive integer; the K is related to the number of bits in the second block of bits.

Technical Field

The present application relates to transmission schemes for wireless signals in wireless communication systems, and more particularly, to methods and apparatus used for transmission of channel coding.

Background

Cyclic Redundancy Check (CRC) is a hash function that generates a short fixed bit Check code from data such as network packets or computer files, and is mainly used to detect or Check errors that may occur after data transmission or storage. It uses the principle of division and remainder to detect the error. In a conventional LTE (Long Term Evolution) system, a Cyclic Redundancy Check (CRC) performs specific functions such as error checking and identification of a target receiver.

Polar Codes (Polar Codes) is a coding scheme first proposed by professor Erdal Arikan university of turkish birken in 2008, and is a code construction method that can realize the capacity of a symmetric Binary input Discrete Memoryless Channel (B-DMC). At 3GPP (3rd Generation Partner Project) RAN1#87 conference, 3GPP has determined a control channel coding scheme that employs a polar code scheme as a 5G eMBB (enhanced mobile broadband) scenario. Some 3GPP documents (e.g., R1-1611254) propose the use of CRC bits for pruning and early termination (earlytemination) during channel decoding of polar codes.

In the 5G system, how to design CRC bits according to a novel coding scheme such as a polar code is a problem to be solved.

Disclosure of Invention

The inventor has found through research that if a part of CRC bits are used for pruning and early termination, the number of CRC bits used for conventional error checking is reduced, thereby reducing the performance of error checking and increasing the false alarm (false alarm) probability. How to design CRC, which enables CRC bits to be used for pruning and early termination of a polarization code, without raising false alarm (false alarm) is a problem to be solved.

In view of the above, the present application discloses a solution. Without conflict, embodiments and features in embodiments in a first node of the present application may be applied to a second node and vice versa. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

The application discloses a method in a first node used for wireless communication, comprising:

-generating a first block of bits;

-performing channel coding;

-transmitting a first wireless signal;

wherein the first block of bits is used for the input of the channel coding and the output of the channel coding is used for generating the first wireless signal; the first bit block comprises all bits in the second bit block and all bits in the third bit block; a block of cyclic redundancy check bits of a fourth block of bits is used to generate the third block of bits; the fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the values of the bits in the fifth bit block are fixed, the fifth bit block consists of K bits, the K is a positive integer; if the number of bits in the second block of bits is equal to Q1, the K is equal to K1; if the number of bits in the second block of bits is equal to Q2, the K is equal to K2; the Q1 is less than the Q2, the K1 is less than or equal to the K2; the Q1, the Q2, the K1 and the K2 are positive integers, respectively.

As an embodiment, the above method has a benefit that the cyclic redundancy check bit block generated by the above method has a good error checking performance, and a low false alarm (false alarm) probability can still be achieved in case that a part of bits in the cyclic redundancy check bit block is used for pruning and early termination (early termination) in channel decoding corresponding to the channel coding.

As an embodiment, the cyclic Redundancy check bit block of the fourth bit block is a crc (cyclic Redundancy check) bit block of the fourth bit block.

As an embodiment, the third block of bits is a block of cyclic redundancy check bits of the fourth block of bits.

As an embodiment, the third bit block is a bit block after the cyclic redundancy check bit block of the fourth bit block is scrambled.

As an embodiment, the scrambling code sequence used by the scrambling code is related to the identity of the first node.

As an embodiment, the first node is a UE (User Equipment), and the identity of the first node is an RNTI (Radio Network Temporary Identifier).

As an embodiment, the first node is a base station, and the identity of the first node is a PCI (Physical Cell Identifier).

As an embodiment, the scrambling code employs a scrambling code sequence related to an identity of a target recipient of the first wireless signal.

As an embodiment, the first node is a base station and the identity of the target recipient of the first wireless signal is an RNTI.

As an embodiment, the cyclic redundancy check bit block of the fourth bit block is an output of the fourth bit block after passing through a CRC cyclic generator polynomial (cyclic generator polynomial).

As an embodiment, the bits in the fourth bit block are sequentially input into the CRC cyclic generator polynomial.

As an embodiment, the polynomial formed by the fourth bit block and the cyclic redundancy check bit block of the fourth bit block is divisible by the CRC cyclic generation polynomial over GF (2), i.e., the remainder obtained by dividing the polynomial formed by the fourth bit block and the cyclic redundancy check bit block of the fourth bit block by the CRC cyclic generation polynomial is zero. Specific Technical details of generating the cyclic redundancy check bit block are described in section 5.1.1 of the Technical Specification (TS-Technical Specification) 36.212.

As one embodiment, the CRC round robin generator polynomial is D²⁴+D²³+D¹⁸+D¹⁷+D¹⁴+D¹¹+D¹⁰+D⁷+D⁶+D⁵+D⁴+D³+D+1。

As one embodiment, the CRC round robin generator polynomial is D²⁴+D²³+D⁶+D⁵+D+1。

As one embodiment, the CRC round robin generator polynomial is D¹⁶+D¹²+D⁵+1。

As one embodiment, the CRC round robin generator polynomial is D⁸+D⁷+D⁴+D³+D+1。

As an embodiment, the fourth bit block consists of all bits in the second bit block and all bits in the fifth bit block.

As an embodiment, all bits in the second bit block are arranged in sequence in the fourth bit block.

As an embodiment, all bits in the fifth bit block are arranged in sequence in the fourth bit block.

As an embodiment, all bits in the second bit block occur in the fourth bit block and only once, and all bits in the fifth bit block occur in the fourth bit block and only once.

As an embodiment, the channel coding is based on Turbo coding.

As an embodiment, the channel coding is based on LDPC coding.

As an embodiment, the channel coding is based on a polar (polar) code.

As a sub-embodiment of the above embodiment, the channel coded input bit sequence is multiplied by a polar coding matrix, and the obtained output is the output of the channel coding. The polar coding matrix is obtained by multiplying a bit reversal permutation matrix (bit reversal permutation matrix) and a first matrix, wherein the first matrix is an n-order Kronecker power of a kernel matrix, n is a logarithm of the length of the input bit sequence of the channel coding with the base 2, the kernel matrix is a matrix with two rows and two columns, two elements of the first row are 1 and 0 respectively, and two elements of the second row are 1 respectively.

As an embodiment, the channel coded input does not include the fifth bit block.

As an embodiment, the bits in the first bit block are sequentially input into the channel encoder corresponding to the channel coding.

As an embodiment, the bits in the first bit block are sequentially arranged to form the channel-coded input bit sequence.

As an embodiment, the first bit block consists of all bits in the second bit block and all bits in the third bit block.

As an embodiment, the first bit block consists of all bits in the second bit block, all bits in the third bit block, and all bits in a frozen bit block, the frozen bit block comprising a positive integer number of bits, the values of all bits in the frozen bit block being predetermined.

As a sub-embodiment of the above embodiment, the values of all bits in the frozen bit block are 0.

As a sub-embodiment of the above embodiment, the identity of the first node is used to generate the bits in the block of frozen bits.

As a sub-embodiment of the above embodiment, the identification of the target recipient of the first wireless signal is used to generate the bits in the frozen block of bits.

As an embodiment, the first bit block does not include the fifth bit block.

As an embodiment, all bits in the second bit block occur in the first bit block and only once, and all bits in the third bit block occur in the first bit block and only once.

As an embodiment, the channel coding includes rate matching (ratelocking).

In one embodiment, at least two bits of the second bit block are discontinuous in the first bit block, and at least two bits of the third bit block are discontinuous in the first bit block.

As an embodiment, all bits in the second bit block are arranged sequentially in the first bit block.

As an embodiment, all bits in the third bit block are arranged in sequence in the first bit block.

As an embodiment, all bits in the fifth bit block are 0.

As an embodiment, all bits in the fifth bit block are 1.

As an embodiment, the values of at least two bits in the fifth bit block are unequal.

As an embodiment, the value of the bits in the fifth bit block is fixed for a given said K.

As one embodiment, the second bit block is generated at a physical layer of the first node.

As an embodiment, the first node is a base station, and the first node generates the second bit block according to a scheduling result.

As an embodiment, the first node is a UE, and the first node generates the second bit block according to scheduling of a base station.

As an embodiment, for any bit in the third bit block, the any bit is equal to a sum of a positive integer number of bits in the fourth bit block modulo 2.

As an embodiment, for any bit in the third bit block, the any bit is obtained by performing an exclusive or operation on a sum of positive integer numbers of bits in the fourth bit block modulo 2 and a corresponding bit in a scrambling code sequence.

As an embodiment, the number of bits in the second block of bits is used to determine the K.

As an embodiment, the relation between the number of bits in the second bit block and the K is fixed.

As an embodiment, the relation between the number of bits in the second bit block and the K is predetermined (configuration is not required).

As an embodiment, if the number of bits in the second bit block is equal to Q1, the K is equal to K1; if the number of bits in the second block of bits is equal to Q2, the K is equal to K2; the Q1 is less than the Q2, the K1 is less than or equal to the K2; the Q1, the Q2, the K1 and the K2 are positive integers, respectively.

As an embodiment, the K is independent of the value of the bits in the second block of bits.

As an embodiment, the K is uniquely determined by the number of bits in the second bit block.

As an embodiment, said K is related to only the number of bits in said second block of bits.

As an embodiment, the K is related to a length of the channel coded output bit sequence.

As an embodiment, the first radio signal is an output of the channel coded output after sequentially performing Scrambling (Scrambling), Modulation Mapper (Modulation Mapper), Layer Mapper (Layer Mapper), Precoding (Precoding), Resource Element Mapper (Resource Element Mapper), and multi-carrier symbol Generation (Generation).

As an embodiment, the first wireless signal is an output of the channel coding after sequentially passing through a scrambling code, a modulation mapper, a layer mapper, a conversion precoder (transform precoder), a precoding, a resource element mapper, and a multi-carrier symbol generation.

As an embodiment, the bits in the first bit block are arranged sequentially.

As an embodiment, the bits in the second bit block are arranged sequentially.

As an embodiment, the bits in the third bit block are arranged sequentially.

As an embodiment, the bits in the fourth bit block are arranged sequentially.

As an example, the first wireless signal is transmitted on a physical layer control channel (i.e., a physical layer channel that cannot be used to transmit physical layer data).

As one embodiment, the first wireless signal is transmitted on a physical layer data channel (i.e., a physical layer channel that can be used to carry physical layer data).

As an embodiment, the first node is a UE.

As a sub-embodiment of the foregoing embodiment, the first radio signal is transmitted on a PUCCH (Physical uplink control Channel).

As a sub-embodiment of the foregoing embodiment, the first wireless signal is transmitted on sPUCCH (short PUCCH).

As a sub-embodiment of the above embodiment, the first Radio signal is transmitted on NR-PUCCH (New Radio PUCCH).

As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NB-PUCCH (NarrowBand band PUCCH).

As a sub-embodiment of the above-mentioned embodiment, the first wireless signal is transmitted on a PUSCH (Physical Uplink Shared CHannel).

As a sub-embodiment of the above embodiment, the first wireless signal is transmitted on a short PUSCH (short PUSCH).

As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NR-PUSCH (new radio PUSCH).

As a sub-implementation of the above-described embodiment, the first radio signal is transmitted on NB-PUSCH (NarrowBand band PUSCH).

As an embodiment, the first node is a base station.

As a sub-embodiment of the foregoing embodiment, the first radio signal is transmitted on a PDCCH (Physical downlink control Channel).

As a sub-embodiment of the foregoing embodiment, the first wireless signal is transmitted on an sPDCCH (short PDCCH).

As a sub-embodiment of the above-mentioned embodiments, the first Radio signal is transmitted on an NR-PDCCH (New Radio PDCCH).

As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NB-PDCCH (NarrowBand PDCCH).

As a sub-embodiment of the above embodiment, the first wireless signal is transmitted on a PDSCH (Physical Downlink Shared CHannel).

As a sub-embodiment of the above embodiment, the first radio signal is transmitted on sPDSCH (short PDSCH).

As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NR-PDSCH (new radio PDSCH).

As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NB-PDSCH (NarrowBand band PDSCH).

In particular, according to one aspect of the present application, it is characterized in that for a given number of bits in said second bit block, the position of all bits in said fifth bit block in said fourth bit block is fixed.

As an embodiment, a bit block obtained by deleting all bits in the fifth bit block in the fourth bit block is the second bit block.

As an embodiment, the probability of false alarm (false alarm) corresponding to information bits at positions of all bits in the fifth bit block in the fourth bit block is higher.

As an embodiment, the positions of all bits in the fifth bit block in the fourth bit block are the positions of information bits with higher false alarm (false alarm) probability in the fourth bit block.

As an embodiment, the positions of K bits in the fifth bit block in the fourth bit block are K reference positions, respectively, and a false alarm (false alarm) probability corresponding to an information bit at any one of the K reference positions is greater than a given threshold, where the given threshold is a positive real number not greater than 1.

As an embodiment, for a given number of bits in the second bit block, the positions of all bits in the fifth bit block in the fourth bit block are predetermined (not required to be configured).

As an embodiment, if the number of bits in the second bit block is equal to Q1, the fifth bit block consists of K1 bits; the fifth bit block consists of K2 bits if the number of bits in the second bit block is equal to Q2; the Q1 is less than the Q2, the K1 is less than or equal to the K2. The positions of the K1 bits in the fourth bit block are K1 reference positions, respectively; the positions of the K2 bits in the fourth bit block are K2 reference positions, respectively, the K1 reference positions being a subset of the K2 reference positions. The Q1, the Q2, the K1 and the K2 are positive integers, respectively.

As an embodiment, the above method has a benefit that inserting a fixed bit at a position corresponding to a higher false alarm (false alarm) probability in the fourth bit block can reduce the overall false alarm probability.

As an embodiment, the positions of any two bits in the fifth bit block in the fourth bit block are consecutive.

As an embodiment, the position of any bit in the fifth bit block in the fourth bit block precedes any bit in the second bit block.

As an embodiment, the values of the bits in the fifth bit block are fixed for a given number of bits in the second bit block.

As an embodiment, the values of the bits in the fifth bit block are pre-set (not required to be configured) for a given number of bits in the second bit block.

Specifically, according to an aspect of the present application, there are at least two bits in the fifth bit block whose positions in the fourth bit block are discontinuous.

As an embodiment, the positions of any two bits in the fifth bit block in the fourth bit block are discontinuous.

As an embodiment, there are at least two bits in the fifth bit block whose positions in the fourth bit block are consecutive.

Specifically, according to one aspect of the present application, there are at least two bits in the third bit block whose positions in the first bit block are discontinuous; for any given bit in the third block of bits, the position of all bits in the second block of bits associated with the given bit in the first block of bits precedes the given bit.

As an embodiment, the above method has a benefit that a part of bits in the third bit block are associated with only a part of bits in the second bit block, and the part of bits in the third bit block can be used for pruning and early termination (early termination) in a channel decoding process corresponding to the channel coding.

As an embodiment, two bits are associated to mean: the value of one bit is related to the value of another bit.

As an embodiment, two bits are associated to mean: one bit is equal to the sum of another bit and the other M bits modulo 2, M being a non-negative integer.

As an embodiment, two bits are associated to mean: one bit is obtained by taking the sum of another bit and other M bits to perform the modulus 2 and then performing the exclusive-or operation on the sum and the corresponding bit in the scrambling code sequence, wherein M is a non-negative integer.

As an embodiment, the bits in the third bit block are arranged in sequence in the first bit block according to the number of associated bits in the second bit block.

As an embodiment, a first bit is located before a second bit in the first bit block, the first bit and the second bit are any two bits in the third bit block, and the number of bits associated with the first bit in the second bit block is smaller than the number of bits associated with the second bit in the second bit block.

As an embodiment, the third bit is positioned foremost in the first bit block among all bits associated with the first target bit and not associated with the second target bit in the third bit block. A fourth bit is positioned foremost in the first bit block among all bits of the third bit block that are associated with the second target bit and are not associated with the first target bit. The third bit is located before the fourth bit in the first bit block, and the first target bit is located before the second target bit in the first bit block. The first target bit and the second target bit are any two bits in the second block of bits.

As an embodiment, there are at least two reference bits in the third bit block, and all bits of the second bit block associated with a latter one of the two reference bits are located between the two reference bits in the first bit block.

As an embodiment, the position of the first given bit in the given bit block before the second given bit means: the index of the first given bit in the given bit block is smaller than the index of the second given bit in the given bit block.

Specifically, according to an aspect of the present application, the first node is a base station, and the second bit block includes downlink control information; or the first node is a user equipment, and the second bit block includes uplink control information.

As an embodiment, the downlink control information includes at least one of corresponding Data { an occupied time domain resource, an occupied frequency domain resource, an MCS (Modulation and Coding Scheme, Redundancy Version, NDI (New Data Indicator), and HARQ (Hybrid Automatic Repeat reQuest) process number }.

As an embodiment, the uplink control information includes at least one of { HARQ-ACK (Acknowledgement), CSI (channel state information), SR (Scheduling Request), CRI (CSI-RS resource indication) }.

The application discloses a method in a second node used for wireless communication, comprising:

-receiving a first wireless signal;

-performing channel decoding;

-recovering the first bit block;

wherein the first block of bits is used for the channel decoding of a corresponding channel encoded input, the channel encoded output being used for generating the first wireless signal; the first bit block comprises all bits in the second bit block and all bits in the third bit block; a block of cyclic redundancy check bits of a fourth block of bits is used to generate the third block of bits; the fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the values of the bits in the fifth bit block are fixed, the fifth bit block consists of K bits, the K is a positive integer; if the number of bits in the second block of bits is equal to Q2, the K is equal to K2; the Q1 is less than the Q2, the K1 is less than or equal to the K2; the Q1, the Q2, the K1 and the K2 are positive integers, respectively.

As an embodiment, the cyclic Redundancy check bit block of the fourth bit block is a crc (cyclic Redundancy check) bit block of the fourth bit block.

As an embodiment, the channel coding is based on a polar (polar) code.

As an embodiment, the output of the channel decoding is used to recover the first bit block.

As an embodiment, the output of the channel decoding is used to recover the second block of bits.

As an embodiment, the relation between the number of bits in the second bit block and the K is fixed.

As an embodiment, the relation between the number of bits in the second bit block and the K is predetermined (configuration is not required).

As an embodiment, the K is independent of the value of the bits in the second block of bits.

As an embodiment, the second node is a base station.

As an embodiment, the second node is a UE (User Equipment).

In particular, according to one aspect of the present application, it is characterized in that for a given number of bits in said second bit block, the position of all bits in said fifth bit block in said fourth bit block is fixed.

Specifically, according to an aspect of the present application, there are at least two bits in the fifth bit block whose positions in the fourth bit block are discontinuous.

Specifically, according to one aspect of the present application, there are at least two bits in the third bit block whose positions in the first bit block are discontinuous; for any given bit in the third block of bits, the position of all bits in the second block of bits associated with the given bit in the first block of bits precedes the given bit.

Specifically, according to an aspect of the present application, the second node is a user equipment, and the second bit block includes downlink control information; or the second node is a base station, and the second bit block includes uplink control information.

The application discloses an apparatus in a first node used for wireless communication, comprising:

a first processor generating a first bit block, performing channel coding;

a first transmitter that transmits a first wireless signal;

wherein the first block of bits is used for the input of the channel coding and the output of the channel coding is used for generating the first wireless signal; the first bit block comprises all bits in the second bit block and all bits in the third bit block; a block of cyclic redundancy check bits of a fourth block of bits is used to generate the third block of bits; the fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the values of the bits in the fifth bit block are fixed, the fifth bit block consists of K bits, the K is a positive integer; if the number of bits in the second block of bits is equal to Q2, the K is equal to K2; the Q1 is less than the Q2, the K1 is less than or equal to the K2; the Q1, the Q2, the K1 and the K2 are positive integers, respectively.

As an embodiment, the apparatus in a first node for wireless communication as described above is characterized in that for a given number of bits in said second bit block, the position of all bits in said fifth bit block in said fourth bit block is fixed.

As an embodiment, the apparatus in a first node for wireless communication as described above is characterized in that the position of at least two bits in the fifth bit block in the fourth bit block is discontinuous.

As an embodiment, the apparatus in a first node for wireless communication as described above is characterized in that the position of at least two bits in said third bit block in said first bit block is discontinuous; for any given bit in the third block of bits, the position of all bits in the second block of bits associated with the given bit in the first block of bits precedes the given bit.

As an embodiment, the apparatus in a first node for wireless communication as described above is characterized in that the first node is a base station and the second bit block includes downlink control information.

As an embodiment, the apparatus in the first node for wireless communication described above is characterized in that the first node is a user equipment, and the second bit block includes uplink control information.

The application discloses an apparatus in a second node used for wireless communication, comprising:

a first receiver that receives a first wireless signal;

a second processor for performing channel decoding to recover the first bit block;

wherein the first block of bits is used for the channel decoding of a corresponding channel encoded input, the channel encoded output being used for generating the first wireless signal; the first bit block comprises all bits in the second bit block and all bits in the third bit block; a block of cyclic redundancy check bits of a fourth block of bits is used to generate the third block of bits; the fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the values of the bits in the fifth bit block are fixed, the fifth bit block consists of K bits, the K is a positive integer; if the number of bits in the second block of bits is equal to Q2, the K is equal to K2; the Q1 is less than the Q2, the K1 is less than or equal to the K2; the Q1, the Q2, the K1 and the K2 are positive integers, respectively.

As an embodiment, the apparatus in the second node for wireless communication as described above is characterized in that for a given number of bits in the second bit block, the position of all bits in the fifth bit block in the fourth bit block is fixed.

As an embodiment, the apparatus in the second node for wireless communication as described above is characterized in that the position of at least two bits in the fifth bit block in the fourth bit block is discontinuous.

As an embodiment, the apparatus in a second node for wireless communication as described above is characterized in that the position of at least two bits in said third bit block in said first bit block is discontinuous; for any given bit in the third block of bits, the position of all bits in the second block of bits associated with the given bit in the first block of bits precedes the given bit.

As an embodiment, the apparatus in the second node for wireless communication as described above is characterized in that the second node is a user equipment, and the second bit block includes downlink control information.

As an embodiment, the apparatus in a second node for wireless communication as described above is characterized in that the second node is a base station and the second bit block includes uplink control information.

As an example, compared with the conventional scheme, the method has the following advantages:

the cyclic redundancy check bit block generated by the method in the present application has good error checking performance. A part of the cyclic redundancy check bits may be used for pruning and early termination (early termination) in the channel decoding process of Polar codes; the remaining crc bits are used for conventional error checking functions and still achieve a low false alarm (false) probability.