阅读说明：本技术 一种视频矩阵中视频无缝切换方法及系统 (Method and system for seamless switching of videos in video matrix ) 是由 韦纯 李昌绿 张常华 朱正辉 赵定金 于 2021-07-29 设计创作，主要内容包括：本发明公开一种视频矩阵中视频无缝切换方法及系统,方法包括：将用于存储视频数据的存储器上的存储器地址划分为若干存储空间；若控未接收到视频切换指令,则执行正常读写视频数据步骤,若接收到视频切换指令,则执行步骤：视频切换指令维持有效期间,写控制模块跳回当前写入的存储空间的首地址,向当前存储空间写入切换后的目标通道视频数据中的一帧图像,读控制模块跳回当前读取的存储空间的首地址,向当前存储空间读取一帧图像,直至视频切换指令失效,写控制模块和读控制模块转向各自的下一个存储器空间,并继续读写下一个图像帧。本发明实现视频无缝切换且避免切换过程中出现黑屏、图像撕裂等问题,保证流畅地无缝切换视频。(The invention discloses a method and a system for seamless switching of videos in a video matrix, wherein the method comprises the following steps: dividing memory addresses on a memory for storing video data into a number of memory spaces; if the control unit does not receive the video switching instruction, executing the step of normally reading and writing the video data, and if the control unit receives the video switching instruction, executing the step of: and during the effective period of the video switching instruction, the writing control module jumps back to the head address of the currently written storage space, writes one frame of image in the switched target channel video data into the current storage space, and the reading control module jumps back to the head address of the currently read storage space, reads one frame of image into the current storage space until the video switching instruction fails, and then the writing control module and the reading control module turn to the respective next storage space and continue to read and write the next image frame. The invention realizes seamless video switching, avoids the problems of black screen, image tearing and the like in the switching process and ensures smooth seamless video switching.)

1. A method for seamless switching of videos in a video matrix is characterized by comprising the following steps:

step 1: dividing memory addresses on a memory for storing video data into a plurality of memory spaces, each memory space comprising a plurality of memory addresses;

step 2: if the controller does not receive the video switching instruction, executing the step 3, otherwise, executing the step 4, wherein the video switching instruction comprises target channel information, and the target channel information comprises a target input channel and a target output channel;

and step 3: a write control module in the controller receives video data of a current input channel and writes the video data into the memory according to image frames, one frame of image is correspondingly stored in a storage space in the memory, a read control module in the controller reads the image frames in the memory and outputs the image frames outwards at the current output channel, the write control module writes the next complete frame of image into the next storage space after completing writing the complete frame of image, the read control module reads the complete frame of image of the current storage space and reads the complete frame of image into the next storage space,

the reading and writing sequence between the writing of the video data into the memory by the writing control module and the reading of the video data from the memory by the reading control module is read and written according to a first preset rule:

a first preset rule: after the read control module and the write control module start reading and writing, according to the address sequence of the memory, the read control module starts reading the video data only after the write control module writes a complete frame of image at least, and the read control module starts reading the next frame of image after the write control module writes the complete frame of image; when the read control module reads a complete frame of image, the write control module starts to write the next frame of image so as to enable the write control module and the read control module to maintain ordered synchronous reading and writing;

and 4, step 4: and during the effective period of the video switching instruction, the writing control module jumps back to the head address of the currently written storage space, writes one frame of image in the switched target input channel video data into the current storage space, and the reading control module jumps back to the head address of the currently read storage space, reads one frame of image into the current storage space, and outputs the image frame to the target output channel until the video switching instruction fails, and the writing control module and the reading control module turn to the respective next storage space and continue to read and write the next image frame.

2. The method of claim 1, wherein the memory is a RAM memory or a ROM memory.

3. The method of claim 1, wherein the memory addresses of any two adjacent memory spaces are separated by at least one memory address, such that the memory addresses of any two adjacent memory spaces are non-consecutive.

4. The method of claim 1, wherein the video switching command is issued by a channel switching device.

5. The method of claim 1, wherein the video switch command maintains the effective time as a duration occupied by a number of frames of images.

6. The method of claim 5, wherein the video switch command is maintained for a duration of 2 frames of video.

7. The method of claim 6, wherein the video switch command is maintained for 0.033 seconds.

8. The method of any of claims 1 to 7, wherein the video switch command is a level signal, and the video switch command remains active when the video switch command is at a high level.

9. A video seamless switching system in a video matrix is characterized by comprising a controller, a memory and a channel switching device, wherein the memory and the channel switching device are both electrically connected with the controller,

a memory for receiving the image frames output by the controller through the output channel, wherein one image frame is stored in one storage space, and different image frames are stored in different storage spaces,

a channel switching device for sending a video switching instruction to the controller, the video switching instruction including a target channel, the target channel including a target input channel and a target output channel,

a controller, including a read control module and a write control module, for receiving the video data input by the input channel and executing the corresponding steps according to whether the received video switching instruction is received, if yes, executing step 3, if no, executing step 4,

and step 3: a write control module in the controller receives video data of a current input channel and writes the video data into the memory according to image frames, one frame of image is correspondingly stored in a storage space in the memory, a read control module in the controller reads the image frames in the memory and outputs the image frames outwards at the current output channel, the write control module writes the next complete frame of image into the next storage space after completing writing the complete frame of image, the read control module reads the complete frame of image of the current storage space and reads the complete frame of image into the next storage space,

the reading and writing sequence between the writing of the video data into the memory by the writing control module and the reading of the video data from the memory by the reading control module is read and written according to a first preset rule:

a first preset rule: after the read control module and the write control module start reading and writing, according to the address sequence of the memory, the read control module starts reading the video data only after the write control module writes a complete frame of image at least, and the read control module starts reading the next frame of image after the write control module writes the complete frame of image; when the read control module reads a complete frame of image, the write control module starts to write the next frame of image so as to enable the write control module and the read control module to maintain ordered synchronous reading and writing;

and 4, step 4: and during the effective period of the video switching instruction, the writing control module jumps back to the head address of the currently written storage space, writes one frame of image in the switched target channel video data into the current storage space, and the reading control module jumps back to the head address of the currently read storage space, reads one frame of image into the current storage space until the video switching instruction fails, and then the writing control module and the reading control module turn to the respective next storage space and continue to read and write the next image frame.

Technical Field

The invention relates to the technical field of video switching, in particular to a method and a system for seamless switching of videos in a video matrix.

Background

In many video scenes needing to be applied, there are often requirements for multiple input and multiple output of video sources, that is, a video matrix is needed. The input in the video matrix has multiple paths, each path has different video sources, the output in the video matrix is also the output, and each path of output can output different video sources. The video of any input channel can be selected through the video matrix to be output through any output channel, in the process, video switching is involved, and a video source of the current input channel is switched to an input source of another input channel to be output. For example, the video source currently output by the output channel a is the video source c1 of the input channel b1, and now the video source output by the output channel a needs to be switched to the video source c2 of the input channel b2, that is, the video source c1 of the input channel b1 is switched to the video source c2 of the input channel b2, so as to complete video switching.

The existing video switching technology often has one or more defects including short-time black screen, image tearing, short-time image freezing and the like in the switching process, so that the video switching effect is reduced, and the user experience is influenced. Particularly, the probability of image tearing occurring in video switching is high, which affects user experience, and image tearing refers to that when switching is performed, an image output by a video matrix is a complete frame image, and more than two frames of image frames are mixed and then output or only half frame image frames are output. Therefore, a processing method capable of avoiding image tearing at the time of video switching is required to avoid such a situation.

Disclosure of Invention

Aiming at the defects of the prior art, one of the purposes of the invention is to provide a method for seamlessly switching videos in a video matrix, which can solve the problem of image tearing during video switching;

the second objective of the present invention is to provide a video seamless switching system in video matrix, which can solve the problem of image tearing during video switching;

the technical scheme for realizing one purpose of the invention is as follows: a method for seamless switching of videos in a video matrix comprises the following steps:

step 1: dividing memory addresses on a memory for storing video data into a plurality of memory spaces, each memory space comprising a plurality of memory addresses;

step 2: if the controller does not receive the video switching instruction, executing the step 3, otherwise, executing the step 4, wherein the video switching instruction comprises target channel information, and the target channel information comprises a target input channel and a target output channel;

and step 3: a write control module in the controller receives video data of a current input channel and writes the video data into the memory according to image frames, one frame of image is correspondingly stored in a storage space in the memory, a read control module in the controller reads the image frames in the memory and outputs the image frames outwards at the current output channel, the write control module writes the next complete frame of image into the next storage space after completing writing the complete frame of image, the read control module reads the complete frame of image of the current storage space and reads the complete frame of image into the next storage space,

the reading and writing sequence between the writing of the video data into the memory by the writing control module and the reading of the video data from the memory by the reading control module is read and written according to a first preset rule:

a first preset rule: after the read control module and the write control module start reading and writing, according to the address sequence of the memory, the read control module starts reading the video data only after the write control module writes a complete frame of image at least, and the read control module starts reading the next frame of image after the write control module writes the complete frame of image; when the read control module reads a complete frame of image, the write control module starts to write the next frame of image so as to enable the write control module and the read control module to maintain ordered synchronous reading and writing;

and 4, step 4: and during the effective period of the video switching instruction, the writing control module jumps back to the head address of the currently written storage space, writes one frame of image in the switched target input channel video data into the current storage space, and the reading control module jumps back to the head address of the currently read storage space, reads one frame of image into the current storage space, and outputs the image frame to the target output channel until the video switching instruction fails, and the writing control module and the reading control module turn to the respective next storage space and continue to read and write the next image frame.

Further, the memory is a RAM memory or a ROM memory.

Furthermore, the memory addresses of any two adjacent memory spaces are separated by at least one memory address, so that the memory addresses of any two adjacent memory spaces are not continuous.

Further, the video switching instruction is sent by the channel switching equipment.

Further, the video switching instruction maintains the effective time as the time length occupied by a plurality of frames of images.

Further, the video switching instruction maintains the effective time as the time length occupied by the 2-frame image.

Further, the video switch instruction maintains an effective time of 0.033 seconds.

Further, the video switch command is a level signal, and the video switch command remains active, which means that the video switch command is at a high level.

The second technical scheme for realizing the aim of the invention is as follows: a video seamless switching system in a video matrix comprises a controller, a memory and a channel switching device, wherein the memory and the channel switching device are both electrically connected with the controller,

a memory for receiving the image frames output by the controller through the output channel, wherein one image frame is stored in one storage space, and different image frames are stored in different storage spaces,

a channel switching device for sending a video switching instruction to the controller, the video switching instruction including a target channel, the target channel including a target input channel and a target output channel,

a controller, including a read control module and a write control module, for receiving the video data input by the input channel and executing the corresponding steps according to whether the received video switching instruction is received, if yes, executing step 3, if no, executing step 4,

and step 3: a write control module in the controller receives video data of a current input channel and writes the video data into the memory according to image frames, one frame of image is correspondingly stored in a storage space in the memory, a read control module in the controller reads the image frames in the memory and outputs the image frames outwards at the current output channel, the write control module writes the next complete frame of image into the next storage space after completing writing the complete frame of image, the read control module reads the complete frame of image of the current storage space and reads the complete frame of image into the next storage space,

the reading and writing sequence between the writing of the video data into the memory by the writing control module and the reading of the video data from the memory by the reading control module is read and written according to a first preset rule:

a first preset rule: after the read control module and the write control module start reading and writing, according to the address sequence of the memory, the read control module starts reading the video data only after the write control module writes a complete frame of image at least, and the read control module starts reading the next frame of image after the write control module writes the complete frame of image; when the read control module reads a complete frame of image, the write control module starts to write the next frame of image so as to enable the write control module and the read control module to maintain ordered synchronous reading and writing;

and 4, step 4: and during the effective period of the video switching instruction, the writing control module jumps back to the head address of the currently written storage space, writes one frame of image in the switched target channel video data into the current storage space, and the reading control module jumps back to the head address of the currently read storage space, reads one frame of image into the current storage space until the video switching instruction fails, and then the writing control module and the reading control module turn to the respective next storage space and continue to read and write the next image frame.

The invention has the beneficial effects that: according to the invention, in the video switching process, the output image is a complete frame image all the time, but not a half-frame image or a multi-frame image mixed with a plurality of input channels, so that the problems of black screen, image tearing and the like in the switching process are avoided, smooth and seamless video switching is ensured, the effective time extreme (usually 0.033 second) of a video switching instruction is maintained, the image freezing effect cannot be perceived by human eyes, the human feeling is instantaneous switching, the switching is very smooth, and the high-quality seamless video switching is realized.

Drawings

Fig. 1 is a schematic framework diagram of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, specific embodiments of the present application will be described in detail with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some but not all of the relevant portions of the present application are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.

Referring to fig. 1, a method for seamless switching of videos in a video matrix includes the following steps:

step 1: the memory addresses on the memory for storing video data are divided into several memory spaces, N memory spaces being divided in fig. 1. Each storage space stores a frame of image in the video data, each storage space comprises a plurality of memory addresses, the foremost memory address in the storage space is a head address, and the last memory address is a tail address. For example, the memory address of the first frame memory space for storing the first frame image in the video data is 1-10000, which includes 10000 memory addresses, wherein the memory address 1 (i.e. the foremost memory address) is the head address and the memory address 10000 (i.e. the last memory address) is the tail address.

The memory is typically a cache device, either a RAM memory or a ROM memory.

In an alternative embodiment, the memory addresses of any two adjacent memory spaces are each separated by at least one memory address, so that the memory addresses of any two adjacent memory spaces are non-consecutive. For example, the first frame memory space and the second frame memory space are two adjacent memory spaces, the memory address of the first frame memory space is 1-10000, the memory address of the second memory space is 20000-30000, the tail address of the first memory space is 10000, and the head address of the second memory space is 20000, so that a plurality of memory addresses are spaced between the tail address of the first memory space and the head address of the second memory space, and the two are discontinuous. By dividing the adjacent storage space into discontinuous storage spaces, the readability of codes for reading and writing image frames from the storage space subsequently is higher, and the maintainability is higher. The reason is that the storage space occupied by one frame of image is not all integer, and for example, in a frame of image with 1080P format, the number of bytes occupied is 1920 × 1080 × 3(RGB triple channel) ═ 6220800Byte, and the occupied storage space is not an integer multiple of the memory address. Therefore, the storage space is divided into non-continuous spaces, the readability of the codes is stronger, and the maintenance is easier.

Step 2: and if the controller does not receive the video switching instruction, executing the step 3, otherwise, executing the step 4. The video switching instruction comprises target channel information, and the target channel information comprises a target input channel and a target output channel, so that the current input channel is switched to the target input channel to receive video data, and the current output channel is switched to the target output channel to output the video data received from the target input channel. The plurality of input channels and the plurality of output channels form the video matrix.

In this step, the controller can receive a video switching instruction sent by a channel switching device for controlling video switching, and the channel switching device can be an MCU or an ARM or other chip, and can be made into an independent module.

And step 3: a write control module in the controller receives video data of a current input channel and writes the video data into the memory according to image frames, and one image frame is correspondingly stored into a storage space in the memory. And a reading control module in the controller reads the video data currently stored in the memory and reads the video data according to the image frame, and the read image frame is output outwards at the current output channel. And the writing control module writes the next complete frame image into the next storage space after finishing writing the complete frame image, and repeating the steps to continuously write new image frames until all the image frames are written or the capacity of the storage is full. Similarly, the reading control module reads a complete frame of image of the current storage space, reads a complete frame of image of the next storage space, and continuously reads new image frames until all image frames are read or a reading stopping instruction is received.

The reading and writing sequence between the writing of the video data into the memory by the writing control module and the reading of the video data from the memory by the reading control module is read and written according to a first preset rule:

a first preset rule: after the read control module and the write control module start reading and writing, according to the address sequence of the memory, the read control module starts reading the video data only after the write control module writes in at least one complete frame of image, and the read control module starts reading the next frame of image only after the write control module writes in one complete frame of image; after the read control module reads a complete frame of image, the write control module starts to write the next frame of image, so that the write control module and the read control module maintain ordered synchronous reading and writing. By maintaining the ordered and synchronous reading and writing of the writing control module and the reading control module, the reading control module can be ensured to read a complete frame image all the time, and the output image is prevented from generating a half frame image.

It should be noted that, after the read control module reads a complete frame of image, the write control module starts to write the next frame of image, which is not a cause-and-effect or conditional restriction relationship, but indicates the coordination of the read control module and the write control module in the read-write time, that is, when the read control module reads a complete frame of image, the write control module starts to write the next frame of image, or conversely, when the write control module starts to write the next frame of image, the read control module finishes reading the frame of image, and the two read-write control modules are mutually coordinated in the read-write time.

For example, after the read control module and the write control module start to be powered on and enter to start reading and writing, the write control module and the read control module usually start to read and write from a first memory address or from high to low according to the sequence of memory addresses, and certainly can start to read and write from a middle memory address, where taking the first memory address as an example, after the write control module writes a first frame image into the first memory address, the read control module reads the first frame image from the first memory address and outputs the first frame image, then, after the write control module continues to write a second frame image into a next memory address (i.e., a second memory address), the read control module reads a second frame image from the second memory address and outputs the second frame image, and so on, the read control module always lags behind one memory address, and maintains ordered synchronous reading and writing.

And 4, step 4: and during the effective period of the video switching instruction, the writing control module jumps back to the head address of the currently written storage space, writes one frame of image in the switched target input channel video data into the current storage space, and the reading control module jumps back to the head address of the currently read storage space, reads one frame of image in the current channel video data before switching into the current storage space until the video switching instruction fails, and the writing control module and the reading control module stop reading and writing the image frame into the respective current storage space but turn to the respective next storage space to continuously read and write the next image frame and output the image frame to the target output channel.

In an optional embodiment, the video switching instruction keep-alive time is a time length occupied by two frames of images, or a time length occupied by other frames of images, but the video switching instruction keep-alive time cannot be too long. For video data with a refresh rate of 60Hz, i.e. video data displaying 60 image frames in 1 second, the video switch command duration is 0.033 second, which is equivalent to the time length occupied by two frames of images. In such an extreme time, the human eye does not feel the video is switched, so that the seamless switching of the video is realized.

The video switching instruction is invalid, namely the controller does not receive the video switching instruction or the video switching instruction disappears, that is, the read-write control module does not receive the video switching instruction. The video switching instruction is usually a level signal, when the video switching instruction maintains a high level, the video switching instruction is effective, and the read-write control module receives the video switching instruction; when the video switching command maintains a low level (usually, zero level), the video switching command fails, and the read-write control module does not receive the video switching command.

For example, immediately before receiving a video switching instruction (i.e. before switching), that is, when the video data is normally read and written according to step 3, the write control module is writing the second frame image of the current channel into the second storage space, and the read control module is reading the first frame image (the first frame image is from the video data of the current channel) into the first storage space. When a video switching instruction is received (namely in the switching process), after the writing of a second frame image in the second storage space is finished, the writing control module jumps back to the head address of the second storage space from the tail address of the second storage space, and writes a frame image of a target input channel into the second storage space, after the reading of a first frame image in the first storage space is finished, the reading control module jumps back to the head address of the first storage space from the tail address of the first storage space, and continues to read the first frame image from the first storage space until the video switching instruction fails (namely after the switching), the writing control module writes a third frame image into the third storage space, and the reading control module reads an image frame of the second storage space from the second storage space (the image frame at this time is video data from the target input channel) and sequentially proceeds.

Through the processing of the step, the output image is a complete frame image all the time in the video switching process, but not a half-frame image or a multi-frame image mixed with a plurality of input channels, so that the problems of black screen, image tearing and the like in the switching process are avoided, smooth seamless video switching is ensured, the effective time extreme (usually 0.033 second) is maintained by a video switching instruction, the image freezing effect cannot be perceived by human eyes, the human feeling is instantaneous switching, and the switching is very smooth.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.