阅读说明：本技术 一种多类型自适应分辨率的图像转换方法及装置 (Multi-type adaptive resolution image conversion method and device ) 是由 唐俊 汪智 胡楷 朱鸿泰 于 2021-08-24 设计创作，主要内容包括：本发明公开一种多类型自适应分辨率的图像转换方法及装置,属于视频信号数据采集领域。FPGA对四种类型的视频接口芯片进行驱动配置,恢复视频信号；对视频信号分别进行检测,判断该路视频数据是否正常接收；对图像分辨率,帧率进行检测；对视频信号进行时钟同步；根据对前端视频的检测以及外部指令,选择需要处理的视频类型,图像的各种参数和需要输出的端口；根据指令响应,分别对各类型数据进行处理；将处理后视频数据缓存到外部存储器,通过不同的输出格式进行读取输出。(The invention discloses an image conversion method and device for multi-type adaptive resolution, and belongs to the field of video signal data acquisition. The FPGA carries out drive configuration on the four types of video interface chips and recovers video signals; respectively detecting the video signals and judging whether the video data of the channel are normally received; detecting the image resolution and the frame rate; performing clock synchronization on the video signal; selecting a video type to be processed, various parameters of an image and a port to be output according to the detection of a front-end video and an external instruction; processing each type of data respectively according to the instruction response; and caching the processed video data into an external memory, and reading and outputting the video data through different output formats.)

1. A multi-type adaptive resolution image conversion method is characterized by comprising the following steps:

the method comprises the following steps: the FPGA carries out drive configuration on the four types of video interface chips and recovers video signals; respectively detecting the video signals and judging whether the video data of the channel are normally received; detecting the image resolution and the frame rate; performing clock synchronization on the video signal;

step two: selecting a video type to be processed, various parameters of an image and a port to be output according to the detection of a front-end video and an external instruction;

step three: processing each type of data respectively according to the instruction response;

step four: and caching the processed video data into an external memory, and reading and outputting the video data through different output formats.

2. The multi-type adaptive resolution image conversion method according to claim 1, wherein said step one comprises:

step 1.1, when no external video is input, no video is output, and video access is waited;

step 1.2, when any video is input, firstly decoding the detected video data to obtain frame synchronization, line synchronization and image data signals, and then performing clock synchronization processing on the effective resolution, line-field blanking and frame rate parameters of each type of video image.

3. The multi-type adaptive resolution image conversion method according to claim 2, wherein said step two comprises:

and 2.1, when image parameters are given, determining that a plurality of paths of video data exist currently, and selecting the video data needing to be processed through an external instruction at the moment.

4. The multi-type adaptive resolution image conversion method according to claim 3, wherein said step three comprises:

step 3.1, different processing flows are carried out according to the output result, when the CVBS data are output, the processing flow is data bit width conversion, and the data are written into a DDR3 memory according to the converted frame synchronization, line synchronization, pixel clock and image effective data;

when SDI data is output, the processing flow comprises data bit width conversion and resolution and frame rate adjustment;

when CAMERALINK or HDMI data is output, the processing flow is color space conversion, data bit width conversion, resolution and frame rate adjustment.

5. The multi-type adaptive resolution image conversion method according to claim 4, wherein said three steps of processing each type of data include bit width conversion of four types of image data:

the resolution and the frame rate of the four types of image data are different, and when the instruction response is different types of video output, the frame rate and the resolution need to be adjusted; CAMERALINK and HDMI video data include RGB, which requires color space conversion.

6. The multi-type adaptive resolution image conversion method according to claim 5, wherein said step four includes:

step 4.1, the data cache realizes the frame cache of the processed single-type video data; and selecting the corresponding video type to output according to the output channel selection instruction, and generating image data meeting the output interface protocol according to the frame rate and the resolution parameter.

7. The image conversion device is characterized by comprising a CVBS interface, a CVBS coding and decoding chip, an SDI interface, an SDI coding and decoding chip, an CAMERA LINK interface, a CAMERALINK coding and decoding chip, an HDMI interface and an HDMI coding and decoding chip; the device also comprises an FPGA chip, a DDR3 external memory, a power management unit, a clock management unit and an external serial port communication circuit;

and the data clock and the control signal of each type of video coding and decoding chip are connected with the FPGA chip, and the FPGA chip is used for carrying out power-on control, resetting and register configuration on each type of video coding and decoding chip.

8. The multi-type adaptive resolution image conversion apparatus according to claim 7, wherein all types of video data determine an output interface type of a current video source according to the detection result and an external command, and the default output type is an SDI format.

9. The multi-type adaptive resolution image conversion apparatus according to claim 8, wherein the video output resolution and the frame rate are input to the video output according to an external command, and the video output pixel clock is generated according to the clock management unit.

Technical Field

The invention relates to the technical field of video signal data acquisition, in particular to a multi-type adaptive resolution video conversion method and device.

Background

The video transmission interfaces applied in various products at present are various in types and generally divided into analog video transmission interfaces and digital video transmission interfaces, wherein a CVBS interface is an analog interface; the SDI/3G-SDI interface, the CAMERA LINK interface, and the HDMI interface are digital interfaces, and are currently widely used as video interfaces in the field of broadcast and television, security monitoring, industrial equipment, and digital electronic equipment, respectively.

The CVBS is a composite video broadcast signal and is a standard definition analog video signal interface; the CVBS signal is an interlaced video signal, and is divided into a PAL system resolution 720x576 and an NTSC system resolution 720x 480; the SDI is a digital component serial interface, is divided into standard definition SD-SDI, high definition standard HD-SDI and full high definition standard 3G-SDI according to the rate, has the corresponding rates of 270Mb/s, 1.485Gb/s and 2.97Gb/s, and has the advantages of easy use, non-compressibility, high definition real-time performance and the like; the CAMERA LINK interface is a communication interface proposed on the basis of the Channel Link technology, and is divided into four modes of Base/Medium/Full/Deca according to the difference of the throughput of data and the data rate of transmission; CAMERA LINK the video protocol determines the flexibility of the video signal transmission, and can realize the transmission of video images with any frame frequency and resolution ratio on the premise of meeting the maximum transmission rate; the HDMI is a high-definition multimedia end interface, can support various resolutions, has a HDMI2.0 transmission speed as high as 18Gb/s, and has ultrahigh-definition video transmission.

For multi-type video signal interfaces, the conventional method is to receive video signals of various types through a plurality of hardware interfaces, and then to decode and display the video signals of various types by a plurality of external devices, so that video data of different types cannot be converted; such as: the CVBS video needs to be displayed through a special analog image acquisition box or a special display, the Camerlink video needs to be displayed through an CAMERALINK acquisition card, the SDI video needs to be displayed through an SDI acquisition box or a special display, and the HDMI video needs to be displayed through an HDMI acquisition card or a HDMI display.

Disclosure of Invention

The invention aims to provide a method and a device for converting images with multi-type self-adaptive resolution, which aim to solve the problems in the background art.

In order to solve the above technical problem, the present invention provides a method for converting an image with multiple types of adaptive resolutions, comprising:

the method comprises the following steps: the FPGA carries out drive configuration on the four types of video interface chips and recovers video signals; respectively detecting the video signals and judging whether the video data of the channel are normally received; detecting the image resolution and the frame rate; performing clock synchronization on the video signal;

step two: selecting a video type to be processed, various parameters of an image and a port to be output according to the detection of a front-end video and an external instruction;

step three: processing each type of data respectively according to the instruction response;

step four: and caching the processed video data into an external memory, and reading and outputting the video data through different output formats.

Optionally, the first step includes:

step 1.1, when no external video is input, no video is output, and video access is waited;

step 1.2, when any video is input, firstly decoding the detected video data to obtain frame synchronization, line synchronization and image data signals, and then performing clock synchronization processing on the effective resolution, line-field blanking and frame rate parameters of each type of video image.

Optionally, the second step includes:

and 2.1, when image parameters are given, determining that a plurality of paths of video data exist currently, and selecting the video data needing to be processed through an external instruction at the moment.

Optionally, the third step includes:

step 3.1, different processing flows are carried out according to the output result, when the CVBS data are output, the processing flow is data bit width conversion, and the data are written into a DDR3 memory according to the converted frame synchronization, line synchronization, pixel clock and image effective data;

when SDI data is output, the processing flow comprises data bit width conversion and resolution and frame rate adjustment;

when CAMERALINK or HDMI data is output, the processing flow is color space conversion, data bit width conversion, resolution and frame rate adjustment.

Optionally, the processing of each type of data in the three steps includes bit width conversion of four types of image data:

the resolution and the frame rate of the four types of image data are different, and when the instruction response is different types of video output, the frame rate and the resolution need to be adjusted; CAMERALINK and HDMI video data include RGB, which requires color space conversion.

Optionally, the fourth step includes:

step 4.1, the data cache realizes the frame cache of the processed single-type video data; and selecting the corresponding video type to output according to the output channel selection instruction, and generating image data meeting the output interface protocol according to the frame rate and the resolution parameter.

The invention also provides an image conversion device with multi-type self-adaptive resolution, which comprises a CVBS interface, a CVBS coding and decoding chip, an SDI interface, an SDI coding and decoding chip, an CAMERA LINK interface, a CAMERALINK coding and decoding chip, an HDMI interface and an HDMI coding and decoding chip; the device also comprises an FPGA chip, a DDR3 external memory, a power management unit, a clock management unit and an external serial port communication circuit;

the data clock and the control signal of each type of video coding and decoding chip are connected with the FPGA chip, and the FPGA chip is used for carrying out power-on control, reset and register configuration on each type of video coding and decoding chip

Optionally, the output interface type of the current video source is determined by all types of video data according to the detection result and an external instruction, and the default output type is an SDI format.

Optionally, the video output resolution and the frame rate may be input to the video output according to an external instruction, and the video output pixel clock is generated according to the clock management unit.

The invention mainly has the following advantages: for different types of video interfaces, the use of external image capture boxes may be reduced. In practical application, only one acquisition box of any one of the four types is needed to be provided, so that the four types of video data can be output and displayed, the external hardware cost is greatly reduced, and the four types of video protocols can be flexibly converted into one another.

Drawings

FIG. 1 is a schematic diagram of a multi-type adaptive resolution image conversion apparatus provided by the present invention;

FIG. 2 is a flow chart of a multi-type adaptive resolution image conversion method provided by the present invention;

FIG. 3 is a schematic view of a collection module process flow;

FIG. 4 is a process module flow diagram.

Detailed Description

The following describes a multi-type adaptive resolution image conversion method and apparatus according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a multi-type adaptive resolution image conversion method and a device,

the hardware components of the invention are first explained: a multi-type adaptive resolution image conversion apparatus, as shown in fig. 1, comprising:

connecting the CVBS interface and the CVBS coding and decoding chip according to the requirements;

connecting the SDI interface and the SDI coding and decoding chip according to requirements;

connecting an CAMERA LINK interface and a CAMERALINK coding and decoding chip according to requirements;

and connecting the HDMI interface and the HDMI coding and decoding chip according to the requirement.

The hardware composition of the image conversion device also comprises an FPGA chip, a DDR3 external memory, a power management unit, a clock management unit and an external serial port communication circuit. And the data clock and the control signal of each type of video coding and decoding chip are connected with the FPGA chip, and the FPGA chip is used for carrying out power-on control, reset and register configuration on the video coding and decoding chip.

All types of video data can be processed in the FPGA chip, the current video source can be determined to be output from which type of video interface according to the detection result of the acquisition module and an external serial port communication instruction, and the default output type is an SDI format.

The video output resolution and the frame rate can be input to the video output module according to an external serial port communication instruction, and the video output pixel clock is generated according to a clock management unit in the FPGA chip.

The following describes a multi-type adaptive resolution image conversion method, including the following steps:

the method comprises the following steps: an acquisition module of the FPGA chip carries out drive configuration on four types of video interface chips and recovers video signals; respectively detecting the video signals and judging whether the video data of the channel are normally received; detecting the image resolution and the frame rate; the video signal is clock synchronized.

When the acquisition module finds that no external video is input, the device has no video output and waits for video access; when the acquisition module finds that any video is input, the acquisition module firstly decodes the detected video data to obtain frame synchronization, line synchronization and image data signals, and parameters such as effective resolution, line-field blanking and frame rate of each type of video image, and then carries out clock synchronization processing.

Step two: and a selection module of the FPGA chip selects the type of the video to be processed, various parameters of the image and a port to be output according to the detection of the front-end video and an external instruction.

When the acquisition module provides image parameters and determines that a plurality of paths of video data exist currently, the video data needing to enter the processing module are selected through an external instruction.

Step three: the processing module of the FPGA chip respectively processes various types of data mainly according to the instruction response in the selection module, such as bit width conversion of four types of image data: the resolution and the frame rate of the four types of image data are different from each other, so when the instruction response is different types of video output, a certain processing mode is required to be adopted to adjust the frame rate and the resolution; CAMERALINK and HDMI video data includes RGB, which requires color space conversion in the processing module.

The processing module carries out different processing flows according to the output result of the selection module, when the selection module outputs the CVBS data, the processing flow is data bit width conversion, and the data are written into a DDR3 memory according to the converted frame synchronization, line synchronization, pixel clock and image effective data; when the selection module outputs SDI data, the processing flow comprises data bit width conversion and resolution and frame rate adjustment; when the selection module outputs CAMERALINK or HDMI data, the processing flow includes color space conversion, data bit width conversion, resolution and frame rate adjustment.

Step four: and the data cache and video output module of the FPGA chip caches the processed video data to an external memory, and reads and outputs the video data through different output formats.

The data cache mainly realizes frame cache of the processed single-type video data; and selecting a corresponding video type output module according to the channel selection instruction output by the selection module, and generating image data meeting the output interface protocol according to parameters such as frame rate, resolution and the like.

Fig. 1 is a schematic structural diagram of a multi-type adaptive resolution image conversion method and device, which mainly includes four types of image encoding and decoding chips, an FPGA chip, a clock management unit, a serial communication circuit, a power management unit, and an external storage unit DDR 3. Fig. 2 shows an image conversion flow chart of multiple types of adaptive resolutions, which includes a CVBS interface, an SDI interface, an CAMERALINK interface, and an HDMI interface, and includes a drive configuration, a video decoding, a video detection, a parameter acquisition, and a clock synchronization through an acquisition module, and selects a corresponding video signal to enter a processing module through an instruction response, and then performs data buffering and protocol encoding, and finally outputs a required video.

As shown in fig. 3, in the acquisition module, the main operation of the driving configuration is to drive an external interface chip, and the driving configuration is mainly divided into that the FPGA chip configures a CVBS decoding chip ADV7180 and an encoding chip ADV7391 through an IIC bus protocol and configures registers in an HDMI decoding chip ADV7601 and an encoding chip ADV7511, the SPI bus protocol configures an SDI interface chip LMH0387 register and a chip periphery thereof, and the LMH0387 can realize the reception and transmission of an SDI signal through configuration; CAMERALINK the decoding chip DS90CR288 and the encoding chip DS90CR287 only need to be configured with power-on enable signals; thereby driving the chip to work normally and outputting a digital signal; video decoding, which mainly analyzes a protocol in an FPGA chip and recovers image line and field synchronous signals, a clock and video data; video detection, namely performing video signal state detection on the four types of interfaces to judge whether normal video signals exist; parameter acquisition, which mainly has the functions of acquiring parameters such as the resolution, the frame rate, the blanking area length and the like of an image from line and field synchronous signals when video signals exist, feeding back to a monitoring point of the device if the signals of the type are found to be absent or abnormal, determining whether external equipment and connection are normal, and simultaneously carrying out driving configuration on the chip again; clock synchronization, which is mainly to avoid time sequence violation caused by multi-channel video data switching under different clock domains, and synchronize the video data of different clock sources to the same clock source, thereby achieving the function of optimizing time sequence; and responding to the instruction, sending an external instruction signal to the FPGA chip through the serial port, and analyzing the instruction by the FPGA chip, selecting the video type to be processed and entering the processing module.

As shown in fig. 4, in the processing module, a corresponding processing path is selected according to a video detection result, which is mainly divided into color space conversion, and mainly aiming at CAMERALINK and HDMI RGB video signals, the RGB signals need to be converted into YUV signals for subsequent processing, while the CVBS and SDI video signals are in YUV format, so that color space conversion processing is not needed; after the data bit width conversion and the resolution and frame rate adjustment, writing the data into DDR3 for caching according to a frame synchronization signal and a line effective signal; in the image protocol coding module, a corresponding image coding protocol is generated according to the input instruction and the parameters acquired in the acquisition module and is output.

It should be noted that the acquisition module, the selection module, and the processing module are all logic implementations of FPGA content, and belong to a code implementation part.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.