阅读说明：本技术 提供高分辨率精细增益的包含具有δ-σ调制器的小数分频器的斜坡发生器 (Ramp generator including fractional divider with delta sigma modulator providing high resolution fine gain ) 是由 范理杭 左亮 江妮君 瞿旻 刘雪莲 于 2021-05-06 设计创作，主要内容包括：本申请案涉及一种提供高分辨率精细增益的斜坡发生器,其包含具有Δ-Σ调制器的小数分频器。一种提供具有高分辨率精细增益的斜坡信号的斜坡发生器包含电流镜,其具有传导电容器电流及响应于所述电容器电流的积分器电流的第一及第二路径。第一及第二开关电容器电路经耦合到所述第一路径。小数分频器电路经耦合以接收时钟信号以响应于可调整小数分频器比率K而产生在第一与第二状态之间振荡以控制所述第一及第二开关电容器电路的开关电容器控制信号。所述第一及第二开关电容器电路经耦合以响应于每一所述开关电容器控制信号而交替地由所述电容器电流充电及放电。积分器经耦合到所述第二路径以响应于所述积分器电流而产生所述斜坡信号。(The application relates to a ramp generator that provides high resolution fine gain, including a fractional divider with a delta-sigma modulator. A ramp generator that provides a ramp signal with high resolution fine gain includes a current mirror having first and second paths that conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits in response to an adjustable fractional divider ratio K. The first and second switched capacitor circuits are coupled to be alternately charged and discharged by the capacitor current in response to each of the switched capacitor control signals. An integrator is coupled to the second path to generate the ramp signal in response to the integrator current.)

1. A ramp generator for providing a ramp signal having a high resolution fine gain, comprising:

a current mirror having a first path coupled to conduct a capacitor current and a second path coupled to conduct an integrator current in response to the capacitor current;

a first switched capacitor circuit and a second switched capacitor circuit coupled to the first path;

a fractional divider circuit coupled to receive a clock signal to generate a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits in response to an adjustable fractional divider ratio K, wherein the first switched capacitor circuit is coupled to be charged by the capacitor current and the second switched capacitor circuit is coupled to be discharged in response to each first state of the switched capacitor control signal, wherein the first switched capacitor circuit is coupled to be discharged and the second switched capacitor circuit is coupled to be charged by the capacitor current in response to each second state of the switched capacitor control signal; and

an integrator coupled to the second path to generate the ramp signal in response to the integrator current.

2. The ramp generator according to claim 1, wherein the first switched capacitor circuit comprises:

a first capacitor;

a first switch coupled between the first capacitor and the first path, wherein the first switch is configured to turn on in response to the first state and turn off in response to the second state; and

a second switch coupled across the first capacitor, wherein the second switch is configured to turn off in response to the first state and turn on in response to the second state.

3. The ramp generator according to claim 2, wherein the second switched capacitor circuit comprises:

a second capacitor;

a third switch coupled between the second capacitor and the first path, wherein the third switch is configured to turn off in response to the first state and turn on in response to the second state; and

a fourth switch coupled across the second capacitor, wherein the fourth switch is configured to turn on in response to the first state and turn off in response to the second state.

4. The ramp generator according to claim 1, wherein the current mirror comprises:

a first transistor coupled between a voltage supply rail and the first path, wherein a control terminal of the first transistor is coupled to the first path; and

a second transistor coupled between the voltage supply rail and the second path, wherein a control terminal of the second transistor is coupled to the control terminal of the first transistor.

5. The ramp generator according to claim 4, further comprising:

a first operational amplifier having a non-inverting input coupled to a reference capacitor voltage; and

a third transistor coupled between the first transistor and the first switched capacitor circuit, the second switched capacitor circuit, and an inverting input of the first operational amplifier through the first path, wherein a control terminal of the third transistor is coupled to an output of the first operational amplifier, and wherein the first operational amplifier is coupled to turn off the third transistor in response to voltages at the first switched capacitor circuit and the second switched capacitor circuit reaching the reference capacitor voltage.

6. The ramp generator according to claim 1, wherein the integrator comprises:

a second operational amplifier having a non-inverting input coupled to a reference voltage;

a third capacitor coupled between an inverting input of the second operational amplifier and an output of the second operational amplifier; and

a third switch coupled between the inverting input of the second operational amplifier and the output of the second operational amplifier, wherein the integrator is coupled to reset in response to the third switch, and wherein the ramp signal is coupled to be generated at the output of the second operational amplifier.

7. The ramp generator of claim 1, wherein the fractional divider circuit comprises:

a programmable integer divider coupled to receive a clock signal and an output integer signal, wherein the programmable integer divider is coupled to divide the clock signal by a factor in response to the output integer signal to generate the switched capacitor control signal; and

a delta-sigma modulator coupled to receive a fractional modulus signal and an input integer signal to generate the output integer signal, wherein the output integer signal is a signal that is different at each cycle of the switched capacitor control signal and has a long-term average DC value substantially equal to the fractional divider ratio K, wherein the high resolution fine gain provided by the ramp generator is responsive to the fractional divider ratio K.

8. The ramp generator according to claim 7, wherein the programmable integer divider comprises:

a programmable counter coupled to receive the clock signal and the output integer signal from the delta-sigma modulator to generate a programmable counter output signal, wherein the programmable counter output signal comprises a plurality of pulses; and

a pulse width expander coupled to receive the programmable counter output signal to generate the switched capacitor control signal, wherein pulse width expander is configured to expand each of the plurality of pulses of the programmable counter output signal to a fixed duration for each first state of the switched capacitor control signal, and wherein each second state of the switched capacitor control signal has a variable duration.

9. The ramp generator according to claim 8, wherein each first state of the switched capacitor control signal is a logic high signal value, and wherein each second state of the switched capacitor control signal is a logic low signal value.

10. The ramp generator according to claim 7, wherein the delta-sigma modulator comprises a third order delta-sigma modulator.

11. The ramp generator according to claim 10, wherein the third order delta-sigma modulator comprises:

a first accumulator having a first input coupled to receive the fractional modulus signal and a second input coupled to receive an output of the first accumulator through a first z-transform functional block;

a second accumulator having a first input coupled to receive the output of the first accumulator and a second input coupled to receive an output of the second accumulator through a second z-transform functional block;

a third accumulator having a first input coupled to receive the output of the second accumulator and a second input coupled to receive an output of the third accumulator through a third z-transform functional block;

a first summing block coupled to add a carry output of the second accumulator, add a carry output of the third accumulator, and subtract an output of a fourth z-transform functional block coupled to the carry output of the third accumulator;

a second summing block coupled to add a carry output of the first accumulator, to add an output of the first summing block, and to subtract an output of a fifth z-transform functional block coupled to the output of the first summing block; and

a third summing block coupled to add the input integer signal to an output of the second summing block to generate the output integer signal.

12. An imaging system, comprising:

a pixel array having a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits is coupled to generate an image signal in response to incident light;

control circuitry coupled to the pixel array to control operation of the pixel array; and

readout circuitry coupled to the pixel array to readout the image data from the plurality of pixel cells over bit lines, wherein the readout circuitry comprises

A column comparator coupled to the bit line to receive the image data from the plurality of pixels and further coupled to receive a ramp signal during an analog-to-digital conversion operation to responsively provide a digital representation of the image data; and

a ramp generator coupled to generate the ramp signal with a high resolution fine gain in response to an adjustable fractional divider ratio K, the ramp generator comprising:

a current mirror having a first path coupled to conduct a capacitor current and a second path coupled to conduct an integrator current in response to the capacitor current;

a first switched capacitor circuit and a second switched capacitor circuit coupled to the first path;

a fractional divider circuit coupled to receive a clock signal to generate a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits in response to the fractional divider ratio K, wherein in response to each first state of the switched capacitor control signal,

the first switched capacitor circuit is coupled to be charged by the capacitor current and the second switched capacitor circuit is coupled to be discharged, wherein in response to each second state of the switched capacitor control signal, the first switched capacitor circuit is coupled to be discharged and the second switched capacitor circuit is coupled to be charged by the capacitor current; and

an integrator coupled to the second path to generate the ramp signal in response to the integrator current.

13. The imaging system of claim 12, further comprising functional logic coupled to the readout circuitry to store the image data read out of the pixel array.

14. The imaging system of claim 12, wherein the first switched capacitor circuit comprises:

a first capacitor;

a first switch coupled between the first capacitor and the first path, wherein the first switch is configured to turn on in response to the first state and turn off in response to the second state; and

a second switch coupled across the first capacitor, wherein the second switch is configured to turn off in response to the first state and turn on in response to the second state.

15. The imaging system of claim 14, wherein the second switched capacitor circuit comprises:

a second capacitor;

a third switch coupled between the second capacitor and the first path, wherein the third switch is configured to turn off in response to the first state and turn on in response to the second state; and

a fourth switch coupled across the second capacitor, wherein the fourth switch is configured to turn on in response to the first state and turn off in response to the second state.

16. The imaging system of claim 12, wherein the current mirror comprises:

a first transistor coupled between a voltage supply rail and the first path, wherein a control terminal of the first transistor is coupled to the first path; and

a second transistor coupled between the voltage supply rail and the second path, wherein a control terminal of the second transistor is coupled to the control terminal of the first transistor.

17. The imaging system of claim 16, wherein the ramp generator further comprises:

a first operational amplifier having a non-inverting input coupled to a reference capacitor voltage; and

a third transistor coupled between the first transistor and the first switched capacitor circuit, the second switched capacitor circuit, and an inverting input of the first operational amplifier through the first path, wherein a control terminal of the third transistor is coupled to an output of the first operational amplifier, and wherein the first operational amplifier is coupled to turn off the third transistor in response to voltages at the first switched capacitor circuit and the second switched capacitor circuit reaching the reference capacitor voltage.

18. The imaging system of claim 12, wherein the integrator comprises:

a second operational amplifier having a non-inverting input coupled to a reference voltage; and

a third capacitor coupled between an inverting input of the second operational amplifier and an output of the second operational amplifier; and

a third switch coupled between the inverting input of the second operational amplifier and the output of the second operational amplifier, wherein the integrator is coupled to reset in response to the third switch, and wherein the ramp signal is coupled to be generated at the output of the second operational amplifier.

19. The imaging system of claim 12, wherein the fractional divider circuit comprises:

a programmable integer divider coupled to receive a clock signal and an output integer signal, wherein the programmable integer divider is coupled to divide the clock signal by a factor in response to the output integer signal to generate the switched capacitor control signal; and

a delta-sigma modulator coupled to receive a fractional modulus signal and an input integer signal to generate the output integer signal, wherein the output integer signal is a signal that is different at each cycle of the switched capacitor control signal and has a long-term average DC value substantially equal to the fractional divider ratio K, wherein the high resolution fine gain provided by the ramp generator is responsive to the fractional divider ratio K.

20. The imaging system of claim 19, wherein the programmable integer divider comprises:

a programmable counter coupled to receive the clock signal and the output integer signal from the delta-sigma modulator to generate a programmable counter output signal, wherein the programmable counter output signal comprises a plurality of pulses; and

a pulse width expander coupled to receive the programmable counter output signal to generate the switched capacitor control signal, wherein pulse width expander is configured to expand each of the plurality of pulses of the programmable counter output signal to a fixed duration for each first state of the switched capacitor control signal, and wherein each second state of the switched capacitor control signal has a variable duration.

21. The imaging system of claim 20, wherein each first state of the switched capacitor control signal is a logic high signal value, and wherein each second state of the switched capacitor control signal is a logic low signal value.

22. The imaging system of claim 19, wherein the delta-sigma modulator comprises a three-level delta-sigma modulator.

23. The imaging system of claim 22, wherein the three-level delta-sigma modulator comprises:

a first accumulator having a first input coupled to receive the fractional modulus signal and a second input coupled to receive an output of the first accumulator through a first z-transform functional block;

a second accumulator having a first input coupled to receive the output of the first accumulator and a second input coupled to receive an output of the second accumulator through a second z-transform functional block;

a third accumulator having a first input coupled to receive the output of the second accumulator and a second input coupled to receive an output of the third accumulator through a third z-transform functional block;

a first summing block coupled to add a carry output of the second accumulator, add a carry output of the third accumulator, and subtract an output of a fourth z-transform functional block coupled to the carry output of the third accumulator;

a second summing block coupled to add a carry output of the first accumulator, to add an output of the first summing block, and to subtract an output of a fifth z-transform functional block coupled to the output of the first summing block; and

a third summing block coupled to add the input integer signal to an output of the second summing block to generate the output integer signal.

Technical Field

The present disclosure relates generally to image sensors and, in particular, but not exclusively, to ramp generators for use in image sensors.

Background

Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing.

Typical image sensors operate in response to image light from an external scene being incident on the image sensor. An image sensor includes an array of pixel cells having a photosensitive element (e.g., a photodiode) that absorbs a portion of incident image light and generates image charge after absorption of the image light. The image charge produced by the pixel cell can be measured as an analog output image signal on the column bit line that varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as analog signals from the column bitlines and converted to digital values to generate a digital image (i.e., image data) representing the external scene.

Disclosure of Invention

In one aspect, the present application provides a ramp generator providing a ramp signal with high resolution fine gain, comprising: a current mirror having a first path coupled to conduct a capacitor current and a second path coupled to conduct an integrator current in response to the capacitor current; a first switched capacitor circuit and a second switched capacitor circuit coupled to the first path; a fractional divider circuit coupled to receive a clock signal to generate a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits in response to an adjustable fractional divider ratio K, wherein the first switched capacitor circuit is coupled to be charged by the capacitor current and the second switched capacitor circuit is coupled to be discharged in response to each first state of the switched capacitor control signal, wherein the first switched capacitor circuit is coupled to be discharged and the second switched capacitor circuit is coupled to be charged by the capacitor current in response to each second state of the switched capacitor control signal; and an integrator coupled to the second path to generate the ramp signal in response to the integrator current.

In another aspect, the present application provides an imaging system comprising: a pixel array including a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits is coupled to generate an image signal in response to incident light; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry coupled to the pixel array to readout the image data from the plurality of pixel cells over bit lines, wherein the readout circuitry comprises: a column comparator coupled to the bit line to receive the image data from the plurality of pixels and further coupled to receive a ramp signal during an analog-to-digital conversion operation to responsively provide a digital representation of the image data; and a ramp generator coupled to generate the ramp signal with high resolution fine gain in response to an adjustable fractional divider ratio, K, the ramp generator comprising: a current mirror having a first path coupled to conduct a capacitor current and a second path coupled to conduct an integrator current in response to the capacitor current; a first switched capacitor circuit and a second switched capacitor circuit coupled to the first path; a fractional divider circuit coupled to receive a clock signal to generate a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits in response to the fractional divider ratio K, wherein the first switched capacitor circuit is coupled to be charged by the capacitor current and the second switched capacitor circuit is coupled to be discharged in response to each first state of the switched capacitor control signal, wherein the first switched capacitor circuit is coupled to be discharged and the second switched capacitor circuit is coupled to be charged by the capacitor current in response to each second state of the switched capacitor control signal; and an integrator coupled to the second path to generate the ramp signal in response to the integrator current.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Figure 1 illustrates one example of an imaging system including an image sensor with readout circuitry including a ramp generator with high resolution analog fine gain using a fractional divider with a delta-sigma modulator according to the teachings of this disclosure.

Fig. 2 is a graph illustrating the ideal gain of the measured gain relative to an example of a ramp generator without a high resolution analog fine gain using a fractional divider with a delta-sigma modulator according to the teachings of this disclosure.

Fig. 3A illustrates one example of a ramp generator with high resolution analog fine gain using a fractional divider with a delta-sigma modulator according to the teachings of the present disclosure.

Fig. 3B illustrates one example of an output ramp signal with an adjustable gain setting provided by a ramp generator with a high resolution analog fine gain using a fractional divider with a delta-sigma modulator according to the teachings of the present disclosure.

Fig. 4A shows one example diagram of a fractional divider with a delta-sigma modulator according to the teachings of this disclosure.

Fig. 4B shows one example of a signal in a fractional divider with a delta-sigma modulator according to the teachings of the present disclosure.

Fig. 5A shows a diagram of one example of a delta-sigma modulator according to the teachings of the present disclosure.

Fig. 5B shows an example plot of power spectral density of a delta-sigma modulator with respect to high order low pass filtering for reducing quantization noise according to the teachings of the present disclosure.

Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Additionally, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

Detailed Description

Various examples are described herein relating to imaging systems including image sensors having readout circuitry including ramp generators having high resolution analog fine gain using fractional dividers with delta-sigma modulators. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects.

Reference in the specification to "one example" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the invention. Thus, the appearances of the phrase "in one example" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

Spatially relative terms, such as "under," "below," "lower," "beneath," "above," "upper," "top," "bottom," "left," "right," "center," "middle," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s), as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or flipped, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an above and below orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In this specification, several terms of art are used. These terms have the ordinary meaning in the art to which they pertain unless specifically defined herein or otherwise clearly implied by the context of their use. It should be noted that element names and symbols are used interchangeably in the present invention (e.g., Si and silicon); however, both have the same meaning.

As will be discussed, examples of imaging systems are disclosed that include readout circuitry including a ramp generator with high resolution analog fine gain using a fractional divider with a delta-sigma modulator. In various examples, it will be appreciated that ultra-high resolution fine gain is achieved with little loss in power consumption or chip area. For example, in one example, 1/2 according to the teachings of this disclosure²⁰Can be achieved in a 40nm process using an area of about 40 μmx 100 μm and a power consumption of less than 1 mW.

By way of example, fig. 1 illustrates one example of an imaging system 100 according to an embodiment of the present disclosure. Imaging system 100 includes pixel array 102, control circuitry 110, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array of pixel cells 104 including one or more photodiodes (e.g., pixels P1, P2, …, Pn). As illustrated in the example, the pixel cells 104 are arranged in rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, location, object, etc., which can then be used to render a 2D image of the person, location, object, etc. It should be appreciated, however, that the pixel cells 104 do not necessarily have to be arranged in rows and columns, and other configurations may be employed.

In one example, control circuitry 110 is coupled to pixel array 102 to control the operation of a plurality of pixel cells 104 in pixel array 102. For example, the control circuitry 110 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal that is used to simultaneously enable all pixel cells 104 within the pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, each column, or each group of pixel cells 104 is sequentially enabled during a continuous acquisition window. In another example, image acquisition is synchronized with a lighting effect, such as a flash.

In one example, the imaging system 100 may be included in a digital camera, cell phone, laptop, or the like. In addition, the imaging system 100 may be coupled to other hardware parts, such as a processor (general purpose or otherwise), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lights/flashes, electrical input devices (keyboard, touch display, touch pad, mouse, microphone, etc.), and/or a display. Other hardware parts may deliver instructions to the imaging system 100, extract image data from the imaging system 100, and/or manipulate image data supplied by the imaging system 100.

In one example, after each pixel cell 104 in pixel array 102 acquires its image charge through the photo-generation of the image charge, the corresponding image data is readout by readout circuitry 106 and then transferred to functional logic 108. Readout circuitry 106 can be coupled to readout image data from a plurality of pixel cells 104 in pixel array 102. In the illustrated example, readout circuitry 106 may include analog-to-digital conversion (ADC) circuitry 113, amplification circuitry, and other image sensing readout circuitry. In the illustrated example, the ramp generator 114 and the column comparator 118 may be included in the readout circuitry 106. In some embodiments, there may be a column comparator 118 for each read column, and the ramp generator 114 may be coupled to provide a ramp signal VRAMP 116 to each column comparator 118. Functional logic 108 may be coupled only to readout circuitry 106 to store image data or even manipulate image data by applying post-image effects (e.g., cropping, rotating, red-eye removal, brightness adjustment, contrast adjustment, or otherwise). In one example, readout circuitry 106 may readout a row of image data at a time along bit lines 112, as illustrated, or may readout the image data using various other techniques (not illustrated), such as serial readout or readout of all pixel cells 104 all in parallel at the same time.

In the depicted example, the ADC 113 included in the readout circuitry 106 is a ramp-type ADC that performs analog-to-digital conversion using a ramp generator 114 to provide a ramp signal VRAMP 116 as a reference to a column comparator 118 associated with each readout column. For the ramp type ADC, a counter (not illustrated) starts counting at the start of the ramp signal VRAMP 116, and is compared with the analog image signal. At a point in time when the ramp signal VRMAP 116 is equal to the analog image signal, the value of the counter is latched as a digital representation of the analog image signal.

In one example, to implement an image sensor with high resolution analog-to-digital conversion, the gain of the ramp signal VRAMP 116 is adjusted. The gain of the ramp signal VRAMP 116 is the ratio of the ramp slopes, which is defined as the following equation (1):

therefore, the gain of the ramp signal is equal to the slope of the ramp signal when the gain is equal to 1 divided by the slope of the ramp signal. In other words, the gain is inversely proportional to the slope or:

analog coarse gain adjustment may be performed in the array column circuitry (e.g., 1x, 2x, 4x, 8x adjustment), while analog fine gain adjustment may be performed in the ramp generator. One challenge in performing analog fine gain adjustment in a ramp generator is that there are typically only a limited number of fine gain adjustment steps that can be performed, such as, for example, 1/16 adjustments. In this limited number of fine gain adjustment steps (e.g., 1/16 adjustments) in the ramp generator, there is a large gain error, especially at higher gain values.

For example, fig. 2 is a graph 220 showing the ideal gain of the measured gain relative to the example of the ramp generator described above with only a limited number of fine gain adjustment steps. As illustrated in the example of fig. 2, the ideal gain is shown as a smooth diagonal, while the measured gain of a ramp generator with limited fine gain adjustment steps is a "staircase" line with "steps" that become more and more prominent as the gain increases. In a ramp generator with such limited gain steps, the relative distance between the diagonal ideal gain map and the measured gain map with steps is not equal and deteriorates as the gain increases. In other words, the distance of the actual steps 222 and 226 to the ideal diagonal is not equal to the distance of the point 224 where the gain is measured to the ideal diagonal. Therefore, there is a large gain error at point 224 where the gain map is measured.

As will be described below, a ramp generator according to the teachings of this disclosure utilizes a delta-sigma modulator divider to achieve ultra-high resolution fine gain steps. By way of example, fig. 3A illustrates one example of a ramp generator 314 having a high resolution analog fine gain using a fractional divider with a delta-sigma modulator according to the teachings of the present disclosure. It should be appreciated that the ramp generator 314 of fig. 3A may be one example of the ramp generator 114 in the readout circuitry 106 of the image sensor 100 shown in fig. 1, and similarly named and numbered elements described above are similarly coupled and operated below.

As illustrated in the depicted example, the hair is rampedThe generator 314 includes a current mirror including transistors 328 and 330, the transistors 328 and 330 having their gate terminals coupled to each other, as shown. In an example, transistors 328 and 330 are P-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). In other examples, it should be appreciated that other types of transistors may be used to implement the current mirror. In an example, the source terminal of the transistor 328 is coupled to the voltage supply rail, and the gate and drain terminals of the transistor 328 are coupled together. A source terminal of transistor 330 is coupled to the voltage supply rail. Thus, the current mirror has a first current mirror path 329 coupled to transistor 328 and a second current mirror path 333 coupled to transistor 330. In an example, transistor 328 has a relative channel width proportional to M, and transistor 330 has a relative channel width proportional to N. Thus, the capacitor current I is dependent on the N/M ratio of the first 328 and second 330 transistors_cap331 is conducted through the first path 329 and mirrors the integrator current I_integ335 are passed through a second path 333.

As shown in the example of fig. 3A, a first switched capacitor circuit 341 and a second switched capacitor circuit 343 are coupled to the first path 329. The first switched capacitor circuit 341 includes a switch 342, a first capacitor 354, and a switch 350 coupled as shown. The second switched-capacitor circuit 343 includes a switch 352, a second capacitor 356, and a switch 344 coupled as shown.

The depicted example also illustrates that the ramp generator 314 includes a fractional divider circuit 336. In an example, the fractional divider circuit 336 has an adjustable fractional divider ratio, K, that provides high resolution analog fine gain to the ramp generator 314 in accordance with the teachings of this disclosure. The fractional divider circuit 336 is coupled to receive the clock signal PLL _ CLK (f)_pll)338 for generating a switched capacitor control signal sc _ ctrl (f) in response to an adjustable fractional divider ratio K_sc)340. Switched capacitor control signal sc _ ctrl (f)_sc)340 oscillate between first and second states (e.g., on and off states or logic high and logic low states) to control the switching of the first switched capacitor circuit 341 and the second switched capacitor circuit 343. In operation, in response to a switchEach first state of the capacitor control signal 340, the first switched capacitor circuit 341, is coupled to be driven by a capacitor current I_cap331 are charged and the second switched capacitor circuit 343 is coupled to be discharged. In response to each second state of the switched capacitor control signal 340, the first switched capacitor circuit 341 is coupled to discharge and the second switched capacitor circuit 343 is coupled to be charged by the capacitor current I_cap331 is charged.

In the depicted example, the fractional divider circuit 336 is also coupled to generate a switched capacitor control signal sc _ ctrl _ b (f)_sc)348 that oscillate between second and first states (e.g., off and on states or logic low and logic high states) to control the first and second switched capacitor circuits 341, 343. In one example, switched capacitor control signal sc _ ctrl _ b (f)_sc)348 is responsive to the switched capacitor control signal sc _ ctrl (f)_sc)340 such that only one of the two signals may be in a first state (e.g., an on state) at a time. In one example, switched capacitor control signal sc _ ctrl 340 and switched capacitor control signal sc _ ctrl _ b 348 are complementary to each other, or in another example, switched capacitor control signal sc _ ctrl 340 and switched capacitor control signal sc _ ctrl _ b 348 are out of phase with each other, such that it is not possible for both signals to be in the first state at the same time. In addition, both switched capacitor control signal sc _ ctrl 340 and switched capacitor control signal sc _ ctrl _ b 348 have the same frequency f_sc。

Thus, in the example depicted in fig. 3A, switches 342 and 344 are coupled to be responsive to switched capacitor control signal sc _ ctrl (f)_sc)340 is in a first state to turn on to charge capacitor 354 and discharge capacitor 356. Meanwhile, switches 350 and 352 are coupled to be responsive to switched capacitor control signal sc _ ctrl _ b (f)_sc)348 is in a second state and is off to enable charging of capacitor 354 and prevent charging of capacitor 356. Similarly, switches 350 and 352 are coupled in response to switched capacitor control signal sc _ ctrl _ b (f)_sc)348 is in a first state to turn on to discharge capacitor 354 and charge capacitor 356. Also, switches 342 and 344 are coupled in responseAt switched capacitor control signal sc _ ctrl (f)_sc)340 is in a second state and is off to prevent the capacitor 354 from being charged and to enable charging of the capacitor 356. Thus, capacitors 354 and 356 are responsive to switched capacitor control signal sc _ ctrl (f)_sc)340 and switched capacitor control signal sc _ ctrl _ b (f)_sc)348 to alternately charge and discharge.

In the illustrated example, the ramp generator 314 also includes an operational amplifier 334 having a voltage V coupled to a reference capacitor_{ref_cap}Is provided. The transistor 332 is coupled between the transistor 328 and the first switched capacitor circuit 341, the second switched capacitor circuit 343, and the inverting input of the operational amplifier 334 through a current path 329. A control terminal (e.g., gate) of transistor 332 is coupled to the output of operational amplifier 334. Thus, the operational amplifier 334 is coupled to be responsive to the voltage V at the first switched capacitor circuit 341 or the second switched capacitor circuit 343_capUp to the reference capacitor voltage V_{ref_cap}And turns off transistor 332. Thus, the operational amplifier 334 and the transistor 332 are coupled to V at the first switched capacitor circuit 341 or the second switched capacitor circuit 343_capVoltage is fully charged to V_{ref_cap}Turning off the charging capacitor current I through current path 329 after the reference voltage_cap 331。

The depicted example also illustrates that the ramp generator 314 includes a current path 333 coupled to be responsive to the integrator current I_integ335 to produce a ramp signal VRAMP 316. In one example, ramp signal VRAMP 316 is coupled to be received by a column comparator, such as column comparator 118 illustrated in fig. 1. As shown in the example illustrated in FIG. 3A, the integrator includes an operational amplifier 358 having a coupling to a reference voltage V_refIs provided. Capacitor C_integ360 is coupled between the inverting input of operational amplifier 358 and the output of operational amplifier 358. Switch 362 is coupled between the inverting input of operational amplifier 358 and the output of operational amplifier 358. The integrator is coupled to reset in response to closing switch 362, and each ramp of ramp signal VRAMP 316 is coupled to operate when switch 362 is openedBeginning at the output of amplifier 358.

In operation, ultra-high resolution analog fine gain is achieved with the ramp generator 314 using a fractional divider 336, the fractional divider 336 including circuitry for generating a switched capacitor control signal sc _ ctrl (f)_sc)340 and switched capacitor control signal sc _ ctrl _ b 348 (f)_sc) To control the switching of the switched capacitor circuits 341 and 343 comprising capacitors 354 and 356, respectively. As will be discussed, the ultra-high resolution analog fine gain varies the capacitor current I by adjusting the fractional divider ratio K of the fractional divider 336 in response to teachings in accordance with this disclosure_cap331. In an example, the charging capacitor current I_cap331 is generated by switching switched capacitor circuits 341 and 343. In particular, the charging capacitor current I_cap331 is defined by the following equation (3):

I_cap＝f_scC₀V_cap (3)

wherein the switched capacitor control signal sc _ ctrl (f)_sc)340 and switched capacitor control signal sc _ ctrl _ b (f)_sc)348 has a switching frequency f_scThe capacitance of both capacitors 354 and 356 is equal to C₀And the voltage across capacitors 354 and 356 of the switched capacitor circuit is V_cap. Due to the current I through path 329_cap331 mirrors to path 333 using a current mirror, so integrator current I_integ335 is defined as the following equation (4):

where N represents the relative channel width of transistor 330, M represents the relative channel width of transistor 328, and f_pllIs the frequency of the phase-locked loop clock signal (PLL _ CLK)338 received by the fractional divider 336, and K is the adjustable fractional divider ratio of the fractional divider circuit 336.

Suppose V_cap、C₀N and M are constant, then the ultra-high resolution fine gain is adjusted by ramp generator circuit 314Integer fractional divider ratio K. Thus, the gain of the ramp generator circuit 314 is defined by the relationship of equation (5):

thus, assuming, for example, that the fractional divider ratio K-8 provides a fine gain equal to 1, then the fractional divider ratio K-16 will provide a gain of 16/8-2 according to equation (5). Similarly, 1¹/₃₂The gain of (c) is provided at K-8.25 because 8.25/8-1¹/₃₂，1²/₃₂Is provided under K ═ 8.5, since 8.5/8 ═ 1²/₃₂And so on. Thus, ultra-high resolution fine gain is achieved by ramp generator circuit 314 by adjusting the fractional divider ratio, K, according to the teachings of this disclosure.

Fig. 3B illustrates one example for which the fractional divider ratio K setting is adjusted to achieve a high resolution analog fine gain of the output ramp signal VRAMP 316 in a ramp generator using a fractional divider with a delta sigma modulator according to the teachings of the present disclosure. As discussed above in equation (2), the gain is inversely proportional to the slope. Thus, the gain of ramp signal 316-2 is twice the gain of ramp signal 316-1 because the slope of ramp signal 316-2 is 0.5 times the slope of ramp signal 316-1. In an example where the fractional divider ratio K-8, a fine gain equal to 1 is provided to provide the ramp signal 316-1, then in that example K is adjusted to K-16 to provide the ramp signal 316-2 with a fine gain equal to 2 or a slope of 0.5 times, in accordance with the teachings of this disclosure.

Fig. 4A shows one example diagram of a fractional divider 436 with a delta-sigma modulator according to the teachings of this disclosure. It should be appreciated that the fractional divider 436 of fig. 4A may be one example of the fractional divider 336 shown in fig. 3A, and similarly named and numbered elements described above are similarly coupled and operate below. In the example depicted in fig. 4A, the fractional divider 436 includes a programmable integer divider 464 coupled to receive the clock signal PLL _ CLK(f_pll)438 and output integer signal P<7:0>468. In operation, the programmable integer divider 464 is coupled to be responsive to the output integer signal P<7:0>468 to enable the clock signal PLL _ CLK (f)_pll)438 by a factor to produce the switched capacitor control signal sc _ ctrl (f)_sc)440. The delta-sigma modulator 466 is coupled to receive a fractional modulus signal dsm _ frac<19:0>472 and an input integer signal dsm _ integer<6:0>470 to generate the output integer signal P<7:0>468. In an example, the output integer signal P generated by the delta-sigma modulator 466<7:0>468 is a switched capacitor control signal sc _ ctrl (f) having a long-term average DC value over time substantially equal to the fractional divider ratio K_sc)440 different signals per cycle.

In operation, the high resolution fine gain provided by ramp generator 314 is responsive to the fractional divider ratio K described above with respect to equation (5) in accordance with the teachings of this disclosure. As will be described in more detail below, in one example, the accumulator included in the delta-sigma modulator 466 is a cascaded 20-bit overflow accumulator. Thus, the fractional divider ratio K can be defined using equation (6) as follows:

wherein P is_avgIs an integer whose long-term DC average is the fractional divider ratio K, dsm _ integer<6:0>Is an input integer signal, and dsm _ frac<19:0>Is a fractional modulus signal. Thus, the long-term average frequency f of the switched capacitor control signal sc _ ctrl 440_sc,avgCan be defined as follows using equation (7):

wherein f is_pllIs the switching frequency of the clock signal PLL _ CLK 438.

Continuing with the example depicted in FIG. 4A, the programmable integer divider 464 includes a programmable counter 474 coupled to receive the clock signal PLL \uCLK(f_pll)438 and the output integer signal P from the delta sigma modulator 466<7:0>468 to generate a programmable counter output signal PCNT 475. In an example, the programmable counter output signal PCNT 475 comprises a plurality of short pulses. Pulse width expander 476 is coupled to receive programmable counter output signal PCNT 475 to generate switched capacitor control signal sc _ ctrl (f)_sc)440, switched capacitor control signal sc _ ctrl (f), as described above_sc)440 are used to control switched capacitor circuits 341 and 343 in fig. 3A. In operation, the pulse width expander 476 is configured to expand each of a plurality of short pulses of the programmable counter output signal PCNT 475 to be used for the switched capacitor control signal sc _ ctrl (f)_sc)440 for a fixed duration of each first state (e.g., each logic high state), and switched capacitor control signal sc _ ctrl (f)_sc) Each second state (e.g., each logic low state) of 440 has a variable duration.

By way of example, fig. 4B shows one example of the signals seen in the fractional divider 436 with a delta-sigma modulator 466 in accordance with the teachings of the present disclosure. As shown in FIG. 4B, the clock signal PLL _ CLK (f)_pll)438 is a high frequency pulse train of short pulses. Output integer signal P generated by delta-sigma modulator 466<7:0>468 is at the switched capacitor control signal sc _ ctrl (f)_sc)440 each cycle of the loop by a different integer value. Output integer signal P<7:0>The long-term average DC value over time of 468 is substantially equal to the fractional divider ratio K. The programmable counter output signal PCNT 475 is a plurality of short pulses, which in the illustrated example, have a pulse width equal to the clock signal PLL _ CLK (f)_pll)438 pulse width of 1 input clock cycle. Switched capacitor control signal sc _ ctrl (f)_sc)440 are generated by pulse width expander 476 in response to programmable counter output signal PCNT 475. In an example, pulse width expander 476 expands each short pulse of programmable counter output signal PCNT 475 to a particular fixed '1' pulse width.

It should be appreciated that switched capacitor control signal sc _ ctrl (f)_sc) One key consideration for the fixed '1' pulse width per pulse of 440 is to maintain good linearity and ensure switched capacitance in fig. 3ARespective capacitors 354 and 356 of the respective converter circuits 341 and 343 may be responsive to the switched capacitor control signal sc _ ctrl (f)_sc)440 are fully charged for each fixed pulse width of each '1' pulse and are in switched capacitor control signal sc _ ctrl (f)_sc)440 are fully discharged within each non-fixed or variable pulse width of each '0' pulse.

In various examples, the switched capacitor control signal sc _ ctrl (f) generated by fractional divider 436_sc)440 have skewed duty cycles while maintaining fixed width '1' pulses and non-fixed or variable pulse width '0' pulses, as shown in fig. 4B. Thus, in various examples, switched capacitor control signal sc _ ctrl (f) is switched every cycle_sc) The minimum period of 440 is at least twice the width of the fixed '1' pulse width. In other words, in one example, switched capacitor control signal sc _ ctrl (f)_sc) The maximum duty cycle per cycle of 440 is 50%.

Fig. 5A shows a diagram of one example of a delta-sigma modulator 566 in accordance with the teachings of the present disclosure. It should be appreciated that the delta-sigma modulator 566 of fig. 5A may be one example of the delta-sigma modulator 466 of fig. 4A or the delta-sigma modulator included in the fractional divider 336 of fig. 3A, and similarly named and numbered elements described above are similarly coupled and operated below. It should be appreciated that the delta-sigma modulator 566 illustrated in fig. 5A is an example of a 3-order multi-level noise shaping (MASH) delta-sigma modulator with dithering that includes three cascaded overflow accumulators, each of which is equivalent to a 1-order delta-sigma modulator. In the example, the carry outputs are combined by the shown summation and z-transform functional blocks or delays to generate output integer signals P <7:0>568, which are pseudorandom sequences having long-term average DC values substantially equal to the fractional divider ratio K over time. In other examples, it should be appreciated that the delta-sigma modulator 566 may be implemented using other suitable delta-sigma or sigma-delta modulator structures in accordance with the teachings of this disclosure.

As shown in the example illustrated in FIG. 5A, the delta-sigma modulator 566 includes a first accumulator 578-1 having a first input A coupled to receive a fractional modulus signal dsm _ frac <19:0>570 (which is also referred to as "k" in FIG. 5A) and a second input B coupled to receive an output A + B of the first accumulator 578-1 through a first z-transform functional block 580-1. The second accumulator 578-2 includes a first input A coupled to receive the output A + B of the first accumulator 578-1 and a second input B coupled to receive the output A + B of the second accumulator 578-2 through a second z-transform functional block 580-2. The third accumulator 578-3 includes a first input A coupled to receive the output A + B of the second accumulator 578-2 and a second input B coupled to receive the output A + B of the third accumulator 578-3 through a third z-transform functional block 580-3. First summing block 582-1 is coupled to add carry output c2[ n ] of second accumulator 578-2, add carry output c2[3] of third accumulator 578-3, and subtract the output of fourth z-transform function block 580-4 coupled to carry output c3[ n ] of third accumulator 578-3. The second summing block 582-2 is coupled to add the carry output c1[ n ] of the first accumulator 578-1, add the output of the first summing block 582-1, and subtract the output of the fifth z-transform function block 580-5 coupled to the output of the first summing block 582-1. The third summing block 582-3 is coupled to add an input integer signal dsm _ integer <6:0> (which is also referred to as "N" in FIG. 5A) to the output of the second summing block 582-2 to produce an output integer signal P <7:0 >.

In operation, each stage of the delta-sigma modulator 566 cancels the quantization noise e of the previous stage_x[n]. Thus, e3[ n ] remains]The quantization noise is the quantization noise of the delta-sigma modulator 566, which is shaped by the third order high pass filtering provided by the three-level delta-sigma modulator 566 example shown in fig. 5A. Note that Δ [ n ] output by second z-transform block 580-2 to the B input of second accumulator 578-2]Jitter is 1-bit Pseudo Random Binary Sequence (PRBS) jitter noise that is shaped by a second order high pass. Therefore, it should also be noted that the input dN of the third summing block 582-3 may be characterized as follows using equation (8):

dN＝k+e3[n](1-z^-1)³+Δ[n](1-z^-1)² (8)

where dN represents the output of the second summing block 582-2, k represents the input a to the first accumulator 578-1, and Δ n represents the jitter output from the second z transform block 580-2.

FIG. 5B shows a delta-sigma modulator 566 output with respect to reducing quantization noise according to teachings of the present disclosureAn example illustration of the provided higher order low pass filtered Power Spectral Density (PSD) of the acoustic effect. In particular, the graph on the left side of fig. 5B shows that the power spectral density of the output of the delta-sigma modulator 566 has a peak energy near the Nyquist frequency, which is about half the sampling frequency, or f_s/2. It will be appreciated that quantization noise will affect the line time noise (RTN) of the image sensor. However, the delta-sigma modulator 566 in accordance with the teachings of this disclosure shapes the quantization noise such that most of the quantization noise is pushed to the higher frequency region, as shown in the left side of the graph of fig. 5B. Additionally, an example imaging system in accordance with the teachings of this disclosure has multiple poles (e.g., switched capacitor circuits, current mirrors, ramp buffer operational amplifiers, comparators, etc.) that are used as (at least) 4 th order low pass filtering to help reduce the effects of noise, as illustrated in the graph on the right side of fig. 5B. As illustrated, the higher order low pass filtering reduces the effect of quantization noise because most quantization noise is pushed to higher frequency regions according to the teachings of this disclosure.

The above description of illustrated examples of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with accepted theories as interpreted by the claims.