阅读说明：本技术 具有电流测量电路的功率晶体管布置 (Power transistor arrangement with current measurement circuit ) 是由 R·埃克尔特 S·施特拉赫 A·巴尔纳 T·罗扎尔 于 2020-03-13 设计创作，主要内容包括：描述一种功率晶体管布置(11),其包括功率晶体管(12)和与所述功率晶体管(12)连接的电流测量电路(13),所述电流测量电路用于确定通过所述功率晶体管(12)的通过电流。所述通过电流从所述功率晶体管(12)的源极连接端(14)经由至少一个源极键合线(15)传导。在所述源极键合线(15)的朝向所述源极连接端的(14)第一端(17)与所述源极连接端(14)之间连接有第一测量键合线(16)。在所述源极键合线(15)的背向所述源极连接端(14)的第二端(19)的后面连接有第二测量键合线(18)。所述两个测量键合线(16,18)与所述电流测量电路(13)连接。已知的功率晶体管布置仅具有有限可靠的过电流保护。根据本发明,除了所述第一和第二测量键合线(16,18)之外,在所述源极键合线(15)的第二端(19)的后面还连接有第三测量键合线(21),其中,所述第三测量键合线(21)也与所述电流测量电路(13)连接。由此能够独立于通过所述源极键合线(15)的电流地确定栅极电荷,由此改善用于所述功率晶体管(12)的过电流保护。(A power transistor arrangement (11) is described, comprising a power transistor (12) and a current measurement circuit (13) connected to the power transistor (12) for determining a through current through the power transistor (12). The through current is conducted from a source connection (14) of the power transistor (12) via at least one source bonding wire (15). A first measuring bond wire (16) is connected between a first end (17) of the source bond wire (15) facing the source connection (14) and the source connection (14). A second measuring bond wire (18) is connected to the rear of a second end (19) of the source bond wire (15) facing away from the source connection (14). The two measuring bond wires (16, 18) are connected to the current measuring circuit (13). The known power transistor arrangements have only a limited reliable overcurrent protection. According to the invention, in addition to the first and second measuring bond wires (16, 18), a third measuring bond wire (21) is connected behind the second end (19) of the source bond wire (15), wherein the third measuring bond wire (21) is also connected to the current measuring circuit (13). Thereby enabling determination of the gate charge independently of the current through the source bond wire (15), thereby improving overcurrent protection for the power transistor (12).)

1. A power transistor arrangement (11) comprising a power transistor (12) and a current measurement circuit (13) connected to the power transistor (12) for determining a passing current through the power transistor (12),

wherein the through current is conducted from a source connection (14) of the power transistor (12) via at least one source bonding wire (15),

wherein a first measuring bond wire (16) is connected between a first end (17) of the source bond wire (15) facing the source connection (14) and the source connection (14),

wherein a second measuring bond wire (18) is connected behind a second end (19) of the source bond wire (15) facing away from the source connection (14),

wherein the two measuring bond wires (16, 18) are connected with the current measuring circuit (13),

characterized in that in addition to the first and second measuring bond wires (16, 18) a third measuring bond wire (21) is connected in front of the first end (17) of the source bond wire (15), wherein the third measuring bond wire (21) is connected to the reference ground of the current measuring circuit (13).

2. The power transistor arrangement (11) according to claim 1, wherein the power transistor arrangement comprises a gate drive circuit (20) for manipulating the gate connection terminal of the power transistor (12), wherein the first and second measurement bond wires (16, 18) are decoupled from the gate drive circuit (20) by the third measurement bond wire (21).

3. The power transistor arrangement (11) according to claim 1 or 2, wherein the current measurement circuit (13) comprises a differential amplifier (22) to determine a voltage difference between the two ends (17, 19) of the source bond wire (15) from the voltage obtained by the measurement bond wires (16, 18, 21) and to determine therefrom a through current through the power transistor (12).

4. The power transistor arrangement (11) according to claim 3, wherein the current measurement circuit (13) is arranged for reprocessing the output of the differential amplifier (22) by analog analysis processing and/or digital analysis processing.

5. The power transistor arrangement (11) according to any of the preceding claims, wherein a first voltage path (23) of the first measurement bond wire (16) between the first end (17) of the source bond wire (15) and the current measurement circuit (13) and a second voltage path (24) of the second measurement bond wire (18) between the second end (19) of the source bond wire (15) and the current measurement circuit (13) are connected via an integrator (25).

6. The power transistor arrangement (11) according to claim 6, wherein the second voltage path (24) provides a second signal input for the differential amplifier (22).

7. The power transistor arrangement (11) according to any of the preceding claims, wherein the current measurement circuit (13) is provided for determining not only a passing current through the power transistor (12) but also a gate charge during a switching process of the power transistor (12).

Technical Field

The invention relates to a power transistor arrangement comprising a power transistor and a current measuring circuit connected to the power transistor for determining a through current (Durchgangstrom) through the power transistor, wherein the through current is conducted from a source connection of the power transistor via at least one source bonding wire, wherein a first measuring bonding wire is connected between a first end of the source bonding wire facing the source connection and the source connection. This also has the function of both ground reference and gate-steered powering of the gate driver. A second measuring bond wire is connected to the rear of a second end of the source bond wire, which end faces away from the source connection, wherein the two measuring bond wires are connected to a current measuring circuit.

Background

In inverters for controlling electric motors in electric vehicles, it is known to measure the current flowing through the respective power transistor in order to detect an overload (also referred to as current sensing). For this purpose, a number of different methods are used, for example DESAT identification, the voltage being integrated over the source inductance (of the source bond wires) or also the so-called SENSE emitter output in IGBTs (Insulated-Gate Bipolar transistors) or the SENSE FET in MOSFETs (metal-oxide-semiconductor-field effect transistors).

Due to new fast power semiconductor technologies, such as silicon carbide (SiC) transistors and gallium nitride (GaN) transistors, the requirements for safe turn-off of such power transistors are becoming more and more stringent. The concept of redundancy is also preferred within the scope of the safety requirements.

DESAT (desaturation) recognition is currently mainly used. The DESAT recognition can be implemented very simply in IGBT systems. Furthermore, IGBTs are typically short-circuit safe up to 10 μ s, so that the time requirement for overcurrent detection is lower than in the case of newer SiC and GaN technologies. Since the high-voltage diode is externally wired for decoupling in the DESAT detection, an additional dead time (ausbletzeit) must be introduced in order to prevent incorrect detection.

As an alternative, a SENSE FET, i.e. a part of the power semiconductor for measuring the through current, is used. This solution has the following drawbacks: a special layout of the power semiconductors has to be given. Furthermore, the dynamics are limited and the high cost compared to conventional power semiconductors makes this solution therefore less interesting.

For high current variations, the method of integrating the voltage over the source bond wire is very fast and sufficiently accurate. The resulting measurement signals are very large and can therefore be processed in a good manner. In clocked DC/DC converters, this method is also used for current sensing and can be found in the literature under the keyword "DCR sensing".

Alternatively, however, the gate charge is also measured and taken into account for the overcurrent evaluation, for example. The latter are known from "A high-speed protection Circuit for designing objects to hard-switching functions" by T.horiguchi and H.Akagi (IEEE Transactions on Industrial Applications, 51 st., No. 2, 1774 pages 1781, 2015. 3) (hereinafter: Horiguchi et al) and from "Short Circuit Detection Using the Gate Charge transfer for Trench/Fieldtop IGBTs" (18 th European Power electronics and Applications conference for ECE ', 2016) (hereinafter: Obereck et al) by K.Oberdieck, S.Soenke and R.W.DeDonker (18 th European Power and Applications conference for ECE', 2016), hereinafter: Oberdike et al, are known. This solution is cost effective and can be performed with low overhead and thus the overcurrent can be detected very quickly. As in the case of the solution for measuring the voltage at the source inductance, too, the nodes that are critical for high voltages are not detected. Since the MOSFET is operated by means of a voltage source, a series resistance is required in the implementation, as a result of which the gate charge can be measured. In current source based gate drive circuits, no external gate resistance is required. Thus, the measurement of the gate charge becomes more difficult, because an additional shunt is required, which generates losses, produces only a small signal, and has an influence on the manipulation.

Disclosure of Invention

According to the invention, a power transistor of the type mentioned at the beginning is provided, wherein a third measuring bond wire is connected in front of the first end of the source bond wire in addition to the first and second measuring bond wires, wherein the third measuring bond wire is also connected to the reference ground of the current measuring circuit.

THE ADVANTAGES OF THE PRESENT INVENTION

With this solution a power transistor arrangement is provided which is capable of measuring the gate charge in a combination consisting of a source inductance measurement and a parallel source inductance measurement without gate charge errors. A difference can be formed by the two measurements, by means of which the gate charge can be determined. Thereby, a dynamic measurement of the gate charge can be achieved in a current source based gate drive circuit without the same disadvantages as in a current source based gate drive circuit with an additional shunt. The additional overhead for detecting the gate charge is low and can be integrated very simply in an ASIC, for example.

With the new scheme of gate charge measurement in a current source based gate drive circuit, a second dynamic over-current detection can be achieved with minimal additional overhead (second bonding).

By redundant measurement of the voltage at the source inductanceIt is possible to simultaneously measure not only the direct current value in the power path, but also the gate charge required to turn on the power transistor. This can also be done without an external shunt, contrary to the solution in Horiguchi et al or Oberdieck et al, and can therefore also be used in gate drive circuits using the current source principle. By evaluation of the gate charge, different criteria can be evaluated. Capable of detecting over-currents or taking characterization measurements. This can also be done independently of the actuation. In contrast to gate drive circuits using the current source principle, in gate drive circuits based on a voltage source, a series resistance is presentIt must be designed differently according to the operating point. The splitter-based evaluation circuit (Horiguchi et al or obendieck et al) must always be matched again here.

The second measuring bond wire may differ from the third measuring bond wire, for example, in that the second measuring bond wire is coupled to the first measuring bond wire by an integrator. The integrator is preferably a resistor-capacitor network (RC network).

In a preferred embodiment, the power transistor arrangement comprises a gate drive circuit for operating the gate connection of the power transistor, wherein the first and second measurement bond wires are decoupled from the gate drive circuit by a third measurement bond wire. By means of an additional measuring bond wire decoupling the gate drive circuit from the current measuring circuit, the through current through the power transistor can be measured very well. By performing the scheme of two integrations, the following difference is obtained: this difference presents an error through the gate charge path and corresponds accurately to the gate charge. By means of this differential measurement, the gate charge during each switching process can additionally be determined, and an evaluation of the operating point can be carried out, and a safety shutdown can be carried out in the event of a short circuit. Furthermore, in a power transistor arrangement with power semiconductors connected in parallel, it is possible to identify the case in which individual components fail or are no longer switched on. This may be the case, for example, when the bond is broken or delaminated (Delamination).

In another embodiment, the current measurement circuit includes a differential amplifier to determine a voltage difference between the two ends of the source bond wire from the voltage obtained by the measurement bond wire and thereby determine the through current through the power transistor. The through current may be calculated by integration. In addition to the exact determination of the pass current, the gate charge can also be determined additionally by taking into account the third measuring bond wire, and thus a redundant overcurrent protection is achieved.

It is preferred if the current measurement circuit is arranged for reprocessing the output of the differential amplifier by means of an analog analysis process and/or a digital analysis process. This functionality may be integrated, for example, in an ASIC of the current measuring circuit.

In a preferred embodiment, a first voltage path of the first measurement bond wire between the first end of the source bond wire and the current measurement circuit and a second voltage path of the second measurement bond wire between the second end of the source bond wire and the current measurement circuit are connected via an integrator. The integrator is preferably a resistor-capacitor network (RC network) in this case. The voltage difference over the source bond wire can thus be determined by the current measurement circuit.

In another embodiment, the second voltage path provides a second signal input to the differential amplifier. By combining the two signals from the three voltage paths of the three measuring bond wires, it is then possible to determine not only the through current but also the gate charge accurately. The operating point can thus be evaluated and a more reliable safety shutdown can be achieved in the event of a short circuit.

It is preferred if the current measuring circuit is arranged for determining not only the through current through the power transistor but also the gate charge during the switching process of the power transistor.

Advantageous embodiments of the invention are specified in the dependent claims and are described in the description.

Drawings

Embodiments of the present invention are explained in more detail based on the drawings and the following description. The figures show:

figure 1 shows an embodiment of a power transistor arrangement according to the invention,

figure 2 shows an embodiment of a power transistor arrangement according to the invention,

fig. 3 shows another embodiment of a power transistor arrangement according to the present invention.

Detailed Description

Fig. 1 shows a prior art power transistor arrangement 1. The power transistor arrangement 1 comprises a power transistor 2 and a current measuring circuit 3 connected to the power transistor for determining the through current through the power transistor 1. The through current (indicated from top to bottom by the dashed arrow) is conducted from the source connection 4 of the power transistor 2 via at least one source bond wire 5.

A first measuring bond wire 6 is connected between a first end 7 of the source bond wire 5 facing the source connection 4 and the source connection 4. A second measuring bond wire 8 is connected downstream of a second end 9 of the source bond wire 5 facing away from the source connection 4. The two measurement bond wires 6, 8 are connected to the current measurement circuit 3, wherein the first measurement bond wire 6 is connected to the current measurement circuit 3 via a gate drive circuit 10.

The following classical scheme can be seen in fig. 1: with this scheme, the through current (or overcurrent) in the power semiconductor is detected by the inductance of the source bonding wire. The gate charge path is traced with a dashed loop. The driver transistors P1 and N1 of the gate driver circuit 10 here form a driver for the gate charging path for operating the power transistor 2. The current measuring circuit 3 on the right is required for the evaluation and signal matching. The source bond wire 5 comprises a parasitic element for passing current measurement (shown as a series connection of a resistance and an inductance for all bond wires in the figure). A reference point is created by the first measuring bond wire 6. The current measuring circuit 3 detects the voltage dropped on the source bonding wire 5. This voltage is integrated through the wiring with the second measuring bond wire 8 and thus maps the current through the source bond wire 5.

The detection of the voltage on the source bond wire 5 must be started with the switching on of the power semiconductor. Due to the circuit arrangement, the current of the gate charging path (dashed loop) is additionally integrated at the first measuring bond wire 6 with the switching on of the power transistor. It should be noted here that the inductance is significantly larger with respect to the power path on the source bond wire 5 and therefore the error in the ratio of the inductance/resistance of the first measurement bond wire 6 becomes larger. Thereby creating measurement errors in this known circuit type.

Fig. 2 shows an embodiment of a power transistor arrangement 11 according to the invention. The power transistor arrangement 11 comprises a power transistor 12 and a current measuring circuit 13 connected to the power transistor for determining the through current through the power transistor 12. The through current is conducted from the source connection 14 of the power transistor 12 via at least one source bonding wire 15.

A first measurement bond wire 16 is connected between a first end 17 of the source bond wire 15 facing the source connection 14 and the source connection 14. A second measuring bond wire 18 is connected behind a second end 19 of the source bond wire 15 facing away from the source connection 14. The first and second measuring bond wires 16, 18 are connected to the current measuring circuit 13, wherein, however, here (in contrast to fig. 1), both are decoupled from the gate drive circuit 20.

In addition to the first and second measuring bond wires 16, 18, a third measuring bond wire 21 is connected behind the first end 17 of the source bond wire 15, wherein this third measuring bond wire 21 is also connected to the current measuring circuit 13.

The current measuring circuit 13 comprises a differential amplifier 22 in order to determine the voltage difference between the two ends 17, 19 of the source bond wire 15 from the voltage obtained by the measuring bond wires 16, 18, 21 and thereby determine the through current through the power transistor 12. The through current can be determined as mentioned above by integrating the voltage difference over time. In addition to the exact determination of the pass current, the gate charge of the gate of the power transistor 12 can additionally be determined by taking into account the third measuring bond wire 21, and therefore a redundant overvoltage protection is achieved.

A first voltage path 23 of the first measurement bond wire 16 between the first end 17 of the source bond wire 15 and the current measurement circuit and a second voltage path 24 of the second measurement bond wire 18 between the second end of the source bond wire 15 and the current measurement circuit 13 are connected via an integrator 25 (here in an implementation of an RC network).

The first voltage path 23 merges with a third voltage path 26 of the third measurement bond wire 21 in front of the differential amplifier 22, which third voltage path extends between the second end 19 of the source bond wire 15 and the current measurement circuit 13 to provide a common first signal input for the differential amplifier 22.

The second voltage path 24 provides a second signal input to the differential amplifier 22. By combining the two concepts from fig. 1 and 2 and differential analysis processing of the signals, it is then possible to determine not only the through current but also the gate charge accurately. The operating point can thus be evaluated and a more reliable safety shutdown can be achieved in the event of a short circuit. The current measuring circuit 13 is provided to determine not only the through-current through the power transistor but also the gate charge during the switching process of the power transistor. For this purpose, evaluation electronics for analog or digital reprocessing of the output of the differential amplifier 22 can be provided in the power transistor arrangement 11 (or in the current measurement circuit 13), for example.

This is illustrated in fig. 3, which combines the two concepts of fig. 1 and 2 and shows an embodiment of a power transistor arrangement according to the present invention. Thus, with this solution, current sensing according to the solutions from the first two embodiments is combined for gate charge measurement according to the present invention. Corresponding elements have the same reference numerals as in the previous embodiment. In addition to the differential amplifier 22, a second differential amplifier 27 supplies signals corresponding to the configuration according to fig. 1. The signals are compared in a difference former (Differenzbildner)28 and are processed analytically in a calculation unit 29. In this way, the gate charge can additionally be determined by integration over time of the difference of the respectively measured currents.