阅读说明：本技术 一种用于片上检测的控制系统及控制方法 (Control system and control method for on-chip detection ) 是由 陈济 于 2020-05-06 设计创作，主要内容包括：本发明涉及芯片测试技术领域,公开了一种用于片上检测的控制系统及控制方法,通过与待测芯片电连接的上位机设置待测芯片的目标温度；响应于上位机的控制指令,配置控制参数生成第一检测电压；根据所述第一检测电压生成检测信号；根据所述检测信号调整所述控制参数,控制所述第一检测电压的大小,使所述检测信号达到所述目标温度对应的电压设定值,其中,所述检测信号用以表征待测芯片的温度,所述控制指令包括检测所述待测芯片的温度,所述控制参数包括电源参数和/或负载参数。由此可解决传统测量方法以芯片周围温度代替芯片节温的问题,在保证温度控制动态响应的同时,增强系统减小稳态误差的能力。(The invention relates to the technical field of chip testing, and discloses a control system and a control method for on-chip detection.A target temperature of a chip to be detected is set through an upper computer electrically connected with the chip to be detected; responding to a control instruction of an upper computer, configuring control parameters and generating first detection voltage; generating a detection signal according to the first detection voltage; adjusting the control parameter according to the detection signal, controlling the first detection voltage to reach a voltage set value corresponding to the target temperature, wherein the detection signal is used for representing the temperature of a chip to be detected, the control instruction comprises the temperature of the chip to be detected, and the control parameter comprises a power supply parameter and/or a load parameter. Therefore, the problem that the temperature of the chip is saved by replacing the ambient temperature of the chip in the traditional measuring method can be solved, and the capability of the system for reducing the steady-state error is enhanced while the dynamic response of temperature control is ensured.)

1. A control system for on-chip detection, comprising:

the upper computer is electrically connected with the chip to be tested;

the power supply module is provided with a first input port for receiving the control instruction of the upper computer and a first output port for transmitting data, is controlled by the upper computer and is used for configuring power supply parameters to generate a first detection voltage of the chip to be detected;

a load module which is provided with a second input port for receiving the upper computer control instruction and a second output port for transmitting data, is controlled by the upper computer and configures load parameters to select the load state accessed to the control system,

the chip to be detected generates a detection signal according to the first detection voltage, the upper computer adjusts a control parameter according to the detection signal when detecting the chip to be detected, controls the magnitude of the first detection voltage, and enables the detection signal to reach a voltage set value corresponding to the target temperature of the chip to be detected,

the detection signal is used for representing the temperature of a chip to be detected, the control instruction comprises the temperature of the chip to be detected, and the control parameter comprises the power supply parameter and/or the load parameter.

2. The control system according to claim 1, wherein the power module includes an enable module, the enable module has a third input port for receiving the upper computer control instruction and a third output port for transmitting data, and is controlled by the upper computer to select an on-off state of the enable module, and configure an enable parameter in the on-off state of the enable module to generate a second detection voltage.

3. The control system of claim 1, wherein the upper computer has a controller, the controller comprising:

the oscilloscope control unit responds to the control instruction to configure the oscilloscope parameters and display and store the output data;

a power control unit, responding to a control instruction to configure power control parameters and transmit the first detection voltage, wherein the power parameters comprise the power control parameters;

a load control unit, which responds to a control instruction to configure the load parameter;

and the enabling control unit is used for responding to a control instruction to configure an enabling parameter and transmit the second detection voltage.

4. The control system of claim 3, wherein the controller further comprises:

and the input/output capacitance control unit responds to a control instruction to configure the input/output capacitance parameters accessed into the control system.

5. The control system of claim 4, wherein the control parameters further comprise at least one of the enable parameter, the input/output capacitance parameter, and the oscilloscope parameter.

6. The control system according to claim 3, wherein the power control unit includes a power protection unit, the power protection unit configures a power protection parameter in response to a control command, detects the first detection voltage according to the power protection parameter, and interrupts a detection process of the control system when the parameter of the first detection voltage exceeds a set range of the power protection parameter, and reports a fault abnormality to the control system,

wherein the power supply parameters further include the power supply protection parameters.

7. The control system of claim 6, wherein the power supply protection parameter is at least one selected from the group consisting of a high voltage threshold, a low voltage threshold, a positive current threshold, and a negative current threshold.

8. The control system of claim 3, further comprising:

the first detection circuit is connected with the chip to be detected, the input end of the first detection circuit is connected with the first output port of the power supply module, and the detection signal is generated according to the first detection voltage;

a second detection circuit having a fourth input port receiving the first detection voltage and a fifth input port receiving the second detection voltage, and generating the second detection voltage constant when the second detection voltage is greater than the first detection voltage.

9. The control system of claim 8, wherein the first detection circuit comprises:

the first detection chip is connected with the chip to be detected and is provided with an input pin, an output pin and a grounding pin;

the first capacitor is connected between the power supply end and the ground;

the second capacitor is connected in parallel to two ends of the first capacitor; and

a first resistor and a third capacitor connected in series between the output pin and ground,

the input pin of the first detection chip is connected with a power supply end, and the connection node of the first resistor and the third capacitor is used as the output end of the first detection circuit and used for providing the detection signal.

10. The control system of claim 8, wherein the second detection circuit comprises a second detection chip having a plurality of pins, and a second resistor, a third resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a seventh capacitor,

the second resistor is connected between the fourth input port and the first input pin of the second detection chip, the sixth capacitor is connected between the first output pin of the second detection chip and the ground, the third resistor is connected between the fifth input port and the second input pin of the second detection chip, the second output pin of the second detection chip is grounded through the seventh capacitor, the power supply pin of the second detection chip is connected with the power supply end, the fourth capacitor is connected between the power supply pin of the second detection chip and the ground, and the fifth capacitor is connected in parallel with two ends of the fourth capacitor.

11. The control system of claim 10, wherein the second detection circuit further comprises a third detection chip having a plurality of pins, and a fourth resistor, a fifth resistor, a sixth resistor, and an eighth capacitor,

the fourth resistor and the fifth resistor are connected in series at two ends of the sixth capacitor, a connection node of the fourth resistor and the fifth resistor is connected with a first class pin of the third detection chip, the third detection chip is provided with a plurality of second class pins and a plurality of third class pins, the plurality of second class pins are connected to the ground, the plurality of third class pins are connected to a first end of the sixth resistor, a second end of the sixth resistor is connected with the plurality of second class pins, and the connection node of the plurality of third class pins is connected with an output end of the second detection circuit through the eighth capacitor.

12. The control system of claim 10, wherein the second detection circuit further comprises a fourth detection chip having a plurality of pins, and a seventh resistor, an eighth resistor, a ninth resistor, and a ninth capacitor,

the seventh resistor and the eighth resistor are connected in series at two ends of the seventh capacitor, a connection node of the seventh resistor and the eighth resistor is connected with a first class pin of the fourth detection chip, the fourth detection chip is provided with a plurality of second class pins and a plurality of third class pins, the plurality of second class pins are connected to the ground in common, the plurality of third class pins are connected to a first end of the ninth resistor in common, a second end of the ninth resistor is connected with the plurality of second class pins, and the connection node of the plurality of third class pins is connected with the output end of the second detection circuit through the ninth capacitor.

13. The control system of claim 1, wherein the first detection chip is a complementary metal oxide semiconductor temperature sensor chip.

14. The control system of claim 10, wherein the second detection chip is a comparator circuit.

15. The control system according to claim 4, wherein the upper computer further includes:

the display unit is in communication connection with the controller and is used for displaying the output data;

an input unit, communicatively connected to the controller, for executing the control command to complete the configuration of the control parameter,

and the output data comprises the detection data of the chip to be detected and the corresponding control parameters during detection.

16. A control method for on-chip detection, wherein the control method is applied to the control system of any one of the preceding claims 1 to 15, and comprises:

setting a target temperature of a chip to be detected;

responding to a control instruction of an upper computer, configuring power supply parameters and generating first detection voltage;

generating a detection signal according to the first detection voltage;

adjusting control parameters according to the detection signal, controlling the first detection voltage to make the detection signal reach a voltage set value corresponding to the target temperature,

the detection signal is used for representing the temperature of the chip to be detected, the control instruction comprises the temperature of the chip to be detected, and the control parameter comprises a power supply parameter and/or a load parameter.

17. The control method of claim 16, wherein configuring the power supply parameter to generate the first detection voltage comprises:

configuring an input/output capacitance parameter accessed to the control system in response to a control instruction;

configuring power supply control parameters to generate the first detection voltage;

configuring a load parameter to select a load state of access to the control system,

wherein the power supply parameter comprises the power supply control parameter.

18. The control method of claim 17, wherein after the configuring the power supply parameter to generate the first detection voltage, further comprising:

responding to the control instruction to configure the parameters of the oscilloscope and display and store the output data; and

the configuration enable parameter generates a second detection voltage,

and the output data comprises the detection data of the chip to be detected and the corresponding control parameters during detection.

19. The control method of claim 16, wherein the control parameters further comprise at least one of the enable parameter, the input/output capacitance parameter, and the oscilloscope parameter.

20. The control method of claim 17, wherein configuring the power supply parameter to generate the first detection voltage further comprises:

responding to a control instruction to configure power protection parameters, detecting the first detection voltage according to the power protection parameters, interrupting the detection process of the control system when the parameters of the first detection voltage exceed the set range of the power protection parameters, and reporting fault abnormity to the control system,

wherein the power supply parameters further include the power supply protection parameters.

21. The control method of claim 20, wherein the power supply protection parameter is at least one selected from a high voltage threshold, a low voltage threshold, a positive current threshold, and a negative current threshold.

22. The control method of claim 17, wherein the configuring the enable parameter to generate the second detection voltage comprises:

generating the second detection voltage to be constant if the second detection voltage is greater than the first detection voltage.

23. The control method according to claim 17, before the setting the target temperature of the chip to be tested, comprising:

initializing the control system; and

storing a current configuration of the control parameter.

24. The control method according to claim 16, wherein after adjusting a control parameter according to the detection signal and controlling the magnitude of the first detection voltage to make the detection signal reach a voltage set value corresponding to the target temperature, a fault detection process is further performed on the control system, and the fault detection process includes:

if the control system is found to have faults, the detection of the chip to be detected is interrupted, and the faults are processed according to the priority;

and if the control system is found to have no fault, calling the configuration information of the corresponding control parameter and the detection data of the chip to be detected for storage, and then continuously executing the fault detection process.

25. The control method according to claim 16, characterized by further comprising:

and when the control system detects the chip to be detected for the first time, the chip to be detected is electrified in a soft start mode.

Technical Field

The invention relates to the technical field of chip testing, in particular to a control system and a control method for on-chip detection.

Background

In the prior art, when the input/output characteristics of a Low Drop-out Linear Regulator (LDO) chip are measured, a tester manually adjusts a high-temperature device, a Low-temperature device, a power supply, an electronic load and an oscilloscope respectively to perform testing. The problems of complex operation, long testing time and incapability of accurately reaching the set temperature in time exist, and once misoperation occurs or the chip has design defects, the system can not accurately detect which fault occurs in time, so that the chip and the testing equipment are damaged.

The existing solutions in the process of testing the input/output characteristics of the LDO chip mainly include: directly detecting the temperature of air around the chip by high-low temperature equipment and defaulting the temperature as the chip temperature saving, wherein the temperature of the air around the chip is usually lower than the temperature saving, so that the temperature of the chip can not be saved to reach the set temperature; an operator must control a plurality of devices at the same time, and the power-on sequence and the power-off sequence must be noticed in the operation process, so that the test is long in time and complicated to operate; in the traditional measuring system, because the potential difference between the power input end and the enabling end of the LDO chip cannot be monitored in real time, once misoperation occurs, all related equipment can be closed, so that the potential of the enabling end is easily higher than the input potential, and the measured chip can be burnt; when the input and output short circuit occurs to the tested chip, the traditional method cannot rapidly detect where the tested chip fails, and a tester can only manually close corresponding testing equipment but cannot timely and effectively process the failure, so that the corresponding equipment is damaged.

Disclosure of Invention

In order to solve the technical problem, the invention provides a control system and a control method for on-chip detection, which can solve the problem that the traditional measurement method uses the ambient temperature of a chip to replace the temperature of the chip for saving, and enhance the capability of the system for reducing steady-state errors while ensuring the dynamic response of temperature control.

In one aspect, the present invention provides a control system for on-chip detection, comprising:

the upper computer is electrically connected with the chip to be tested;

the power supply module is provided with a first input port for receiving the control instruction of the upper computer and a first output port for transmitting data, is controlled by the upper computer and is used for configuring power supply parameters to generate a first detection voltage of the chip to be detected;

a load module which is provided with a second input port for receiving the upper computer control instruction and a second output port for transmitting data, is controlled by the upper computer and configures load parameters to select the load state accessed to the control system,

the chip to be detected generates a detection signal according to the first detection voltage, the upper computer adjusts a control parameter according to the detection signal when detecting the chip to be detected, controls the magnitude of the first detection voltage, and enables the detection signal to reach a voltage set value corresponding to the target temperature of the chip to be detected,

the detection signal is used for representing the temperature of a chip to be detected, the control instruction comprises the temperature of the chip to be detected, and the control parameter comprises the power supply parameter and/or the load parameter.

Preferably, the power module includes an enabling module, the enabling module has a third input port for receiving the upper computer control instruction and a third output port for transmitting data, and is controlled by the upper computer to select an on-off state of the enabling module, and configure an enabling parameter in the on-off state of the enabling module to generate the second detection voltage.

Preferably, the upper computer has a controller, and the controller includes:

the oscilloscope control unit responds to the control instruction to configure the oscilloscope parameters and display and store the output data;

a power control unit, responding to a control instruction to configure power control parameters and transmit the first detection voltage, wherein the power parameters comprise the power control parameters;

a load control unit, which responds to a control instruction to configure the load parameter;

and the enabling control unit is used for responding to a control instruction to configure an enabling parameter and transmit the second detection voltage.

Preferably, the controller further comprises:

and the input/output capacitance control unit responds to a control instruction to configure the input/output capacitance parameters accessed into the control system.

Preferably, the control parameters further include at least one of the enable parameter, the input/output capacitance parameter, and the oscilloscope parameter.

Preferably, the power control unit includes a power protection unit, the power protection unit configures a power protection parameter in response to a control instruction, detects the first detection voltage according to the power protection parameter, and interrupts a detection process of the control system when a parameter of the first detection voltage exceeds a set range of the power protection parameter, and reports a fault abnormality to the control system,

wherein the power supply parameters further include the power supply protection parameters.

Preferably, the power supply protection parameter is at least one selected from a high voltage threshold, a low voltage threshold, a positive current threshold and a negative current threshold.

Preferably, the control system further comprises:

the first detection circuit is connected with the chip to be detected, the input end of the first detection circuit is connected with the first output port of the power supply module, and the detection signal is generated according to the first detection voltage;

a second detection circuit having a fourth input port receiving the first detection voltage and a fifth input port receiving the second detection voltage, and generating the second detection voltage constant when the second detection voltage is greater than the first detection voltage.

Preferably, the first detection circuit includes:

the first detection chip is connected with the chip to be detected and is provided with an input pin, an output pin and a grounding pin;

the first capacitor is connected between the power supply end and the ground;

the second capacitor is connected in parallel to two ends of the first capacitor; and

a first resistor and a third capacitor connected in series between the output pin and ground,

the input pin of the first detection chip is connected with a power supply end, and the connection node of the first resistor and the third capacitor is used as the output end of the first detection circuit and used for providing the detection signal.

Preferably, the second detection circuit comprises a second detection chip with a plurality of pins, and a second resistor, a third resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor and a seventh capacitor, wherein the second resistor is connected between the fourth input port and the first input pin of the second detection chip, the sixth capacitor is connected between the first output pin of the second detection chip and the ground, the third resistor is connected between the fifth input port and the second input pin of the second detection chip, a second output pin of the second detection chip is grounded through the seventh capacitor, a power supply pin of the second detection chip is connected with the power supply end, the fourth capacitor is connected between a power supply pin of the second detection chip and the ground, and the fifth capacitor is connected in parallel to two ends of the fourth capacitor.

Preferably, the second detection circuit further comprises a third detection chip having a plurality of pins, and a fourth resistor, a fifth resistor, a sixth resistor and an eighth capacitor,

the fourth resistor and the fifth resistor are connected in series at two ends of the sixth capacitor, a connection node of the fourth resistor and the fifth resistor is connected with a first class pin of the third detection chip, the third detection chip is provided with a plurality of second class pins and a plurality of third class pins, the plurality of second class pins are connected to the ground, the plurality of third class pins are connected to a first end of the sixth resistor, a second end of the sixth resistor is connected with the plurality of second class pins, and the connection node of the plurality of third class pins is connected with an output end of the second detection circuit through the eighth capacitor.

Preferably, the second detection circuit further comprises a fourth detection chip having a plurality of pins, and a seventh resistor, an eighth resistor, a ninth resistor and a ninth capacitor,

the seventh resistor and the eighth resistor are connected in series at two ends of the seventh capacitor, a connection node of the seventh resistor and the eighth resistor is connected with a first class pin of the fourth detection chip, the fourth detection chip is provided with a plurality of second class pins and a plurality of third class pins, the plurality of second class pins are connected to the ground in common, the plurality of third class pins are connected to a first end of the ninth resistor in common, a second end of the ninth resistor is connected with the plurality of second class pins, and the connection node of the plurality of third class pins is connected with the output end of the second detection circuit through the ninth capacitor.

Preferably, the first detection chip is a complementary metal oxide semiconductor temperature sensor chip.

Preferably, the second detection chip is a comparator circuit.

Preferably, the host computer further includes:

the display unit is in communication connection with the controller and is used for displaying the output data;

an input unit, communicatively connected to the controller, for executing the control command to complete the configuration of the control parameter,

and the output data comprises the detection data of the chip to be detected and the corresponding control parameters during detection.

In another aspect, the present invention further provides a control method for on-chip detection, where the control method is applied to the control system described above, and includes:

setting a target temperature of a chip to be detected;

responding to a control instruction of an upper computer, configuring power supply parameters and generating first detection voltage;

generating a detection signal according to the first detection voltage;

adjusting control parameters according to the detection signal, controlling the first detection voltage to make the detection signal reach a voltage set value corresponding to the target temperature,

the detection signal is used for representing the temperature of the chip to be detected, the control instruction comprises the temperature of the chip to be detected, and the control parameter comprises a power supply parameter and/or a load parameter.

Preferably, the configuring the power supply parameter to generate the first detection voltage comprises:

configuring an input/output capacitance parameter accessed to the control system in response to a control instruction;

configuring power supply control parameters to generate the first detection voltage;

configuring a load parameter to select a load state of access to the control system,

wherein the power supply parameter comprises the power supply control parameter.

Preferably, after the configuring the power supply parameter generates the first detection voltage, the method further includes:

responding to the control instruction to configure the parameters of the oscilloscope and display and store the output data; and

the configuration enable parameter generates a second detection voltage,

and the output data comprises the detection data of the chip to be detected and the corresponding control parameters during detection.

Preferably, the control parameters further include at least one of the enable parameter, the input/output capacitance parameter, and the oscilloscope parameter.

Preferably, the configuring the power supply parameter to generate the first detection voltage further comprises: responding to a control instruction to configure power protection parameters, detecting the first detection voltage according to the power protection parameters, interrupting the detection process of the control system when the parameters of the first detection voltage exceed the set range of the power protection parameters, and reporting fault abnormity to the control system, wherein the power parameters also comprise the power protection parameters. .

Preferably, the power supply protection parameter is at least one selected from a high voltage threshold, a low voltage threshold, a positive current threshold and a negative current threshold.

Preferably, the configuration enabling parameter after generating the second detection voltage comprises: generating the second detection voltage to be constant if the second detection voltage is greater than the first detection voltage.

Preferably, before the setting of the target temperature of the chip to be tested, the method includes: initializing the control system; and storing the current configuration of the control parameter.

Preferably, after adjusting a control parameter according to the detection signal and controlling the magnitude of the first detection voltage to make the detection signal reach a voltage set value corresponding to the target temperature, a fault detection process is further performed on the control system, where the fault detection process includes:

if the control system is found to have faults, the detection of the chip to be detected is interrupted, and the faults are processed according to the priority;

and if the control system is found to have no fault, calling the configuration information of the corresponding control parameter and the detection data of the chip to be detected for storage, and then continuously executing the fault detection process.

Preferably, the control method further includes: and when the control system detects the chip to be detected for the first time, the chip to be detected is electrified in a soft start mode.

The invention has the beneficial effects that: the invention provides a control system and a control method for on-chip detection.A target temperature of a chip to be detected is set through an upper computer electrically connected with the chip to be detected; then responding to a control instruction of the upper computer, configuring control parameters and generating a first detection voltage; generating a detection signal according to the first detection voltage; adjusting the control parameter according to the detection signal, controlling the first detection voltage to enable the detection signal to reach a voltage set value corresponding to the target temperature, wherein the detection signal is used for representing the temperature of a chip to be detected, the control instruction comprises the temperature of the chip to be detected, and the control parameter comprises a power supply parameter and/or a load parameter, so that the outer loop control of the slow regulation control technology on the chip temperature is realized;

secondly, a power protection unit in the power module responds to a control instruction to configure power protection parameters, detects the first detection voltage according to the power protection parameters, interrupts the detection process of the control system when the parameters of the first detection voltage exceed the set range of the power protection parameters, and reports fault abnormity to the control system, so that inner loop control of the anti-saturation PI control technology on the chip temperature is realized;

in the process of detecting the input/output characteristics of the chip, a comparator circuit (or a chip) is used for comparing the magnitude relation between the second detection voltage and the first detection voltage, and the potential difference between the input end and the enable end of the chip to be detected is monitored in real time so as to prevent the enable end of the chip to be detected from being higher than the potential of the input end and further burn the chip; meanwhile, in the detection process, once the enable terminal potential is higher than the input terminal potential, that is, the second detection voltage is higher than the first detection voltage, the system clamps the voltage of the enable terminal in time by using a schottky diode (a third detection chip or a fourth detection chip) and outputs the constant second detection voltage;

in addition, in the detection process, when a plurality of faults of the system are alarmed due to the problem of the chip to be detected, the control instruction is sent out and corresponding processing is executed in an interrupt priority mode, so that the damage of the faults to the control system is reduced to the maximum extent.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 is a schematic diagram illustrating a control system for on-chip detection according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram showing the structure of an upper computer in the control system shown in FIG. 1;

FIGS. 3a and 3b are schematic views of Labview-based programs of units in the controller shown in FIG. 2, respectively;

FIG. 4 is a schematic diagram of an oscilloscope control program based on a Labview program of the upper computer in the embodiment shown in FIG. 1;

FIG. 5 is a schematic diagram illustrating a program for controlling the input power, the enable power and the load of the upper computer in the embodiment shown in FIG. 1;

FIG. 6 is a schematic diagram showing a control procedure for controlling the I/O capacitance access system by the upper computer in the embodiment shown in FIG. 1;

FIG. 7 is a schematic diagram of a first detection circuit in the embodiment of FIG. 1;

FIG. 8 is a schematic diagram of a second detection circuit in the embodiment of FIG. 1;

fig. 9 is a flowchart illustrating a control method for on-chip detection according to an embodiment of the present application.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

First, a virtual instrument (virtual instrument) is a computer-based instrument. The close integration of computers and instruments is an important direction in the development of current instruments. Roughly speaking, there are two ways of combining this, one is to install a computer into the instrument, and a typical example of this is a so-called intelligent instrument (e.g., an instrument with an embedded system). The other method is to load the instrument into a computer and realize various instrument functions by using general computer hardware and an operating system as a support, and the virtual instrument mainly refers to the method.

The basic theories involved in the study of virtual instruments are mainly computer data acquisition and digital signal processing. Currently, the more widely used computer language in this field is labview by the us NI corporation. labview is a program development environment similar to C and BASIC development environments, but the salient differences of labview from other computer languages are: other computer languages use text-based languages to generate code, and labview uses a graphical editing language G to write a program, the generated program being in the form of a block diagram. The data acquisition system designed by the labview can be used for simulating and acquiring various signals, and meanwhile, the labview can provide a plurality of controls with the appearance similar to that of a traditional instrument (such as an oscilloscope and a universal meter), so that a user interface can be conveniently created. The user interface is referred to as a front panel in labview, and objects on the front panel can be programmatically controlled using icons and links. The main convenience of the method is that under the condition of one piece of hardware, the functions of different instruments can be realized by changing software, the capability of a computer can be fully exerted, instruments with stronger functions can be created by the powerful data processing function of the computer, and users can define and manufacture various instruments according to the requirements of the users.

In the control system, PI control means that a controlled object is controlled by linearly combining the proportion and integral of a control deviation formed by a given value and an actual output value to form a control quantity. Controllers with integral characteristics are subject to integral saturation problems, i.e. such controllers have an output that changes in the direction of the two extreme positions (maximum or minimum) depending on the polarity of the deviation, as long as the deviation does not disappear. This can cause controller or actuator damage and degrade the control quality of the system by reducing the speed at which the reverse disturbance is overcome.

In general, methods for preventing integral saturation include: the method comprises the following steps of improving the conventional PI controller by adopting a proportional controller and an amplitude limiting device, adopting a PD controller and adopting a series PID controller, wherein the proportional controller is the simplest method for preventing integral saturation, but can generate static errors in the system; the output of the controller can not exceed the output range limited by the controller by adopting the amplitude limiting device according to the amplitude limiting range of the amplitude limiting device, but the output amplitude limiting is not really integral saturation prevention and can not improve the control quality of overcoming reverse disturbance; the integrating networks of a plurality of controllers are fixedly and internally connected with the output of the controllers, and the existing PI controller can be improved by designing a saturation point signal and adding an outer loop control by adopting an external wiring so as to achieve the aim of preventing integral saturation; the adoption of the PD controller can reduce overshoot (also called maximum deviation), and compared with a pure proportional controller, the adoption of the PD controller can also reduce the static error of a system, but cannot eliminate the static error; when load and setpoint changes are possible, and overshoot and static errors are not allowed, the best solution to account for integral saturation is to use a series PID controller.

PID control, namely proportional-integral-derivative control, is realized by a proportional unit (P), an integral unit (I) and a derivative unit (D) through PID parameter setting of a controller, so that the controller achieves the optimal control effect. Specifically, P represents a proportional action, and the larger the proportional degree (i.e., proportional band) of the controller is, the smaller the amplification factor of the controller is, the more stable the curve of the controlled parameter is, and the smaller the opposite proportional degree is, the larger the amplification factor of the controller is, the more fluctuant the curve of the controlled parameter is;

i is an integral function, which is set to eliminate the static error of the autonomous system. Integration, that is, when there is a deviation input e, the deviation is continuously accumulated by the integral controller along with time, that is, the speed of integral accumulation is proportional to the magnitude of the deviation e and the integration speed, and a proportional Plus Integral (PI) controller is usually used to make the system have no steady-state error after entering a steady state;

d denotes a derivative action, in the conventional PID controller, the output change of the derivative action is proportional to a derivative time and a speed of the change of the deviation, regardless of the magnitude of the deviation, and the larger the speed of the change of the deviation, the longer the derivative time, the larger the output change of the derivative action, but if the derivative action is too strong, it may cause oscillation by itself due to too fast a change, causing a noticeable "spike" or "kick" in the controller output. In order to avoid the disturbance, a differential advanced PID operation rule can be used in a PID regulator and a Data Collection System (DCS), that is, only a Process Value (PV) is differentiated, when a set value (SP, set Point) of a controller is manually changed, the sudden change of the output of the controller is not caused, and the disturbance brought to a control System at the moment of changing the SP is avoided.

For different temperatures, when the input/output characteristics of a chip to be tested are tested, the temperature of the chip to be tested can not be directly detected due to various environmental factors, the control system provided by the application adopts the temperature detection chip to directly measure the temperature of the chip layer to be tested, so that the problem that the traditional measurement method replaces the temperature of the chip by the ambient temperature of the chip can be solved, and meanwhile, when the temperature of the chip to be tested is controlled, the control system adopts a double-closed-loop control strategy, so that the dynamic response of temperature control can be ensured, and the capability of the system for reducing the steady-state error is enhanced.

The present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of a control system for on-chip detection provided in an embodiment of the present application, and fig. 2 shows a schematic structural diagram of an upper computer in the control system shown in fig. 1.

Referring to fig. 1 and 2, an embodiment of the present application provides a control system 100 for on-chip detection, including: the device comprises a chip to be tested 110, an upper computer 120, a load module 130 and a power module 140, wherein the upper computer 120 is electrically connected with the chip to be tested 110; the power module 140 has a first input port for receiving a control instruction sent by the upper computer 120 and a first output port for transmitting data, and the power module 140 is controlled by the upper computer 120 and configures power parameters to generate a first detection voltage for detecting the chip 110 to be detected; the load module 130 has a second input port for receiving a control instruction sent by the upper computer 120 and a second output port for transmitting data, the load module 130 is controlled by the upper computer 120, a load state of a load parameter selection access control system 100 is configured, the chip 110 to be tested generates a detection signal according to the first detection voltage, when the upper computer 120 detects the chip 110 to be tested, the upper computer adjusts a control parameter according to the detection signal, controls the magnitude of the first detection voltage, and enables the detection signal to reach a voltage set value corresponding to a target temperature of the chip 110 to be tested, wherein the detection signal is used for representing the temperature of the chip 110 to be tested, the control instruction includes the temperature of the chip 110 to be tested, and the control parameter includes the power parameter and/or the load parameter.

In a preferred embodiment, the power module includes an enabling module (not shown in the figure), the enabling module has a third input port for receiving a control instruction sent by the upper computer 120 and a third output port for transmitting data, is controlled by the upper computer 120, selects an on-off state of the enabling module, and configures an enabling parameter to generate the second detection voltage in the on-off state of the enabling module.

In a preferred embodiment, the upper computer 120 has a controller 1201, and the controller 1201 is used for communication connection (such as bus) with the chip to be tested and the modules, which includes but is not limited to: the oscilloscope comprises an oscilloscope control unit 121, a power supply control unit 122, a load control unit 123, an enable control unit 124 and an input/output capacitance control unit 125, wherein the oscilloscope control unit 121 responds to a control instruction to configure oscilloscope parameters and display and store output data; the power control unit 122 configures power control parameters to generate and transmit the first detection voltage in response to a control instruction; the load control unit 123 configures the load parameters in response to the control instructions; the enable control unit 124 configures an enable parameter and transmits the second detection voltage in response to a control instruction; and the input/output capacitance control unit 125 configures an input/output capacitance parameter of the access control system 100 in response to the control instruction, wherein the power supply parameter includes the power supply control parameter.

In a preferred embodiment, the control parameter further comprises at least one of the enable parameter, the input/output capacitance parameter, and the oscilloscope parameter.

Fig. 3a and 3b respectively show a program schematic diagram of each unit in the controller shown in fig. 2 based on Labview, fig. 4 shows an oscilloscope control program schematic diagram of the upper computer in the embodiment shown in fig. 1 based on Labview program, fig. 5 shows a program schematic diagram of the upper computer in the embodiment shown in fig. 1 for controlling the input power supply, the enable power supply and the load, and fig. 6 shows a control program schematic diagram of the upper computer in the embodiment shown in fig. 1 for controlling the input/output capacitor access system.

In a preferred embodiment, the power control unit 122 includes a power protection unit 1221, where the power protection unit 1221 configures a power protection parameter in response to a control instruction, detects the first detection voltage according to the power protection parameter, and interrupts a detection process of the control system 100 and reports a fault exception to the control system 100 when the parameter of the first detection voltage exceeds a set range of the power protection parameter, where the power parameter further includes the power protection parameter.

In a preferred embodiment, the power protection parameter is at least one selected from but not limited to a high voltage threshold, a low voltage threshold, a positive current threshold and a negative current threshold, and specifically, each parameter corresponds to a block diagram as shown in fig. 3a and 4, and the program setting of the power protection parameter corresponds to: high voltage limit, low voltage limit, positive current limit, negative current limit.

In this embodiment, the control system that this application provided adopts when the temperature is closed loop to prevent saturation PI control technique to carry out inner loop control to the temperature, on the basis of guaranteeing dynamic response, has increased the steady state error of system. Therefore, the problems that in the initial stage of temperature control, the proportion of the proportion part in the total adjustment amount in PI adjustment is too large and the proportion of the integral link is too small due to the fact that the difference between the set temperature and the actual temperature is large, the capability of the system for reducing steady-state errors is weakened, relatively large overshoot is generated, the temperature is changed violently near the set value, and rapid stabilization is difficult can be avoided.

Further, the program setting of the power control unit 122 at least includes: power protection, power control and power switch, specifically, referring to fig. 3a, the power protection includes the program setting of the power protection parameters mentioned above; the power supply control device comprises: peak-to-peak, duty cycle 1, frequency 1, dc offset and phase; the setting of switch includes: DC power switch and AC power switch, and

the program settings of the oscilloscope control unit 121 at least include: the configuration and storage confirmation is invoked, specifically, the configuration is configured as a configuration of parameter configuration of the oscilloscope and control parameters corresponding to each display waveform, a file storage confirmation (a confirmation of a storage location and a confirmation of a storage file name, as shown in fig. 4) and a picture storage confirmation (a picture storage confirmation including display waveforms of OSC1, OSC2, and OSC3 shown in fig. 5, and OSC4 display waveforms shown in fig. 6) when the confirmation is that the system is not faulty.

The picture storing the collected input/output characteristic data of the LDO chip can be automatically stored in the designated folder of the user through the program in fig. 4, and the related parameters such as the test temperature LMT _ OUT, the power parameter, the load parameter, the connection capacity value of the input/output capacitor (accessing and displaying CIN/displaying COUT), and the like are recorded in the stored picture name.

Further, the program settings of the load control unit 123 include: load switch, voltage gear selection, current gear selection, and load parameter, wherein, load switch's program setting includes: direct current output switch and interchange output switch, the setting procedure of load parameter includes: high current leveling, low current leveling, frequency 2 and duty cycle 2, the programming settings for voltage step selection in one embodiment, for example, include: 150V gear and 15V gear, the current gear selection program is arranged in one embodiment and comprises the following steps: 400mA gear, 4A gear and 40mA gear, as shown in FIG. 5, the related parameters of PWM wave, load and enabled power supply output by the power module can be set through the partial program.

FIG. 6 is a control program diagram of the control system for controlling the input/output capacitors of FIG. 3b, which can control the capacitance and number of the input capacitors (input capacitors 1-4) in the display CIN/the output capacitors (output capacitors 5-12) in the display OUT according to the user's setting. Therefore, the user can control the storage of the virtual oscilloscope realized on the upper computer and call the corresponding configuration of the virtual oscilloscope so as to meet the test requirements of the user.

Based on the above, the control system provided by the application can automatically adjust power supply parameters (such as the amplitude and frequency of an input voltage or output current PWM wave) according to user settings on the basis of performing inner loop control on the temperature by adopting an anti-saturation PI control technology, performs outer loop control on the temperature by adopting a slow regulation control technology, converts a closed-loop control mode from the anti-saturation PI control technology to the slow regulation control technology when the actual temperature is close to the set temperature, further weakens dynamic response and enhances the capability of reducing steady-state errors, and enables the temperature to smoothly and accurately reach a set value under the condition of small overshoot.

In a preferred embodiment, as shown in fig. 7, the control system 100 further comprises: a first detection circuit 150 and a second detection circuit 160, wherein the first detection circuit 150 is connected to the chip 110 to be tested, and an input end thereof is connected to the first output port of the power module 140 to receive the first detection voltage from the power module 140. The first detection circuit 150 is used for sensing a temperature and generating a detection signal LMT _ OUT of the temperature at an output terminal.

Specifically, the first detection circuit 150 includes a first detection chip U1, a first capacitor C1, a second capacitor C2, a first resistor R1, and a third capacitor C3, wherein the first detection chip U1 is connected to the chip 110 to be detected and has an input pin VDD, an output pin OUT, and a ground pin GND, the first capacitor C1 is connected between the power supply terminal and the ground, the second capacitor C2 is connected in parallel to two ends of the first capacitor C1, and a first resistor R1 and a third capacitor C3 are connected in series between the output pin OUT and the ground, the input pin VDD of the first detection chip U1 is connected to the power supply terminal, and a connection node between the first resistor R1 and the third capacitor C3 serves as an output terminal of the first detection circuit 150 to provide the detection signal LMT _ OUT.

In a preferred embodiment, as shown in fig. 8, the control system 100 further comprises a second sensing circuit 160 having a fourth input port receiving the first sensing voltage and a fifth input port receiving the second sensing voltage, and generating a constant second sensing voltage VIN when the second sensing voltage is greater than the first sensing voltage.

Specifically, the second detection circuit 160 includes a second detection chip U2 having a plurality of pins, and a second resistor R2, a third resistor R3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6 and a seventh capacitor C7, wherein, the second resistor R2 is connected between the fourth input port I/O02 and the first input pin INA of the second sense chip U2, the sixth capacitor C6 is connected between the first output pin OUTA of the second sense chip U2 and ground, the third resistor R3 is connected between the fifth input port I/O01 and the second input pin INB of the second sense chip U2, the second output pin OUTB of the second sensing chip U2 is grounded through a seventh capacitor C7, the power pin VCC of the second detecting chip U2 is connected to the power supply terminal, the fourth capacitor C4 is connected between the power pin VCC of the second detecting chip U2 and the ground, and the fifth capacitor C5 is connected in parallel to two ends of the fourth capacitor C4.

Further, the second detection circuit 160 further includes a third detection chip U3 having a plurality of pins, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and an eighth capacitor CIN1, wherein the fourth resistor R4 and the fifth resistor R5 are connected in series to two ends of the sixth capacitor C6, a connection node of the fourth resistor R4 and the fifth resistor R5 is connected to the first pin G of the third detection chip U3, the third detection chip U3 has a plurality of second pins S and a plurality of third pins D, the plurality of second pins S are commonly connected to ground, the plurality of third pins D are commonly connected to a first end of the sixth resistor R6, a second end of the sixth resistor R6 is connected to the plurality of second pins S, and a connection node of the plurality of third pins D is connected to the output terminal CIN1 of the second detection circuit 160.

Further, the second detection circuit 160 further includes a fourth detection chip U4 having a plurality of pins, and a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a ninth capacitor CIN2, wherein the seventh resistor R7 and the eighth resistor R8 are connected in series to two ends of the seventh capacitor C7, and a connection node of the seventh resistor R7 and the eighth resistor R8 is connected to the first pin G of the fourth detection chip U4, the fourth detection chip U4 has a plurality of second pins S and a plurality of third pins D, the plurality of second pins S are commonly connected to ground, the plurality of third pins D are commonly connected to a first end of the ninth resistor R9, a second end of the ninth resistor R9 is connected to the plurality of second pins S, and a connection node of the plurality of third pins D is connected to the output terminal VIN of the ninth detection circuit 160 through the ninth capacitor CIN 2.

In a preferred embodiment, the first sense die U1 is a Complementary Metal Oxide Semiconductor (CMOS) temperature sensor die, the second sense die U2 is a comparator circuit, and the third sense die U3 and the fourth sense die U4 are schottky diode circuit dies.

Based on the above embodiment, the control system that this application provided utilizes the comparator real-time supervision LDO input end (receiving the fourth input port of first detection voltage) and the potential difference of enabling end (receiving the fifth input port of second detection voltage) at the detection chip in-process, in case the condition that enables the end potential and be higher than the input potential appears, the output of comparator turns into the high level from the low level in the twinkling of an eye, this high level will drive corresponding chip (third detection chip U3 or fourth detection chip U4), will enable the end and the input between the circuit chip of access schottky diode to the end voltage of clamp enabling, and then prevent that chip enable end potential is higher than the input potential and burns out the chip.

In a preferred embodiment, the upper computer further comprises a display unit 1202 and an input unit 1203, wherein the display unit 1202 is in communication with the controller 1201 for displaying output data, such as a liquid crystal display; the input unit 1203 is communicatively connected to the controller 1201 and configured to execute a control instruction to complete configuration of the control parameter, specifically, for example, a keyboard and a mouse connected to the display unit 1202, or a touch display device built in the display unit, where the output data includes detection data of the chip 110 to be detected and the corresponding control parameter during detection.

In a preferred embodiment, the first detection circuit and/or the second detection circuit are protected by sandwiching a heat insulating material between two layers of circuit boards. Because the test hardware must work under high and low temperature environment, the hardware system must adapt to the severe temperature environment of-60 ℃ to 160 ℃, and most of the chips in the test circuit can only work under the environment of-40 ℃ to 125 ℃, thus the detection of the input/output characteristics of the chips under the severe temperature environment can be completed under the condition that the electrical components and the chips which do not resist temperature change in the detection circuit normally work.

In conclusion, the control system controls the intelligent power supply, the chip to be tested, the intelligent load and the virtual oscilloscope realized by the upper computer through the upper computer by utilizing Labview software, so that the input/output characteristics of the LDO chip can be automatically detected under the conditions of high temperature and low temperature. The system has the capabilities of intelligently checking temperature, automatically detecting input and output voltage and current waveforms, storing waveform pictures, and automatically accessing various control parameters, and can automatically adjust the amplitude and frequency of PWM waves of the input voltage and the output current according to user settings. The system abandons the defects of the traditional methods of inaccurate temperature regulation, frequent adjustment of the range and the trigger position of the oscilloscope, complex instrument operation, long measuring time and the like when the input/output characteristic characteristics of the LDO chip are detected under the conditions of high temperature and low temperature. The system has the advantages of high intelligent degree, simple operation, accurate temperature control, less time consumption for detecting the input/output characteristics of the LDO chip, accurate result and the like.

In addition, in the detection process, when a plurality of devices of the control system alarm due to the chip problem, the traditional system adopts a stacking mode, the priority of alarm information cannot be distinguished, and the devices for alarming are processed in sequence, so that the chip is easily burnt due to the closed alarm devices. The control system overcomes the defect of the traditional system, and adopts a mode of interrupting priority to send out control instructions and carry out corresponding processing so as to reduce the damage to detection equipment and the detection equipment when the chip has problems to the greatest extent.

Fig. 9 is a flowchart illustrating a control method for on-chip detection according to an embodiment of the present application.

On the other hand, an embodiment of the present application further provides a control method for on-chip detection, where the control method is applied to the control system 100 in the foregoing embodiment, and the control method includes:

setting a target temperature of a chip to be detected;

responding to a control instruction of an upper computer, configuring power supply parameters and generating first detection voltage;

generating a detection signal according to the first detection voltage;

adjusting control parameters according to the detection signal, controlling the first detection voltage to make the detection signal reach a voltage set value corresponding to the target temperature,

the detection signal is used for representing the temperature of the chip to be detected, the control instruction comprises the temperature of the chip to be detected, and the control parameter comprises a power supply parameter and/or a load parameter.

Further, the configuring the power supply parameter to generate the first detection voltage comprises:

configuring an input/output capacitance parameter accessed to the control system in response to a control instruction;

configuring power supply control parameters to generate the first detection voltage;

configuring a load parameter to select a load state of access to the control system,

wherein the power supply parameter comprises the power supply control parameter.

Further, after the configuring the power supply parameter to generate the first detection voltage, the method further includes: responding to the control instruction to configure the parameters of the oscilloscope and display and store the output data; and configuring an enabling parameter to generate a second detection voltage, wherein the output data comprises detection data of the chip to be detected and the control parameter corresponding to the detection data.

Further, the control parameter further includes at least one of the enable parameter, the input/output capacitance parameter, and the oscilloscope parameter.

Further, after adjusting a control parameter according to the detection signal and controlling the magnitude of the first detection voltage to make the detection signal reach a voltage set value corresponding to the target temperature, a fault detection process is performed on the control system, where the fault detection process includes:

if the control system is found to have faults, the detection of the chip to be detected is interrupted, and the faults are processed according to the priority;

and if the control system is found to have no fault, calling the configuration information of the corresponding control parameter and the detection data of the chip to be detected for storage, and then continuously executing the fault detection process.

Specifically, referring to fig. 9, the control method includes the following steps:

step S2101: and starting.

Step S2102: and (5) initializing the system.

Step S2103: the oscilloscope configuration is stored.

Step S2104: and (4) setting the temperature.

Step S2105: an input/output capacitor is connected.

Step S2106: and turning on the power supply.

Step S2107: the load is turned on.

Step S2108: and detecting whether the control system has a fault.

Step S2109: and (6) processing the fault.

Step S2110: and calling parameter configuration of each module in the control system.

Step S2111: and adjusting the oscilloscope to store the picture.

Referring to the steps, after the control system starts, firstly, the power supply parameters, the oscilloscope parameters and the load parameters of the system are initialized, and then, the programs written and made by Labview software are used for storing the related configurations of the oscilloscope needing to be called. Then the system executes a main cycle, after the system enters the main cycle, the system firstly sends a control instruction through a controller, and double closed-loop control is carried out on the temperature of the chip to be measured by adopting an anti-saturation PI inner-loop temperature control technology and a slow-regulation temperature outer-loop control technology, so that the temperature stably reaches a set temperature while ensuring dynamic response; secondly, the system sequentially accesses corresponding input capacitors, starts an intelligent power supply and an intelligent load according to user set parameters; finally, entering a fault detection cycle, if a fault exists in the system, no relevant detection is carried out, and entering the cycle, and processing each fault according to the priority by adopting an interruption mode; and if the system is found to have no fault, calling corresponding oscilloscope configurations for storing pictures, wherein the stored pictures comprise parameter configurations of the oscilloscope, display waveforms and configurations of corresponding control parameters.

Further, the control method further includes: and when the control system detects the chip to be detected for the first time, the chip to be detected is electrified in a soft start mode.

Further, the configuring the power supply parameter to generate the first detection voltage further includes: responding to a control instruction to configure power protection parameters, detecting the first detection voltage according to the power protection parameters, interrupting the detection process of the control system when the parameters of the first detection voltage exceed the set range of the power protection parameters, and reporting fault abnormity to the control system, wherein the power parameters also comprise the power protection parameters.

Further, the power supply protection parameter is at least one selected from a high voltage threshold, a low voltage threshold, a positive current threshold, and a negative current threshold.

Further, the step of generating the second detection voltage by the configuration enabling parameter comprises: generating the second detection voltage to be constant if the second detection voltage is greater than the first detection voltage.

Further, before the setting of the target temperature of the chip to be tested, the control method includes: initializing the control system; and storing the current configuration of the control parameter.

In summary, the control system and the control method for on-chip detection provided by the invention set the target temperature of the chip to be detected through the upper computer electrically connected with the chip to be detected; then responding to a control instruction of the upper computer, configuring control parameters and generating a first detection voltage; generating a detection signal according to the first detection voltage; adjusting the control parameter according to the detection signal, controlling the first detection voltage to enable the detection signal to reach a voltage set value corresponding to the target temperature, wherein the detection signal is used for representing the temperature of a chip to be detected, the control instruction comprises the temperature of the chip to be detected, and the control parameter comprises a power supply parameter and/or a load parameter, so that the outer loop control of the slow regulation control technology on the chip temperature is realized;

secondly, a power protection unit in the power module responds to a control instruction to configure power protection parameters, detects the first detection voltage according to the power protection parameters, interrupts the detection process of the control system when the parameters of the first detection voltage exceed the set range of the power protection parameters, and reports fault abnormity to the control system, so that inner loop control of the anti-saturation PI control technology on the chip temperature is realized;

in the process of detecting the input/output characteristics of the chip, a comparator circuit (or a chip) is used for comparing the magnitude relation between the second detection voltage and the first detection voltage, and the potential difference between the input end and the enable end of the chip to be detected is monitored in real time so as to prevent the enable end of the chip to be detected from being higher than the potential of the input end and further burn the chip; meanwhile, in the detection process, once the enable terminal potential is higher than the input terminal potential, that is, the second detection voltage is higher than the first detection voltage, the system clamps the voltage of the enable terminal in time by using a schottky diode (a third detection chip or a fourth detection chip) and outputs the constant second detection voltage;

in addition, in the detection process, when a plurality of faults of the system are alarmed due to the problem of the chip to be detected, the control instruction is sent out and corresponding processing is executed in an interrupt priority mode, so that the damage of the faults to the control system is reduced to the maximum extent.

It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.

Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.