阅读说明：本技术 一种可变增益放大器 (Variable gain amplifier ) 是由 李天一 于 2019-02-27 设计创作，主要内容包括：一种可变增益放大器VGA,第一共源管对分别与第一共栅管对和第二共栅管对构成共源共栅结构,第二共源管对分别与第三共栅管对和第四共栅管对构成共源共栅结构,第一负载电阻分别耦合第一共栅管对中一个共栅管的漏极和第三共栅管对中一个共栅管的漏极,第二负载电阻分别耦合第一共栅管对中另一个共栅管的漏极和第三共栅管对中另一个共栅管的漏极,第一虚拟电阻分别耦合第二虚拟电阻、第二共栅管对中两个共栅管的漏极和第四共栅管对中两个共栅管的漏极,分流电路分别耦合第一共栅管对中两个共栅管的源极和第一虚拟电阻,反向并联电路分别耦合第三共栅管对中两个共栅管的源极、第一负载电阻和第二负载电阻。本申请实施例,可以提高VGA的性能。(The invention discloses a variable gain amplifier VGA. A first common source tube pair forms a common source and common gate structure respectively with a first common gate tube pair and a second common gate tube pair, the second common source tube pair forms a common source and common gate structure respectively with a third common gate tube pair and a fourth common gate tube pair, a first load resistor is respectively coupled with a drain electrode of one common gate tube in the first common gate tube pair and a drain electrode of one common gate tube in the third common gate tube pair, a second load resistor is respectively coupled with a drain electrode of the other common gate tube in the first common gate tube pair and a drain electrode of the other common gate tube in the third common gate tube pair, a first virtual resistor is respectively coupled with a second virtual resistor, drain electrodes of two common gate tubes in the second common gate tube pair and drain electrodes of two common gate tubes in the fourth common gate tube pair, a shunt circuit is respectively coupled with source electrodes of two common gate tubes in the first common gate tube pair and the first virtual resistor, and an anti-parallel circuit is respectively coupled with source electrodes of two common gate tubes in the third common gate tube pair, the first load resistor and the second load resistor. According to the embodiment of the invention, the performance of the VGA can be improved.)

The variable gain amplifier VGA is characterized by comprising a first variable gain circuit, a second variable gain circuit, a shunt circuit, an inverse parallel circuit, a first load resistor, a second load resistor, a first dummy (dummy) resistor and a second dummy resistor, wherein the first variable gain circuit comprises a first common source tube pair, a first common gate tube pair and a second common gate tube pair, the second variable gain circuit comprises a second common source tube pair, a third common gate tube pair and a fourth common gate tube pair, and the first variable gain circuit, the second variable gain circuit and the second variable gain circuit are respectively connected in series and in parallel, wherein:

the first common source tube pair and the first common gate tube pair respectively form a cascode structure, the second common source tube pair and the third common gate tube pair and the fourth common gate tube pair respectively form a cascode structure, the first load resistor is respectively coupled with the drain electrode of one common gate tube in the first common gate tube pair and the drain electrode of one common gate tube in the third common gate tube pair, the second load resistor is respectively coupled with the drain electrode of the other common gate tube in the first common gate tube pair and the drain electrode of the other common gate tube in the third common gate tube pair, the first virtual resistor is respectively coupled with the second virtual resistor, the drain electrodes of the two common gate tubes in the second common gate tube pair and the drain electrodes of the two common gate tubes in the fourth common gate tube pair, and the shunt circuit is respectively coupled with the source electrodes of the two common gate tubes in the first common gate tube pair and the first virtual resistor, the inverse parallel circuit is respectively coupled with the source electrodes of the two common-gate tubes in the third common-gate tube pair, the first load resistor and the second load resistor.

The VGA of claim 1 wherein the anti-parallel circuit is a fifth common-gate transistor pair consisting of two common-gate transistors, wherein:

the inverse parallel circuit respectively couples the source electrodes of the two common-gate transistors in the third common-gate transistor pair, the first load resistor and the second load resistor, and includes:

the first load resistor is coupled with the drain electrode of one common-gate tube in the fifth common-gate tube pair, the second load resistor is coupled with the drain electrode of the other common-gate tube in the fifth common-gate tube pair, the source electrode of one common-gate tube in the fifth common-gate tube pair is coupled with the source electrode of the other common-gate tube in the third common-gate tube pair, and the source electrode of the other common-gate tube in the fifth common-gate tube pair is coupled with the source electrode of one common-gate tube in the third common-gate tube pair.

The VGA of claim 1 wherein the shunt circuit is a sixth common-gate pair of two common-gate transistors, wherein:

the shunt circuit respectively couples the source electrodes of the two common-gate transistors in the first common-gate transistor pair and the first virtual resistor, and the shunt circuit comprises:

the first virtual resistor is respectively coupled with the drain electrodes of the two common-gate tubes in the sixth common-gate tube pair, the source electrode of one common-gate tube in the sixth common-gate tube pair is coupled with the source electrode of one common-gate tube in the first common-gate tube pair, and the source electrode of the other common-gate tube in the sixth common-gate tube pair is coupled with the source electrode of the other common-gate tube in the first common-gate tube pair.

The VGA of claim 1 wherein the shunt circuit comprises a first shunt resistor and a second shunt resistor, wherein:

the shunt circuit respectively couples the source electrodes of the two common-gate transistors in the first common-gate transistor pair and the first virtual resistor, and the shunt circuit comprises:

the first virtual resistor is respectively coupled with one end of the first shunt resistor and one end of the second shunt resistor, the other end of the first shunt resistor is coupled with the source electrode of one common gate tube in the first common gate tube pair, and the other end of the second shunt resistor is coupled with the source electrode of the other common gate tube in the first common gate tube pair.

The VGA of any of claims 1-4, wherein the first load resistor, the second load resistor, the first virtual resistor and the second virtual resistor are each configured to couple to a power supply.

The VGA of any of claims 1-5, wherein the first variable gain circuit further comprises a first current source and a second current source, and the second variable gain circuit further comprises a third current source and a fourth current source, wherein:

the first current source is respectively coupled with the source electrode and the ground end of one common source tube in the first common source tube pair, the second current source is respectively coupled with the source electrode and the ground end of the other common source tube in the first common source tube pair, the third current source is respectively coupled with the source electrode and the ground end of one common source tube in the second common source tube pair, and the fourth current source is respectively coupled with the source electrode and the ground end of the other common source tube in the second common source tube pair.

The VGA according to any of claims 1-6, wherein the first variable gain circuit further comprises a first capacitor, and the second variable gain circuit further comprises a second capacitor, and wherein:

two ends of the first capacitor are respectively coupled with the source electrodes of the two common source tubes in the first common source tube pair, and two ends of the second capacitor are respectively coupled with the source electrodes of the two common source tubes in the second common source tube pair.

The VGA according to any of claims 1-7, wherein the first variable gain circuit further comprises a first degeneration resistor, and the second variable gain circuit further comprises a second degeneration resistor, wherein:

two ends of the first degeneration resistor are respectively coupled with the source electrodes of the two common source tubes in the first common source tube pair, and two ends of the second degeneration resistor are respectively coupled with the source electrodes of the two common source tubes in the second common source tube pair.

The VGA is characterized by comprising a first variable gain circuit, a second variable gain circuit, a shunt circuit, an inverse parallel circuit, a first load resistor, a second load resistor, a first virtual resistor and a second virtual resistor, wherein the first variable gain circuit comprises a first common emitter tube pair, a first common base tube pair and a second common base tube pair, the second variable gain circuit comprises a second common emitter tube pair, a third common base tube pair and a fourth common base tube pair, and the first variable gain circuit comprises a first common emitter tube pair, a second common base tube pair and a fourth common base tube pair, wherein:

the first common emitter tube pair and the first common base tube pair and the second common base tube pair respectively form a common-emitter common-base structure, the second common emitter tube pair and the third common base tube pair and the fourth common base tube pair respectively form a common-emitter common-base structure, the first load resistor is respectively coupled with a collector electrode of one common base tube in the first common base tube pair and a collector electrode of one common base tube in the third common base tube pair, the second load resistor is respectively coupled with a collector electrode of the other common base tube in the first common base tube pair and a collector electrode of the other common base tube in the third common base tube pair, the first virtual resistor is respectively coupled with the second virtual resistor, collector electrodes of the two common base tubes in the second common base tube pair and collector electrodes of the two common base tubes in the fourth common base tube pair, and the shunt circuit is respectively coupled with an emitter electrode and the first virtual resistor of the two common base tubes in the first common base tube pair, the anti-parallel circuit is respectively coupled with the emitting electrodes of the two common base tubes in the third common base tube pair, the first load resistor and the second load resistor.

The VGA of claim 9 wherein the anti-parallel circuit is a fifth pair of common base pipes consisting of two common base pipes, wherein:

the inverse parallel circuit respectively couples the emitters of the two common base pipes in the third common base pipe pair, the first load resistor and the second load resistor, and comprises:

the first load resistor is coupled with a collector electrode of one common base pipe in the fifth common base pipe pair, the second load resistor is coupled with a collector electrode of the other common base pipe in the fifth common base pipe pair, an emitter electrode of one common base pipe in the fifth common base pipe pair is coupled with an emitter electrode of the other common base pipe in the third common base pipe pair, and an emitter electrode of the other common base pipe in the fifth common base pipe pair is coupled with an emitter electrode of one common base pipe in the third common base pipe pair.

The VGA of claim 9 wherein the shunt circuit is a sixth pair of common base pipes consisting of two common base pipes, wherein:

the shunt circuit respectively couples the emitters of the two common base tubes in the first common base tube pair and the first virtual resistor, and comprises:

the first virtual resistors are respectively coupled with the collectors of the two common base tubes in the sixth common base tube pair, the emitter of one common base tube in the sixth common base tube pair is coupled with the emitter of one common base tube in the first common base tube pair, and the emitter of the other common base tube in the sixth common base tube pair is coupled with the emitter of the other common base tube in the first common base tube pair.

The VGA of claim 9 wherein the shunt circuit comprises a first shunt resistor and a second shunt resistor, wherein:

the shunt circuit respectively couples the emitters of the two common base tubes in the first common base tube pair and the first virtual resistor, and comprises:

the first virtual resistor is respectively coupled with one end of the first shunt resistor and one end of the second shunt resistor, the other end of the first shunt resistor is coupled with an emitter of one common base tube in the first common base tube pair, and the other end of the second shunt resistor is coupled with an emitter of the other common base tube in the first common base tube pair.