阅读说明：本技术 一种用于pam4接收机的时钟与数据恢复电路 (Clock and data recovery circuit for PAM4 receiver ) 是由 谢生 郏成奎 毛陆虹 于 2021-08-20 设计创作，主要内容包括：本发明公开了一种用于PAM4接收机的时钟与数据恢复电路,包括：一个波形筛选器,从12种跳变方式中筛选4种既过中心阈值又过中心零点的跳变,既保证跳变沿密度足够高,又解决了跳变过零点离散导致的输入抖动；一个鉴相器,用于得出筛选信号与恢复时钟之间的相位超前/滞后信息；一个差分V/I转换器,用于将反映相位差的电压脉冲转换为充放电流,充分考虑路径的一致性；一个环路滤波器,用于反映相位差的脉冲电流对电容进行充放电,滤除电压信号的纹波；一个压控振荡器,实现频率改变到相位偏移的转换。本发明提出的PAM4CDR输出的时钟具有抖动小、摆幅大的优势。对于PAM4接收机CDR的波形跳变选择,实现低抖动、高稳定性具有很好的作用,拥有广阔的应用前景。(The invention discloses a clock and data recovery circuit for a PAM4 receiver, which comprises: a waveform filter, which filters 4 jumps which not only pass through the central threshold value but also pass through the central zero point from 12 jump modes, thereby ensuring that the jump edge density is high enough and solving the input jitter caused by jump zero-crossing point dispersion; a phase discriminator for deriving phase lead/lag information between the filtered signal and the recovered clock; a differential V/I converter for converting the voltage pulse reflecting the phase difference into a charge-discharge current, taking the consistency of the paths into full consideration; the loop filter is used for charging and discharging the capacitor by pulse current reflecting the phase difference and filtering ripples of the voltage signal; a voltage controlled oscillator performs conversion of frequency change to phase shift. The clock with PAM4CDR output provided by the invention has the advantages of small jitter and large swing amplitude. The method has good effects of realizing low jitter and high stability for the waveform jump selection of the CDR of the PAM4 receiver, and has wide application prospect.)

1. A clock and data recovery circuit for a PAM4 receiver, the circuit comprising:

the waveform filter is used for carrying out logic judgment on three thermometer code data and edge information of the PAM4 receiver and screening 4 jumps which exceed a central threshold value and a central zero point from 12 jumps through 2 simple and effective screening modes, so that the problem of large input jitter of CDR input signals caused by inconsistent zero crossing points of the 12 jumps of PAM4 signals is solved on the premise of ensuring that the jump edge density is high enough;

a phase discriminator circuit for comparing the phase difference between the filtered signal of the waveform filter and the clock recovered by the CDR to obtain the phase lead/lag information between the filtered signal and the clock recovered by the CDR;

the V/I converter is used for converting voltage pulses reflecting phase differences into charge and discharge currents, fully considers the consistency of charge and discharge paths of a capacitor of the loop filter, avoids triangular pulses with nonzero net area generated on control signals due to inconsistent arrival time of phase information pulses, and improves the accuracy of clock data recovery;

the loop filter is used for charging and discharging the capacitor by pulse current reflecting the phase difference, converting the current signal into a control voltage signal which is increased or decreased along with the phase difference, and reducing ripples of the voltage signal;

and the voltage-controlled oscillator adopts a PMOS cross coupling structure, regenerates a clock according to a control terminal voltage signal, and realizes the conversion from frequency change to phase deviation by changing the output clock frequency along with the control voltage.

2. The clock and data recovery circuit for PAM4 receiver of claim 1, wherein the waveform filter filters out 4 transition signals that pass through both the center zero and the center threshold in 2 simple and effective ways, the phase detector circuit uses a full rate Alexander phase detector to identify the phase lead/lag information of the clock and data, and after being enabled by the waveform filter, generates voltage pulses to be supplied to the V/I converter.

3. The clock and data recovery circuit for the PAM4 receiver of claim 1, wherein the 4 transition filtering modes that are both over center threshold and over center zero are specifically:

the first hopping screening mode: v_A、V_CAll have no jump, V_BJumping occurs;

the second hopping screening mode: v_A、V_BAnd V_CA jump occurs.

4. The clock and data recovery circuit of claim 1, wherein the logic timing of the waveform filter is:

from top to bottom, respectively are a random PAM4 signal, a first type of hopping edge screening signal, a second type of hopping edge screening signal and 4 types of hopping edge screening signals passing through a center zero point;

the output is logically ANDed with the UP and DN output of the phase discriminator respectively to control whether the phase lead/lag information obtained by the current jump period is effective or not.

Technical Field

The invention relates to the field of high-speed communication, in particular to a clock and data recovery circuit for a PAM4 receiver.

Background

In the face of pressure caused by transmission rate and circuit bandwidth limitation, in order to realize higher-rate transmission of information, 4-level Pulse Amplitude Modulation (PAM 4) or other multi-level Modulation modes are considered to break through the problem.

The PAM4 receiver includes circuits such as an analog front end circuit, a Clock Data Recovery (CDR) circuit, and a digital signal processing circuit. Since there is usually no separate channel for transmitting the clock signal in serial communication, the clock needs to be recovered from the data at the receiving end. The clock data recovery circuit plays a crucial role in the whole serial link, and the performance of the clock data recovery circuit directly influences the quality of a received signal.

Because the PAM4 signal has 4 levels and 12 hopping modes, and the zero-crossing point of the hopping mode takes a discrete form, thermometer code periods (pulse widths) recovered from the PAM4 signal are inconsistent, and the PAM4 signal of the receiver is greatly influenced by clock jitter during judgment, a more reliable CDR circuit is needed, so that a high-speed and low-jitter clock data recovery circuit becomes a core circuit of the PAM4 receiving circuit. After the PAM4 signal passes through the threshold decision device, three thermometer codes are generated, and the thermometer codes belong to NRZ codes (non-return-to-zero codes). Due to the fact that the zero-crossing point positions of different jump modes are different, the three thermometer codes have larger data jitter compared with the traditional NRZ code.

In order to prevent the asymmetrical data waveforms from affecting subsequent circuits, the transition waveforms passing through the center zero point need to be screened out before clock recovery, but the normal decision of the CDR on the phase difference cannot be affected. And phase discrimination is carried out according to the screened data waveform and the recovered clock, and the recovered clock retimes the three thermometer codes.

The PAM4 receiver clock data recovery circuit with the waveform screening function and the PAM4 receiver (application number: 202010455938.8) screen all 8 jump modes passing through a center zero point by adopting three waveform selection modes as input ends of PAM4CDR, input signals are 40Gb/s PAM4 data, and finally the peak-to-peak jitter of a recovered clock is 6.5 ps. The PAM4CDR with the waveform filter provided by the patent has higher phase discrimination density, but the circuit structure of the filter mode is slightly complicated, and obvious delay difference exists among different filter paths, so that the stability of the PAM4CDR is not facilitated.

The frequency discriminator, PAM4 clock data frequency locking method, recovery method and circuit (application number: 201811637731.1) adopts a frequency discriminator and a dual-charge pump structure, and the PAM4 level jump screening mode is as follows: when two adjacent sample data jump between 0 or 1 and 2 or 3, the data are considered to be valid; otherwise, the data is considered invalid. The phase frequency detector has strong phase locking capacity, but the used waveform screening mode only filters the jump mode of passing the central threshold, and the jump mode of passing the central zero point is not screened although the edge density required by phase discrimination is ensured to be high enough. Therefore, the screened input signals still have phase jitter introduced by different zero-crossing points.

In summary, the PAM4 signal has 4 levels and 12 transitions, so that the zero-crossing points are different, and the discrete zero-crossing points cause the thermometer code periods (pulse widths) recovered by the PAM4 signal to be different, thereby causing phase jitter. This not only causes timing errors in subsequent decoding circuits, but also increases the instability of the receiver CDR circuitry. Therefore, the waveform filter circuit is used as a core circuit of the PAM4CDR, and the jump mode of the over-center zero point is selected from 12 jump modes, so that it is very important to ensure a uniform and fixed zero crossing point.

Disclosure of Invention

The invention provides a clock and data recovery circuit for a PAM4 receiver, which reduces input jitter caused by the jump characteristic of a PAM4 signal on the premise of ensuring accurate locking of a phase-locked loop (CDR). Different from other PAM4CDR waveform screeners (using various complex modes to screen the jump mode only passing through the central threshold or only passing through the central zero point), the waveform screener introduced by the invention can screen 4 jump modes not only passing through the central threshold but also passing through the central zero point from 12 jump modes through 2 screening modes, and the screening circuit has the advantages of consistent screening circuit delay and simple and effective screening mode. The jump mode of the center zero point can effectively avoid data phase jitter caused by different jump zero points, the stability of the PAM4CDR is improved, the jump mode of the center threshold value can ensure that the phase discrimination density of the PAM4CDR is high enough, and the locking of the CDR to the frequency and the phase of the input signal is accelerated. The PAM4CDR of the invention adopts the Alexander phase detector in the full-rate Bang-Bang phase detector as a switch type system, which not only can automatically retime the input data, but also does not affect the control signal of the oscillator when the input data does not jump. The invention designs a V/I converter (voltage-current converter), fully considers the consistency of the charge and discharge paths of the capacitor of the loop filter, avoids triangular pulses with non-zero net area generated on control signals due to inconsistent arrival time of phase information pulses, and improves the accuracy of clock data recovery. See the description below for details:

a clock and data recovery circuit for a PAM4 receiver, the circuit comprising:

the waveform filter is used for carrying out logic judgment on three thermometer code data and edge information of the PAM4 receiver and screening 4 jumps which exceed a central threshold value and a central zero point from 12 jumps through 2 simple and effective screening modes, so that the problem of large input jitter of CDR input signals caused by inconsistent 12 jump zero points of PAM4 signals is solved on the premise of ensuring that the jump edge density is high enough;

a phase discriminator circuit for comparing the phase difference between the filtered signal of the waveform filter and the CDR recovery clock to obtain the phase lead/lag information between the filtered signal and the CDR recovery clock;

the V/I converter is used for converting voltage pulses reflecting phase differences into charge and discharge currents, fully considers the consistency of charge and discharge paths of a capacitor of the loop filter, avoids triangular pulses with nonzero net area generated on control signals due to inconsistent arrival time of phase information pulses, and improves the accuracy of clock data recovery;

the loop filter is used for charging and discharging the capacitor by pulse current reflecting the phase difference, converting the current signal into a control voltage signal which is increased or decreased along with the phase difference, and reducing ripples of the voltage signal;

and the voltage-controlled oscillator adopts a PMOS cross coupling structure, regenerates a clock according to a control terminal voltage signal, and realizes the conversion from frequency change to phase deviation by changing the output clock frequency along with the control voltage.

The phase discriminator circuit adopts a full-rate Alexander phase discriminator to discriminate the phase lead/lag information of the clock and the data, and generates pulses to be supplied to the V/I converter for use.

Further, the waveform filter filters out 4 filtering modes with the characteristics of passing through the center zero point and passing through the center threshold jump as follows:

the first hopping screening mode: v_A、V_CAll have no jump, V_BJumping occurs;

the second hopping screening mode: v_A、V_BAnd V_CA jump occurs.

And the jump waveform screened by the waveform filter is logically AND-ed with the UP and DN output by the phase discriminator respectively to control whether the phase lead/lag information obtained by the current jump period is effective or not, so that the enabling of the phase information is realized.

The technical scheme provided by the invention has the beneficial effects that:

1. the invention designs a waveform filter with a simpler structure, and screens 4 data waveforms which pass through a central threshold and a central zero point from 12 hopping modes through 2 waveform screens to phase-discriminate. The jump of the over-center zero point can avoid the influence of the code period of the thermometer and the jitter of the data edge on the CDR phase lock; the transition of the over-center threshold has a higher edge density, so that the CDR phase locking speed is faster.

2. The V/I converter designed by the invention adopts a fully differential structure, fully considers the consistency of the charge and discharge paths of the capacitor of the loop filter, avoids the generation of triangular pulses with nonzero net area on control signals caused by inconsistent arrival time of phase information pulses, and improves the accuracy of clock data recovery.

3. The PAM4CDR designed by the invention fully considers the PAM4 signal characteristic and the PAM4 receiver circuit collocation, the POMS cross-coupled VCO adopted by the PAM4CDR has the characteristics of low phase noise and strong driving capability, the fluctuation of the VCO control voltage is relieved by the differential V-I converter, and the input jitter caused by the PAM4 jump characteristic is eliminated by the waveform screener. Therefore, the PAM4CDR designed by the invention realizes larger clock output swing on the premise of ensuring smaller clock peak-to-peak value jitter.

In summary, the invention provides a simpler and effective scheme for screening low-jitter zero-crossing point hopping modes, and 4 data waveforms which pass through a central threshold and a central zero point are screened out from 12 hopping modes through 2 waveform screening modes for phase discrimination. A brand new V/I converter is provided, and the consistency of the charge and discharge paths of the loop filter capacitor is ensured. The clock output by the 50Gb/s PAM4CDR has the advantages of small jitter and large swing. The method has good effects on the selection of the CDR waveform jump of the PAM4 receiver, the realization of low jitter and high stability, and can meet the design requirements of the PAM4 receiver on a clock recovery circuit.

Drawings

Fig. 1 is an overall circuit block diagram of a PAM4 receiver;

FIG. 2 is a PAM4 signal eye diagram and 12 hopping patterns thereof;

FIG. 3 is a schematic block circuit diagram of an edge detector;

FIG. 4 is a schematic block circuit diagram of a waveform selector;

FIG. 5 is a timing diagram of an edge detector (double edge detection);

FIG. 6 is a timing diagram of an edge detector (single edge detection);

FIG. 7 is a timing diagram of the waveform selector;

FIG. 8 is a block diagram of an Alexander full rate phase detector;

FIG. 9 is a circuit schematic of a differential V/I converter;

FIG. 10 is a circuit output waveform of a differential V/I converter;

FIG. 11 is a circuit schematic of a Voltage Controlled Oscillator (VCO);

fig. 12 is an output eye diagram of the VCO.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below.

Example 1

An embodiment of the present invention provides a clock and data recovery circuit for a PAM4 receiver, and referring to fig. 1, the circuit includes:

the waveform filter is used for carrying out logic judgment on three thermometer code data and edge information of the PAM4 receiver and screening 4 jumps which exceed a central threshold value and a central zero point from 12 jumps through 2 simple and effective screening modes, so that the problem of large input jitter of CDR input signals caused by inconsistent 12 jump zero points of PAM4 signals is solved on the premise of ensuring that the jump edge density is high enough;

a phase discriminator circuit for comparing the phase difference between the filtered signal of the waveform filter and the clock recovered by the CDR to obtain the phase lead/lag information between the filtered signal and the clock recovered by the CDR;

the V/I converter is used for converting voltage pulses reflecting phase differences into charge-discharge currents, fully considers the consistency of paths when the capacitors of the loop filter are charged and discharged, avoids triangular pulses with non-zero net areas generated on control signals due to inconsistent arrival times of phase information pulses, and improves the accuracy of clock data recovery;

the loop filter is used for charging and discharging the capacitor by pulse current reflecting the phase difference, converting the current signal into a control voltage signal which is increased or decreased along with the phase difference, and reducing ripples of the voltage signal;

and the voltage-controlled oscillator adopts a PMOS cross coupling structure, regenerates a clock according to a control terminal voltage signal, and realizes the conversion from frequency change to phase deviation by changing the output clock frequency along with the control voltage.

The waveform filter is used for carrying out logic judgment on three paths of thermometer code data and edge information of the PAM4 receiver, screening 4 jumps which exceed a central threshold value and a central zero point from 12 jump modes through 2 simple and effective screening modes, and solving the problem of large input jitter of CDR input signals caused by inconsistent 12 jump zero points of PAM4 signals on the premise of ensuring that the jump edge density is high enough.

The phase discriminator circuit adopts a full-rate Alexander phase discriminator to discriminate the phase lead/lag information of the clock and the data, and generates pulses to be supplied to the V/I converter for use. The Alexander phase detector serving as a full-rate Bang-Bang phase detector has the advantages that a switch type system can automatically retime input data, control signals of an oscillator are not affected when the input data do not jump, and the phase difference judgment accuracy is higher.

The differential pulse signals output by the phase discriminator are converted into charge and discharge currents through the two V/I converters respectively, the consistency of charge and discharge paths of a capacitor of the loop filter is fully considered, triangular pulses with nonzero net area on control signals caused by inconsistent arrival time of phase information pulses are avoided, and the accuracy of clock data recovery is improved;

furthermore, compared with NMOS cross coupling with stronger compensation driving capability, the voltage-controlled oscillator adopts a PMOS cross coupling type VCO, which has lower phase noise and better improves clock jitter of CDR. The VCO regenerates a clock according to the voltage signal at the control end, and the output clock frequency of the VCO changes along with the control voltage to realize the conversion from frequency change to phase offset.

Compared with the prior art, the embodiment of the invention not only ensures higher jump edge density, but also reduces the input phase jitter, improves the phase discrimination precision and improves the jitter performance of the CDR recovery clock by reducing the input data jitter by screening the input data waveform. The fully differential V/I converter fully considers the consistency of the charge and discharge paths of the loop filter capacitor and improves the accuracy of clock data recovery.

Example 2

The scheme of example 1 is further described below with reference to the specific drawings, which are described in detail below:

after the PAM4 signal passes through threshold judgment (threshold comparator) of a receiver, the PAM4 signal is converted into three paths of NRZsCounting codes, each being V_A、V_BAnd V_CAs shown in fig. 1, these three thermometer codes are all output to the PAM4CDR as input data to the CDR.

The design of the PAM4CDR circuit comprises: circuit blocks such as a waveform filter, a Phase Frequency Detector (PFD), a V/I converter (or charge pump), a loop filter, a Voltage Controlled Oscillator (VCO), and a data retimer.

The waveform filter is a core module of PAM4CDR, and extracts edge information and data information of data according to the input three-way thermometer code data, and effectively filters jump edges according to the edge information and the data information.

The PAM4 waveform has 4 levels and 12 transition patterns, as shown in fig. 2 and table 1:

wherein, when the PAM4 high-order signal jumps, the level jumps over the central threshold (i.e. the thermometer code V)_BHopping occurs) and there are 8 hopping patterns ((c-r). And only (c-c) 4 jump modes of 8 jump modes of over-centre threshold value are passed through centre zero point. The function of the waveform filter in the embodiment of the present invention is to filter out the 4 jumping edges that are both over the center threshold and over the center zero.

Characteristics of table 112 hopping patterns

The waveform filter is composed of two parts, namely an edge detector and a waveform selector, which are respectively shown in fig. 3 and 4. In the edge detector, a single path with DA (one of NRZ signals output from the limiting amplifier) as input data is taken as an example (the same applies to other paths), and DA is V_AThe DA is delayed by a period to obtain DA1, and the DA is XOR-ed with DA1 (i.e. DA is XOR-ed with DA 1)) Then, the edge information EA of the DA is obtained, and the logic timing diagram of the edge information EA is shown in fig. 5, where the timing diagram is from top to bottom DA, DA1 and EA respectively. DA and DA1 are respectively subjected to mirror delay of an exclusive-OR gate and then subjected to AND with EALogic (DA · EA ═ EAH, DA1 · EA ═ EAL), then EAH and EAL are obtained, where EAH is the rising edge information of DA, EAL is the falling edge information of DA, and the logic timing diagram is shown in fig. 6, and the timing diagrams are DA, EAH, EAL and EA, respectively, from top to bottom.

The waveform selector needs to screen the (c) -b in the upper table from 12 jump edges, and the 4 jump edges can be divided into two categories:

1 → 2, 2 → 1, characteristics: v_A、V_CAll have no jump, V_BJumping occurs;

0 → 3, 3 → 0, characteristic: v_A、V_BAnd V_CA jump occurs.

The waveform selector is designed based on the transition information as described above, and as shown in figure 4,and EA, EB, EC are the selection logics of the two categories, respectively. WhileThe selection logic of 4 kinds of jump edges which are both over the central threshold value and over the central zero point is the jump edge enable signal. The logic timing sequence of the waveform selector is shown in fig. 7, and includes, from top to bottom, a random PAM4 signal, a first type of transition edge screening signal, a second type of transition edge screening signal, and 4 types of transition edge screening signals that both pass through the center threshold and the center zero. The output of the waveform selector is logically AND-ed with the output UP and DN of the phase discriminator respectively to control whether the phase lead/lag information obtained by the current jump cycle is effective or not.

Fig. 8 shows an Alexander full-rate phase detector and a phase detector pair V used in the embodiment of the present invention_BSampling is performed and phase difference information of the data is output. However random signal V_BThe occurrence of a transition does not mean that it is a valid transition edge, and it is required to logically and the output enable signal of the waveform selector to transfer the phase pulse signal to the V/I converter of the next stage.

Fig. 9 shows a fully differential V/I converter and a loop filter designed according to an embodiment of the present invention. The traditional V/I converter faces the problem that the arrival time of phase pulse signals UP and DN is inconsistent due to circuit delay, so that triangular pulses with non-zero net areas are generated on control signals, and the stability of a phase-locked loop is influenced. The fully differential V/I converter not only solves the problem of converting differential into single end, but also solves the problem of delay deviation of the traditional V/I converter because UP _ P and DN _ N both need to reach a loop filter through a current mirror image to generate control signals for charging and discharging of a capacitor. The output of the phase-lead time V/I converter increases from 440mV to 780mV as shown in fig. 10, and after 40ns, it tends to be stable with ripple jitter less than 5 mV.

Fig. 11 shows a PMOS cross-coupled VCO according to an embodiment of the present invention, which uses a three-terminal inductor and a variable capacitor as a resonant tank, and the PMOS cross-coupled circuit provides a negative resistance for the VCO to compensate for energy loss.

FIG. 11 is a clock eye diagram for PAM4CDR recovery with a power supply voltage of 0.9V and a transmission rate of 50Gb/s, according to the invention, based on TSMC 28nm technology, and used for integrating and optimizing the performance of the circuit module. As can be seen, an output swing greater than 700mV is sufficient to place the retiming flip-flop of the receiver in a large signal switching state. After PAM4CDR locking, the output clock eye peak-to-peak jitter is less than 2ps, and the low jitter output clock not only greatly improves CDR stability, but also the receiver NRZ signal jitter is smaller by retiming.

In summary, the embodiment of the present invention designs a PAM4CDR circuit with a waveform filter, which provides a simpler and more effective scheme for filtering a low-jitter zero-crossing hopping pattern, and selects 4 data waveforms that pass through a central threshold and a central zero point from 12 hopping patterns through 2 waveform filtering with consistent delay for phase discrimination, so that jitter of a data phase caused by zero-crossing point dispersion in the hopping patterns can be reduced, and a sufficiently high phase discrimination density of the PAM4CDR can be ensured. The invention provides a brand-new fully-differential V/I converter, which ensures the consistency of the charge and discharge paths of the capacitor of the loop filter, avoids the generation of triangular pulses with nonzero net area on control signals caused by inconsistent arrival time of phase information pulses, and improves the accuracy of clock data recovery. The 50Gb/s PAM4CDR output clock designed by the invention has the advantages of small jitter and large swing, and based on the TSMC 28nm technology, the jitter of the eye pattern peak value of the output clock is less than 2ps and the swing of the output clock is more than 700mV under the condition that the power supply voltage is 0.9V. The low-jitter and large-swing PAM4CDR designed by the invention provides an effective solution for reducing data jitter and bit error rate of a 50Gb/s PAM4 receiver.

In the embodiment of the present invention, except for the specific description of the model of each device, the model of other devices is not limited, as long as the device can perform the above functions.

Those skilled in the art will appreciate that the drawings are only schematic illustrations of preferred embodiments, and the above-described embodiments of the present invention are merely provided for description and do not represent the merits of the embodiments.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.