阅读说明：本技术 硅基太阳能电池单元及其制造方法 (Silicon-based solar cell unit and manufacturing method thereof ) 是由 张俊兵 蒋秀林 尹海鹏 单伟 于 2021-08-31 设计创作，主要内容包括：本公开的实施例提供硅基太阳能电池单元及其制造方法。硅基太阳能电池单元包括：第一型的硅基底,其具有第一表面和与所述第一表面相对的第二表面；多个第一掺杂部分,其在所述硅基底的第一表面中,所述多个第一掺杂部分彼此分开并且掺杂有第一型的掺杂粒子；多个第一掺杂源部分,所述多个第一掺杂部分分别设置在所述多个第一掺杂部分的背向所述硅基底的表面并且掺杂有所述第一型的掺杂粒子；以及第一钝化层,覆盖所述硅基底的第一表面和所述多个第一掺杂源部分背向所述硅基底的表面。由于省略了移除第一掺杂源部分的步骤,电池单元的制造过程被简化,制造成本降低。(Embodiments of the present disclosure provide silicon-based solar cells and methods of fabricating the same. The silicon-based solar cell unit includes: a silicon substrate of a first type having a first surface and a second surface opposite to the first surface; a plurality of first doping parts in a first surface of the silicon substrate, the plurality of first doping parts being separated from each other and doped with doping particles of a first type; a plurality of first doping source portions respectively disposed at surfaces of the plurality of first doping portions facing away from the silicon substrate and doped with doping particles of the first type; and the first passivation layer covers the first surface of the silicon substrate and the surface of the first doping source parts, which faces away from the silicon substrate. Since the step of removing the first doping source portion is omitted, the manufacturing process of the battery cell is simplified and the manufacturing cost is reduced.)

1. A silicon-based solar cell unit, comprising:

a silicon substrate of a first type having a first surface and a second surface opposite to the first surface;

a plurality of first doping parts in a first surface of the silicon substrate, the plurality of first doping parts being separated from each other and doped with doping particles of a first type;

a plurality of first doping source portions respectively disposed at surfaces of the plurality of first doping portions facing away from the silicon substrate and doped with doping particles of the first type; and

a first passivation layer covering a first surface of the silicon substrate and a surface of the plurality of first dopant source portions facing away from the silicon substrate.

2. The battery cell of claim 1,

the plurality of first doping parts are respectively formed by activating first type doping particles in the plurality of first doping source parts to dope the first type doping particles into the first surface of the silicon substrate.

3. The battery cell of claim 1, further comprising:

a plurality of first contact electrodes penetrating the first passivation layer to make ohmic contact with the first doping source portion.

4. The battery cell of claim 1,

and the projection of the first contact electrode on the silicon substrate along the thickness direction of the silicon substrate falls into the projection of the first doping source part on the silicon substrate along the thickness direction of the silicon substrate.

5. The battery cell of claim 1,

the silicon substrate and the first doped portion are monocrystalline silicon or polycrystalline silicon,

the first dopant source portion includes one or more of microcrystalline silicon, amorphous silicon, or polycrystalline silicon.

6. The battery cell of claim 1,

the first passivation layer comprises a single layer or a lamination layer of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer and a silicon carbide layer.

7. The battery cell of any of claims 1-6, further comprising:

a passivation dielectric layer on the second surface of the silicon substrate;

the selective carrier transmission layer is arranged on the surface, back to the silicon substrate, of the passivation medium layer and is doped with second-type doping particles; and

a second passivation layer on a surface of the selective carrier transport layer facing away from the silicon substrate.

8. The battery cell of claim 7, further comprising:

a plurality of second contact electrodes that penetrate the second passivation layer to make ohmic contact with the selective carrier transport layer.

9. The battery cell of claim 7,

the first type is n-type and the second type is p-type.

10. A method of manufacturing a battery cell, comprising:

providing a silicon substrate of a first type, wherein the silicon substrate comprises a first surface and a second surface opposite to the first surface;

forming a plurality of first doping source portions on a first surface of the silicon substrate, the plurality of first doping source portions being separated from each other and doped with doping particles of a first type;

activating first-type doping particles in the plurality of first doping source parts through high-temperature annealing treatment so as to form a plurality of first doping parts in the first surface of the silicon substrate respectively; and

and forming a first passivation layer which covers the first surface of the silicon substrate and the surface of the first doping source parts, which faces away from the silicon substrate.

Technical Field

Embodiments of the present disclosure relate to silicon-based solar cells and methods of fabricating the same.

Background

Human survival and development are not energy-efficient. Solar energy is one of the clean energy sources that can be live, large in volume. Silicon-based solar cells are a class of semiconductor devices that convert light energy directly into electrical energy. The PERC (Passivated Emitter and reader Cell) structure is the mainstream direction for the development of the silicon-based solar Cell technology due to its high photoelectric conversion efficiency. Compared with a conventional aluminum back surface field battery structure, the PERC battery structure is also provided with a back surface passivation layer, so that minority carrier recombination is reduced. For example, a silicon-based solar cell with a PERC structure has been proposed, in which a p-n junction is disposed on the back surface of a cell, so that the absorption of an amorphous silicon thin film to light is greatly reduced, and the photoelectric conversion efficiency of the cell is effectively improved. However, such silicon-based solar cells are complex and costly to manufacture. Further improvements in the photoelectric conversion efficiency of the cell are desired and silicon-based solar cells with simplified manufacturing steps and lower costs are desired.

Disclosure of Invention

Embodiments of the present disclosure provide a silicon-based solar cell unit, comprising: a silicon substrate of a first type having a first surface and a second surface opposite to the first surface; a plurality of first doping parts in a first surface of the silicon substrate, the plurality of first doping parts being separated from each other and doped with doping particles of a first type; a plurality of first doping source portions respectively disposed at surfaces of the plurality of first doping portions facing away from the silicon substrate and doped with doping particles of the first type; and the first passivation layer covers the first surface of the silicon substrate and the surface of the first doping source parts, which faces away from the silicon substrate.

By directly passivating the undoped region of the silicon substrate, minority carrier recombination at the first surface can be greatly reduced compared with the whole doped surface. Since the cell unit adopts local doping at the first surface, the first doping source part for forming the first doping part only partially covers the silicon substrate at the position of the first contact electrode, and the silicon substrate is not obviously shielded, so that the light conversion efficiency of the cell unit is not reduced. Thus, the first dopant source portion remains between the first contact electrode and the first doped portion in the silicon substrate. In fabricating the cell, the silicon substrate may be doped using the first dopant source portion as a dopant source to form the first dopant portion, but without removing the first dopant source portion. Since the step of removing the first doping source portion is omitted, the manufacturing process of the battery cell is simplified and the manufacturing cost is reduced.

For example, in some embodiments, the plurality of first doping portions are respectively formed by doping a first type of doping particles in the plurality of first doping source portions into the first surface of the silicon substrate by activating the first type of doping particles.

For example, in some embodiments, the battery cell further comprises a plurality of first contact electrodes that penetrate the first passivation layer to make ohmic contact with the first doping source portion.

For example, in some embodiments, a projection of the first contact electrode on the silicon substrate in a thickness direction of the silicon substrate falls within a projection of the first dopant source portion on the silicon substrate in the thickness direction of the silicon substrate.

For example, in some embodiments, the silicon substrate and the first doped portion are single crystal silicon or polycrystalline silicon. The first dopant source portion includes one or more of microcrystalline silicon, amorphous silicon, or polycrystalline silicon.

For example, in some embodiments, the first passivation layer comprises a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer, and a silicon carbide layer.

For example, in some embodiments, the battery cell further comprises: a passivation dielectric layer on the second surface of the silicon substrate; the selective carrier transmission layer is arranged on the surface, back to the silicon substrate, of the passivation medium layer and is doped with second-type doping particles; and a second passivation layer on the surface of the selective carrier transport layer, which faces away from the silicon substrate.

For example, in some embodiments, the battery cell further comprises: a plurality of second contact electrodes that penetrate the second passivation layer to make ohmic contact with the selective carrier transport layer.

For example, in some embodiments, the first type is n-type and the second type is p-type.

For example, in some embodiments, the first type is p-type and the second type is n-type.

For example, in some embodiments, the selective carrier transport layer comprises one or more of microcrystalline silicon, amorphous silicon, and polycrystalline silicon.

For example, in some embodiments, the second passivation layer comprises a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer, and a silicon carbide layer.

For example, in some embodiments, the passivation dielectric layer comprises a single layer or a stack of one or more of a non-metal oxide layer and a metal oxide layer.

For example, in some embodiments, the passivation dielectric layer comprises a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, and a silicon nitride layer.

For example, in some embodiments, the thickness of the passivation dielectric layer is in the range of 0.1nm to 10.0 nm.

An embodiment of the present disclosure provides a method of manufacturing a battery cell, including: providing a silicon substrate of a first type, wherein the silicon substrate comprises a first surface and a second surface opposite to the first surface; forming a plurality of first doping source portions on a first surface of the silicon substrate, the plurality of first doping source portions being separated from each other and doped with doping particles of a first type; activating first-type doping particles in the plurality of first doping source parts through high-temperature annealing treatment so as to form a plurality of first doping parts in the first surface of the silicon substrate respectively; and forming a first passivation layer which covers the first surface of the silicon substrate and the surface of the first doping source parts, which faces away from the silicon substrate.

For example, in some embodiments, the method of manufacturing further comprises: forming a plurality of first contact electrodes such that the plurality of first contact electrodes are in ohmic contact with the plurality of first doping source portions through the first passivation layer.

For example, in some embodiments, the method of manufacturing further comprises: forming a passivation dielectric layer on the second surface of the silicon substrate; forming a selective carrier transmission layer on the surface of the passivation medium layer, which is opposite to the silicon substrate, wherein the selective carrier transmission layer is doped with second type doped particles; forming a second passivation layer on the surface of the selective carrier transmission layer, which faces away from the silicon substrate; and forming a plurality of second contact electrodes which penetrate through the second passivation layer to make ohmic contact with the selective carrier transport layer.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present disclosure, and therefore should not be considered as limiting the scope of protection, and for those skilled in the art, other related drawings may be obtained from the drawings without inventive effort.

Fig. 1 is a schematic cross-sectional view of a battery cell according to a first embodiment of the present disclosure;

fig. 2 is a schematic flow chart of a method of manufacturing a battery cell according to a first embodiment of the present disclosure;

fig. 3A to 3G are schematic structural views corresponding to different steps of a method of manufacturing a battery cell according to a first embodiment of the present disclosure, respectively;

fig. 4 is a schematic flow chart of a method of manufacturing a battery cell according to a second embodiment of the present disclosure;

fig. 5 is a schematic structural diagram after forming a plurality of first dopant source portions on a first surface of a silicon substrate and a passivation dielectric layer, a first selective carrier transport pre-layer and a second selective carrier transport pre-layer on a second surface of the silicon substrate according to a second embodiment of the present disclosure;

fig. 6 is a schematic flow chart of a method of manufacturing a battery cell according to a third embodiment of the present disclosure;

fig. 7 is a schematic structural view after forming a plurality of first dopant source portions and a plurality of front dopant portions on a first surface of a silicon substrate and a passivation dielectric layer and a first selective carrier transport front layer on a second surface of the silicon substrate according to a third embodiment of the present disclosure;

fig. 8 is a schematic flow chart of a method of manufacturing a battery cell according to a fifth embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

It is to be noted that technical or scientific terms used herein should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

Herein, the front surface and the light receiving surface of the battery cell shown as the upper side of the battery cell in the drawings may be used interchangeably, and the back surface or the backlight surface of the battery cell shown as the lower side of the battery cell in the drawings may be used interchangeably. Herein, "intrinsic" means not doped with doping particles.

The silicon substrate in a silicon-based solar cell unit is typically plate-shaped or sheet-shaped, extending substantially in a plane and having a certain thickness. For convenience and clarity in describing the battery cell according to the present disclosure, a direction perpendicular to a plane in which a silicon substrate of the battery cell extends is defined as a "thickness direction" of the silicon substrate.

SUMMARY

Embodiments of the present disclosure provide a silicon-based solar cell unit, comprising: a silicon substrate of a first type having a first surface and a second surface opposite to the first surface; a plurality of first doping parts in a first surface of the silicon substrate, the plurality of first doping parts being separated from each other and doped with doping particles of a first type; a plurality of first doping source portions respectively disposed on surfaces of the plurality of first doping portions facing away from the silicon substrate and doped with first type doping particles; and a first passivation layer covering the first surface of the silicon substrate and the surface of the plurality of first doping source parts back to the silicon substrate.

By locally passivating the undoped region of the silicon substrate, minority carrier recombination at the first surface can be greatly reduced compared to a fully doped surface. Since the cell unit adopts local doping at the first surface, the first doping source part for forming the first doping part only partially covers the silicon substrate at the position of the first contact electrode, and the silicon substrate is not obviously shielded, so that the light conversion efficiency of the cell unit is not reduced. Thus, the first dopant source portion remains between the first contact electrode and the first doped portion in the silicon substrate. In fabricating the cell, the silicon substrate may be doped using the first dopant source portion as a dopant source to form the first dopant portion, but without removing the first dopant source portion. Since the step of removing the first doping source portion is omitted, the manufacturing process of the battery cell is simplified and the manufacturing cost is reduced.

Embodiments of the present disclosure provide a method of manufacturing a battery cell, which may be used, for example, to manufacture a battery cell as above. The method comprises the following steps: providing a first type of substrate comprising a first surface and a second surface opposite the first surface; forming a plurality of first dopant source portions on a first surface of a substrate, the plurality of first dopant source portions being separated from each other and doped with dopant particles of a first type; activating the first type dopant particles in the plurality of first dopant source portions by a high temperature annealing process to form a plurality of first dopant portions in the first surface of the substrate, respectively; and forming a first passivation layer covering the first surface of the silicon substrate and the surface of the first doping source parts, which faces away from the silicon substrate.

In the manufacturing method, a plurality of first doping portions are locally formed using a plurality of first doping source portions separated from each other, and a first passivation layer is formed on a first surface of a silicon substrate with the first doping source portions remaining after the first doping portions are formed, without removing the first doping source portions. Since the step of removing the first doping source portion is omitted, the manufacturing process of the battery cell is simplified and the manufacturing cost is reduced.

The above and other aspects of the disclosure are described below by way of example.

It should be noted that, in the present specification, the steps in the method do not have to be performed in the described order, and may be performed in other orders, with at least one step omitted, or with at least one additional step added, and the disclosure is not limited thereto. One skilled in the art may combine or modify the steps, features, processes, parameters in the embodiments presented herein to arrive at additional embodiments without departing from the scope of the claims of the present disclosure.

First embodiment

Fig. 1 is a schematic cross-sectional view of a battery cell according to a first embodiment of the present disclosure. Fig. 2 is a schematic flow chart of a method of manufacturing a battery cell according to the first embodiment. Fig. 3A to 3G are schematic structural views corresponding to different steps of the method of manufacturing a battery cell according to the first embodiment of the present disclosure, respectively.

As shown in fig. 1, the battery cell includes a silicon substrate 111 of a first type, a first doping layer including a plurality of first doping parts 116, a first doping source layer including a plurality of first doping source parts 1151, a plurality of first contact electrodes 1191, a first passivation layer 117, a passivation dielectric layer 112, a selective carrier transport layer 113, a plurality of second contact electrodes 1192, and a second passivation layer 118. The plurality of first doping parts 116 are formed in the first surface of the silicon substrate 111 separately from each other and doped with doping particles of the first type. The plurality of first doping source portions 1151 are respectively formed on a surface of each of the plurality of first doping portions 116 facing away from the silicon substrate 111, and are doped with doping particles of the first type. A first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first dopant source portion 1151 facing away from the silicon substrate 111. The plurality of first contact electrodes 1191 ohmic-contact the plurality of first dopant source portions 1151 of the first dopant source layer through the first passivation layer 117. The projection of the first contact electrode 1191 on the silicon substrate 111 in the thickness direction of the silicon substrate 111 falls within the projection of the first doping source portion 1151 on the silicon substrate 111 in the thickness direction of the silicon substrate 11. The passivation dielectric layer 112 is formed on a second surface of the silicon substrate 111. The selective carrier transport layer 113 is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate and is doped with doping particles of the second type. The second passivation layer 118 is formed on a surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. The plurality of second contact electrodes 1192 ohmic-contact the selective carrier transport layer 113 through the second passivation layer 118. A first surface of the silicon substrate 111 may face a front surface of the battery cell, and a second surface of the silicon substrate 111 may face a rear surface of the battery cell.

The passivation dielectric layer 112 and the selective carrier transport layer 113 constitute a passivation contact structure, which allows an emitter to be formed on the back surface of the cell due to the different types of doping particles of the selective carrier transport layer 113 and the silicon substrate 111. The passivation structure reduces metal contact recombination. The selective carrier transport layer 113 can selectively transport carriers, and contributes to reduction of back surface recombination and realization of high open voltage performance.

In addition, local doping is applied to the first surface of the silicon substrate 111 on the front side of the cell, which greatly reduces surface recombination on the front side of the cell compared to full-area doping. Therefore, minority carrier recombination of the front side and the back side of the battery unit is effectively reduced through the matching of the front side passivation structure and the back side passivation structure of the battery unit, and therefore a better passivation effect and a higher open-circuit voltage are obtained.

In addition, since the cell employs local doping on the first surface of the silicon substrate 111, the first doping source layer including the plurality of first doping source portions 1151 only partially covers the silicon substrate 111, and does not significantly shield the silicon substrate 111 to cause a decrease in light conversion efficiency of the cell. Thus, the first dopant source portion 1151 remains between the first contact electrode 1191 and the first doped portion 116 in the silicon substrate 111. In the process of fabricating the battery cell, the silicon substrate 111 may be doped using the first dopant source portion 1151 as a doping source to form the first doped portion 116, but the first dopant source portion 1151 need not be removed. Since the step of removing the first doping source portion 1151 is omitted, the manufacturing process of the battery cell is simplified and the manufacturing cost is reduced.

The first type may be p-type and the second type may be n-type. Alternatively, the first type may be n-type and the second type may be p-type. In the case where the silicon substrate 111 is a p-type silicon substrate 111, the cost of the silicon substrate 111 is reduced, and thus the cost of the battery cell is reduced. In the case where the silicon substrate 111 is an n-type silicon substrate 111, the substrate life of the silicon substrate 111 of the battery cell is high. Thus, the life of the battery cell is improved.

In the case where the first type is a P-type and the second type is an n-type, the doping particles of the first type may be group III element particles such as boron (B) and the doping particles of the second type may be group V element particles such as phosphorus (P). In the case where the first type is n-type and the second type is P-type, the doping particles of the first type may be particles of a V-th main group element such as phosphorus (P), and the doping particles of the second type may be particles of a III-th main group element such as boron (B).

The silicon substrate 111 may be single crystal silicon or polycrystalline silicon. For example, the silicon substrate 111 has a resistivity in the range of 0.1 to 20 Ω · cm, such as 0.1 Ω · cm, 1 Ω · cm, 5 Ω · cm, 10 Ω · cm, or 15 Ω · cm or 20 Ω · cm, and a thickness in the range of 50 to 300nm, such as 80 to 300nm, 50 to 100nm, 50 to 80nm, 100-.

The second surface of the silicon substrate 111 may be a flat or rough surface such as a polished surface, a wet-etched surface, or a textured surface.

The first doping portion 116 of the first doping layer is formed by doping the first type of doping particles into the silicon substrate 111 by activating the first type of doping particles in the first doping source portion 1151. The first doped layer may be single crystal silicon or polycrystalline silicon, similar to the silicon substrate 111.

The first doping source layer includes one or more of microcrystalline silicon, amorphous silicon, or polycrystalline silicon. For example, the thickness of the first dopant source layer is in the range of 10-300nm, such as 20-100nm, 40-80nm, 40nm, 50nm, and the like.

Passivation dielectric layer 112, which may also be referred to as a tunneling passivation layer, may include a metal oxide or a non-metal oxide, for example, it may include silicon oxide (SiO)_x) Layer, silicon oxynitride (SiO)_xN_1-x) Layer, aluminum oxide (AlO)_x) Layer, titanium oxide (TiO)_x) Layer and gallium oxide (GaOx) layer, silicon carbide (SiC)_x) A single layer or a laminate of one or more of a layer and an aluminum oxynitride layer. For example, the thickness of the passivation dielectric layer 112 may be in the range of 0.1-10nm, such as 0.1-5nm, 0.5-2nm, 1.5nm, 1.8nm, and the like.

The selective carrier transport layer 113 may include one or more of a microcrystalline silicon layer, an amorphous silicon layer, and a polycrystalline silicon layer. For example, the thickness of the selective carrier transport layer 113 is in the range of 1-300nm, such as 10-300nm, 10-100nm, 30-100nm, 50-100nm, 70nm, and the like.

The first passivation layer 117 may include a single layer or a stacked layer of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon carbide layer, and a silicon layer (a polycrystalline silicon layer, an amorphous silicon layer, or a microcrystalline silicon layer). For example, the thickness of the first passivation layer 117 may be 1-300nm, such as 10-300nm, 10-100nm, 30-100nm, 50-100nm, 70nm, and the like. For example, the first passivation layer 117 may be designed to function as an anti-reflective. When the materials of each layer are different in the multilayer stack, the passivation effect and the antireflection effect of each layer are different, and the first passivation layer 117 can be given a good passivation effect and antireflection effect by the cooperation of the layers.

Similarly, the second passivation layer 118 may include a single layer or a stacked layer of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon carbide layer, a silicon layer (a polycrystalline silicon layer, an amorphous silicon layer, or a microcrystalline silicon layer). For example, the thickness of the second passivation layer 118 may be 1-300nm, such as 10-300nm, 10-100nm, 30-100nm, 50-100nm, 70nm, and the like. When the materials of the layers in the multilayer stack are different, the passivation effect and the antireflection effect of each layer are different, and the second passivation layer 118 can be endowed with a good passivation effect and an excellent antireflection effect through the cooperation of the layers.

As shown in fig. 1 to 3G, in the present embodiment, the method of manufacturing the battery cell may include:

step S11, a first type of silicon substrate 111 is provided and a surface treatment is performed on the first surface and the second surface of the silicon substrate 111, as shown in fig. 3A. For example, the surface treatment includes surface texturing the first surface and the second surface of the silicon substrate 111 using a sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution in a texturing bath to form a textured structure including a plurality of pyramid-shaped sub-structures, and applying nitric acid (HNO)₃) And smoothing the pyramid-shaped substructure with a hydrofluoric acid (HF) mixed solution, and polishing the second surface with a tetramethylammonium hydroxide (TMAH) solution. In other embodiments, ozone (O), for example, may be used₃) Carrying out smooth treatment on the pyramid of the texture surface by using a mixed solution of HF and HF; for example, HNO may be used₃And the second surface is subjected to wet etching or polishing treatment by a mixed solution of HF, a NaOH solution or a KOH solution. Specifically, in the present embodiment, the silicon substrate 111 is p-type single crystal silicon having a resistivity of 2 Ω · cm.

In step S12, a passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111, as shown in fig. 3B. Specifically, in the present embodiment, a silicon dioxide layer having a thickness of 1.8nm is formed as the passivation dielectric layer 112 by Plasma Enhanced Chemical Vapor Deposition (PECVD). In addition, the passivation dielectric Layer 112 may be formed, for example, by a Low temperature furnace tube oxidation process, a nitric acid oxidation process, an ozone oxidation process, an Atomic Layer Deposition (ALD) process (including, for example, a Plasma Enhanced Atomic Layer Deposition (PEALD), etc.), a Chemical Vapor Deposition (CVD) process (including, for example, PECVD, Low Pressure Chemical Vapor Deposition (LPCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), etc.), a Physical Vapor Deposition (PVD) process (such as sputtering or evaporation), a Rapid Plasma Deposition (RPD), etc.

In step S13, a first selective carrier transport pre-layer 113' with second type of doped particles is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate, as shown in fig. 3C. Specifically, in the present embodiment, a phosphorus-doped amorphous silicon layer having a thickness of 70nm was formed as the first selective carrier transport pre-layer 113' by PVD. In the present embodiment, the first selective carrier transport pre-layer 113 'is doped in-situ, i.e. the selective carrier transport pre-layer 113' has been doped with doping particles of the second type. The first selective carrier transport pre-layer 113' is not crystallized. Herein, the "selective carrier transport pre-layer" is used to distinguish from the selective carrier transport layer 113 that has been crystallized.

In step S14, a first doping source layer including a plurality of first doping source portions 1151 doped with doping particles of the first type is formed on a local region on the first surface of the silicon substrate 111, as shown in fig. 3D. Specifically, in the present embodiment, a plurality of boron-containing amorphous silicon portions having a thickness of 40nm are formed as a plurality of first dopant source portions 1151 by a PVD process using a reticle.

In step S15, a high temperature annealing process is performed on the structure formed in step S14 so that the doping particles of the first type in the first doping source portion 1151 are activated to form a plurality of first doping portions 116 in the first surface of the silicon substrate 111, and the doping particles of the second type in the first selective carrier transport pre-layer 113 'are activated and the first selective carrier transport pre-layer 113' is crystallized to form the selective carrier transport layer 113, as shown in fig. 3E. In addition, during the high temperature annealing process, a first oxide layer 1152 is formed on the first dopant source layer and the first surface of the silicon substrate 111, and a second oxide layer 1131 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. Specifically, in the present embodiment, the high temperature annealing treatment includes performing a high temperature heat treatment at 950 ℃ in an annealing furnace tube.

In step S16, the first oxide layer 1152 and the second oxide layer 1131 are removed, as shown in fig. 3F. Specifically, in this embodiment, the first oxide layer 1152 generated due to the high-temperature annealing treatment and the second oxide layer 1131 generated due to the high-temperature annealing treatment are cleaned off with an HF solution.

In step S17, a first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first dopant source layer facing away from the silicon substrate, and a second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate, as shown in fig. 3G. Specifically, in the present embodiment, the first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first doping source layer facing away from the silicon substrate 111 by tubular PECVD, and the second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, alternatively or additionally, the first passivation layer 117 and the second passivation layer 118 may be formed using ALD, PEALD, or the like. For example, the first passivation layer 117 and the second passivation layer 118 may be a stack of an aluminum oxide layer and a silicon nitride layer, respectively.

In step S18, a first contact electrode 1191 and a second contact electrode 1192 are formed, as shown in fig. 1. Specifically, in the present embodiment, a metal contact paste such as a silver paste, an aluminum paste, or a silver-aluminum paste is printed on the surfaces of the first passivation layer 117 and the second passivation layer 118 by screen printing, and then the solidified first contact electrode 1191 and second contact electrode 1192 are obtained by sintering. Alternatively, the first contact electrode 1191 and the second contact electrode 1192 may be formed by plating or the like.

In the present embodiment, the step of removing the first doping source layer is omitted, thereby simplifying the manufacturing process and reducing the manufacturing cost.

Further, in the present embodiment, the simultaneous heat treatment of the front and back surfaces of the semiconductor structure is realized by one high-temperature annealing treatment step (step S15), that is: on the front side, the doping particles of the first type are activated to form a plurality of first doping portions 116; on the back side, the second type of doping particles are activated and the first selective carrier transport pre-layer 113' is crystallized to form the selective carrier transport layer 113. The manufacturing steps are simplified, the manufacturing cost is reduced, and the method is suitable for large-scale production.

Further, in the present embodiment, the first selective carrier transport pre-layer 113' and the first dopant source portion 1151 are formed using a PVD process. Compared with the CVD and other processes, the PVD process can form a single-sided film layer on the target surface, and a film layer is not formed on the surface or the side surface opposite to the target surface, namely, the phenomenon of winding plating is avoided. Thus, an additional manufacturing step for removing an undesired film layer due to the coil plating is not required, improving the production efficiency.

In addition, in the present embodiment, since the first selective carrier transfer pre-layer 113 ' and the first dopant source portion 1151 are both formed using a PVD process, by performing the steps of forming the first selective carrier transfer pre-layer 113 ' and the first dopant source portion 1151 in consecutive steps, the first selective carrier transfer pre-layer 113 ' and the first dopant source portion 1151 can be formed in the same PVD apparatus, which further simplifies the manufacturing steps and improves the production efficiency.

It should be noted that, in the present specification, the steps in the method do not have to be performed in the above order, and may be performed in other orders, with at least one step omitted, or with at least one additional step added, and the disclosure is not limited thereto. One skilled in the art may combine or modify the steps, features, processes, parameters in the embodiments presented herein to arrive at additional embodiments without departing from the scope of the claims of the present disclosure. Methods of manufacturing battery cells according to other embodiments of the present disclosure are given below, for example.

Second embodiment

Fig. 4 is a schematic flow chart of a method of manufacturing a battery cell according to a second embodiment of the present disclosure. Fig. 5 is a schematic structural view after forming a plurality of first dopant source portions 1151 on a first surface of a silicon substrate 111 and a passivation dielectric layer 112, a first selective carrier transport pre-layer 113' and a second selective carrier transport pre-layer 113 ″ on a second surface of the silicon substrate 111 according to a second embodiment of the present disclosure.

The structure of the battery cell manufactured using the manufacturing method according to the second embodiment is substantially the same as that of the battery cell manufactured using the manufacturing method according to the first embodiment as shown in fig. 1, and will not be described again.

A method of manufacturing a battery cell according to a second embodiment of the present disclosure includes:

step S21, a first type of silicon substrate 111 is provided and a surface treatment is performed on a first surface and a second surface of the silicon substrate 111. Specifically, in the present embodiment, the silicon substrate 111 is p-type single crystal silicon having a resistivity of 1 Ω · cm. For example, the surface treatment includes surface texturing the first surface and the second surface of the silicon substrate 111 using a sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution in a texturing bath to form a textured structure including a plurality of pyramid-shaped sub-structures, rounding the pyramid-shaped sub-structures using a mixed solution of O3 and HF, and finally polishing the second surface using an HNO3 and HF solution.

In step S22, a first dopant source layer including a plurality of first dopant source portions 1151 having dopant particles of a first type is formed on a first surface of the silicon substrate 111. Specifically, in the present embodiment, a plurality of boron-containing amorphous silicon portions having a thickness of 30nm are formed as a plurality of first dopant source portions 1151 by a PVD process using a reticle.

In step S23, a passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111. Specifically, in the present embodiment, a silicon dioxide layer having a thickness of 1.5nm is formed as the passivation dielectric layer 112 by ALD.

Step S24, a stack of a first selective carrier transport pre-layer 113' having the second type of dopant particles and an intrinsic second selective carrier transport pre-layer 113 ″ is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111, as shown in fig. 5. For example, a phosphorus-doped amorphous silicon thin film layer having a thickness of 40nm is formed as the first selective carrier transport pre-layer 113' by PVD, and an undoped amorphous silicon thin film layer having a thickness of 30nm is formed as the second selective carrier transport pre-layer 113 ″. In other embodiments, the positions of the first and second selective carrier transport pre-layers 113', 113 "may be interchanged.

Unlike the single layer of the first selective carrier transport pre-layer 113 'of in-situ doped particles of the second type in the first embodiment, in the second embodiment the structure formed during the manufacturing process comprises a stack of the first selective carrier transport pre-layer 113' with doped particles of the second type and the intrinsic second selective carrier transport pre-layer 113 ". The first selective carrier transport layer 113' provides the second type of doped particles for forming the selective carrier transport layer 113 in a subsequent high temperature annealing process and is crystallized to form a portion of the selective carrier transport layer 113. The second selective carrier transport pre-layer 113 ″ receives the second type of doping particles from the first selective carrier transport layer 113' in a subsequent high temperature annealing process and is also crystallized to form a portion of the selective carrier transport layer 113.

The advantage of the first selective carrier transport pre-layer 113' of in-situ doped particles of the second type forming a single layer in the first embodiment is that it requires only one step and is simpler to operate.

The advantage of forming the stack of the first selective carrier transport pre-layer 113 ' and the intrinsic second selective carrier transport pre-layer 113 "in the second embodiment is that the production efficiency is increased, since it takes longer to form the in-situ doped first selective carrier transport pre-layer 113 ', while here a part of the in-situ doped first selective carrier transport pre-layer 113 ' is replaced by the intrinsic second selective carrier transport pre-layer 113".

Further, the manufacturing method according to the second embodiment further includes the following steps that are the same as or similar to those of the first embodiment:

in step S25, the semiconductor structure formed in step S24 is subjected to a high temperature annealing process so that the doping particles of the first type in the first doping source portion 1151 are activated to form a plurality of first doping portions 116 in the first surface of the silicon substrate 111, and at the same time, the doping particles of the second type in the first selective carrier transport pre-layer 113 'are activated and the first and second selective carrier transport pre-layers 113' and 113 ″ are crystallized to form the doped selective carrier transport layer 113. In addition, during the high temperature annealing process, a first oxide layer 1152 is formed on a surface of the first dopant source portion 1151 facing away from the silicon substrate 111 and the first surface of the silicon substrate 111, and a second oxide layer 1131 is formed on a surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. Specifically, in the present embodiment, the high temperature annealing treatment includes performing a high temperature heat treatment at 920 ℃ in an annealing furnace tube.

In step S26, the first oxide layer 1152 and the second oxide layer 1131 are removed. For example, an HF solution is used.

In step S27, a first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first dopant source layer facing away from the silicon substrate 111, and a second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, the first passivation layer 117 and the second passivation layer 118 may be a stack of a titanium oxide layer and a silicon oxynitride layer, respectively.

In step S28, a first contact electrode 1191 and a second contact electrode 1192 are formed.

Other descriptions of the manufacturing methods according to the second embodiment and the following third and fourth embodiments may refer to the corresponding descriptions of the first embodiment.

Third embodiment

Fig. 6 is a schematic flow chart of a method of manufacturing a battery cell according to a third embodiment of the present disclosure. Fig. 7 is a schematic structural view after forming a plurality of first dopant source portions 1151 and a plurality of front dopant portions 116 'on a first surface of a silicon substrate 111 and a passivation dielectric layer 112 and a first selective carrier transport pre-layer 113' on a second surface of the silicon substrate 111 according to a third embodiment of the present disclosure.

The structure of the battery cell manufactured by the manufacturing method according to the third embodiment is substantially the same as that of the battery cell manufactured by the manufacturing method according to the first embodiment as shown in fig. 1, and will not be described again.

A method of manufacturing a battery cell according to a third embodiment of the present disclosure includes:

step S31, a first type of silicon substrate 111 is provided and a surface treatment is performed on a first surface and a second surface of the silicon substrate 111. Specifically, in the present embodiment, the silicon substrate 111 is p-type single crystal silicon having a resistivity of 4 Ω · cm. For example, the surface treatment includes surface texturing the first surface and the second surface of the silicon substrate 111 using a sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution in a texturing bath to form a textured structure including a plurality of pyramid-shaped sub-structures, rounding the pyramid-shaped sub-structures using a mixed solution of O3 and HF, and finally polishing the second surface using an HNO3 and HF solution.

In step S32, a passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111. Specifically, in the present embodiment, a silicon dioxide layer with a thickness of 1.8nm is formed as the passivation dielectric layer 112 by Plasma Enhanced Chemical Vapor Deposition (PECVD).

In step S33, a first doped layer including a plurality of first dopant source portions 1151 having dopant particles of the first type and a front doped layer including a plurality of intrinsic front doped portions 116' are sequentially formed on the first surface of the silicon substrate 111. Specifically, in the present embodiment, boron-containing microcrystalline silicon portions having a thickness of 20nm are formed as the plurality of first dopant source portions 1151 and intrinsic amorphous silicon thin film portions having a thickness of 20nm are formed as the front doped portions 116' by a PVD process using a reticle. Since the growth rate of the intrinsic front doping layer is faster than that of the in-situ doped first doping layer, the replacement of a portion of the first doping layer with the front doping layer can shorten the fabrication time and improve the fabrication efficiency.

In step S34, a first selective carrier transport pre-layer 113' is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111, as shown in fig. 7. Specifically, in the present embodiment, an amorphous silicon layer doped with phosphorus and having a thickness of 80nm was formed as the first selective carrier transport pre-layer 113' by PVD.

In step S35, a high temperature annealing process is performed on the structure formed in step S34 so that the doping particles of the first type in the first doping source portion 1151 are activated to form a plurality of first doping portions 116 in the first surface of the silicon substrate 111, and at the same time, the doping particles of the second type in the first selective carrier transport pre-layer 113 'are activated and the first selective carrier transport pre-layer 113' is crystallized to form the selective carrier transport layer 113. In addition, during the high-temperature annealing treatment, a first oxide layer 1152 is also formed on the surface of the first dopant source portion 1151 facing away from the silicon substrate 111 and the first surface of the silicon substrate 111, and a second oxide layer 1131 is also formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. Specifically, in the present embodiment, the high temperature annealing process includes performing a high temperature heat treatment on the intermediate semiconductor structure at 900 ℃ in an annealing furnace tube.

In step S36, the first oxide layer 1152 and the second oxide layer 1131 are removed. For example, the first oxide layer 1152 generated due to the high-temperature annealing treatment and the second oxide layer 1131 generated due to the high-temperature annealing treatment are cleaned off with an HF solution.

In step S37, a first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the first dopant layer, and a second passivation layer 118 is formed on the selective carrier transport layer 113. For example, the first passivation layer 117 and the second passivation layer 118 may be a stack of a gallium oxide layer and a silicon oxynitride layer, respectively.

In step S38, a first contact electrode 1191 and a second contact electrode 1192 are formed.

Fourth embodiment

The structure of the battery cell manufactured by the manufacturing method according to the fourth embodiment is mainly different from the structure of the battery cell manufactured by the manufacturing method according to the first embodiment as shown in fig. 1 in that, in the first embodiment, the first type is p-type and the second type is n-type; in a fourth embodiment, the first type is n-type and the second type is p-type.

A method of manufacturing a battery cell according to a fourth embodiment of the present disclosure includes:

step S41, a silicon substrate 111 of n-type single crystal silicon having a resistivity of 3 Ω · cm is provided and surface treatment is performed on a first surface and a second surface of the silicon substrate 111.

In step S42, a stack of alumina and titania with a thickness of 2.0nm is formed on the second surface of the silicon substrate 111 as the passivation dielectric layer 112.

In step S43, a boron-containing amorphous silicon layer with a thickness of 80nm is formed on the passivation dielectric layer 112 as the first selective carrier transport pre-layer 113' by PVD.

In step S44, a plurality of phosphorus-containing amorphous silicon portions as a plurality of first dopant source portions 1151 are locally formed on the second surface of the front surface of the silicon substrate 111 by a PVD process using a reticle.

In step S45, a high temperature annealing process is performed on the structure formed in step S44 so that the n-type dopant particles in the first dopant source portion 1151 are activated to form a plurality of first dopant portions 116 in the second surface of the silicon substrate 111, the p-type dopant particles in the first selective carrier transport pre-layer 113 'are activated and the first selective carrier transport pre-layer 113' is crystallized to form the selective carrier transport layer 113. In addition, during the high temperature annealing process, a first oxide layer 1152 is formed on a surface of the first dopant source portion 1151 facing away from the silicon substrate 111 and the first surface of the silicon substrate 111, and a second oxide layer 1131 is formed on a surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, the high temperature annealing process includes high temperature heat treating the intermediate semiconductor structure in an annealing furnace at 970 ℃.

In step S46, the first oxide layer 1152 and the second oxide layer 1131 are removed. For example, an HF solution is used.

In step S47, a first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first dopant source layer facing away from the silicon substrate 111, and a second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, the first passivation layer 117 and the second passivation layer 118 may be a stack of an aluminum oxide layer, a gallium oxide layer, and a silicon oxynitride layer, respectively.

In step S48, a first contact electrode 1191 and a second contact electrode 1192 are formed.

In the first to fourth embodiments described above, the simultaneous heat treatment of the front and back surfaces of the semiconductor structure of the battery cell to be formed is achieved by one high-temperature annealing treatment step, but the present disclosure is not limited thereto. The front and back sides of the semiconductor structure, on which the battery cell is to be formed, may also be heat treated separately.

Further, the above-described selective carrier transport pre-layers 113', 113 ″ are not limited to being formed by PVD, and other methods, such as CVD such as PECVD, may also be employed.

For example, an exemplary explanation is made by the following fifth embodiment.

Fifth embodiment

Fig. 8 is a schematic flow chart of a method of manufacturing a battery cell according to a fifth embodiment of the present disclosure.

The structure of the battery cell manufactured by the manufacturing method according to the fifth embodiment is substantially the same as that of the battery cell manufactured by the manufacturing method according to the first embodiment as shown in fig. 1, and will not be described again.

A method of manufacturing a battery cell according to a fifth embodiment of the present disclosure includes:

step S51, a first type of silicon substrate 111 is provided and a surface treatment is performed on a first surface and a second surface of the silicon substrate 111.

In step S52, a first dopant source layer including a plurality of first dopant source portions 1151 having dopant particles of a first type is locally formed on a first surface of the silicon substrate 111.

In step S53, the structure formed in step S52 is subjected to a high temperature annealing process to activate the first type dopant particles in the first dopant source portion 1151 to form a plurality of first dopant portions 116 separated from each other in the first surface of the silicon substrate 111.

In step S54, a passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111.

In step S55, a first selective carrier transport pre-layer 113' having second type of dopant particles is formed on the surface of the passivation dielectric layer 112 opposite to the silicon substrate 111. The second type of doping particles in the first selective carrier transport pre-layer 113 'are activated by a high temperature annealing process and the first selective carrier transport pre-layer 113' is crystallized to form the selective carrier transport layer 113. In addition, during the high temperature annealing process, a first oxide layer 1152 is formed on a surface of the first doping portion 116 facing away from the silicon substrate 111 and the first surface of the silicon substrate 111, and a second oxide layer 1131 is formed on a surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, the high temperature annealing process includes a high temperature heat treatment at 850 ℃ in an annealing furnace tube.

In step S56, the first oxide layer 1152 and the second oxide layer 1131 are removed.

In step S57, a first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first dopant source layer facing away from the silicon substrate 111, and a second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111.

In step S58, a first contact electrode 1191 and a second contact electrode 1192 are formed.

In addition, the order of step S52 and step S54 in the fifth embodiment may be interchanged.

The embodiment of the disclosure also comprises the following technical scheme:

technical solution 1, a silicon-based solar cell unit, comprising:

a silicon substrate of a first type having a first surface and a second surface opposite to the first surface;

a plurality of first doping parts in a first surface of the silicon substrate, the plurality of first doping parts being separated from each other and doped with doping particles of a first type;

a plurality of first doping source portions respectively disposed at surfaces of the plurality of first doping portions facing away from the silicon substrate and doped with doping particles of the first type; and

a first passivation layer covering a first surface of the silicon substrate and a surface of the plurality of first dopant source portions facing away from the silicon substrate.

The battery unit according to claim 2 or 1, wherein,

the plurality of first doping parts are respectively formed by activating first type doping particles in the plurality of first doping source parts to dope the first type doping particles into the first surface of the silicon substrate.

Claim 3 and the battery unit according to claim 1, further comprising:

a plurality of first contact electrodes penetrating the first passivation layer to make ohmic contact with the first doping source portion.

Claim 4 the battery cell according to claim 1, wherein,

and the projection of the first contact electrode on the silicon substrate along the thickness direction of the silicon substrate falls into the projection of the first doping source part on the silicon substrate along the thickness direction of the silicon substrate.

Claim 5 the battery cell according to claim 1, wherein,

the silicon substrate and the first doped portion are monocrystalline silicon or polycrystalline silicon,

the first dopant source portion includes one or more of microcrystalline silicon, amorphous silicon, or polycrystalline silicon.

Claim 6 the battery cell according to claim 1, wherein,

the first passivation layer comprises a single layer or a lamination layer of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer and a silicon carbide layer.

Claim 7, and the battery unit according to any one of claims 1 to 6, further comprising:

a passivation dielectric layer on the second surface of the silicon substrate;

the selective carrier transmission layer is arranged on the surface, back to the silicon substrate, of the passivation medium layer and is doped with second-type doping particles; and

a second passivation layer on a surface of the selective carrier transport layer facing away from the silicon substrate.

The battery unit according to claim 8 or 7, further comprising:

a plurality of second contact electrodes that penetrate the second passivation layer to make ohmic contact with the selective carrier transport layer.

The battery unit according to claim 9 or 7, wherein,

the first type is n-type and the second type is p-type.

The battery cell according to claim 10 or 7, wherein,

the first type is p-type and the second type is n-type.

Claim 11 and claim 7, wherein the battery unit,

the selective carrier transport layer includes one or more of microcrystalline silicon, amorphous silicon, and polycrystalline silicon.

The battery cell according to claim 12 or 7, wherein,

the second passivation layer comprises a single layer or a lamination layer of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer and a silicon carbide layer.

The battery cell according to claim 13 or 7, wherein,

the passivation dielectric layer comprises a single layer or a laminated layer of one or more of a non-metal oxide layer and a metal oxide layer.

The battery cell according to claim 14 or 7, wherein,

the passivation dielectric layer comprises a single layer or a lamination of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer and a silicon nitride layer.

The battery cell according to claim 15 or 7, wherein,

the thickness of the passivation dielectric layer is within the range of 0.1nm-10.0 nm.

The invention defined in claim 16 provides a method for manufacturing a battery cell, comprising:

providing a silicon substrate of a first type, wherein the silicon substrate comprises a first surface and a second surface opposite to the first surface;

forming a plurality of first doping source portions on a first surface of the silicon substrate, the plurality of first doping source portions being separated from each other and doped with doping particles of a first type;

activating first-type doping particles in the plurality of first doping source parts through high-temperature annealing treatment so as to form a plurality of first doping parts in the first surface of the silicon substrate respectively; and

and forming a first passivation layer which covers the first surface of the silicon substrate and the surface of the first doping source parts, which faces away from the silicon substrate.

The method of manufacturing a battery cell according to claim 17 or 16, further comprising:

forming a plurality of first contact electrodes such that the plurality of first contact electrodes are in ohmic contact with the plurality of first doping source portions through the first passivation layer.

The method of manufacturing a battery cell according to claim 18 or 16, further comprising:

forming a passivation dielectric layer on the second surface of the silicon substrate;

forming a selective carrier transmission layer on the surface of the passivation medium layer, which is opposite to the silicon substrate, wherein the selective carrier transmission layer is doped with second type doped particles;

forming a second passivation layer on the surface of the selective carrier transmission layer, which faces away from the silicon substrate; and

forming a plurality of second contact electrodes that penetrate the second passivation layer to make ohmic contact with the selective carrier transport layer.

The scope of the present disclosure is not defined by the above-described embodiments but is defined by the appended claims and equivalents thereof.