阅读说明：本技术 Iii-v构造集成在iv族基材上 (III-V architecture integration on group IV substrates ) 是由 L·维特斯 N·瓦尔登 A·M·沃克 B·库纳特 Y·莫里斯 于 2021-05-17 设计创作，主要内容包括：一种用于在IV族基材(1)上形成III-V构造的方法,所述方法包括：a.提供包括IV族基材(1)和其上的电介质(2)的组件,所述介电层包括底部暴露于IV族基材(1)的沟槽,b.沟槽中开始生长第一III-V结构,c.在位于底部部分(4)顶部的沟槽外继续生长,d.在第一III-V结构的顶部部分(5)上外延生长第二III-V牺牲结构(6),e.在第二III-V牺牲结构(6)上外延生长第三III-V结构(7,7’,7”,8),所述第三III-V结构(7,7’,7”,8)包括：ii.顶部III-V层,f.使顶部层的第一部分(8’)与其第二部分(8’)物理断开,以及g.使第二III-V牺牲结构(6)与液体蚀刻介质接触。(A method for forming a III-V configuration on a group IV substrate (1), the method comprising: a. providing an assembly comprising a group IV substrate (1) and a dielectric (2) thereon, the dielectric layer comprising a trench with a bottom exposed to the group IV substrate (1), b. growing a first III-V structure in the trench, c. growing further outside the trench on top of the bottom portion (4), d. epitaxially growing a second III-V sacrificial structure (6) on the top portion (5) of the first III-V structure, e. epitaxially growing a third III-V structure (7,7',7 ", 8) on the second III-V sacrificial structure (6), the third III-V structure (7,7', 7", 8) comprising: -a top III-V layer, f-physically disconnecting a first portion (8') of the top layer from a second portion (8') thereof, and g-contacting the second III-V sacrificial structure (6) with a liquid etching medium.)

1. A method for forming a III-V semiconductor construction on a single crystalline group IV substrate (1), the method comprising:

a. providing an assembly in an epitaxial growth chamber, the assembly comprising a single crystal group IV substrate (1) and a first dielectric layer (2) thereon, the first dielectric layer (2) comprising a trench having a bottom exposed to the group IV substrate (1),

b. starting to grow a first III-V structure in the trench, thereby forming a bottom portion (4) of the first III-V structure within the trench,

c. continuing the growth outside the trench at the top of the bottom portion (4), thereby forming a top portion (5) of the first III-V structure,

d. epitaxially growing a second III-V sacrificial structure (6) on a top portion (5) of the first III-V structure, said second III-V sacrificial structure (6) being selectively etchable in a liquid etching medium with respect to the first III-V structure (4,5),

e. epitaxially growing a third III-V structure (7,7',7 ", 8) on the second III-V sacrificial structure (6), the third III-V structure (7,7', 7", 8) comprising:

i. a bottom III-V layer (7) on the second III-V sacrificial structure (6), wherein the second III-V sacrificial structure (6) is selectively etchable in a liquid etching medium relative to the bottom III-V layer (7),

a top III-V layer,

f. physically disconnecting a first portion (8') of the top layer of the third III-V structure (7,7', 8) from a second portion (8') thereof, and

g. the second III-V sacrificial structure (6) is contacted with a liquid etching medium, whereby the second III-V sacrificial structure (6) is selectively etched with respect to the first III-V structure (4,5) and the bottom layer (7), thereby forming a chamber (23).

2. The method of claim 1, wherein the single crystalline group IV substrate (1) is a single crystalline silicon substrate (1).

3. A method according to claim 1 or claim 2, wherein the group IV substrate (1) exposed at the bottom of the trench is V-shaped.

4. The method of any one of the preceding claims, wherein the first III-V structure (4,5) comprises In_xGa_{1- x}As_zE_1-zWherein 0. ltoreq. x.ltoreq.1, 0. ltoreq. z.ltoreq.1, and E is selected from P, Sb and N.

5. The method according to any of the preceding claims, wherein the second III-V sacrificial structure (6) comprises InP.

6. The method according to any one of the preceding claims, wherein the bottom III-V layer (7) comprises: in_yAl_1-yAs, wherein y is 0.51 to 0.53; or In_wGa_1-wAs, wherein w is 0.52 to 0.54.

7. The method according to any of the preceding claims, wherein the top III-V layer (8) comprises InP.

8. The method of claim 6 or claim 7 when dependent on claim 6, wherein the third III-V structure (7,7',7 ", 8) comprises a bottom first In_yAl_1-yAs layer (7), bottom first In_yAl_1-yIn on the As layer_wGa_1-wAn As layer (7') In_wGa_1-wSecond In over and above As layer_yAl_1-yAn As layer (7 ″), and a second In layer_yAl_1-yA top InP layer (8) on the As layer (7'), thereby In_wGa_1-wAn As layer (7') sandwiched between two layers of In_yAl_1-yBetween the As layers (7, 7').

9. The method of any preceding claim, wherein the III-V semiconductor construction is a field effect transistor and the method comprises a step f' performed between or after step f and step g of: a first portion (8') of the top layer (8) of the third III-V structure (7,7', 8) is exposed and a source (20), a drain (21) and a gate stack (16,14) are formed thereon.

10. The method of claim 9, wherein the field effect transistor is a high electron mobility transistor.

11. The method according to any one of the preceding claims, wherein the method further comprises, after step g, step h: the cavity (23) is filled with a dielectric material (24).

12. The method according to any of the preceding claims, wherein the temperature in the chamber is set to 400 ℃ or higher when the top portion (5) is grown out of the trench.

13. The method according to any of the preceding claims, wherein at least one surfactant is added to the chamber when the top portion (5) grows out of the trench.

14. A III-V semiconductor construction, comprising:

a. an assembly comprising a single crystalline group IV substrate (1) and a first dielectric layer (2) thereon, said first dielectric layer (2) comprising a trench having a bottom exposed to the group IV substrate (1),

b. a first III-V structure (4,5) comprising a bottom portion (4) inside the trench and a top portion (5) on top of the bottom portion (4) outside the trench,

c. a cavity (23) or a dielectric structure (24) on a top portion (5) of the first III-V structure,

d. a third III-V structure (7,7', 8) on the chamber (23) or the dielectric structure (24), the third III-V structure (7,7', 8) comprising a bottom III-V layer (7) and a top III-V layer on the chamber (23) or the dielectric structure (24), the top III-V layer comprising a first portion (8') physically disconnected from a second portion (8').

15. The III-V semiconductor construction of claim 14 wherein the top portion (5) is wider than the bottom portion (4).

Technical Field

The present invention relates to the field of III-V semiconductors. More particularly, the present invention relates to a method of monolithically integrating III-V constructions on group IV substrates.

Background

III-V materials (e.g., GaAs, InGaAs, or InP) typically exhibit higher electron mobility and saturation velocity than Si. The material can also provide higher power at high frequencies than Si. Therefore, the material is widely used in radio frequency applications. When very high frequencies (GHz or higher) are targeted, Si devices cannot be used effectively. Devices using III-V materials are now built on small-sized III-V wafers. However, this wafer is very expensive compared to a Si wafer. Therefore, there is an interest in finding ways to monolithically integrate III-V devices on silicon substrates.

However, this is difficult due to the lattice mismatch between the III-V material and the silicon substrate, as it can cause defects in the III-V material being grown.

Using selective area growth, III-V materials can be deposited on silicon substrates by a variety of methods. These methods ensure that a threading dislocation free material is located on top of the structure building the III-V device by confining defects generated by the large lattice mismatch between the III-V material and Si to the lower portion of the III-V material.

One of these methods is to use nano-ridges.

The nanoridge is a semiconductor structure having a first width at the bottom and a second width at the top, the second width being greater than the first width. The first portion is grown in the dielectric trench and the second portion is formed when growth is continued outside the dielectric trench. The width of the second portion base expands as it moves away from the interface between the first and second portions, thereby forming a funnel-shaped base. On top of the substrate is an upper portion of the second section, which may have a constant width and a flat top surface, the width being equal to the width of the upper surface of the second section substrate. Kuner et al have described this structure (Applied Physics Letters, 109,091101 (2016)).

Since the bottom portion grows in a narrow trench, it benefits from aspect ratio trapping (aspect ratio trapping) and its top surface has little or no defects. Thus, the top portion is also low or no defects.

In addition to defects, the background doping level of the layers making up the III-V structure is also important. For example, background doping levels in layers below the transistor channel can result in undesirable leakage paths.

Accordingly, there remains a need in the art for improved methods and devices in which the background doping level is very low.

Disclosure of Invention

It is an object of the present invention to provide a good device or method for integrating III-V structures on Si substrates.

The above objects are achieved by the method and device according to the present invention.

In a first aspect, the invention relates to a method of forming a group III-V semiconductor construction on a group IV substrate, the method comprising:

a. providing an assembly in an epitaxial growth chamber, the assembly comprising a single crystal group IV substrate and a first dielectric layer thereon, the first dielectric layer comprising a trench having a bottom exposed to the group IV substrate,

b. growing a first III-V structure in the trench, thereby forming a bottom portion of the first III-V structure within the trench,

c. continuing growth outside the trench at the top of the bottom portion, thereby forming a top portion of the first III-V structure,

d. epitaxially growing a second III-V sacrificial structure on a top portion of the first III-V structure, the second III-V sacrificial structure being selectively etchable in a liquid etching medium relative to the first III-V structure,

e. epitaxially growing a third III-V structure on the second III-V sacrificial structure, the third III-V structure comprising:

i. a bottom III-V layer on a second III-V sacrificial structure (6), wherein the second III-V sacrificial structure is selectively etchable in a liquid etching medium relative to the bottom layer,

a top III-V layer,

f. physically disconnecting the first part of the third III-V structure from the second part of the third III-V structure, an

g. The second III-V sacrificial structure is contacted with a liquid etching medium, thereby selectively etching the second III-V sacrificial structure relative to the first III-V structure and the bottom layer, thereby forming a chamber.

In a second aspect, the invention relates to a III-V semiconductor construction comprising:

a. an assembly comprising a single crystal group IV substrate and a first dielectric layer thereon, the first dielectric layer comprising a trench having a bottom exposed to the group IV substrate,

b. a first III-V structure including a bottom portion within the trench and a top portion outside the trench on top of the bottom portion,

c. a cavity or dielectric structure on a top portion of the first III-V structure,

d. a third III-V structure on the chamber or the dielectric structure, the third III-V structure including a bottom III-V layer and a top III-V layer on the chamber or the dielectric structure, the top III-V layer including a first portion physically disconnected from a second portion.

An advantage of an embodiment of the first aspect is that it allows for the integration of III-V devices on group IV substrates.

An advantage of an embodiment of the first aspect is that it allows for the formation of devices for RF applications on group IV substrates.

An advantage of an embodiment of the first aspect is that it allows for the formation of devices for RF applications on group IV substrates.

An advantage of an embodiment of the first aspect is that it allows the formation of devices exhibiting high electron mobility and saturation rate on group IV substrates.

An advantage of an embodiment of the first aspect is that it allows for the formation of devices on group IV substrates that can provide high power at high frequencies.

An advantage of an embodiment of the first aspect is that it allows for the formation of III-V devices at low cost.

An advantage of an embodiment of the first aspect is that it allows the formation of III-V devices with low defectivity on group IV substrates.

An advantage of an embodiment of the first aspect is that it allows the formation of III-V transistor devices on group IV substrates, where the background doping level in the layers below the transistor channel is very low.

An advantage of an embodiment of the first aspect is that it allows the formation of III-V structures and devices with low parasitic capacitive coupling to the substrate.

Accordingly, there remains a need in the art for improved methods and devices in which the background doping level is very low.

Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features from the independent claims and features from other dependent claims as appropriate and not merely as explicitly set out in the claims.

While improvements, changes and developments in the art have continued, the inventive concept is believed to represent a sufficiently new and novel improvement, including departures from the present practice, resulting in the provision of more efficient, more stable and more reliable devices of this nature.

The above and other characteristics, features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. This description is intended for purposes of illustration only and is not intended to limit the scope of the present disclosure. The reference figures quoted below refer to the attached drawings.

Drawings

Fig. 1-4 and 7-8 are schematic vertical cross-sectional views of intermediates in a process according to one embodiment of the invention.

Fig. 5 is a schematic perspective view of the intermediate structure shown in fig. 4.

Fig. 6 is a schematic perspective view of the intermediate structure obtained between fig. 4 and fig. 7.

Fig. 9 and 10 schematically illustrate placement strategies for HEMTs according to some embodiments of the present invention.

The same reference numbers in different drawings identify the same or similar elements.

Detailed Description

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only illustrative and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and relative dimensions do not correspond to actual reductions to practice of the invention.

Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Furthermore, in the description and claims, the terms top, bottom, over, under and the like are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

It is to be noticed that the term 'comprising', used in the claims, should not be interpreted as being limitative to the parts listed thereafter, but does not exclude other elements or steps. It will be understood, therefore, that the presence of stated features, integers, steps or components or groups thereof does not preclude the presence or addition of one or more other features, integers, steps or groups thereof. Thus, the terms "comprises" and "comprising" cover the presence of the stated features alone and the presence of these features in combination with one or more other features. Thus, the word "comprising" according to instant invention also includes an embodiment in which no other components are present. Thus, the scope of the expression "a device comprising the components a and B" should not be understood as limiting the device to being constituted by the components a and B only. It is indicated that for the present invention, the only relevant components of the device are a and B.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments as would be apparent to one of ordinary skill in the art.

Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various aspects of the invention. However, the methods in this disclosure should not be understood to reflect the intent: the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Furthermore, when some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are intended to be included within the scope of the invention and form different embodiments, as would be understood by those skilled in the art. For example, in the appended claims, any of the claimed embodiments may be used in any combination.

Furthermore, certain embodiments are described herein as a method, or a combination of method elements, implemented by a processor of a computer system or by other means of performing a function. A processor having the instructions required to implement the method or method element thus forms an apparatus for implementing the method or method element. Additionally, the elements of an apparatus embodiment described herein are examples of means for performing the function performed by the element for performing the purpose of the present invention.

Numerous specific details are set forth in the description herein. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, procedures, and techniques have not been shown in detail in order not to obscure an understanding of this description.

The following terms are provided merely to facilitate understanding of the present invention.

As used herein, unless otherwise specified, when the term "III-V" is applied to a material, it refers to a material composed of at least one group III (group 13 in IUPAC) element and at least one group V (group 15 in IUPAC) element. This includes binary compounds, but also higher compounds, such as ternary compounds.

The present invention will now be described by a detailed description of several embodiments of the invention. It is clear that other embodiments of the invention can be constructed according to the knowledge of a person skilled in the art without departing from the true technical teaching of the invention, which is limited only by the claims appended hereto.

A reference transistor. These transistors are three terminal devices having a first main electrode (e.g. a drain), a second main electrode (e.g. a source) and a control electrode (e.g. a gate) for controlling the flow of charge between the first main electrode and the second main electrode.

In a first aspect, the invention relates to a method of forming a group III-V semiconductor construction.

The construction typically includes a plurality of different III-V semiconductor layers. Which is typically a III-V semiconductor device, or an intermediate in the construction of a semiconductor device.

The group IV substrate is typically a Si or Ge substrate (e.g., a wafer), but most typically a Si substrate.

FIG. 1 shows a single crystal group IV substrate (1) (e.g., Si) in which the fin has been patterned with a hard mask (3) and covered with a dielectric layer (e.g., SiO)₂) The top surface of the dielectric layer is coplanar with the top surface of the hard mask (3). The structure of fig. 1 may then be subjected to hard mask (3) removal and the single crystal group IV substrate (1) is etched selectively to the dielectric layer (3) to form the trenches of the component provided in step a. For example, if the substrate (1) is a Si substrate (1), the etching may be performed with tetramethylammonium hydroxide (TMAH). This has the advantage of forming a V-shaped trench bottom.

Fig. 2 shows an example of the configuration obtained in the embodiment after steps a to e.

Step a of the method of the first aspect comprises: an assembly is provided in an epitaxial growth chamber, the assembly comprising a single crystal group IV substrate (1) and a first dielectric layer (2) thereon, the first dielectric layer comprising a trench having a bottom exposed to the group IV substrate (1).

To form this configuration, the assembly is placed in an epitaxial growth chamber where growth conditions can be controlled. For example, a Metal Organic Vapor Phase Epitaxy (MOVPE) chamber may be used.

The first dielectric layer (2) on the single crystal group IV substrate (1) is preferably an oxide layer. Preferably, it is a layer of an oxide of a group IV material constituting the substrate (1). For example, if the substrate (1) is a Si substrate (1), the first dielectric layer (2) is preferably a silicon oxide layer, and the assembly comprises the Si substrate (1) and the silicon oxide layer thereon.

For example, the thickness of the first dielectric layer (2) may be 200nm to 500nm, for example 250nm to 450 nm.

The first dielectric layer (2) comprises a trench.

The component may be formed by a shallow trench isolation process, whereby one or more trenches are obtained in the dielectric layer. Defects are trapped in the trenches. Therefore, the trench width is preferably smaller than the trench depth. For example, the trench width is 1/6 to 1/2 of the thickness of the dielectric layer in which the trench is present. For example, if the dielectric layer thickness is 300nm, the trench width may be 50nm to 150 nm.

Preferably, the aspect ratio (trench depth relative to trench width) is greater than 1.43. This is advantageous because it allows capturing all defects caused by mismatches. The trench is prepared through a dielectric layer, which means that it can be prepared by direct physical contact of the trench with the group IV substrate (1). In some embodiments of the present invention, the dielectric trench may have a V-shaped group IV bottom. This is advantageous because it avoids inverse phase disorders in the III/V layer. However, the present invention is not limited thereto. For example, the bottom may also be flat.

An advantage of embodiments of the present invention is that strain-induced defects (strain-induced defects) caused by lattice mismatch between the group III-V material and the group IV substrate (1) are trapped at the sidewalls of the trench near the group III-V to group IV interface. Therefore, the defect density of the overgrown top of the first III-V structure is significantly reduced, which is very advantageous for device integration.

Step b of the method comprises: starting to grow a first III-V structure in the trench, thereby forming a bottom portion (4) of the first III-V structure within the trench,

in some embodiments, to initiate growth of the first III-V structure in the trench, precursors of a group III element and a group V element of a III-V material comprising the first III-V structure may be introduced into the chamber.

The composition of each III-V structure of the first aspect, in particular the first, second and third III-V structures (7,7',7 ", 8), and the composition of the layers making up the third III-V structure (7,7', 7", 8) are: it contains 50 atomic% of group V atoms and 50 atomic% of group III atoms.

In some embodiments, the first III-V structure may comprise In_xGa_1-xAs_zE_1-zWherein 0. ltoreq. x.ltoreq.1, 0. ltoreq. z.ltoreq.1, and E is selected from P, Sb and N.

In some embodiments, 0.5 ≦ z ≦ 1. In a preferred embodiment, z may be equal to 1.

In some embodiments, the first III-V structureMay contain In_xGa_1-xAs, wherein x is 0 to 1. The entire range from GaAs to InAs is suitable.

In some embodiments, 0.51 ≦ x ≦ 0.55, and z ≦ 1. This is particularly suitable when the top III-V layer of the third III-V structure (7,7',7 ", 8) is InP, since it enables a good matching of the lattice constant of the first structure to that of InP. In this case, it is preferable that 0.52 ≦ x ≦ 0.54 and z is 1, more preferably that x is 0.53 and z is 1.

Preferably, the material of the first III-V structure is selected in such a way that: the mismatch between the lattice constant of the material when unstrained (i.e. relaxed) and the lattice of the top III-V layer material of the third III-V structure (7,7',7 ", 8) when unstrained (i.e. relaxed) is at most 1%, preferably at most 0.5%.

Preferably, the material of the first III-V structure is selected in such a way that: the mismatch between the lattice constant of the material when unstrained, i.e. relaxed, and the lattice of the top III-V layer material of the third III-V structure (7,7',7 ", 8) and the material of all layers in between is at most 1%, preferably at most 0.5%.

Examples of precursors for forming the respective III-V structures of the first aspect, in particular the first, second and third III-V structures (7,7',7 ", 8), and the layers forming the third III-V structure (7,7', 7", 8), are: trialkylgallium such as triethylgallium (TEGa) and trimethylgallium (TMGa); trialkylenium (e.g. trimethylindium (TMIn)), alkyl arsine (e.g. tert-butyl arsine (TBA)), arsine gas (AsH)₃) Trialkyl antimony (e.g., triethyl antimony (TESb) or trimethyl antimony (TMSb)), trialkyl aluminum (e.g., trimethyl aluminum (TMAl)), tertiary alkyl phosphine (e.g., Tertiary Butyl Phosphine (TBP)), Phosphine (PH)₃) And dialkylhydrazines (e.g., 1-dimethylhydrazine).

For example, when the first III-V structure may contain In_xGa_1-xAs (where x is 0 to 1), the following precursor combinations may be used:

-TMGa,TMIn,TBAs；

-TMGa,TMIn,AsH₃；

TEGa, TMIn, TBAs; and

-TEGa,TMIn,AsH₃。

the molar flux applied may for example be in the range between the following values:

for example, the molar flux (mol-flux) of TMGa may be 1.0E-5 to 2.0E-4[ mol/min ], or more preferably 1.5E-5 to 1E-4[ mol/min ], or, for example, the molar flux of TEGa may be 0.2E-5 to 2.0E-4[ mol/min ], or more preferably 1.0E-5 to 1E-4[ mol/min ].

For example, the molar flux of TMIn may be from 1.9E-5 to 1.9E-4[ moles/minute ], or more preferably from 3.8E-5 to 1.5E-4[ moles/minute ].

The flux of TBA can be adjusted to meet a specific TBAs/(TMGa + TMIn) or TBAs/(TEGa + TMIn) ratio according to the Ga + In moles/minute flux. This ratio is preferably from 5 to 200, or even more preferably from 10 to 80.

The AsH can be adjusted according to the Ga + In mol/min flux₃To meet a specific AsH₃/(TMGa + TMIn) or AsH₃/(TEGa + TMIn) ratio. This ratio is preferably from 50 to 1000, or even more preferably from 50 to 500.

In some embodiments, step b may be performed in two stages. In a first stage, seed layer nucleation of the first III-V structure material may be achieved on the group IV surface, while in a second stage, the remaining trenches may be filled, thereby completing the bottom portion (4) of the first III-V structure. In some embodiments, the filling of the seed layer and the remaining trenches is performed under different growth conditions. The seed layer may have a thickness in the range of 5nm to 30 nm.

In some embodiments, the seed layer (III-V nucleation on group IV surfaces) may be performed, for example, at 300 ℃ to 450 ℃.

In some embodiments, filling the remaining trenches may be performed, for example, at 350 ℃ to 700 ℃, preferably 350 ℃ to 500 ℃.

Typically, step b may be carried out at a temperature of from 300 ℃ to 500 ℃. Step c is generally carried out at a temperature at least equal to the temperature used in step b for starting the growth.

The seed layer is advantageous in that it provides group IV (e.g., for the next layer)Si) good wettability of the substrate (1) and compensates, together with the filling layer, the group IV substrate (1) (Si) and the first III-V structure (e.g. In)_xGa_1-xAs) and which does not affect the shape of the top portion of the first III-V structure.

In step c, the growth started in the trench is continued outside the trench on top of the bottom portion (4), thereby forming a top portion (5) of the first III-V structure.

In some embodiments, the temperature in the chamber may be set at least 50 ℃ higher during step c than during step b.

In some embodiments, the temperature in the chamber may be set to 400 ℃ or higher when the top portion (5) of the first III-V structure is grown outside the trench.

In some embodiments, at least one surfactant may be added to the chamber as the top portion (5) of the first III-V structure grows out of the trench. Preferably, no surfactant is added if threading dislocations are still present on the top surface of the III-V structure being grown. Typically, the surfactant is added only after the top surface of the III-V structure being grown is free of threading dislocations. This is typically the case during step c. It is preferred to add the surfactant when the first III-V structure is grown out of the trench. In some embodiments of the present invention, a surfactant may also be added in step b while the growth front of the first III-V structure is still within the trench. The best point for adding the surfactant is when the first III-V structure is fully relaxed and all threading dislocations are trapped at the trench sidewalls. In some embodiments, this may occur within the trench during step b. Depending on the trench depth, the moment when the first III-V structure is fully relaxed may be when the fill layer is still within the trench. For deeper trenches, the point at which the III-V layer is fully relaxed and free of threading dislocations will be deeper within the trench.

The surfactant changes the surface energy and thereby the migration length of atoms involved in the growth process of the first III-V structure. Surfactants alter the properties of the crystal surface and thus the growth characteristics. An advantage of some embodiments of the present invention is that by using a surfactant, a first III-V structure with a flat (001) surface can be obtained at a higher temperature than without the use of a surfactant. Thus, funnel-shaped or box-shaped first III-V structures can be formed at high growth temperatures. The temperature may be, for example, above 400 ℃, for example above 500 ℃. The temperature may be, for example, above 525 ℃. And may be, for example, a temperature of 500 ℃ to 700 ℃ or preferably a temperature of 525 ℃ to 625 ℃. By increasing the temperature, not only the relaxation degree of the trench can be improved, but also the mobility of atoms and molecules on the surface can be improved. Without being bound by theory, it is speculated that the addition of surfactant in step c reduces the mobility of group III-and group V-atoms already incorporated into the first group III-V structure.

In an embodiment of the present invention, the at least one surfactant may be selected from the list of surfactants consisting of: gallium precursors (e.g., trialkylgallium, such as triethylgallium (TEGa) and trimethylgallium (TMGa)), indium precursors (e.g., trialkylindium, such as trimethylindium (TMIn)), arsenic precursors (e.g., alkyl arsines, such as t-butyl arsine (TBAs), or arsine gas (AsH)₃) Antimony precursors (e.g., trialkylsilyntimony, such as triethylantimony (TESb) or trimethylantimony (TMSb)), bismuth precursors (e.g., triphenylbismuth or trimethylbismuth), tellurium precursors (e.g., diethyltellurium), zinc precursors (e.g., dimethylzinc or diethylzinc), magnesium precursors (e.g., magnesium metallocenes), manganese precursors (e.g., biscyclopentadienylmanganese), tin precursors (e.g., tin chloride), hydrogen chloride, carbon tetrabromide, chlorine, bromochloromethane (e.g., CCl @)₃Br，CCl₂Br₂And CClBr₃) And carbon tetrachloride. The surfactant may not comprise a group III or group V element that has been used to grow the first III-V structure in step b. The surfactant preferably comprises a group III or group V element different from the group III or group V element that has been used to grow the first III-V structure in step b.

In some embodiments, when the first III-V structure contains In_xGa_1-xAs, where x is 0 to 1, the surfactant may be a Sb precursor, such As a trialkylsilylene (e.g., TESB or TMSb). In this case, for example, for TESB or TMSb, the molar flux may range from 1.0E-5 to 6.5E-4. Preferably 3.3E-5 to 3.2E-4[ mol/min ]]。

In some embodiments, the amount of surfactant may be adjusted so that it will be below 1E19cm^-3And preferably below 1E20cm^-3Is incorporated into the top portion of the first III-V structure. Preferably, no surfactant is incorporated into the first III-V structure. This is advantageous because it allows the surfactant to modify the growth characteristics without significantly altering the chemistry of the III-V structure.

In some embodiments, the time that the first III-V structure is exposed to the surfactant can be adjusted such that no surfactant is incorporated into the first III-V structure. This is advantageous because it allows the surfactant to modify the growth characteristics without altering the chemistry of the III-V structure.

Preferably the first III-V structure obtained at the end of step c has a flat (001) surface. Although the first III-V structure having a flat (001) surface can be grown at a low growth temperature, this easily produces an uneven structure having a rough top (001) surface due to low-temperature growth. This is disadvantageous for device integration. Thus, advantageously, the growth temperature can be increased by the addition of a surfactant while still forming a flat (001) surface.

In some embodiments, a plurality of first III-V structures are grown during steps b and c, and steps d through g are performed on each of the plurality of first III-V structures.

In some embodiments, the plurality of first III-V structures formed all have the same shape and size. In other words, it may be uniform. Typically, the top surfaces of the III-V structures in the plurality are coplanar. It is therefore an advantage of embodiments of the present invention that it enables the hetero-epitaxial integration of coplanar and uniform III-V structures on Si substrates (1) with flat (001) surfaces for device integration.

In a preferred embodiment, the III-V semiconductor construction is grown using Metal Organic Vapor Phase Epitaxy (MOVPE). However, the present invention may also be practiced using hydride vapor phase epitaxy or molecular beam epitaxy.

In the hydrogenationIn vapor phase epitaxy, HCl reacts with the group III metal to produce gaseous chlorides, which enter the deposition chamber. For group V, it uses hydrides with H₂As a carrier gas.

MBE mainly uses solid metal sources (e.g. Ga and As), but other types of sources are also possible. This is an ultra-high vacuum evaporation technique and therefore does not require a carrier gas.

In some embodiments, the carrier gas used to introduce the precursors in the chamber (e.g., MOVPE chamber) may be, for example, N₂Or H₂. The preferred option is H₂。

In some embodiments, the pressure in the chamber (e.g., MOVPE chamber) may range, for example, from 5 torr to 450 torr, more preferably from 10 torr to 150 torr.

In some embodiments, the total carrier gas flow rate during any of steps b to e may range from 10 to 30 liters/minute, more preferably from 15 to 25 liters/minute.

In some embodiments, the first III-V structure may be a nanoridge.

Although the invention has been described in the formation of HEMTs, embodiments of the method can be used to form other types of devices, such as silicon photonics devices, analog RF devices, imagers, and the like.

In step d, a second III-V sacrificial structure (6) is grown on the top portion (5) of the first III-V structure. The second III-V sacrificial structure (6) is selectively etched relative to the first III-V structure in a liquid etching medium.

The second III-V sacrificial structure (6) is typically made of a material having a relaxed (i.e., unstrained) lattice parameter that differs by + -1%, preferably + -0.5%, from the relaxed (i.e., unstrained) lattice parameter of the first III-V structure.

Preferably, the second III-V sacrificial structure (6) is lattice matched to the first III-V structure. In the first III-V structure_xGa_1-xAs (where 0.51 ≦ x ≦ 0.55, preferably 0.52 ≦ x ≦ 0.54, and more preferably x ≦ 0.53), the second III-V sacrificial structure may be InP. This is advantageous because InP can be relatively largeIn_xGa_1-xAs (wherein, x is 0.51. ltoreq. x.ltoreq.0.55) is selectively etched, and because InP and In are doped_xGa_1-xAs (where x ═ 0.53) is lattice matched.

Examples of precursors for InP formation are TMIn and TBP or PH₃。

For example, the flux of TMIn may range from 1.9E-5 to 1.9E-4[ moles/minute ], or more preferably from 2.9E-5 to 1.6E-4[ moles/minute ]. The flux of the TBP can be adjusted to meet a particular TBP/TMIn ratio. This ratio is preferably from 5 to 400, or even more preferably from 10 to 200.

Can adjust PH₃To meet a specific pH₃The ratio of/TMIn. This ratio is preferably from 50 to 1000, or even more preferably from 50 to 600.

For example, InP may be grown at a temperature of 400 ℃ to 700 ℃, preferably 475 ℃ to 625 ℃.

The liquid etching medium is chosen such that it can etch the second III-V structure (6) without etching the bottom III-V layer (7) of the first III-V structure or the third III-V structure (7,7', 8).

For example, to etch InP selectively to InGaAs, concentrated HCl may be used.

In step e, a third III-V structure (7,7', 8) is epitaxially grown on the second III-V sacrificial structure (6), the third III-V structure (7,7', 8) comprising:

i. a bottom III-V layer (7) on the second III-V sacrificial structure (6), wherein the second III-V sacrificial structure (6) is selectively etched relative to the bottom layer in a liquid etching medium; and

a top III-V layer.

The bottom III-V layer (7) is typically made of a material having a relaxed (i.e. unstrained) lattice parameter that differs by + -1%, preferably + -0.5%, from the relaxed (i.e. unstrained) lattice parameter of the second III-V sacrificial structure (6).

In some embodiments, the bottom III-V layer (7) may contain In_yAl_1-yAs, wherein y is 0.51 to 0.53, preferably y is 0.52. In other embodiments, the bottom III-V layer (7) may contain In_wGa_1-wAs, wherein w is 0.52 to 0.54, preferably w is 0.53. When the sacrificial layer is InP, the bottom III-V layer (7) is In_yAl_1-yAs or In_wGa_1-wThese embodiments of As are particularly advantageous because the lattice constant of these materials is close to or even matched to that of InP. In addition, InP may be selectively removed with respect to these layers using a liquid etching medium.

In some embodiments, the lattice constants of the material making up the first III-V structure, the material making up the second III-V sacrificial structure (6), and the material making up the layers of the third III-V structure (7,7', 8) differ from each other by + -1%, preferably + -0.5%. Preferably, the material constituting the first III-V structure, the material constituting the second III-V sacrificial structure (6) and the material constituting the layers of the third III-V structure (7,7', 8) are all lattice matched to one another.

In some embodiments, the top III-V layer may comprise InP. This is particularly advantageous because InP has an electron mobility and saturation rate that is compatible with ultra-high frequency device applications that operate at frequencies of 1GHz or higher.

In some embodiments, the third III-V structure (7,7', 8) may comprise a bottom first In_yAl_1-yAs layer, bottom first In_yAl_1-yIn on the As layer_wGa_1-wAs layer In_wGa_1-wSecond In over and above As layer_yAl_1-yAs layer (thus In)_wGa_1-wAn As layer sandwiched between two layers of In_yAl_1-yBetween As layers), and In the second In_yAl_1-yA top InP layer on the As layer, wherein y is 0.51 to 0.53, and preferably y is 0.52, and w is 0.52 to 0.54, and preferably w is 0.53. These embodiments are particularly suitable for forming HEMTs. In_yAl_1-yAs has a band gap higher than that of In_wGa_1-wAs. In is mixed with_wGa_1-wAs layer sandwiched between In_yAl_1-yIn between As layers_wGa_1-wThe As layer forms a quantum well. As a result, In_wGa_1-wThe As layer serves As a high mobility channel layer that can carry most of the carriers.

In some embodiments, In may be at the top and/or bottom_yAl_1-yDelta doping is performed in the As layer. This is advantageous because carriers provided by the dopant fall into the channel In when the quantum well is formed_wGa_1-wAn As layer forming a 2D electron gas that can be used for carrier conduction. Because the channel remains undoped, it can provide very high mobility for carriers.

Fig. 3 shows an example of a configuration according to an embodiment of the present invention after step f11.

In step f, a first portion (8') of the top layer (8) of the third III-V structure (7,7', 8) is physically disconnected from a second portion (8') thereof. In other words, the top layer (8) of the third III-V structure (7,7',7 ", 8) may be discontinuous by creating a gap between the first portion (8) of the top layer (8) and the second portion (8") thereof. To this end, generally, the first part of the entire third III-V structure (7,7',7 ", 8) may be physically disconnected from its second part.

In some embodiments, step f may comprise the steps of:

f1. forming a passivation layer (10) on the exposed surface of the component and on the top III-V layer (8);

f2. embedding the passivated third III-V structure (7,7', 8) in the second dielectric layer (9) such that the second dielectric layer (9) is coplanar with the top surface of the passivation layer (10),

f3. exposing a top portion of the top III-V layer (8) by etching away the top portion of the passivation layer (10) using the dielectric layer as a mask,

f4. covering the exposed top portion of the top III-V layer (8) and the exposed portion of the second dielectric layer (9) with a third dielectric layer (12),

f5. forming a mask element (e.g., a photoresist) on a first portion (8') of the top III-V layer (8),

f6. etching the third dielectric layer (12) by using the mask element as a mask until part of the top III-V layer (8) and part of the passivation layer (10) are exposed, and

f7. the third III-V structure (7,7', 8) is etched by using the mask element, the passivation layer (10) and the third dielectric layer (12) as a mask, thereby physically disconnecting the first portion (8') of the top layer (8) from the second portion (8') thereof. At the end of step f7, there is a groove (11) which disconnects the first portion (8') from the second portion (8').

At this stage, the first portion (8') of the third III-V structure (7,7',7 ", 8) is typically physically disconnected from its second portion (8 ').

Other steps intended to prepare step f' may be:

f8. the mask elements are removed and the mask elements are removed,

f9. forming a second passivation layer (13) conformally on the structure obtained after step f,

f10. forming a further dielectric layer on the second passivation layer (13),

f11. planarizing (e.g. by chemical mechanical planarization) the top surface of the structure obtained in g2 until the top surface of the second passivation layer (13) is exposed,

f12. further planarization is performed until a first portion (8') of the top III-V layer (8) is exposed.

In some embodiments, the III-V semiconductor construction may be a field effect transistor (e.g., HEMT), and the method may include a step f' performed between or after step f and step g: a first portion (8') of the third III-V structure (7,7', 8) is exposed and a source (20), a drain (21) and a gate stack (14,16) are formed thereon. The gate stack typically includes a gate dielectric (14) and a gate metal (16). There is typically a spacer (15) on either side of the gate stack.

Fig. 4 and 5 show examples of configurations according to embodiments of the present invention after step f' and before step g.

In some embodiments, step f' may comprise the steps of:

f' 1. forming dummy gates on the first portion of the top III-V layer,

f' 2, forming spacers on sidewalls of the dummy gate,

f' 3. growing a source (20) on one side of the dummy gate on the first portion of the top layer and a drain (21) on the other side of the dummy gate,

f' 4. replacing the dummy gate with a metal gate, an

f' 5. forming contacts (17) to the source (20), drain (21) and metal gate.

Step f' is typically performed after step f and before step g.

When step f 'is performed only after step h, step f' is preferably performed after step g (see below). In fact, it is advantageous to form the source (20)/drain (21) and gate electrodes when improving the mechanical stability of the structure by first filling the cavity (23) with a dielectric material (24).

In some embodiments, the gate may have a T-shape.

In fig. 4 and 5, a further passivation layer (18) and a further dielectric layer (19) are used for patterning the top gate and obtaining a "T-shape".

In step g, the second III-V sacrificial structure (6) is contacted with a liquid etching medium, thereby selectively etching the second III-V sacrificial structure (6) with respect to the first III-V structure and the bottom layer, thereby forming a chamber (23).

In some embodiments, step g may comprise the steps of:

g1. exposing the second III-V sacrificial structure (6), and

g2. the second III-V sacrificial structure (6) is contacted with a liquid etching medium, thereby selectively etching the second III-V sacrificial structure (6) relative to the first III-V structure and the bottom layer, thereby forming a chamber (23).

An example of the structure resulting from step g1 can be found in fig. 6.

An example of the structure resulting from step g2 can be found in fig. 7.

In some embodiments, the method may further comprise, after step g, step h: the cavity (23) is filled with a dielectric material (24). This is advantageous because it improves the mechanical stability of the device.

An example of the structure resulting from step h can be found in fig. 8.

Fig. 9 and 10 show: in case a plurality of transistors (e.g. HEMTs) are formed by this method, two different layout strategies are possible to access the second III-V sacrificial structure (6) to contact it with the liquid etching medium. There are many other possible layers. Typically, the entrance into the second III-V sacrificial structure (6) is formed outside the transistors, e.g. in the region present between the transistors. In these figures, the gate and the access point (22) exposing the second III-V sacrificial structure (6) are identified.

In a second aspect, the invention relates to a III-V semiconductor construction comprising:

a. an assembly comprising a single crystal group IV substrate (1) and a first dielectric layer (2) thereon, the first dielectric layer (2) comprising a trench having a bottom exposed to the group IV substrate (1),

b. a first III-V structure comprising a bottom portion (4) inside the trench and a top portion (5) on top of the bottom portion (4) outside the trench,

c. a cavity (23) or dielectric structure on a top portion (5) of the first III-V structure,

d. a third III-VIII-V structure (7,7', 8) on the chamber (23) or the dielectric structure, the third III-V structure (7,7', 8) comprising a bottom III-V layer (7) and a top III-V layer on the chamber (23) or the dielectric structure, the top III-V layer comprising a first portion (8') physically disconnected from a second portion (8').

In some embodiments, the top portion (5) may be wider than the bottom portion (4).

In some embodiments, a III-V semiconductor construction may be obtained by any of the embodiments of the first aspect.

Any feature of the second aspect as also described in the first aspect may be described accordingly.

It is to be understood that although preferred embodiments, specific constructions and configurations, as well as materials, have been discussed herein for devices according to the present invention, various changes or modifications in form and detail may be made without departing from the scope of this invention. Steps may be added or subtracted to the methods described within the scope of the present invention.