阅读说明：本技术 一种pmos通路开关控制电路 (PMOS access switch control circuit ) 是由 邓琴 梁源超 张龙 于 2021-08-19 设计创作，主要内容包括：本发明提供了一种PMOS通路开关控制电路,包括：电压钳位电路、电荷泵调压电路和第一PMOS管；电压钳位电路的第一端、电荷泵调压电路的输入端和第一PMOS管的源极均与电源连接；电压钳位电路的第二端和电荷泵调压电路的输出端均与第一PMOS管的栅极连接；第一PMOS管的漏极与待充电设备连接。本发明通过设置电荷泵调压电路能够在输出电压低于PMOS管的栅源电压时,保证PMOS管正常工作,进而提高充电器的供电效率。(The invention provides a PMOS access switch control circuit, comprising: the voltage clamping circuit, the charge pump voltage regulating circuit and the first PMOS tube are connected in series; the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are all connected with a power supply; the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube; and the drain electrode of the first PMOS tube is connected with the equipment to be charged. According to the invention, the voltage regulating circuit of the charge pump is arranged, so that the normal work of the PMOS tube can be ensured when the output voltage is lower than the grid-source voltage of the PMOS tube, and the power supply efficiency of the charger is further improved.)

1. A PMOS pass switch control circuit, the circuit comprising:

the voltage clamping circuit, the charge pump voltage regulating circuit and the first PMOS tube are connected in series;

the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are all connected with a power supply;

the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube;

and the drain electrode of the first PMOS tube is connected with the equipment to be charged.

2. The PMOS pass switch control circuit of claim 1, wherein said voltage clamp circuit specifically comprises:

n second PMOS tubes;

the grid electrode and the drain electrode of the ith second PMOS tube are both connected with the source electrode of the (i + 1) th second PMOS tube; 1, ·, n;

the source electrode of the 1 st second PMOS tube is used as the first end of the voltage clamping circuit and is connected with the power supply; and the grid electrode and the drain electrode of the nth second PMOS tube are connected as the second end of the voltage clamping circuit and are respectively connected with the output end of the charge pump voltage regulating circuit and the grid electrode of the first PMOS tube.

3. The PMOS pass switch control circuit of claim 1, wherein said charge pump voltage regulator circuit specifically comprises:

the device comprises an input voltage detection circuit, a PMOS gate drive circuit, a negative voltage charge pump and an additional voltage linear converter;

the input end of the input voltage detection circuit and the first input end of the additional voltage linear converter are connected as the input end of the charge pump voltage regulating circuit to be connected with the power supply;

the output end of the input voltage detection circuit is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative-voltage charge pump;

the output end of the additional voltage linear converter is connected with the first port of the negative voltage charge pump;

the second port and the third port of the negative-voltage charge pump are both grounded;

and a fourth port of the negative-voltage charge pump is connected with the output end of the PMOS gate drive circuit, and is used as the output end of the charge pump voltage regulating circuit to be connected with the gate of the first PMOS tube.

4. The PMOS pass-switch control circuit of claim 3, wherein the input voltage detection circuit specifically comprises:

a first resistor, a second resistor and a first operational amplifier;

the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the first operational amplifier;

the second end of the first resistor is used as the input end of the input voltage detection circuit and is connected with the power supply;

the second end of the second resistor is grounded;

a negative input end of the first operational amplifier inputs a reference voltage; the output end of the first operational amplifier is used as the output end of the input voltage detection circuit and is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump.

5. The PMOS pass-switch control circuit of claim 3, wherein the negative charge pump specifically comprises:

the first switch, the second switch, the third switch, the fourth switch and the flying capacitor;

the first end of the first switch and the first end of the second switch are both connected with the first end of the flying capacitor;

the first end of the third switch and the first end of the fourth switch are both connected with the second end of the flying capacitor;

the second end of the first switch is connected with the first port;

a second end of the second switch is connected with the second port;

a second end of the third switch is connected with the third port;

and the second end of the fourth switch is connected with the fourth port.

6. The PMOS pass-switch control circuit of claim 3, wherein the PMOS gate driver circuit specifically comprises:

a pull-up circuit and a pull-down circuit;

the first end of the pull-up circuit is used as the input end of the PMOS grid electrode driving circuit and the output end of the input voltage detection circuit; the second end of the pull-up circuit is used as the output end of the PMOS gate drive circuit and is respectively connected with the gate of the first PMOS tube and the first end of the pull-down circuit; the second terminal of the pull-down circuit is grounded.

7. The PMOS pass-switch control circuit of claim 6, wherein the pull-up circuit specifically comprises:

the first phase inverter and the third PMOS tube;

the power supply end of the first inverter is connected with the source electrode of the third PMOS tube to serve as the first end of the pull-up circuit, and the first end of the pull-up circuit is connected with the source electrode of the first PMOS tube; the input end of the first phase inverter is connected with the switch control signal of the first PMOS tube;

the output end of the first phase inverter is connected with the grid electrode of the third PMOS tube;

and the drain electrode of the third PMOS tube is used as the second end of the pull-up circuit and is connected with the first end of the pull-down circuit.

8. The PMOS pass-switch control circuit of claim 7, wherein the pull-down circuit specifically comprises:

the fourth PMOS tube, the first NMOS tube and the second phase inverter;

the source electrode of the fourth PMOS tube is used as the first end of the pull-down circuit and is connected with the drain electrode of the third PMOS tube; the grid electrode of the fourth PMOS tube inputs a clamping level; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube;

the source electrode of the first NMOS tube is used as the second end of the pull-down circuit and grounded; the grid electrode of the first NMOS tube is connected with the output end of the second phase inverter;

and the input end of the second phase inverter is connected with the switch control signal of the first PMOS tube.

Technical Field

The invention relates to the field of power supply control, in particular to a PMOS (P-channel metal oxide semiconductor) access switch control circuit.

Background

At present, the popularity of the rapid charging technology in portable intelligent mobile electronics such as smart phones, notebook computers, tablet computers and the like is higher and higher, especially, USB PPS (Universal Serial Bus Programmable Power Supply) supports 20mV continuous voltage regulation in a range of 3.3V to 21V, and can support a battery direct charging technology.

When the adapter supports the USB PPS specification, the protocol requirement must support 20mV step continuous voltage regulation in the range of 3.3V to 21V. When the communication of the quick charging protocol between the adapter and the charging equipment is unsuccessful, the adapter must output zero potential, and when the charging equipment successfully communicates and applies for a power demand, the adapter can output a corresponding power according to the application of the charging equipment. Therefore, the output terminal of the USB PD adapter generally has a pass switch for controlling the power supply path.

The power supply path is typically implemented using either PMOS or NMOS. When a PMOS is used as a power path switch, as shown in fig. 1 in the prior art, when the PMOS is turned on, the gate voltage of the PMOS is pulled down, and meanwhile, a clamping circuit is added to ensure that the gate-source voltage is within the safe operating voltage range of the PMOS. If the PMOS gate-source voltage is 5V for normal operation, the gate-source voltage will be clamped to around 5V. If the charging equipment supports USB PPS, when a voltage between 3.3V and 5V is applied, the adapter outputs 3.3V to 5V according to the equipment application. When the charger outputs a voltage within a range of 3.3-5.0V, for example, 3.3V, the conventional method can only pull the gate voltage of the PMOS transistor to ground, and VGS is 3.3V. When VGS is 3.3V, the gate-source voltage is low, so the internal resistance of the PMOS transistor increases, which increases the power consumption of the PMOS channel, thereby reducing the power supply efficiency of the charger, even causing the charger to generate heat seriously, which results in the system not working normally.

Disclosure of Invention

The invention aims to provide a PMOS (P-channel metal oxide semiconductor) access switch control circuit which can ensure that a PMOS (P-channel metal oxide semiconductor) tube works normally when the output voltage is lower than the grid-source voltage of the PMOS tube, thereby improving the power supply efficiency of a charger.

In order to achieve the purpose, the invention provides the following scheme:

a PMOS pass switch control circuit, comprising:

the voltage clamping circuit, the charge pump voltage regulating circuit and the first PMOS tube are connected in series;

the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are all connected with a power supply;

the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube;

and the drain electrode of the first PMOS tube is connected with the equipment to be charged.

Optionally, the voltage clamping circuit specifically includes:

n second PMOS tubes;

the grid electrode and the drain electrode of the ith second PMOS tube are both connected with the source electrode of the (i + 1) th second PMOS tube; 1, ·, n;

the source electrode of the 1 st second PMOS tube is used as the first end of the voltage clamping circuit and is connected with the power supply; and the grid electrode and the drain electrode of the nth second PMOS tube are connected as the second end of the voltage clamping circuit and are respectively connected with the output end of the charge pump voltage regulating circuit and the grid electrode of the first PMOS tube.

Optionally, the voltage regulating circuit of the charge pump specifically includes:

the device comprises an input voltage detection circuit, a PMOS gate drive circuit, a negative voltage charge pump and an additional voltage linear converter;

the input end of the input voltage detection circuit and the first input end of the additional voltage linear converter are connected as the input end of the charge pump voltage regulating circuit to be connected with the power supply;

the output end of the input voltage detection circuit is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative-voltage charge pump;

the output end of the additional voltage linear converter is connected with the first port of the negative voltage charge pump;

the second port and the third port of the negative-voltage charge pump are both grounded;

and a fourth port of the negative-voltage charge pump is connected with the output end of the PMOS gate drive circuit, and is used as the output end of the charge pump voltage regulating circuit to be connected with the gate of the first PMOS tube.

Optionally, the input voltage detection circuit specifically includes:

a first resistor, a second resistor and a first operational amplifier;

the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the first operational amplifier;

the second end of the first resistor is used as the input end of the input voltage detection circuit and is connected with the power supply;

the second end of the second resistor is grounded;

a negative input end of the first operational amplifier inputs a reference voltage; the output end of the first operational amplifier is used as the output end of the input voltage detection circuit and is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump.

Optionally, the negative voltage charge pump specifically includes:

the first switch, the second switch, the third switch, the fourth switch and the flying capacitor;

the first end of the first switch and the first end of the second switch are both connected with the first end of the flying capacitor;

the first end of the third switch and the first end of the fourth switch are both connected with the second end of the flying capacitor;

the second end of the first switch is connected with the first port;

a second end of the second switch is connected with the second port;

a second end of the third switch is connected with the third port;

and the second end of the fourth switch is connected with the fourth port.

Optionally, the PMOS gate driving circuit specifically includes:

a pull-up circuit and a pull-down circuit;

the first end of the pull-up circuit is used as the input end of the PMOS grid electrode driving circuit and the output end of the input voltage detection circuit; the second end of the pull-up circuit is used as the output end of the PMOS gate drive circuit and is respectively connected with the gate of the first PMOS tube and the first end of the pull-down circuit; the second terminal of the pull-down circuit is grounded.

Optionally, the pull-up circuit specifically includes:

the first phase inverter and the third PMOS tube;

the power supply end of the first inverter is connected with the source electrode of the third PMOS tube to serve as the first end of the pull-up circuit, and the first end of the pull-up circuit is connected with the source electrode of the first PMOS tube; the input end of the first phase inverter is connected with the switch control signal of the first PMOS tube;

the output end of the first phase inverter is connected with the grid electrode of the third PMOS tube;

and the drain electrode of the third PMOS tube is used as the second end of the pull-up circuit and is connected with the first end of the pull-down circuit.

Optionally, the pull-down circuit specifically includes:

the fourth PMOS tube, the first NMOS tube and the second phase inverter;

the source electrode of the fourth PMOS tube is used as the first end of the pull-down circuit and is connected with the drain electrode of the third PMOS tube; the grid electrode of the fourth PMOS tube inputs a clamping level; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube;

the source electrode of the first NMOS tube is used as the second end of the pull-down circuit and grounded; the grid electrode of the first NMOS tube is connected with the output end of the second phase inverter;

and the input end of the second phase inverter is connected with the switch control signal of the first PMOS tube.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

the invention provides a PMOS access switch control circuit, comprising: the invention provides a PMOS access switch control circuit, comprising: the voltage clamping circuit, the charge pump voltage regulating circuit and the first PMOS tube are connected in series; the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are all connected with a power supply; the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube; and the drain electrode of the first PMOS tube is connected with the equipment to be charged. According to the invention, the voltage regulating circuit of the charge pump is arranged, so that the normal work of the PMOS tube can be ensured when the output voltage is lower than the grid-source voltage of the PMOS tube, and the power supply efficiency of the charger is further improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a prior art PMOS pass switch control circuit;

FIG. 2 is a PMOS pass switch control circuit in an embodiment of the invention;

FIG. 3 is a first circuit diagram of an additional voltage linear converter in an embodiment of the present invention;

FIG. 4 is a second circuit diagram of an additional voltage linear converter in an embodiment of the present invention;

FIG. 5 is a circuit diagram of a negative charge pump according to an embodiment of the present invention; FIG. 5(a) is a control diagram of a negative charge pump switch in an embodiment of the present invention; FIG. 5(b) is a circuit diagram of a negative charge pump switch in an embodiment of the present invention;

FIG. 6 is a diagram of a PMOS gate driver circuit according to an embodiment of the present invention;

FIG. 7 is a circuit diagram of an input voltage detection circuit according to an embodiment of the present invention;

FIG. 8 is a diagram of a voltage clamp circuit in an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention aims to provide a PMOS (P-channel metal oxide semiconductor) access switch control circuit which can ensure that a PMOS (P-channel metal oxide semiconductor) tube works normally when the output voltage is lower than the grid-source voltage of the PMOS tube, thereby improving the power supply efficiency of a charger.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Fig. 2 is a PMOS pass switch control circuit in an embodiment of the present invention, and as shown in fig. 2, the present invention provides a PMOS pass switch control circuit, including:

the voltage clamping circuit, the charge pump voltage regulating circuit and the first PMOS tube are connected in series;

the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are all connected with a power supply;

the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube;

and the drain electrode of the first PMOS tube is connected with the equipment to be charged.

Fig. 8 is a diagram of a voltage clamping circuit according to an embodiment of the present invention, and as shown in fig. 8, the voltage clamping circuit provided in the present invention specifically includes:

n second PMOS tubes;

the grid electrode and the drain electrode of the ith second PMOS tube are both connected with the source electrode of the (i + 1) th second PMOS tube; 1, ·, n;

the source electrode of the 1 st second PMOS tube is used as the first end of the voltage clamping circuit and is connected with the power supply; and the grid electrode and the drain electrode of the nth second PMOS tube are connected as the second end of the voltage clamping circuit and are respectively connected with the output end of the charge pump voltage regulating circuit and the grid electrode of the first PMOS tube.

Wherein, the charge pump voltage regulating circuit specifically includes:

the device comprises an input voltage detection circuit, a PMOS gate drive circuit, a negative voltage charge pump and an additional voltage linear converter;

the input end of the input voltage detection circuit and the first input end of the additional voltage linear converter are connected as the input end of the charge pump voltage regulation circuit to be connected with the power supply;

the output end of the input voltage detection circuit is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump;

the output end of the additional voltage linear converter is connected with the first port of the negative voltage charge pump;

the second port and the third port of the negative-pressure charge pump are both grounded;

and the fourth port of the negative voltage charge pump is connected with the output end of the PMOS gate drive circuit, and is used as the output end of the charge pump voltage regulation circuit to be connected with the gate of the first PMOS tube.

Fig. 7 is a diagram of an input voltage detection circuit according to an embodiment of the present invention, and as shown in fig. 7, the input voltage detection circuit according to the present invention specifically includes:

a first resistor R1, a second resistor R2 and a first operational amplifier;

the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the first operational amplifier;

the second end of the first resistor is used as the input end of the input voltage detection circuit and is connected with the power supply;

the second end of the second resistor is grounded;

a negative input end of the first operational amplifier inputs a reference voltage; the output end of the first operational amplifier is used as the output end of the input voltage detection circuit and is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump.

Fig. 5 is a circuit diagram of a negative charge pump according to an embodiment of the present invention, and fig. 5(a) is a control diagram of a negative charge pump switch according to an embodiment of the present invention; FIG. 5(b) is a circuit diagram of a negative charge pump switch in an embodiment of the present invention; as shown in fig. 5, the negative charge pump specifically includes:

a first switch S1, a second switch S2, a third switch S3, a fourth switch S4 and a flying capacitor;

the first end of the first switch and the first end of the second switch are both connected with the first end of the flying capacitor;

the first end of the third switch and the first end of the fourth switch are both connected with the second end of the flying capacitor;

the second end of the first switch is connected with the control end;

the second end of the second switch is connected with the second port;

the second end of the third switch is connected with the third port;

the second end of the fourth switch is connected with the fourth port.

Fig. 6 is a diagram of a PMOS gate driver circuit according to an embodiment of the invention, and as shown in fig. 6, the PMOS gate driver circuit according to the invention specifically includes:

a pull-up circuit and a pull-down circuit;

the first end of the pull-up circuit is used as the input end of the PMOS grid electrode driving circuit and the output end of the input voltage detection circuit; the second end of the pull-up circuit is used as the output end of the PMOS gate drive circuit and is respectively connected with the gate of the first PMOS tube and the first end of the pull-down circuit; the second terminal of the pull-down circuit is grounded.

Specifically, the pull-up circuit specifically includes:

a first inverter and a third PMOS transistor M1;

the power supply end of the first phase inverter and the source electrode of the third PMOS tube are connected to serve as the first end of the pull-up circuit and are connected with the source electrode of the first PMOS tube; the input end of the first phase inverter is connected with the switch control signal of the first PMOS tube;

the output end of the first phase inverter is connected with the grid electrode of the third PMOS tube;

the drain electrode of the third PMOS tube is used as the second end of the pull-up circuit and is connected with the first end of the pull-down circuit.

The pull-down circuit specifically comprises:

a fourth PMOS transistor M2, a first NMOS transistor M3 and a second inverter;

the source electrode of the fourth PMOS tube is used as the first end of the pull-down circuit and is connected with the drain electrode of the third PMOS tube; the grid electrode of the fourth PMOS tube inputs a clamping level; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube;

the source electrode of the first NMOS tube is used as the second end of the pull-down circuit and grounded; the grid electrode of the first NMOS tube is connected with the output end of the second phase inverter;

the input end of the second phase inverter is connected with the switch control signal of the first PMOS tube.

In addition, specific circuit diagrams of the additional voltage linear converter in the present invention are shown in fig. 3-4.

Specifically, in order to solve the disadvantages of the existing PMOS pass switch control circuit, the present invention provides a pass control method and circuit for controlling the gate-source voltage of the pass PMOS transistor to a constant value by using a charge pump according to the variation of the input voltage. Through the circuit, when the transmitted input power supply voltage VIN is low, the grid-source voltage of the channel PMOS tube can be kept at a certain voltage value, so that the internal resistance of the channel PMOS tube in the process of transmitting low power supply voltage is effectively reduced, the system efficiency is improved, and the system heating is reduced.

As shown in fig. 2, a detection circuit of the input power VIN, an LDO as an additional voltage linear converter, and a negative voltage charge pump are added on the basis of the conventional PMOS gate driving circuit and VGS clamping circuit.

The voltage clamping circuit is a circuit commonly used in the industry, generally, a Zener diode is used, the Zener diode with the reverse breakdown voltage near the maximum normal working voltage of a PMOS grid source is selected, and the reverse breakdown voltage of the Zener diode can be used for realizing the function of the clamping circuit. The output of the PMOS gate drive circuit is connected to the PMOS gate, while one end is connected to the input voltage detection circuit. The PMOS gate driver circuit is also commonly used in the industry, and as shown in fig. 6, the PMOS transistor can be turned off and on by pulling up the PMOS gate and pulling down the NMOS gate. The input voltage detection circuit is connected to an input power source VIN, the output of the input voltage detection circuit is connected to the additional voltage linear converter, the output of the input voltage detection circuit is connected to the PMOS gate drive circuit and the negative voltage charge pump, and a VIN detection signal is sent to the additional voltage linear converter, the PMOS gate drive circuit and the negative voltage charge pump. The input voltage detection circuit is a general circuit in the industry, and can detect the input voltage by using a divider resistor and a comparator. The control end of the additional voltage linear converter is connected to the input voltage detection circuit, the input end of the additional voltage linear converter is connected to VIN, and the output end of the additional voltage linear converter is connected to the negative voltage charge pump. The negative charge pump has a positive input connected to the output of the additional voltage linear converter and a negative output connected to the PMOS gate.

The normal voltage for starting the grid source of the PMOS tube is assumed to be VGS_SET(typically 5V or 10V etc. are possible). When the input voltage detection circuit detects VIN>VGS_SETAt this time, the additional voltage linear converter is turned off and the negative voltage charge pump is turned off. The PMOS access switch control circuit works in the same way as the conventional control circuit, and the PMOS grid electrode is pulled down and pulled up by the PMOS grid electrode driving circuit to control the conduction and the disconnection of the PMOS tube. The gate-source voltage clamping circuit may be implemented with a corresponding reverse breakdown voltage zener diode. For example, the gate-source voltage of the PMOS at the normal start is 5V, a Zener diode with reverse breakdown voltage of about 5V can be used for clamping, and the voltage clamping circuit ensures that VGS does not exceed VGS_SET. When the input voltage detection circuit detects VIN<VGS_SETAt the moment, the pull-down circuit of the PMOS gate drive circuit is turned off, the additional voltage linear converter starts to work, and VLDO is generated from VIN according to the change of VIN_SETVIN and VLDO to a negative charge pump. The output end of the negative voltage charge pump is connected to the grid of the PMOS, the negative voltage charge pump receives the VLDO and is controlled by the input voltage detection circuit to start working, and the negative voltage charge pump drives the grid to be-VLDO ═ VGS_SET-VIN), thereby achieving VGS + VLDO VGS_SET. The negative charge pump is shown in fig. 5, and the process of driving the gate to a negative potential is as follows: in the first phase, switches S1 and S3 are closed and S2 and S4 are open. The upper plate of the flying capacitor is connected to the output of the LDO by S1, and the lower plate is connected to ground by S3. The capacitor is thus charged by the LDO and the voltage difference across the capacitor equals VLDO. In the second phase, switches S1 and S3 are open and S2 and S4 are closed. The capacitor top plate is connected to ground by S2, the capacitor bottom plate is connected to the output terminal VOUT by S4, and the charge pump output terminal VOUT is connected to the gate of the PMOS pass switch. Because the voltage at the two ends of the capacitor is kept unchanged, the upper polar plate of the capacitor is connected to the ground end, and the charge pump is at VOThe UT terminal outputs a negative voltage-VLDO. The input VIN of the negative charge pump is the output VLDO of the additional linear converter, where VLDO is VGS_SET-VIN. Therefore, the gate of the PMOS transistor will be driven to a negative potential- (VGS)_SET-VIN). Therefore, the difference between the gate-source voltages of the PMOS transistors is VGS ═ VIN + (VGS)_SET-VIN)＝VGS_SET. Thereby ensuring that the PMOS grid source voltage is maintained at VGS_SETTherefore, the PMOS on-resistance is not increased along with the reduction of VIN.

Fig. 3 is a basic principle schematic of the additional voltage linear converter referred to in the present invention. When VIN is detected<VGS_SETWhen VIN is found<VGS_SETThe circuit starts to operate. The voltage difference detection circuit detects VIN and VGS_SETIs output simultaneously with a sum of VIN and VGS_SETVoltage VR proportional to the difference of (1) as the subsequent stage LD_OI.e. VR ═ K × (VGS)_SET-VIN). K is a proportionality coefficient, and the LDO of the later stage generates VLDO (very low density oxygen) from VIN (vinyl chloride) (VGS) according to VR_SET-VIN. The principle of LDO is well known and will not be described here.

FIG. 4 is a detailed description of FIG. 3, based on the principle of using an operational amplifier to convert VGS_SETConversion to one and VGS_SETThe proportional current is converted into a current source through a PMOS mirror imageIs applied to a resistor R to generate a sum VGS_SETA proportional voltage. Meanwhile, VIN is converted into a current proportional to VIN by another operational amplifier, and then the current is converted into a current by PMOS current mirror and primary NMOS current mirrorAnd then to the same resistor terminal as the current source Isource. Thus, a sum VGS can be generated on the resistor_SETVoltage VR, VR ═ R × (Isource-Isink), i.e., VR ═ K × (VGS), proportional to the difference in VIN_SET-VIN). The VR is transmitted to the LDO of the later stage, and the later stage LDO amplifies the VR to 1/K times to obtain VLDO (very low density polyethylene) ═ VGS_SET-VIN。

Fig. 7 is an implementation of an input voltage detection circuit. The input voltage is divided by two resistors, and then the divided voltage signal is connected to the positive input end of a comparator, and the negative input end of the comparator is connected to a reference voltage for comparison, so that whether the input voltage is higher than VGS or not is detected_SET. When VIN > VGS_SETWhen so, the comparator outputs a high signal. When VIN is less than VGS_SETWhen so, the comparator outputs a high signal. The voltage detection circuit is a well-known technology in the industry and has various implementation modes.

The simplest way of voltage clamping is to use a zener diode, implemented with a zener diode reverse breakdown voltage. When the voltage applied to the two ends of the Zener diode exceeds the reverse breakdown voltage of the Zener diode, the Zener diode breaks down in the reverse direction, and the voltage drop of the two ends is clamped at the reverse breakdown voltage. Such as the zener diode shown in fig. 6, functions as a PMOS gate-source voltage clamp. In addition, as shown in fig. 8, a plurality of MOS transistors may be connected in series to realize a clamping function of the PMOS gate-source voltage. The MOS tubes can be connected in series by NMOS or PMOS. In addition, the voltage clamping circuit can be realized by adopting a mode of connecting a diode or a triode in series, and the realization modes are all known in the industry of the voltage clamping circuit.

Further, simplification can be made on the basis of fig. 2, and the same purpose can be achieved. Wherein the additional voltage linear converter can be a general LDO with a fixed output voltage. For example, if the PMOS normally works and the starting working voltage is VGS_SETSuch as VGS_SETWhen 5V, the LDO voltage may be set to a fixed 3V. When the input voltage VIN is less than VGS_SETWhen the output of LDO is fixed to 3V, i.e., VLDO ═ 3V. The negative charge pump starts to operate, pumping the gate voltage to a negative potential using VLDO ═ 3V. And meanwhile, a Zener diode with reverse breakdown voltage of about 5-6V is selected as a voltage clamping circuit. The gate-source voltage is clamped at the breakdown voltage of the zener diode due to the action of the clamped zener diode, so the charge pump cannot pump the gate voltage to-3V. Therefore, the VGS voltage can be kept under a larger voltage difference, and the reduction of the PMOS internal resistance is ensured. The method is simple to implement, but consists ofWhen the zener diode is in a breakdown state, the zener diode may leak electricity when it breaks down, which increases the power consumption of the whole circuit.

Further, when VIN<VGS_SETWhen the PMOS is turned on, the gate voltage of the PMOS needs to be driven to a negative voltage, and the pull-down path of the gate driving circuit shown in fig. 6 needs to be turned off, because the gate voltage is a negative potential at this time, the PMOS transistor M2 shown in fig. 6 should be connected in series by two back-to-back PMOS transistors, so as to prevent the pull-down path from being turned off. This is also a technique well known in the art.

Furthermore, the charge pump has a plurality of structures, the control method is variable, and the same function can be realized by slightly changing the structure. Modifications to the details of the charge pump circuit, or to the details of the LDO circuit, which are based on the present invention, are well within the scope of the basic underlying principles set forth in this disclosure.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. Meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.