阅读说明：本技术 一种nmos通路开关控制电路 (NMOS (N-channel metal oxide semiconductor) access switch control circuit ) 是由 邓琴 梁源超 张龙 于 2021-08-19 设计创作，主要内容包括：本发明提供了一种NMOS通路开关控制电路,包括：NMOS管、第一低压差线性转换器和双电荷泵调压电路；NMOS管的漏极、第一低压差线性转换器的输入端和双电荷泵调压电路的第一输入端和双电荷泵调压电路的第一输出端均与电源连接；第一低压差线性转换器的输出端与双电荷泵调压电路的第二输入端连接；双电荷泵调压电路的第二输出端与NMOS管的栅极连接；NMOS管的源极与待充电设备连接。本发明通过设置双电荷泵调压电路能够在输入电压低于NMOS管的栅源电压时,使NMOS管正常导通,进而提高充电器的供电效率。(The invention provides an NMOS pass switch control circuit, comprising: the device comprises an NMOS (N-channel metal oxide semiconductor) tube, a first low-voltage difference linear converter and a double-charge-pump voltage regulating circuit; the drain electrode of the NMOS tube, the input end of the first low-voltage-difference linear converter, the first input end of the double-charge-pump voltage regulating circuit and the first output end of the double-charge-pump voltage regulating circuit are connected with a power supply; the output end of the first low-voltage difference linear converter is connected with the second input end of the double-charge-pump voltage regulating circuit; the second output end of the double-charge-pump voltage regulating circuit is connected with the grid electrode of the NMOS tube; and the source electrode of the NMOS tube is connected with the equipment to be charged. The dual-charge-pump voltage regulating circuit can enable the NMOS tube to be normally conducted when the input voltage is lower than the grid-source voltage of the NMOS tube, and further improves the power supply efficiency of the charger.)

1. An NMOS pass switch control circuit, the circuit comprising:

the device comprises an NMOS (N-channel metal oxide semiconductor) tube, a first low-voltage difference linear converter and a double-charge-pump voltage regulating circuit;

the drain electrode of the NMOS tube, the input end of the first low-voltage-difference linear converter, the first input end of the double-charge-pump voltage regulating circuit and the first output end of the double-charge-pump voltage regulating circuit are all connected with a power supply;

the output end of the first low-voltage difference linear converter is connected with the second input end of the double-charge-pump voltage regulating circuit;

the second output end of the double-charge-pump voltage regulating circuit is connected with the grid electrode of the NMOS tube;

and the source electrode of the NMOS tube is connected with the equipment to be charged.

2. The NMOS pass-switch control circuit of claim 1 wherein said dual charge pump regulator circuit comprises:

the input detection circuit, the first stage charge pump and the second stage charge pump;

the input end of the input detection circuit is used as the first input end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

the output end of the input detection circuit is connected with the control end of the second-stage charge pump;

a first port of the second-stage charge pump is used as a second input end of the double-charge-pump voltage regulating circuit and is connected with the output end of the first low-voltage-difference linear converter;

the second port and the third port of the second-stage charge pump are both grounded;

the fourth port of the second-stage charge pump is connected with the third port of the first-stage charge pump;

a fourth port of the first-stage charge pump is used as a first output end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

and a second port of the first-stage charge pump is used as a second output end of the double-charge-pump voltage regulating circuit and is connected with the grid electrode of the NMOS tube.

3. The NMOS pass-switch control circuit of claim 1 wherein said dual charge pump regulator circuit comprises:

the input detection circuit, the first stage charge pump, the second stage charge pump and the voltage clamping circuit;

the input end of the input detection circuit is used as the first input end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

the output end of the input detection circuit is connected with the control end of the second-stage charge pump;

the first port of the second-stage charge pump and the first port of the first-stage charge pump are both connected with the output end of the first low-dropout linear converter;

the second port and the third port of the second-stage charge pump are both grounded;

the fourth port of the second-stage charge pump is connected with the third port of the first-stage charge pump;

a fourth port of the first-stage charge pump is used as a first output end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

a second port of the first-stage charge pump is used as a second output end of the double-charge-pump voltage regulating circuit and is respectively connected with the grid electrode of the NMOS tube and the first end of the voltage clamping circuit; and the second end of the voltage clamping circuit is connected with the equipment to be charged.

4. The NMOS pass switch control circuit of claim 3, wherein the voltage clamp circuit specifically comprises: a Zener diode;

the cathode of the Zener diode and the first end of the voltage clamping circuit are respectively connected with the second port of the first-stage charge pump and the grid electrode of the NMOS tube;

the anode of the Zener diode is used as the second end of the voltage clamping circuit and is connected with the source electrode of the NMOS.

5. The NMOS pass switch control circuit of claim 3, wherein the voltage clamp circuit specifically comprises:

n PMOS tubes;

the grid electrode and the drain electrode of the ith PMOS tube are both connected with the source electrode of the (i + 1) th PMOS tube; 1, ·, n;

the source electrode of the 1 st PMOS tube is used as the first end of the voltage clamping circuit and is connected with the fourth port of the first-stage charge pump and the grid electrode of the NMOS switch; and the grid electrode and the drain electrode of the nth PMOS tube are connected and then are used as the second end of the voltage clamping circuit to be respectively connected with the source electrode of the NMOS switch.

6. The NMOS pass switch control circuit of claim 2 or 3, wherein said input detection circuit specifically comprises:

a first resistor, a second resistor and an operational amplifier;

the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the operational amplifier;

the second end of the first resistor is used as the input end of the input detection circuit and is connected with the power supply;

the second end of the second resistor is grounded;

a negative input end of the operational amplifier inputs a reference voltage; and the output end of the operational amplifier is used as the output end of the input detection circuit and is connected with the control end of the second-stage charge pump.

7. The NMOS pass-switch control circuit of claim 1 wherein said dual charge pump regulator circuit comprises:

the input detection circuit, the second low-dropout linear converter, the first-stage charge pump and the second-stage charge pump;

the input end of the input detection circuit, the input end of the first low-dropout linear converter and the first input end of the second low-dropout linear converter are used as the first input end of the double-charge-pump voltage regulation circuit to be connected with a power supply;

the output end of the first low-dropout linear converter is connected with the control end of the first-stage charge pump;

the output end of the input detection circuit is respectively connected with the second input end of the second low dropout linear converter and the control end of the second-stage charge pump;

the output end of the second low dropout linear converter is connected with the first port of the second-stage charge pump;

the second port and the third port of the second-stage charge pump are both grounded;

the fourth port of the second-stage charge pump is connected with the third port of the first-stage charge pump;

a fourth port of the first-stage charge pump is used as a first output end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

and a second port of the first-stage charge pump is used as a second output end of the double-charge-pump voltage regulating circuit and is connected with the grid electrode of the NMOS tube.

8. The NMOS pass switch control circuit of claim 7, wherein said input detection circuit specifically comprises:

a first resistor, a second resistor and an operational amplifier;

the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the operational amplifier;

the second end of the first resistor is used as the input end of the input detection circuit and is connected with the power supply;

the second end of the second resistor is grounded;

a negative input end of the operational amplifier inputs a reference voltage; and the output end of the operational amplifier is used as the output end of the input detection circuit and is connected with the control end of the second-stage charge pump and the second input end of the second low-dropout linear converter.

9. The NMOS pass switch control circuit of claim 2, 3 or 7, wherein the first stage charge pump and the second stage charge pump each comprise:

the first switch, the second switch, the third switch, the fourth switch and the flying capacitor;

the first end of the first switch and the first end of the second switch are both connected with the first end of the flying capacitor;

the first end of the third switch and the first end of the fourth switch are both connected with the second end of the flying capacitor;

the second end of the first switch is connected with the first port;

a second end of the second switch is connected with the second port;

a second end of the third switch is connected with the third port;

and the second end of the fourth switch is connected with the fourth port.

Technical Field

The invention relates to the technical field of power supply control, in particular to an NMOS (N-channel metal oxide semiconductor) access switch control circuit.

Background

At present, the popularity of the rapid charging technology in portable intelligent mobile electronics such as smart phones, notebook computers, tablet computers and the like is higher and higher, especially, USB PPS (Universal Serial Bus Programmable Power Supply) supports 20mV continuous voltage regulation in a range of 3.3V to 21V, and can support a battery direct charging technology.

When the adapter supports the USB PPS specification, the protocol requirement must support 20mV step continuous voltage regulation in the range of 3.3V to 21V. When the communication of the quick charging protocol between the adapter and the charging equipment is unsuccessful, the adapter must output zero potential, and when the charging equipment successfully communicates and applies for a power demand, the adapter can output a corresponding power according to the application of the charging equipment. Therefore, the output terminal of the USB PD adapter generally has a pass switch for controlling the power supply path.

The power supply path is typically implemented using either PMOS or NMOS. When using NMOS as pass MOS, the conventional method is to pump the gate of NMOS to a higher output voltage by a certain value (e.g. 5V) using a charge pump, as shown in fig. 1, and the higher voltage value is generally generated from the input power by LDO. When the voltage of the input power supply is lower than 5V, the LDO only has a voltage reduction function, so that the voltage lower than that of the input power supply can be generated. Therefore, when the charger outputs 3.3V, the LDO can only output 3.3V, and in the prior art, the gate-source voltage of the NMOS can only be controlled to 3.3V by the charge pump. At this time, the grid voltage ratio is low, so that the internal resistance of the NMOS becomes large, which causes the power consumption on the NMOS power supply path to increase, thereby reducing the power supply efficiency of the charger, even causing the charger to generate heat seriously, which causes the charger system not to work normally.

Disclosure of Invention

The invention aims to provide an NMOS (N-channel metal oxide semiconductor) access switch control circuit which can normally conduct an NMOS tube when the input voltage is lower than the grid-source voltage of the NMOS tube, so that the power supply efficiency of a charger is improved.

In order to achieve the purpose, the invention provides the following scheme:

an NMOS pass switch control circuit comprising:

the device comprises an NMOS (N-channel metal oxide semiconductor) tube, a first low-voltage difference linear converter and a double-charge-pump voltage regulating circuit;

the drain electrode of the NMOS tube, the input end of the first low-voltage-difference linear converter, the first input end of the double-charge-pump voltage regulating circuit and the first output end of the double-charge-pump voltage regulating circuit are all connected with a power supply;

the output end of the first low-voltage difference linear converter is connected with the second input end of the double-charge-pump voltage regulating circuit;

the second output end of the double-charge-pump voltage regulating circuit is connected with the grid electrode of the NMOS tube;

and the source electrode of the NMOS tube is connected with the equipment to be charged.

Optionally, the dual-charge-pump voltage regulating circuit specifically includes:

the input detection circuit, the first stage charge pump and the second stage charge pump;

the input end of the input detection circuit is used as the first input end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

the output end of the input detection circuit is connected with the control end of the second-stage charge pump;

a first port of the second-stage charge pump is used as a second input end of the double-charge-pump voltage regulating circuit and is connected with the output end of the first low-voltage-difference linear converter;

the second port and the third port of the second-stage charge pump are both grounded;

the fourth port of the second-stage charge pump is connected with the third port of the first-stage charge pump;

a fourth port of the first-stage charge pump is used as a first output end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

and a second port of the first-stage charge pump is used as a second output end of the double-charge-pump voltage regulating circuit and is connected with the grid electrode of the NMOS tube.

Optionally, the dual-charge-pump voltage regulating circuit specifically includes:

the input detection circuit, the first stage charge pump, the second stage charge pump and the voltage clamping circuit;

the input end of the input detection circuit is used as the first input end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

the output end of the input detection circuit is connected with the control end of the second-stage charge pump;

the first port of the second-stage charge pump and the first port of the first-stage charge pump are both connected with the output end of the first low-dropout linear converter;

the second port and the third port of the second-stage charge pump are both grounded;

the fourth port of the second-stage charge pump is connected with the third port of the first-stage charge pump;

a fourth port of the first-stage charge pump is used as a first output end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

a second port of the first-stage charge pump is used as a second output end of the double-charge-pump voltage regulating circuit and is respectively connected with the grid electrode of the NMOS tube and the first end of the voltage clamping circuit; and the second end of the voltage clamping circuit is connected with the equipment to be charged.

Optionally, the voltage clamping circuit specifically includes: a Zener diode;

the cathode of the Zener diode and the first end of the voltage clamping circuit are respectively connected with the second port of the first-stage charge pump and the grid electrode of the NMOS tube;

the anode of the Zener diode is used as the second end of the voltage clamping circuit and is connected with the source electrode of the NMOS.

Optionally, the voltage clamping circuit specifically includes:

n PMOS tubes;

the grid electrode and the drain electrode of the ith PMOS tube are both connected with the source electrode of the (i + 1) th PMOS tube; 1, ·, n;

the source electrode of the 1 st PMOS tube is used as the first end of the voltage clamping circuit and is connected with the fourth port of the first-stage charge pump and the grid electrode of the NMOS switch; and the grid electrode and the drain electrode of the nth PMOS tube are connected and then are used as the second end of the voltage clamping circuit to be respectively connected with the source electrode of the NMOS switch.

Optionally, the input detection circuit specifically includes:

a first resistor, a second resistor and an operational amplifier;

the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the operational amplifier;

the second end of the first resistor is used as the input end of the input detection circuit and is connected with the power supply;

the second end of the second resistor is grounded;

a negative input end of the operational amplifier inputs a reference voltage; and the output end of the operational amplifier is used as the output end of the input detection circuit and is connected with the control end of the second-stage charge pump.

Optionally, the dual-charge-pump voltage regulating circuit specifically includes:

the input detection circuit, the second low-dropout linear converter, the first-stage charge pump and the second-stage charge pump;

the input end of the input detection circuit, the input end of the first low-dropout linear converter and the first input end of the second low-dropout linear converter are used as the first input end of the double-charge-pump voltage regulation circuit to be connected with a power supply;

the output end of the first low-dropout linear converter is connected with the control end of the first-stage charge pump;

the output end of the input detection circuit is respectively connected with the second input end of the second low dropout linear converter and the control end of the second-stage charge pump;

the output end of the second low dropout linear converter is connected with the first port of the second-stage charge pump;

the second port and the third port of the second-stage charge pump are both grounded;

the fourth port of the second-stage charge pump is connected with the third port of the first-stage charge pump;

a fourth port of the first-stage charge pump is used as a first output end of the double-charge-pump voltage regulating circuit and is connected with the power supply;

and a second port of the first-stage charge pump is used as a second output end of the double-charge-pump voltage regulating circuit and is connected with the grid electrode of the NMOS tube.

Optionally, the input detection circuit specifically includes:

a first resistor, a second resistor and an operational amplifier;

the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the operational amplifier;

the second end of the first resistor is used as the input end of the input detection circuit and is connected with the power supply;

the second end of the second resistor is grounded;

a negative input end of the operational amplifier inputs a reference voltage; and the output end of the operational amplifier is used as the output end of the input detection circuit and is connected with the control end of the second-stage charge pump and the second input end of the second low-dropout linear converter.

Optionally, the first stage charge pump and the second stage charge pump both include:

the first switch, the second switch, the third switch, the fourth switch and the flying capacitor;

the first end of the first switch and the first end of the second switch are both connected with the first end of the flying capacitor;

the first end of the third switch and the first end of the fourth switch are both connected with the second end of the flying capacitor;

the second end of the first switch is connected with the first port;

a second end of the second switch is connected with the second port;

a second end of the third switch is connected with the third port;

and the second end of the fourth switch is connected with the fourth port.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

the invention provides an NMOS pass switch control circuit, comprising: the device comprises an NMOS (N-channel metal oxide semiconductor) tube, a first low-voltage difference linear converter and a double-charge-pump voltage regulating circuit; the drain electrode of the NMOS tube, the input end of the first low-voltage-difference linear converter, the first input end of the double-charge-pump voltage regulating circuit and the first output end of the double-charge-pump voltage regulating circuit are connected with a power supply; the output end of the first low-voltage difference linear converter is connected with the second input end of the double-charge-pump voltage regulating circuit; the second output end of the double-charge-pump voltage regulating circuit is connected with the grid electrode of the NMOS tube; and the source electrode of the NMOS tube is connected with the equipment to be charged. The dual-charge-pump voltage regulating circuit can enable the NMOS tube to be normally conducted when the input voltage is lower than the grid-source voltage of the NMOS tube, and further improves the power supply efficiency of the charger.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a prior art NMOS pass switch control circuit;

FIG. 2 is a NMOS pass switch control circuit according to a first embodiment of the present invention;

FIG. 3 is a NMOS pass switch control circuit according to a second embodiment of the present invention;

fig. 4 is a first circuit diagram of a second low dropout linear converter in an embodiment of the present invention;

fig. 5 is a second circuit diagram of a second low dropout linear converter in an embodiment of the present invention;

FIG. 6 is a circuit diagram of a first stage charge pump according to an embodiment of the present invention; FIG. 6(a) is a diagram of a first stage charge pump switch control in an embodiment of the present invention; FIG. 6(b) is a circuit diagram of a first stage charge pump switch in an embodiment of the present invention;

FIG. 7 is a control circuit of an NMOS pass switch according to a third embodiment of the present invention;

FIG. 8 is a circuit diagram of an input detection circuit according to an embodiment of the present invention;

FIG. 9 is a diagram of a voltage clamp circuit according to a fourth embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention aims to provide an NMOS (N-channel metal oxide semiconductor) access switch control circuit, which can normally conduct an NMOS tube when the input voltage is lower than the grid-source voltage of the NMOS tube, so that the power supply efficiency of a charger is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Example one

Fig. 2 is a NMOS pass switch control circuit according to a first embodiment of the present invention, and as shown in fig. 2, the present embodiment provides an NMOS pass switch control circuit, including:

the device comprises an NMOS (N-channel metal oxide semiconductor) tube, a first low-voltage difference linear converter and a double-charge-pump voltage regulating circuit;

the drain electrode of the NMOS tube, the input end of the first low-voltage-difference linear converter, the first input end of the double-charge-pump voltage regulating circuit and the first output end of the double-charge-pump voltage regulating circuit are connected with a power supply;

the output end of the first low-voltage difference linear converter is connected with the second input end of the double-charge-pump voltage regulating circuit;

the second output end of the double-charge-pump voltage regulating circuit is connected with the grid electrode of the NMOS tube;

and the source electrode of the NMOS tube is connected with the equipment to be charged.

Wherein, the voltage regulating circuit of the double charge pump specifically includes:

the input detection circuit, the first stage charge pump and the second stage charge pump;

the input end of the input detection circuit is used as the first input end of the double-charge-pump voltage regulation circuit and is connected with a power supply;

the output end of the input detection circuit is connected with the control end of the second-stage charge pump;

the first port of the second-stage charge pump is used as the second input end of the double-charge-pump voltage regulating circuit and is connected with the output end of the first low-voltage-difference linear converter;

the second port and the third port of the second-stage charge pump are grounded;

the fourth port of the second-stage charge pump is connected with the third port of the first-stage charge pump;

the fourth port of the first-stage charge pump is used as the first output end of the double-charge-pump voltage regulating circuit and is connected with a power supply;

and a second port of the first-stage charge pump is used as a second output end of the double-charge-pump voltage regulating circuit and is connected with the grid electrode of the NMOS tube.

Fig. 8 is a diagram of an input detection circuit according to an embodiment of the present invention, and as shown in fig. 8, the input detection circuit according to the embodiment specifically includes:

a first resistor R₁A second resistor R₂And an operational amplifier;

the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the operational amplifier;

the second end of the first resistor is used as the input end of the input detection circuit and is connected with the power supply;

the second end of the second resistor is grounded;

a negative input end of the operational amplifier inputs a reference voltage; the output end of the operational amplifier is used as the output end of the input detection circuit and is connected with the control end of the second-stage charge pump.

The circuit structure of the first stage charge pump is shown in fig. 6; fig. 6(a) is a control diagram of a first stage charge pump switch in the embodiment of the present invention; FIG. 6(b) is a circuit diagram of a first stage charge pump switch in an embodiment of the present invention; first order charge pump and second level charge pump all include:

a first switch S1, a second switch S2, a third switch S3, a fourth switch S4 and a flying capacitor;

the first end of the first switch and the first end of the second switch are both connected with the first end of the flying capacitor;

the first end of the third switch and the first end of the fourth switch are both connected with the second end of the flying capacitor;

the second end of the first switch is connected with the first port;

the second end of the second switch is connected with the second port;

the second end of the third switch is connected with the third port;

the second end of the fourth switch is connected with the fourth port.

Specifically, with the method shown in fig. 2, on the basis of an NMOS switch control circuit formed by an existing charge pump and a low dropout linear converter LDO, an input detection circuit is added, and a second-stage charge pump is added at the same time. Assuming that the gate-source voltage of the normally-on NMOS is VGS_SET5V. When the input power detection circuit detects VIN>VGS_SETThen VIN can output VLDO ═ VGS through the low dropout linear converter LDO_SET(for example, 5V), the second stage charge pump is in a bypass mode, VLDO is directly supplied to the first stage charge pump, the access switch control circuit is equivalent to the prior gate driving circuit (figure 1), and the first stage charge pump pumps the gate voltage of the NMOS to VIN + VGS_SETTherefore, VGS ═ VGS_SET5V, the NMOS internal resistance is ensured to be reduced, and the path voltage drop is reduced.

When VIN is detected<VGS_SETWhen the output voltage of LDO is lower than VGS_SET(e.g., 5V) when the second stage charge pump is turned on, the second stage charge pump boosts the LDO output voltage VLDO to VGS_SETThe output is then fed to the first stage charge pump, which uses the output VGS of the second stage charge pump_SETPumping the NMOS gate voltage to VIN + VGS_SETThereby ensuring that the gate-source voltage VGS is VGS_SETEnsuring constant internal resistance without increasing.

Specifically, the first low dropout linear converter adopts a general LDO method.

Example two

Fig. 3 is an NMOS pass switch control circuit in a second embodiment of the present invention, and as shown in fig. 3, the difference between this embodiment and the first embodiment is that the dual charge pump voltage regulation circuit provided in this embodiment specifically includes:

the input detection circuit, the second low-dropout linear converter, the first-stage charge pump and the second-stage charge pump;

the input end of the input detection circuit, the input end of the first low-dropout linear converter and the first input end of the second low-dropout linear converter are used as the first input end of the double-charge-pump voltage regulation circuit to be connected with a power supply;

the output end of the first low-dropout linear converter is connected with the control end of the first-stage charge pump;

the output end of the input detection circuit is respectively connected with the second input end of the second low dropout linear converter and the control end of the second-stage charge pump;

the output end of the second low-dropout linear converter is connected with the first port of the second-stage charge pump;

the second port and the third port of the second-stage charge pump are grounded;

the fourth port of the second-stage charge pump is connected with the third port of the first-stage charge pump;

the fourth port of the first-stage charge pump is used as the first output end of the double-charge-pump voltage regulating circuit and is connected with a power supply;

and a second port of the first-stage charge pump is used as a second output end of the double-charge-pump voltage regulating circuit and is connected with the grid electrode of the NMOS tube.

The input detection circuit specifically includes:

a first resistor, a second resistor and an operational amplifier;

the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the operational amplifier;

the second end of the first resistor is used as the input end of the input detection circuit and is connected with the power supply;

the second end of the second resistor is grounded;

a negative input end of the operational amplifier inputs a reference voltage; the output end of the operational amplifier is used as the output end of the input detection circuit and is connected with the control end of the second-stage charge pump and the second input end of the second low-dropout linear converter.

In addition, the input detection circuit in this embodiment has the same structure as the first embodiment, and is different in that the output terminal of the operational amplifier in the input detection circuit of this embodiment is connected to the second input terminal of the second low dropout linear converter as the output terminal of the input detection circuit, in addition to the control terminal of the second stage charge pump.

Specifically, on the basis of an NMOS switch control circuit formed by an existing charge pump and an LDO, an input detection circuit is added, a second-stage charge is added, and an LDO2 (a second low dropout linear converter) is added, and the existing LDO is used as a first low dropout linear converter LDO1 for distinguishing. Assuming that the gate-source voltage of the normally-on NMOS is VGS_SET5V. When VIN is detected>VGS_SETWhen VIN passes through LDO1, VLDO1 ═ VGS can be output_SET(e.g., 5V), the second stage charge pump is turned off. VLDO1 is directly supplied to the first stage charge pump, and the gate voltage of NMOS is pumped to VIN + VGS by the first stage charge pump when the path switch control circuit is equivalent to the prior gate drive circuit (figure 1)_SETTherefore, VGS ═ VGS_SET5V, the NMOS internal resistance is ensured to be reduced, and the path voltage drop is reduced.

When VIN is detected<VGS_SETAt this time, since the LDO can only step down, the maximum voltage of the LDO1 can only output VIN, at this time, the LDO2 is turned on and outputs a voltage VLDO2 varying with the input power voltage VIN, where VLDO2 is VGS_SET-VIN. The second stage charge pump outputs a negative voltage-VLDO 2 ═ - (VG)_SSETVIN) to the negative input VINN (third port) of the first stage charge pump as ground potential of the first stage charge pump.

In the first phase, S1 and S3 of the first stage charge pump are closed, and S2 and S4 are open. The positive input VINP (control end) of the first stage charge pump is connected to the output of LDO1, i.e., input VIN. The negative input VINN is connected to the second stage charge pump output, i.e., - (VGS)_SET-VIN). The flying capacitor is thus charged to VGS_SET＝VIN+VLDO2。

In the second phase, S1 and S3 are open and S2 and S4 are closed. VOUTP (second port) is connected to the gate of NMOS pass switch, VOUTN (fourth port) is connected to VIN, since the voltage is maintained across the capacitorUnchanged, therefore VOUTP ═ VOUTN + VGS_SET＝VIN+VGS_SET. Therefore, voltage superposition can be realized, and the NMOS grid electrode is pumped to VIN + VGS_SET。

The basic principle of the second low dropout converter LDO2 of the present invention, referred to in fig. 3, is shown in fig. 4. the purpose of LDO2 is to generate an additional voltage, which is supplied to the second stage charge pump. When VIN is found<VGS_SETThe circuit starts to operate. The voltage difference detection circuit detects VIN and VGS_SETIs output simultaneously with a sum of VIN and VGS_SETAs a reference voltage of the subsequent LDO (LDO2), i.e., VR ═ K × (VGS) is proportional to the difference of (v ×)_SET-VIN). K is a proportionality coefficient, and the LDO of the later stage generates VLDO (very low density oxygen) from VIN (vinyl chloride) (VGS) according to VR_SET-VIN. The principle of LDO is well known and will not be described here.

FIG. 5 is a detailed description of FIG. 4, based on the principle of using an operational amplifier to convert VGS_SETConversion to one and VGS_SETThe proportional current is converted into a current source through a PMOS mirror imageIs applied to a resistor R to generate a sum VGS_SETA proportional voltage. Meanwhile, VIN is converted into a current proportional to VIN by another operational amplifier, and then the current is converted into a current by PMOS current mirror and primary NMOS current mirrorAnd then to the same resistor terminal as the current source Isource. Thus, a sum VGS can be generated on the resistor_SETVoltage VR, VIR ═ R × (Isource-Isink), i.e., VR ═ K × (VGS), proportional to the difference in VIN_SET-VIN). The VR is transmitted to the LDO of the later stage, and the later stage LDO amplifies the VR to 1/K times to obtain VLDO (very low density polyethylene) ═ VGS_SET-VIN。

EXAMPLE III

FIG. 7 is a control circuit of an NMOS pass switch according to a third embodiment of the present invention; the difference between the present embodiment and the first embodiment is that the dual charge pump voltage regulating circuit provided in the present embodiment specifically includes:

the input detection circuit, the first stage charge pump, the second stage charge pump and the voltage clamping circuit;

the input end of the input detection circuit is used as the first input end of the double-charge-pump voltage regulation circuit and is connected with a power supply;

the output end of the input detection circuit is connected with the control end of the second-stage charge pump;

the first port of the second-stage charge pump and the first port of the first-stage charge pump are both connected with the output end of the first low-dropout linear converter;

the second port and the third port of the second-stage charge pump are grounded;

the fourth port of the second-stage charge pump is connected with the third port of the first-stage charge pump;

the fourth port of the first-stage charge pump is used as the first output end of the double-charge-pump voltage regulating circuit and is connected with a power supply;

a second port of the first-stage charge pump is used as a second output end of the double-charge-pump voltage regulating circuit and is respectively connected with a grid electrode of the NMOS tube and a first end of the voltage clamping circuit; and the second end of the voltage clamping circuit is connected with the equipment to be charged.

The voltage clamping circuit specifically comprises: a Zener diode;

the first end of the cathode voltage clamping circuit of the Zener diode is respectively connected with the second port of the first-stage charge pump and the grid electrode of the NMOS tube;

the anode of the Zener diode is used as the second end of the voltage clamping circuit and is connected with the source electrode of the NMOS.

Further, the control scheme shown in fig. 3 can be simplified. As shown in fig. 7, a zener diode is added between the gate and the source of the NMOS, for example, to serve as a clamping circuit to ensure that the gate-source voltage is near VGSSET. Meanwhile, the LDO2 is removed, and the input of the charge pump of the second stage directly takes power from the LDO 1. 2 times VIN can be output through superposition of two stages of charge pumps, but since the Zener diode breaks down reversely, the NMOS grid-source voltage is clamped between the grid and the source of the NMOS, the Zener diode is added to serve as a clamping circuit to ensureGate source voltage at VGS_SETNearby.

The simplest way of voltage clamping is to use a zener diode, implemented with a zener diode reverse breakdown voltage. When the voltage applied to the two ends of the Zener diode exceeds the reverse breakdown voltage of the Zener diode, the Zener diode breaks down in the reverse direction, and the voltage drop of the two ends is clamped at the reverse breakdown voltage. Such as the zener diode shown in fig. 7, functions as an NMOS gate-source voltage clamp. In addition, the second stage charge pump can also output positive potential to the first stage charge pump, so that the VLDO1 and VLDO2 voltages are superposed. The specific method is also a variation of the aforementioned negative voltage superposition method, which is also a common practice in the industry and will not be described. Meanwhile, the charge pump has a plurality of structures, the control method is changeable, and the same function can be realized by slightly changing the control method. Modifications to the details of the charge pump circuit, or to the details of the LDO circuit, which are based on the present invention, are well within the scope of the basic underlying principles set forth in this disclosure.

Example four

Fig. 9 is a diagram of a voltage clamp circuit in a fourth embodiment of the present invention, and as shown in fig. 9, a difference between the first embodiment and the second embodiment is that the voltage clamp circuit provided in the present embodiment specifically includes:

the voltage clamping circuit specifically comprises:

n PMOS tubes;

the grid electrode and the drain electrode of the ith PMOS tube are both connected with the source electrode of the (i + 1) th PMOS tube; 1, ·, n;

the source electrode of the 1 st PMOS pipe M1 is used as the first end A of the voltage clamping circuit and is connected with the second port of the first-stage charge pump and the grid electrode of the NMOS switch; and the grid electrode and the drain electrode of the nth PMOS tube Mn are connected and then used as the second end B of the voltage clamping circuit to be respectively connected with the source electrode of the NMOS switch. As shown in fig. 9, a plurality of MOS transistors are connected in series to realize the clamping function of the NMOS gate-source voltage. The MOS tubes can be connected in series by NMOS or PMOS. In addition, the voltage clamping circuit can be realized by connecting a diode or a triode in series, and the realization methods are well known in the industry of voltage clamping circuits and are not described herein again.

FIG. 8 is an input voltage detectorAn implementation of a circuit. The input voltage is divided by two resistors, and then the divided voltage signal is connected to the positive input end of a comparator, and the negative input end of the comparator is connected to a reference voltage for comparison, so that whether the input voltage is higher than VGS or not is detected_SET. When VIN>VGS_SETWhen so, the comparator outputs a high signal. When VIN<VGS_SETWhen so, the comparator outputs a high signal. The voltage detection circuit is a well-known technology in the art, and has various implementation manners, which are not described herein again.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. Meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In summary, this summary should not be construed to limit the present invention.