阅读说明：本技术 具有内容可寻址存储器缓冲器的内容可寻址存储器系统 (Content addressable memory system with content addressable memory buffer ) 是由 A·D·艾卡尔 S·S·艾勒特 于 2020-04-01 设计创作，主要内容包括：本公开揭示一种设备(例如,内容可寻址存储器系统),所述设备可具有控制器；第一内容可寻址存储器,其耦合到所述控制器；及第二内容可寻址存储器,其耦合到所述控制器。所述控制器可经配置以致使所述第一内容可寻址存储器将输入数据与存储在所述第一内容可寻址存储器中的第一数据进行比较,且致使所述第二内容可寻址存储器将所述输入数据与存储在所述第二内容可寻址存储器中的第二数据进行比较,使得同时将所述输入数据与所述第一及第二数据进行比较；及响应于确定所述第一数据为无效的且所述第二数据对应于所述第一数据,将所述输入数据与所述第一数据的所述比较的结果替换为所述输入数据与所述第二数据的所述比较的结果。(An apparatus (e.g., a content addressable memory system) may have a controller; a first content addressable memory coupled to the controller; and a second content addressable memory coupled to the controller. The controller may be configured to cause the first content addressable memory to compare input data with first data stored in the first content addressable memory and to cause the second content addressable memory to compare the input data with second data stored in the second content addressable memory such that the input data is compared with the first and second data simultaneously; and in response to determining that the first data is invalid and the second data corresponds to the first data, replacing a result of the comparison of the input data with the first data with a result of the comparison of the input data with the second data.)

1. An apparatus, comprising:

a controller;

a first content addressable memory coupled to the controller; and

a second content addressable memory coupled to the controller;

wherein the controller is configured to:

causing the first content addressable memory to compare input data to first data stored in the first content addressable memory and causing the second content addressable memory to compare the input data to second data stored in the second content addressable memory such that the input data is compared to the first and second data simultaneously; and

in response to determining that the first data is invalid and the second data corresponds to the first data, replacing a result of the comparison of the input data with the first data with a result of the comparison of the input data with the second data.

2. The apparatus of claim 1, wherein the controller is configured to determine that the first data is invalid by determining that an elapsed time from a time of writing the first data to the first content addressable memory to a time of comparing the input data to first data is less than a threshold length of time for the first data.

3. The apparatus of claim 2, wherein the threshold length of time is an elapsed time from a time the first data is written to the first content addressable memory to a time the first data becomes valid.

4. The apparatus of claim 1, wherein the second content addressable memory comprises volatile memory cells and the first content addressable memory comprises non-volatile memory cells.

5. The apparatus of claim 1, wherein the first data is stored in resistance variable memory cells in the first content addressable memory and the second data is stored in static random access memory cells in the second content addressable memory.

6. The apparatus of claim 1, wherein the controller is configured to:

storing a map that maps locations in the first content addressable memory that store the first data to locations in the second content addressable memory that store the second data; and

invalidating the mapping in response to determining that the first data is valid.

7. The apparatus of claim 1, wherein the controller is configured to remove the second data from the second content addressable memory in response to determining that the first data is valid.

8. The apparatus of any of claims 1-7, wherein the controller is configured to, in response to determining that the first data is invalid and the second data corresponds to the first data, replace a bit value indicating whether the first data matches the input data with a bit value indicating whether the second data matches the input data.

9. The apparatus of any of claims 1-7, wherein the controller is configured to:

causing the first content addressable memory to compare the input data to additional data in the first content addressable memory while comparing the input data to the first data; and

in response to determining that the additional data is valid, combining a result of the comparison of the input data with the additional data with the result of the comparison of the input data with the second data.

10. An apparatus, comprising:

a controller;

a primary content addressable memory coupled to the controller and comprising non-volatile memory cells that drift after being programmed; and

a buffered content addressable memory coupled to the controller and comprising volatile memory cells; wherein the controller is configured to:

causing the primary content addressable memory to program the non-volatile memory cells and the buffer content addressable memory to simultaneously program the volatile memory cells with data;

causing the primary content addressable memory to compare input data to the data programmed in the non-volatile memory cells and causing the buffer content addressable memory to compare the input data to the data programmed in the volatile memory cells; and

in response to determining that the comparison of the input data to the data stored in the non-volatile memory cells is invalid, replacing the comparison of the input data to the data stored in the non-volatile memory cells with the comparison of the input data to the data stored in the volatile memory cells.

11. The apparatus of claim 10, wherein the non-volatile memory cell comprises a chalcogenide-based storage element, wherein the volatile memory cell comprises a static random access memory cell, and wherein the controller is configured to use the comparison of the input data and the data stored in the non-volatile memory cell in response to determining that the comparison of the input data and the data stored in the non-volatile memory cell is valid.

12. The apparatus of claim 10, wherein the controller is configured to:

managing a data structure comprising entries comprising a map that maps locations of the non-volatile memory units in the primary content addressable memory to locations of the volatile memory units in the buffer content addressable memory; and

writing a timestamp in the entry, wherein the timestamp comprises a time that the non-volatile memory cell was programmed with the data.

13. The apparatus of claim 12, wherein the controller is configured to:

responsive to determining that the mapping is the oldest mapping in the data structure, overwriting the mapping with an additional mapping; and

in response to overwriting the mapping with the additional mapping, using the comparison of the input data with the data stored in the non-volatile memory cells.

14. The apparatus of claim 12, wherein the controller is configured to write a timestamp in the entry,

wherein the time stamp comprises a time at which the non-volatile memory cell was programmed with the data; and is

The controller is configured to determine that the comparison of the input data to the data stored in the non-volatile memory cells is invalid by determining that an elapsed time from the time in the timestamp to the time of the comparison of the input data to the data programmed in the non-volatile memory cells is less than a threshold length of time.

15. The apparatus of claim 14, wherein the controller is configured to determine that the non-volatile memory cell is invalid by determining that a time of the comparison of the input data to the data programmed in the non-volatile memory cell is earlier than the time in the timestamp.

16. The apparatus of claim 12, wherein the controller is configured to invalidate the entry mapping the location of the non-volatile memory cell in the primary content addressable memory to the location of the volatile memory cell in the buffer content addressable memory in response to determining that the comparison of the input data to the data stored in the non-volatile memory cell is valid.

17. The apparatus of any one of claims 10-16, wherein the controller is configured to, in response to determining that the buffered content addressable memory is full, simultaneously delay programming the non-volatile memory cells and the volatile memory cells with data until previously stored data in the volatile memory cells is removed from the volatile memory cells.

18. The apparatus of any one of claims 10-16, wherein the controller is configured to determine that the comparison of the input data to the data stored in the non-volatile memory cells is less effective in response to:

reading the data from a non-volatile memory cell;

comparing the read data to data intended to be programmed in the non-volatile memory cells; and

determining that the read data does not match the data intended to be programmed in the non-volatile memory cell.

19. A method, comprising:

comparing an input data vector with a plurality of first data vectors stored in a first content addressable memory to obtain a respective first comparison result for each of the first data vectors of the plurality of first data vectors;

comparing the input data vector with a second data vector stored in a second content addressable memory while comparing the input data vector with the plurality of first data vectors to obtain a second comparison result for the second data vector; and

in response to determining that the particular first data vector corresponds to the second data vector and that the particular first data vector is invalid, replacing the respective first comparison result for a particular first data vector of the plurality of first data vectors with the second comparison result.

20. The method of claim 19, further comprising determining that the particular first data vector corresponds to the second data vector and the particular first data vector is invalid according to an entry in a data structure that corresponds to an address of the particular first data vector and that maps the address of the particular first data vector to an address of the second data vector.

21. The method of claim 19, further comprising:

writing the respective first comparison result for each of the first data vectors as a respective component of a first result vector; and

writing the second comparison result of the second data vector as a component of a second result vector;

wherein replacing the respective first comparison result of the particular first data vector with the second comparison result of the second data vector comprises mapping the respective component of the first result vector that is the respective first comparison result of the particular first data vector to the component of the second result vector that is the second comparison result of second data vector.

22. The method of claim 19, further comprising:

linking a physical address of the particular first data vector to the comparison result of the particular first data vector; and

linking a physical address of the second data vector to the second comparison result for the second data vector;

wherein replacing the respective first comparison result of the particular first data vector with the second comparison result comprises mapping the physical address of the particular first data vector to the physical address of the second data vector;

mapping the physical address of the particular first data vector mapped to the physical address of the second data vector to a logical address; linking the logical address to the second comparison result; and

sending the second comparison result linked to the logical address to a host only if the second comparison result indicates that the second data vector matches the input data vector.

23. The method of any one of claims 19-22, further comprising:

responsive to determining that the second data vector is the oldest data vector in the second content addressable memory, overwriting the second data vector in the second content addressable memory with an additional data vector; and in response to overwriting said second data vector in said second content addressable memory with said additional data vector, using said respective first comparison result for said particular first data vector.

Technical Field

The present disclosure relates generally to content addressable memories, and more particularly, to content addressable memory systems having content addressable memory buffers.

Background

The memory system may be implemented in an electronic system such as a computer, cell phone, handheld electronic device, etc. Some memory systems, such as Solid State Disks (SSDs), embedded multimedia controller (eMMC) devices, Universal Flash Storage (UFS) devices, etc., may include non-volatile storage memory for storing host (e.g., user) data from a host. Non-volatile storage memory can provide persistent data by retaining stored data when not powered, and can include nand flash memory, nor flash memory, Read Only Memory (ROM), electrically erasable programmable ROM (eeprom), erasable programmable ROM (eprom), and resistance variable memory, such as Phase Change Random Access Memory (PCRAM), three-dimensional cross-point memory (e.g., 3D XPoint), Resistive Random Access Memory (RRAM), ferroelectric random access memory (FeRAM), Magnetoresistive Random Access Memory (MRAM), and programmable conductive memory, among other types of memory.

Some memory cells, such as various resistance variable memory cells, may be arranged in a cross-point architecture such that the memory cells are located at the intersection of signal lines for accessing the cells (e.g., located at word lines and bit lines). For example, the state (e.g., stored data value) of a resistance variable memory cell may depend on the programmed resistance of the memory cell.

In some examples, the resistance of a memory cell can be programmed to a low threshold voltage (Vt) state (e.g., a "set" state) or a high Vt state (e.g., a "reset" state). The state of (e.g., the data value stored by) a resistance variable memory cell may be determined by determining whether the cell changes its conductive state (e.g., experiences a switching event), e.g., in response to applying (e.g., crossing) a sensing voltage (which may be referred to as a read voltage or a demarcation voltage) to the cell. For example, the demarcation voltage can be selected to be at a margin between the Vt corresponding to the reset state (e.g., Vt distribution) and the Vt corresponding to the set state (e.g., Vt distribution).

The memory typically returns user data to the host in response to an address supplied by the host (e.g., during a read operation). Another form of memory is a Content Addressable Memory (CAM), also known as an associative mode memory (APM). In some examples, the CAM may receive input data (e.g., a vector of input data) and may perform a search to determine whether the input data is stored in the CAM. For example, the CAM may determine whether stored data (e.g., a stored data vector) in the CAM matches the input data.

The CAM may be used as a hardware-based search device in applications requiring fast searches or pattern matching, such as in computer systems, databases, image or voice recognition, biometric recognition, data compression, cache controllers, or computer and communication networks (e.g., in network switches, media access controllers, network routers, etc.).

Drawings

Fig. 1A is a simplified block diagram of an apparatus according to various embodiments of the present disclosure.

FIG. 1B illustrates an example of threshold voltage distributions of non-volatile memory cells immediately after programming in accordance with various embodiments of the present disclosure.

FIG. 1C illustrates another example of threshold voltage distributions of non-volatile memory cells immediately after programming in accordance with multiple embodiments of the present disclosure.

FIG. 1D illustrates an example of threshold voltage distributions of non-volatile memory cells after a threshold length of time after programming in accordance with multiple embodiments of the present disclosure.

Fig. 1E illustrates an example of a data structure in accordance with various embodiments of the present disclosure.

Fig. 2 is a simplified block diagram of a content addressable memory according to multiple embodiments of the present disclosure.

Fig. 3 illustrates a result vector received at a controller in accordance with various embodiments of the present disclosure.

Fig. 4 illustrates a portion of a non-volatile content addressable memory in accordance with multiple embodiments of the present disclosure.

Fig. 5 illustrates an example of comparing input data with data stored in a non-volatile content addressable memory, in accordance with various embodiments of the present disclosure.

Detailed Description

In various cases, non-volatile memory may be used as the CAM. Providing a non-volatile memory CAM may have various benefits over a volatile CAM (e.g., an SRAM CAM). For example, non-volatile CAMs do not require power to maintain their data, and non-volatile memory cells generally have a smaller footprint than volatile memory cells, and thus can provide greater storage density. However, volatile CAMs can generally provide faster access times (e.g., read/write times) than non-volatile CAMs.

In some cases, data stored in some resistance variable memory cells (e.g., chalcogenide-based memory cells) may not be valid (e.g., reliable) immediately after the memory cell is programmed (e.g., written). As such, such memory cells may not be reliably read immediately after they are programmed. For example, as discussed further herein, it may be desirable to allow such memory cells to drift for a threshold length of time (e.g., on the order of one millisecond) after they are programmed before they can be reliably read, and thus the data stored by the memory cells is valid. Thus, the speed at which a CAM employing such resistance variable memory cells can be accessed may be limited by the length of the threshold time.

As further described herein, various embodiments of the present disclosure provide CAM implementations that can account for the fact that data written in some resistance variable non-volatile memory cells can be invalid immediately after the data is written. Thus, embodiments may provide, among other benefits, a non-volatile CAM with improved access times compared to previous approaches. As an example, embodiments may employ a non-volatile first CAM as the main CAM and a second CAM as the buffer CAM, such as a volatile CAM (e.g., SRAM buffer CAM). For example, data stored in such volatile CAMs can be valid once the data is written, and thus the data can be reliably compared to the input data once the data is written.

In some examples, the input data may be compared to the data stored in the main CAM and the data stored in the buffer CAM simultaneously. In response to determining that the data stored in the main CAM is invalid (unreliable), for example, in response to determining that the result of the comparison of the input data with the data in the main CAM is invalid, the result of the comparison of the input data with the data in the main CAM may be replaced with the result of the comparison of the input data with the data in the buffer CAM. For example, the data in the main CAM and the result of the comparison of the input data with the data in the main CAM may be invalid when an elapsed time from the time the data is written in the first content addressable memory to the time the input data is compared with the data in the first content addressable memory is less than a threshold length of time. It should be noted that the threshold length of time may be, for example, an elapsed time from the time the data is written in the first content addressable memory to the time the data in the master CAM becomes valid and thus the result of the comparison of the input data with the data written in the first content addressable memory becomes valid. A buffered CAM in combination with a primary non-volatile CAM can eliminate delays associated with waiting until the results of a comparison of input data to data in the non-volatile CAM are valid, for example.

Using a buffered CAM buffer in conjunction with the main non-volatile CAM may reduce the energy requirements, cost, and time taken to obtain reliable comparison results as compared to using a DRAM buffer or table as a buffer in conjunction with the main CAM. For example, using a DRAM or table may involve a time consuming process of scanning the entire contents of the DRAM or table to identify data corresponding to the data in the master CAM that is being compared to the input data.

Fig. 1A is a simplified block diagram of an apparatus in the form of a computing system 100 in accordance with multiple embodiments of the present disclosure. Computing system 100 includes an apparatus in the form of a CAM system 102, which may be, for example, a peripheral component interconnect express (PCIe) CAM system.

CAM system 102 may include a controller 104, CAMs 106-1 through 106-8 coupled to controller 104 by a bus 108, and CAMs 110-1 and 110-2 coupled to controller 104. Although eight CAMs 106 and two CAMs 110 are shown, there may be any number of CAMs 106 and CAMs 110. In some examples, CAM106 may be referred to as a master (e.g., primary) CAM, and CAM110 may be referred to as a buffer CAM (e.g., because CAM110 may act as a buffer for CAM 106). In some examples, there may be a single master CAM106 that may include CAMs 106-1 through 106-8, and there may be a single buffer CAM110 that may include CAMs 110-1 and 110-2. Herein, "CAM 106" and/or "master CAM" will be used to refer to one or more of CAMs 106-1 through 106-8, and "CAM 110" and/or "buffer CAM" will be used to refer to one or more of CAMs 110-1 and 110-2.

The controller 104 may cause the CAM106 to compare input data, such as an input data vector (e.g., from the host 103), with stored data, such as a stored data vector, stored in the CAM106, and may cause the CAM110 to compare the input data with data stored in the CAM110, such that the input data is simultaneously compared with the data stored in the CAMs 106 and 110. The controller 104 may replace the result of the comparison of the input data with the data stored in the CAM106 with the result of the comparison of the input data with the data stored in the CAM110 in response to determining that the data stored in the CAM106 is invalid, and thus determining that the result of the comparison of the input data with the data stored in the CAM106 is invalid, and, for example, determining that the data stored in the CAM110 corresponds to the data stored in the CAM 106.

The controller 104 may determine that the data stored in the CAM106 is invalid by determining that an elapsed time from the time the data is written in the CAM106 to the time the input data is compared to the data in the CAM106 is less than a threshold length of time. It should be noted that the threshold time length may be, for example, an elapsed time from the time data is written in the CAM106 to the time data written in the CAM106 becomes valid.

In some examples, the CAM106 may be a non-volatile CAM and the CAM110 may be a volatile CAM, such as an SRAM CAM. For example, the data stored in the CAM110 may be stored in SRAM memory cells, and the data stored in the CAM106 may be stored in non-volatile memory cells. For example, data stored in the CAM106 may drift from the time the data is programmed in the CAM 106. In some examples, CAM106 may be a cross-point device, such as a 3D XPoint device, which may include memory cells that may drift, such as resistance variable memory cells.

In various examples, the controller 104 may include match verification circuitry that may be used to verify a match between an input data vector and a data vector stored in a buffer CAM (e.g., CAM 110) or a main CAM (e.g., CAM 106). For example, in response to receiving an indication that an input data vector matches a stored data vector, match verification circuitry may cause the buffer CAM or the main CAM to read the stored data vector and return the data vector read from the buffer CAM or the main CAM to the controller 104. The match verification circuitry may then compare the returned data vector with the input data vector to determine whether the previously indicated match was valid.

In some examples, the master CAM and the buffer CAM may include match-verification circuitry that may be used to verify matches between input data vectors and stored vectors. For example, in response to an input data vector matching a stored data vector, match verification circuitry may read the stored data vector and compare the read data vector to the input data vector to determine whether a previous indication match was valid. If the match is invalid, the match verification circuitry may change the result of the comparison from a match to a mismatch and send the result to the controller 104. In various instances where match verification circuitry in the master CAM determines that a match between the input data and the stored data vector is invalid, the controller 104 may increase the threshold length of time.

Figure 1B illustrates an example of Vt distributions of non-volatile memory cells immediately after programming (writing), in accordance with multiple embodiments of the present disclosure. Figure 1C illustrates another example of Vt distributions of non-volatile memory cells immediately after programming, according to multiple embodiments of the present disclosure. FIG. 1D illustrates an example of Vt distributions of non-volatile memory cells after a threshold length of time after programming in accordance with multiple embodiments of the present disclosure.

In the example of fig. 1B-1D, Vt distribution 105 can be referred to as a set state and Vt distribution 107 can be referred to as a reset state. In the example of fig. 1B-1D, Vt distribution 105 corresponds to memory cells programmed to store a data value of a logic 1, and Vt distribution 107 corresponds to memory cells programmed to store a data value of a logic 0. However, embodiments are not limited to this assignment encoding. Note that the examples of FIGS. 1B-1D depict programming memory cells from a set state to a reset state.

In the example of fig. 1B-1D, edge voltage E1 can be defined as the Vt corresponding to the upper edge of distribution 105, and edge voltage E2 can be defined as the Vt corresponding to the lower edge of distribution 107. The tolerance (e.g., window) W is the difference between E2 and E1. For example, W ═ E2-E1. In the example of fig. 1B-1D, VDM represents a demarcation voltage that can be used to determine a stored state (e.g., a data value stored thereby) of a memory cell (e.g., "1" or "0"). In some examples, a VDM may correspond to an input data value to be compared to a data value stored by a memory cell. The demarcation voltage VDM can be selected to be within the margin W, as shown in fig. 1D.

In some cases, when various non-volatile memory cells, such as some resistance variable memory cells, are programmed from a set state to, for example, a reset state, the data in the memory cells may not be valid immediately after programming because the margin W may not be sufficient for the VDM to reliably distinguish the set state from the reset state immediately after programming, as shown in fig. 1B and 1C.

In some cases, immediately after programming, margin W may be too small for VDM to be in margin W, as shown in fig. 1B. For example, the VDM is outside the margin W and inside the Vt distribution 107. In some cases, the Vt distributions corresponding to the set and reset states can actually overlap, as shown in FIG. 1C. For example, margin W in fig. 1C is negative because the edge voltage E1 is greater than the edge voltage E2. Note that as in the example of FIG. 1B, VDM is located inside Vt distribution 107 in FIG. 1C.

Applying a VDM to the memory cells immediately after programming, as shown in fig. 1B and 1C, may produce an invalid result. In the example of fig. 1B and 1C, for example, in response to applying VDM, memory cells in the distribution 107 having a Vt less than VDM can be determined to store a data value of 1, and memory cells in the Vt distribution 107 having a Vt greater than VDM can be determined to store a data value of 0. As such, the data stored in the memory cells in fig. 1B and 1C may be invalid.

However, for example, the Vt of some resistance variable memory cells may drift (e.g., to a higher absolute value) over time after they are programmed to the reset state. As the Vt drifts, the reset Vt distribution can move away from the set Vt distribution, as indicated by the arrows in FIGS. 1B and 1C, increasing the margin W. When the margin W has increased to the point where the demarcation voltage is located in the margin rather than in the Vt distribution 105 or the Vt distribution 107, as shown in fig. 1D, the result of reading the memory cell with the VDM, for example, may be (e.g., determined to be) valid. As such, the data stored in the memory cells in fig. 1D may be valid. For example, comparisons of input data having data values corresponding to the VDM with data stored in the memory cells, and thus the results of these comparisons, may be determined to be valid for the case depicted in fig. 1D, but not for the cases depicted in fig. 1B and 1C.

In some examples, the elapsed time from the time (e.g., when) the memory cell was programmed to when the data stored in the memory cell became valid may be the threshold length of time referred to herein. For example, FIG. 1D may correspond to an elapsed time from when the memory cell was programmed, which may be greater than or equal to a threshold length of time. For example, the time at which a memory cell (e.g., a data vector) is programmed can be the time at which a program voltage is applied to or removed from the memory cell. In some examples, the threshold length of time may be about one millisecond.

The data stored in the non-volatile memory cells may be invalid for an elapsed time from the time of writing the data that is less than a threshold length of time and may be valid for an elapsed time from the time of writing the data that is greater than or equal to the threshold length of time. As such, in some examples, the comparisons of input data with data stored in non-volatile memory cells, and thus the results of those comparisons, may be determined to be invalid for an elapsed time from the time of writing the data to the time of comparing the input data with the data that is less than a threshold length of time, and valid for an elapsed time from the time of writing the data to the time of comparing the input data with the data that is greater than or equal to the threshold length of time.

In the example of fig. 1B-1D, the Vt and VDM corresponding to the set and reset states are positive, with the Vt corresponding to the reset state being greater in the positive sense than the Vt corresponding to the set state and the drift acting to increase Vt in the positive sense. However, the Vt and VDM corresponding to the set and reset states can be negative, where the Vt corresponding to the reset state is greater in the negative sense than the Vt corresponding to the set state and the drift acts to increase the Vt in the negative sense.

For at least the reasons just described, the comparison between the input data and the data stored in the memory cells in the CAM106 may be invalid at least for less than a threshold length of time. However, the data stored in the CAM110 may be valid as soon as it is written. This is why the result of comparing the input data with the data stored in the CAM106 may be replaced with the result of comparing the input data with the data stored in the CAM110 during the threshold time length when the data in the CAM106 is invalid.

In some examples, the controller 104 may determine whether the data stored in the CAM10 is valid by reading the data from the CAM106, comparing the read data to the data intended to be programmed in the CAM106, e.g., by comparing the read data to corresponding data in the CAM110, and determining whether the read data matches the data intended to be programmed in the non-volatile memory cells. For example, the controller 104 may determine that the read data is valid in response to determining that the read data matches data intended to be programmed in the CAM106, and may determine that the read data is invalid in response to determining that the read data does not match data intended to be programmed in the CAM 106. Note that the controller 104 may determine that the comparison of the input data to the data stored in the CAM106 is valid by determining that the data stored in the CAM106 is valid and that the comparison of the input data to the data stored in the CAM106 is invalid by determining that the data stored in the CAM106 is invalid.

In some examples, the controller 104 may determine whether the result of the comparison of the input data vector with the data vector in the CAM106 and the result of the comparison of the input data vector with the data vector in the CAM110 corresponding to the data vector in the CAM106 are valid, and thus determine whether the data vector in the CAM106 is valid. If the results match, the result of the comparison of the input data vector with the data vector in the CAM106, and thus the data vector in the CAM106, is valid. If the results are mismatched, the result of the comparison of the input data vector with the data vector in the CAM106 is invalid, and thus the data vector in the CAM106 is invalid.

In some examples, the controller 104 may cause the main CAM106 to write the data vector in the main CAM106 and the buffer CAM110 simultaneously. The controller 104 may create a data structure, such as a lookup (e.g., mapping) table 112 (e.g., in the controller 104) whenever a data vector is written in the main CAM and the buffer CAM simultaneously (e.g., in response to writing the data vector in the main CAM and the buffer CAM simultaneously). In some examples, the controller 104 may manage the lookup table 112.

Fig. 1E illustrates an example of a data structure in the form of a lookup table 112 in accordance with various embodiments of the present disclosure. The lookup table 112 may include (e.g., an ordered sequence of) entries 114-1 through 114-N that may be used to map locations (e.g., location addresses) of data vectors in the main CAM to locations (e.g., location addresses) of corresponding data vectors in the buffer CAM during a period in which the data vectors in the main CAM are invalid.

For example, the locations of the groups of memory cells in the master CAM storing the data vector may be mapped to the locations of the groups of memory cells in the buffer CAM storing the data vector. The entries 114 may include the location addresses (e.g., addresses) of the data vectors in the main CAM, the addresses of the data vectors in the main CAM to be mapped to the addresses of the corresponding data vectors in the buffer CAM, and timestamps corresponding to the data vectors in the main CAM specified in the entries 114. It should be noted that the addresses of the data vectors in the main CAM and the buffer CAM may be referred to as physical addresses.

The timestamp may be the time that the data vector was programmed to the primary CAM address specified in entry 114. The controller 104 may manage the lookup table 112, for example, by writing the address of the data vector in the main CAM, the address of the data vector in the buffer CAM, and the time the data vector was programmed in the main CAM in the entry 114.

In some examples, the storage space in the buffer CAM may be sufficient to store all data vectors written to the buffer CAM and the main CAM simultaneously. However, if the number of data vectors to be written in the main CAM exceeds the storage space in the buffer CAM, the simultaneous writing of data vectors in the main CAM and the buffer CAM may be delayed until space in the buffer CAM becomes available. For example, in response to determining that the buffer CAM is full, the controller 104 may delay the concurrent writes until a data vector previously stored in the buffer CAM is removed from the buffer CAM. In response to determining that the previously stored data vector no longer corresponds to an invalid data vector in the main CAM, the controller 104 may cause the buffer CAM to remove the previously stored data vector from the buffer CAM.

The controller 104 may use the lookup table 112 to determine whether the data vectors in the main CAM and the buffer CAM that are simultaneously compared to the input vector correspond to each other. In response to the main CAM and the buffer CAM simultaneously comparing the input data vector with the data vectors in the main CAM and the buffer CAM, the controller 104 may determine whether an entry corresponding to the address of the data vector in the main CAM exists in the lookup table 112. If no entry exists, the controller 104 may determine that the data vector in the main CAM does not correspond to the data vector in the buffer CAM and/or that the data vector in the main CAM is valid; for example, the result of the comparison of the data vector in the main CAM with the input data vector is valid. Thus, the controller 104 may use the results of the comparison of the input data vector with the data vector in the primary CAM.

If an entry 114 in the lookup table 112 exists that corresponds to the address of the data vector in the main CAM, the controller 104 may determine that the data vector in the main CAM corresponds to the data vector with the address in the buffer CAM in that entry 114, and may determine whether the data vector in the main CAM is valid according to the timestamp in that entry 114.

For example, the controller 104 may determine an elapsed time from the time specified in the timestamp to the time of the comparison. If the elapsed time is less than the threshold length of time, the data vector in the main CAM is invalid (e.g., for comparison), and the data vector address in the main CAM is mapped to the address of the data vector in the buffer CAM. For example, in response to determining that the data vector in the main CAM is invalid, the result of the comparison of the input data vector with the data vector in the buffer CAM may be used instead of the result of the comparison of the input data vector with the data vector in the main CAM.

If the elapsed time is greater than or equal to the threshold length of time, the data vector in the master CAM is valid. In some examples, in response to determining that the data vector having the address specified in the entry is valid, the controller 104 may remove the entry from the lookup table 112 and thus invalidate the address mapping in the entry. For example, the data vectors in the buffer CAM corresponding to the data vectors in the main CAM determined to be valid may be removed from the buffer CAM in response to determining that the data vectors in the main CAM are valid. It should be noted that the threshold length of time may be predetermined and stored in the controller 104, for example.

In some instances, the timestamp may be the time at which the data vector in the master CAM becomes (e.g., is deemed to become) valid. For example, the controller 104 may add a threshold length of time to the time at which the data vector was programmed in the main CAM address specified in the entry 114 to obtain a timestamp. The controller 104 may compare the time of accessing the entry to the timestamp. If the time is earlier than (e.g., less than) the timestamp, the data vector in the main CAM corresponding to the entry is invalid. If the time is later than (e.g., greater than) or equal to the timestamp, then the data vector is valid.

Although the lookup table 112 in fig. 1E includes a timestamp, embodiments are not so limited and, for example, the timestamp may be omitted. For embodiments that omit timestamps, the number of entries in the lookup table 112 may correspond to the number of data vectors that the main CAM may write in the threshold length of time. For example, whenever the buffer CAM and the main CAM write a data vector simultaneously, the respective mappings may be written in the respective entries such that all N entries contain a mapping in the threshold length of time, and thus the lookup table 112 is populated in the threshold length of time. This means that each mapping corresponds to a vector of data written in the main CAM for a threshold length of time, such that each mapping corresponds to an invalid vector of data in the main CAM.

In some examples, the lookup table 112 may be written in a round robin fashion (e.g., using a first-in-first-out (FIFO) method). For example, when the lookup table 112 is full, existing mappings may be overwritten with new mappings in the order in which the existing mappings were written, such that the oldest mapping is overwritten first (e.g., invalidated (removed)), and so on. For example, because the N mappings in the lookup table 112 correspond to N data vectors written in the main CAM in a threshold length of time, the earliest mapping may be stored in the lookup table 112 for at least the threshold length of time, and thus may be overwritten when the corresponding data vector in the main CAM is valid.

Thus, each mapping may be overwritten when the corresponding data vector in its primary CAM is valid. Accordingly, the controller 104 may determine that the data vector in the main CAM is invalid in response to finding a corresponding mapping in the lookup table 112 that has no timestamps. For example, the controller 104 may use a mapping to replace the results of the comparison of the input data vector with the data vectors in the main CAM with the results of the comparison of the input data vector with the data vectors in the buffer CAM. The controller 104 may also use the results of the comparison of the input data vectors to the various data vectors in the primary CAM that the lookup table 112 does not have a mapping, as those data vectors may be valid. For example, in response to overwriting the map with the new map, the controller 104 may use a comparison of the input data vector with the data vector stored in the master CAM corresponding to the overwritten map.

The buffer CAM may be sized to store an amount of the data vector corresponding to the data vector that may be writable in the main CAM for a threshold length of time such that the buffer CAM is populated with the data vector for the threshold length of time. This means that each data vector in the buffer CAM corresponds to an invalid data vector in the main CAM.

In some examples, the buffered CAM may be written in a round robin fashion similar to that described in connection with the lookup table 112. For example, when the buffer CAM is full, existing data vectors may be overwritten with new data vectors in the order in which they were written, such that the oldest data vector in the buffer CAM is overwritten (e.g., removed) first, and so on. For example, because data instances are written in the main CAM and the buffer CAM simultaneously for a threshold length of time, the oldest data vector may be stored in the buffer CAM for at least the threshold length of time, and thus may be overwritten when the corresponding data vector in the main CAM is valid.

The controller 104 may replace the results of the comparison of the input data vector with the data vectors in the main CAM with the results of the comparison of the input data vector with the corresponding data vectors in the buffer CAM, as long as the corresponding vectors are in the buffer CAM. The controller 104 may also use the results of the comparison of the input data vectors with various data vectors in the main CAM that are not in the buffer CAM, as these data vectors may be valid. For example, in response to overwriting a corresponding data vector in the buffer CAM with a new data vector, the controller 104 may use a comparison of the input data vector with the data vector stored in the main CAM.

In some examples, the controller 104 may include a logical-to-physical (L2P) mapping table that may map logical addresses of data vectors received from the host 103 to physical addresses of data vectors in the master CAM.

The controller 104 may be a Field Programmable Gate Array (FPGA) and/or an Application Specific Integrated Circuit (ASIC), among other types of controllers. The host 103 may be, for example, a host system such as a personal laptop computer, desktop computer, digital camera, mobile device (e.g., cell phone), web server, internet of things (IoT) enabled device, or memory card reader, among various other types of hosts. For example, the host 103 may include one or more processors capable of accessing the CAM system 102 (e.g., via the controller 104) through an interface 116, which may include a bus. The interface 116 may be a standardized interface such as serial advanced technology bus attachment (SATA), PCIe, or Universal Serial Bus (USB), among various other interfaces.

In some examples, CAM system 102 may be part of a memory system of computing system 100. For example, the memory system may be a storage system, such as an SSD, a UFS device, an eMMC device, or the like. In various examples in which the CAM system 102 may be part of a memory system, the controller 104 may be part of (e.g., control logic integrated in) a memory system controller (e.g., SSD controller, application specific integrated circuit ASIC, processor, etc.) coupled to the memory system and configured to control various memory devices of the memory system.

Fig. 2 is a simplified block diagram of a CAM 220 according to multiple embodiments of the present disclosure. For example, the CAM 220 may be configured as a master CAM or a buffer CAM. The CAM 220 includes a CAM array 222 that may be coupled to an input data register 224. The CAM array 222 may store data (e.g., in the form of a stored data vector), and the input data register 224 may receive an input data vector from the controller 204 (e.g., which may be the controller 104) for comparison with the stored data vector. In examples where CAM 220 is a buffered CAM, CAM array 222 may be an SRAM memory array having SRAM cells. In examples where CAM 220 is a master CAM, CAM array 222 may be a non-volatile storage array having non-volatile memory cells that are inactive for at least less than a threshold length of time, such as resistance variable memory cells (e.g., arranged in a cross-point fashion).

The CAM 220 may have control circuitry 225 (e.g., a control state machine) that may direct the internal operations of the CAM 220 and may manage the CAM array 222. Control circuitry 225 may receive control signals from controller 204 via control interface 226. For example, the controller 204 may cause the control circuitry 225 to compare an input data vector with a data vector stored in the CAM array 222, and may cause the control circuitry 225 to write the data vector in the CAM array 222. In various examples, controller 225 may include the match verification circuitry previously described in connection with fig. 1A.

The detector 229 may be coupled to the CAM array 222 by lines 230-1 through 230-M (e.g., match lines). For example, each of the respective lines 230-1 through 230-M may correspond to a respective vector of data stored in CAM array 222. In an example where CAM 220 is a buffered CAM, the number of lines 230 may be equal to the number of entries 114 in lookup table 112.

The detector 229 may detect whether the stored data vectors match the input data vectors and may generate a respective result (e.g., data bits) for each respective stored data vector indicating whether the respective stored data vector matches the input data vector. For example, as shown in fig. 2, detector 229 may generate data bits having a logical one (1) value to indicate that the respective stored data vector matches the input data vector and a logical zero (0) value to indicate that the respective stored data vector does not match (e.g., is mismatched) with the input data vector. However, the present disclosure is not limited thereto, and the roles of logic 1 and logic 0 may be interchanged. In some examples, the results of the vector comparisons may be combined to form a resultant (e.g., output) vector 235 having a component (e.g., 1 or 0) corresponding to each stored vector.

The detector 229 may be configured to associate (e.g., link) the address of each respective storage vector to a respective result in a result vector 235 (e.g., a respective component). In some examples, detector 229 may have a sense amplifier (e.g., not shown in FIG. 2) coupled to each of lines 230-1 to 230-M. For example, each sense amplifier may be configured to generate a logic 1 or 0 depending on whether the sense amplifier detects a match or mismatch. The result vector 235 and the associated address of the component may be sent to an input/output (I/O) buffer 232 for output to the controller 204 via an interface 234. It should be noted that in the context of FIG. 1A, the result vectors and associated addresses of the components may be sent from CAM106 and CAM110 (e.g., simultaneously) to controller 104.

Fig. 3 illustrates a result vector received at the controller 304 in accordance with various embodiments of the present disclosure. For example, the controller 304 (which may be, for example, controller 104 or 204) may receive the result vector 335-Main from the master CAM and the result vector 335-Buffer from the Buffer CAM at the same time. Result vector 335-Main has components (e.g., component data values 01101001) associated with addresses 340-1 through 340-8, respectively, and result vector 335-Buffer has components (e.g., component data values 00100101) associated with addresses 342-1 through 342-8, respectively. However, the result vector 335 is not limited to eight components and may have any number of components. In addition, the result vectors 335-Main and 335-Buffer may have different numbers of components. The controller 304 has a look-up table 312 (which may be the look-up table 112, for example).

The result vectors 335-Main and 335-Buffer may be generated simultaneously in response to the simultaneous master CAM comparing the input data vector with the stored data vector in the master CAM and the Buffer CAM comparing the input data vector with the stored data vector in the Buffer CAM. For example, the stored data vectors in the main CAM may be stored at locations in the main CAM having addresses 340-1 through 340-8, respectively, and the stored data vectors in the buffer CAM may be stored at locations in the buffer CAM having addresses 342-1 through 342-8, respectively.

Upon receiving the result vectors 335-Main and 335-Buffer, the controller 304 may compare the addresses 340-1 through 340-8 to the Main CAM address in the entry 114 of the lookup table 112. If any of addresses 340-1 through 340-8 do not match the primary CAM addresses in lookup table 112, controller 304 may determine that the data vector in the primary CAM having those addresses is valid and that the results in the components of acceptable result vector 335-Main associated with those addresses are valid. For example, addresses 340-2, 340-4, 340-5, and 340-7 may not match any of the primary CAM addresses in lookup table 112, and the components of result vector 335-main associated with those addresses may be considered valid.

Further, the controller 304 may determine whether a data vector in the main CAM having an address that matches the main CAM address in an entry in the lookup table 112 is valid according to the timestamp in the entry. For example, addresses 340-1, 340-3, 340-6, and 340-8 may match the master CAM addresses in entries 114-2, 114-4, 114-5, and 114-7, respectively. The controller 304 may then determine whether the data vectors in the master CAM having addresses 340-1, 340-3, 340-6, and 340-8 are valid based on the timestamps in entries 114-2, 114-4, 114-5, and 114-7, as previously described. For example, controller 304 may determine that the vector with addresses 340-1 and 340-8 is valid and may clear entries 114-2 and 114-7, thus invalidating the mappings in those entries. The controller 304 may also remove the data vectors in the buffer CAM having addresses 342-1 and 342-8 corresponding to addresses 340-1 and 340-8 from the buffer CAM in response to determining that the data vectors in the main CAM having addresses 340-1 and 340-8 are valid.

However, controller 304 may determine that the vectors having addresses 340-3 and 340-6 are invalid, and thus determine that the results (e.g., logical 1 and logical 0, respectively) in the components of result vector 335-Main associated with addresses 340-3 and 340-6 are invalid. In the example, entries 114-4 and 114-5 may map addresses 340-3 and 340-6 to addresses 342-1 and 342-8, respectively, of the data vectors in the buffered CAM, as shown in FIG. 3. The mapping produces a resultant data vector having data components 01001101.

It should be noted that addresses 340-1 through 340-8 and 342-1 through 342-8 may be physical addresses. Controller 304 may use an L2P data structure (e.g., L2P mapping table 350) to map respective physical addresses 340-1 through 340-8 to respective logical addresses, where addresses 340-3 and 340-6 are mapped to addresses 342-1 and 342-8, respectively. The controller 304 may then associate the respective data component 01001101 of the result vector with the respective logical address and output the result vector to the host 103 with the associated logical address. In this way, the controller 304 may indicate to the host 103 which data vectors match the input data and which data vectors mismatch the data vectors. For example, the host 103 may determine which data vectors match and which vectors mismatch the input data vectors in the logical address space based on the logical addresses.

In some examples, the controller 304 may indicate to the host 103 only the logical address corresponding to the vector that matches the input data vector. For example, controller 304 may output a logical address that maps to a component of a result vector having a logical 1 data value. For example, controller 304 may output respective logical addresses that map to physical addresses 340-2, 340-5, 340-6, and 340-8, noting that address 340-3 maps to address 342-1 associated with a logical 0 and address 340-6 maps to address 342-8 associated with a logical 1.

Fig. 4 illustrates a portion of a non-volatile CAM in accordance with multiple embodiments of the present disclosure. For example, FIG. 4 illustrates a portion of a non-volatile CAM array of a master CAM, such as data block 452. In some examples, the CAM array of each master CAM may have multiple blocks of memory data 452. Each memory block 452 may have a number of data planes, such as data vector planes 455-1 through 455-J.

Each data vector plane 455 may have wordlines 457-1 through 457-8. Each of word lines 457-1 to 457-8 may cross bit lines 459-1 to 459-8. As such, data vector plane 455 may be a cross-point data vector plane. There may be a memory cell 461, such as a resistance variable memory cell, at each intersection of a word line and a bit line. In some examples, a group of memory cells (e.g., a column of memory cells) commonly coupled to a bit line 459 may store a vector of data. For example, columns of memory cells commonly coupled to bit lines 459-1 to 459-8, respectively, may store data vectors 463-1 to 463-8, respectively. Although eight bit lines and eight word lines are shown, there may be any number of bit lines and word lines.

The bit lines 459-1 to 459-8 in each vector plane 455 may be coupled to sense amplifiers 465-1 to 465-8, respectively. Sense amplifiers 465-1 through 465-8 may generate the results of the comparison of input data vector 466 with stored vectors 463-1 through 463-8, respectively. For example, the result may be a component of result vector 435, which may be result vector 335-Main. In some examples, data vectors stored in a memory data block may be compared to input data vectors 466 one plane at a time (e.g., on a plane-by-plane basis).

In some examples, the location of the stored vector may be specified by specifying the location of a CAM in a CAM system (e.g., CAM106 in CAM system 102), the location of a block of memory data in the CAM, the location of a vector plane in the block of memory data, and the location of the stored data vector in the vector plane. For example, an address specifying the location of a stored data vector may specify the location of a CAM in a CAM system, the location of a block of memory data in the CAM, the location of a plane in the block of memory data, and the location of a data vector in a vector plane.

Fig. 5 illustrates an example of comparing input data with data stored in a non-volatile CAM according to various embodiments of the present disclosure. For example, in FIG. 5, an input data vector 566 is simultaneously compared to data vectors 563-1 to 563-8 in vector plane 555 of the primary CAM. The input data vector 566 may have component data (e.g., Bit) values 00110011 that correspond to bits Bit1 through Bit8, respectively, for example.

Vector plane 555 may have word lines 557-1 through 557-8. Each of the word lines 557-1-557-8 may intersect a bit line 559-1-559-8. There may be a memory cell 561, such as a resistance variable memory cell, at each intersection of a word line and a bit line. Although eight bit lines and eight word lines are shown in the example of fig. 5, embodiments are not limited to a particular number of word lines and/or bit lines.

Data vectors 563-1 to 563-8 may be stored in columns of memory cells commonly coupled to bit lines 559-1 to 559-8, respectively. For example, the memory cells 561-1 through 561-8 in each respective column may be coupled to word lines 557-1 through 557-8, respectively. In this example, data vector 563-1(01111111) is stored in a cell coupled to bit line 559-1, data vector 563-2(11110111) is stored in a cell coupled to bit line 559-2, data vector 563-3 (11111111111) is stored in a cell coupled to bit line 559-3, data vector 563-4(11111101) is stored in a cell coupled to bit line 559-4, data vector 563-5(00110011) is stored in a cell coupled to bit line 559-5, data vector 563-6(00000000) is stored in a cell coupled to bit line 559-6, data vector 563-7(11111110) is stored in a cell coupled to bit line 559-7, and data vector 563-8 (000000000000) is stored in a cell coupled to bit line 559-8. Note that the respective data values (e.g., components) for each of respective data vectors 563-1 to 563-8 are stored in memory units 561-1 to 561-8, respectively

Bit lines 559-1 through 559-8 may be coupled to sense amplifiers 565-1 through 565-8, respectively. Sense amplifiers 565-1 to 565-8 may generate the results of comparisons of input data vector 566 with stored vectors 563-1 to 563-8, respectively. For example, the result may be a component of result vector 535, which may be result vector 335-Main.

Bit1 through Bit8 of the input data vector 566 may be compared to the data stored in the memory cells 561-1 through 561-8, respectively, coupled to each of the data lines 559-1 through 559-8, respectively. By applying a voltage difference across the memory cell, such as the demarcation voltage VDM1, the bit value of logic 0 may be compared to the data stored in memory cell 561. By applying the demarcation voltage VDM2 across the memory cell, a bit value of logic 1 may be compared to the data stored in memory cell 561.

For example, VDM1 may correspond to an input bit value of logic 0 and VDM2 may correspond to an input bit value of logic 1. In some examples, the demarcation voltage may be a voltage applied to a bit line coupled to the memory cell minus a voltage applied to a word line coupled to the memory cell. Note that in this example, VDM1 and VDM2 have opposite polarities, with VDM1 having a negative polarity and VDM2 having a positive polarity. However, the present disclosure is not limited thereto.

In some examples, the memory unit 561 may experience a switching event, such as a threshold event (e.g., a snapback event), in response to VDM1 being applied across the memory unit 561, or a switching event in response to VDM2 being applied across the memory unit 561. For example, memory cell 561 may be switched from one conductive state, e.g., a low conductive state (e.g., a high resistance state), to another conductive state, e.g., a high conductive state (e.g., a low resistance state).

In some examples, memory cells that experience a switching event in response to a demarcation voltage may be considered to store data values that are mismatched with input data values corresponding to the demarcation voltage. For example, a memory cell storing a logic 1 may experience a switching event in response to VDM1 (e.g., corresponding to an input logic 0) being applied across the memory cell, and a memory cell storing a logic 0 may experience a switching event in response to VDM2 (e.g., corresponding to an input logic 1) being applied across the memory cell.

In such examples, memory cells that are responsive to the demarcation voltage without undergoing a switching event can be considered to store a data value that matches an input data value corresponding to the demarcation voltage. For example, a memory cell storing a logic 0 may not experience a switching event in response to the VDM1 being applied across the memory cell, and a memory cell storing a logic 1 may not experience a switching event in response to the VDM2 being applied across the memory cell. However, it should be noted that in other examples, a handover event may indicate a match and no handover event may indicate a mismatch.

It should be noted that data vector 563 may be mismatched with input data vector 566 if the data stored in at least one of the memory cells of data vector 563 is mismatched with the corresponding bits of input data vector 566. Sense amplifier 565 may sense a switching event experienced by one or more memory cells in a corresponding data vector 563 by sensing a current change that may be reflected in an output voltage of the sense amplifier. Thus, the sense amplifier can sense a mismatch between the data vector coupled to the sense amplifier and the input data vector 566 by sensing the switching event. For example, a sense amplifier may generate (e.g., output) a logic 0 in response to sensing a switching event to indicate a mismatch between a data vector coupled to the sense amplifier and the input data vector 566. The sense amplifier may generate a logic 1 in response to not sensing a switching event to indicate a match between the data vector coupled to the sense amplifier and the input data vector 566.

In some examples, a portion of input data vector 566 may be compared to a corresponding portion of data vectors 563-1 to 563-8 during a first time period corresponding to a first phase of comparison, and a remaining portion of input data vector 566 may be compared to a corresponding portion of data vectors 563-1 to 563-8 during a second time period corresponding to a second phase of comparison. During the first phase, the data values stored in memory cells 561-1, 561-2, 561-5, and 561-6 of each of the input data vector 566 having a logic 0, Bit1, Bit2, Bit5, and Bit6 and data vectors 563-1 through 563-8 may be compared by applying VDM1 across those memory cells while applying, for example, zero volts across the remaining memory cells 561-3, 561-4, 561-7, and 561-8, respectively. During the second phase, the data values stored in memory cells 561-3, 561-4, 561-7, and 561-8 of each of Bit3, Bit4, Bit7, and Bit8 and data vectors 563-1 to 563-8, respectively, of input data vector 566 having a logic 1 may be compared by applying VDM2 across those memory cells while applying, for example, zero volts across the remaining memory cells 561-1, 561-2, 561-5, and 561-6. However, the disclosure is not so limited, and VDM1 and VBM2 may be applied simultaneously (e.g., during the same phase).

The CAM array of the main CAM may include a two-dimensional (2D) and/or three-dimensional (3D) array structure, such as a cross-point array structure. Memory cells (e.g., memory cells 461 and 561) can include, for example, various types of resistance variable storage elements and/or switching elements. For example, the cell may be a Phase Change Random Access Memory (PCRAM) cell or a Resistive Random Access Memory (RRAM) cell.

As used herein, a storage element refers to a programmable portion of a memory cell. For example, the main CAM may be a 3D cross-point device, the cells of which may include a "stacked" structure in which storage elements and switching elements are coupled in series and may be referred to herein as 3D Phase Change Material and Switch (PCMS) devices. The 3D PCMS cell may include, for example, a two-terminal chalcogenide-based storage element, such as an Ovonic Threshold Switch (OTS), coupled in series with a two-terminal chalcogenide-based switching element. In some examples, the memory cell may be a self-selecting memory (SSM) cell, in which a single material may be used as both a switching element and a storage element. The SSM cell may comprise a chalcogenide alloy; however, the embodiments are not limited thereto.

As a non-limiting example, the memory cells of the disclosed non-volatile CAM may include a phase change material (e.g., a phase change chalcogenide alloy), such as an indium (In) -antimony (Sb) -tellurium (Te) (IST) material (e.g., In)₂Sb₂Te₅、In₁Sb₂Te₄、In₁Sb₄Te₇Etc.) or germanium (Ge) -antimony (Sb) -tellurium (Te) (GST) materials (e.g., Ge₂Sb₂Te₅、Ge₁Sb₂Te₄、Ge₁Sb₄Te₇Etc.). As used herein, hyphenated chemical composition symbols indicate the elements contained in a particular mixture or compound, and are intended to represent all stoichiometries involving the indicated elements. For example, other memory cell materials may include GeTe, In-Se, Sb₂Te₃GaSb, InSb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sb-Te, Ge-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Te-Sn-Pt, among various other materials.

In the foregoing description of the embodiments of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how various embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.

As used herein, "plurality" or "quantity" of something may refer to one or more of such things. For example, a plurality or quantity of memory cells may refer to one or more memory cells. "plurality" something means two or more than two. As used herein, the term "coupled" may include not electrically coupled, directly coupled, and/or directly connected (e.g., by direct physical contact) to intermediate elements or indirectly coupled and/or connected to intermediate elements, or wirelessly coupled. The term "coupled" may further include two or more elements that cooperate or interact with each other (e.g., as a cause and effect relationship). As used herein, multiple actions performed simultaneously refer to actions that at least partially overlap over a particular period of time.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. The scope of various embodiments of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

In the foregoing detailed description, certain features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.