阅读说明：本技术 一种数据传输方法和装置 (Data transmission method and device ) 是由 何向 于 2019-05-15 设计创作，主要内容包括：本申请实施例公开了一种数据传输方法,包括：第一芯片接收第二芯片器件发送的第一数据流；所述第一数据流为采用第一前向纠错FEC码型编码的数据流；所述第一芯片器件对所述第一数据流再进行至少一次编码,得到第二数据流；其中,所述第二数据流为至少采用所述第一FEC码型和第二FEC码型编码的级联FEC码流。可见,FEC码型的转换过程得以简化,FEC码型转换时所要耗费的时延及设备功耗都得以减小,从而数据传输效率得以提高。此外,本申请实施例还公开了一种数据传输装置。(The embodiment of the application discloses a data transmission method, which comprises the following steps: the first chip receives a first data stream sent by a second chip device; the first data stream is a data stream coded by a first Forward Error Correction (FEC) code pattern; the first chip device encodes the first data stream at least once again to obtain a second data stream; and the second data stream is a cascade FEC code stream coded by at least adopting the first FEC code pattern and the second FEC code pattern. Therefore, the conversion process of the FEC code pattern is simplified, the time delay consumed during the conversion of the FEC code pattern and the equipment power consumption are reduced, and the data transmission efficiency is improved. In addition, the embodiment of the application also discloses a data transmission device.)

A method of data transmission, comprising:

the first chip receives a first data stream sent by the second chip; the first data stream is a data stream coded by a first Forward Error Correction (FEC) code pattern;

the first chip encodes the first data stream at least once again to obtain a second data stream; and the second data stream is a cascade FEC code stream coded by at least adopting the first FEC code pattern and the second FEC code pattern.

The method according to claim 1, wherein the first FEC code pattern is specifically: reed-solomon RS codes, bose-chaudhuri-hocquenghem BCH codes, ladder Staircase codes, low density parity check LDPC codes, Turbo codes or Turbo product codes TPC.

The method according to claim 1 or 2, wherein the second FEC code pattern is specifically: BCH codes, RS codes, Staircase codes, LDPC codes, Turbo codes, or TPC.

The method of any of claims 1 to 3, wherein the first chip encodes the first data stream at least once more to form a second data stream, comprising:

the first chip distributes the first data stream into n third data streams; wherein data of the same codeword block in the first data stream is distributed to a different third data stream;

and the first chip respectively encodes the plurality of third data streams at least once again to form the second data stream.

The method according to claim 4, characterized in that k blocks of code words identified from the first data stream are distributed into n third data streams, data belonging to the k blocks of code words in each of the third data streams being encoded into one block of code words in the second data stream;

wherein, the total data volume contained by the k code word blocks in the first data stream is equal to the payload data volume contained by the n code word blocks in the second data stream.

The method of claim 4, wherein data in the first data stream is distributed in FEC symbol blocks, and wherein data of a same FEC symbol block in the first data stream is encoded in a same codeword block in the second data stream.

The method of claim 4, wherein the data in the first data stream is distributed in terms of a bit stream and the data in the third data stream is encoded in terms of a bit stream.

The method of claims 1 to 7, wherein the first chip and the second chip are located in the same data transmission device, the first chip is an electrical chip, and the second chip is a chip using an Ethernet interface.

A method of data transmission, comprising:

the first chip receives a second data stream sent by the second chip; the second data stream is a cascade FEC code stream coded by at least adopting a first FEC code type and a second FEC code type;

the first chip decodes the second data stream at least once to form a first data stream; the first data stream is a data stream coded by the first FEC code pattern;

the first chip sends the first data stream to a third chip.

The method according to claim 9, wherein the first FEC code pattern is specifically: RS codes, BCH codes, Staircase codes, LDPC codes, Turbo codes, or TPC.

The method according to claim 9 or 10, wherein the second FEC code pattern is specifically: BCH codes, RS codes, Staircase codes, LDPC codes, Turbo codes, or TPC.

The method according to claims 9 to 11, wherein the first data stream is used for decoding by the third chip according to the first FEC code pattern.

The method according to claims 9 to 12, wherein the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, the second chip is an electrical chip, and the third chip is a chip using an ethernet interface.

A data transmission apparatus, wherein the apparatus is a first chip, comprising:

the receiver is used for receiving a first data stream sent by the second chip; the first data stream is a data stream coded by a first Forward Error Correction (FEC) code pattern;

the encoder is used for encoding the first data stream at least once again to obtain a second data stream; and the second data stream is a cascade FEC code stream coded by at least adopting the first FEC code pattern and the second FEC code pattern.

The apparatus according to claim 14, wherein the first FEC code pattern is specifically: RS codes, BCH codes, Staircase codes, LDPC codes, Turbo codes, or TPC.

The apparatus according to claim 14 or 15, wherein the second FEC code pattern is specifically: BCH codes, RS codes, Staircase codes, LDPC codes, Turbo codes, or TPC.

The apparatus according to any of claims 14 to 16, wherein the encoder is specifically configured to:

distributing the first data stream into n third data streams; wherein data of the same codeword block in the first data stream is distributed to a different third data stream;

and respectively encoding the plurality of third data streams at least once again to form the second data stream.

The apparatus of claim 17, wherein k codeword blocks identified from the first data stream are distributed into n third data streams, and wherein data belonging to the k codeword blocks in each of the third data streams is encoded into one codeword block in the second data stream;

wherein, the total data volume contained by the k code word blocks in the first data stream is equal to the payload data volume contained by the n code word blocks in the second data stream.

The apparatus of claim 17, wherein data in the first data stream is distributed in FEC symbol blocks, and wherein data of a same FEC symbol block in the first data stream is encoded in a same codeword block in the second data stream.

The apparatus of claim 17, wherein the data in the first data stream is distributed in accordance with a bit stream, and wherein the data in the third data stream is encoded in accordance with a bit stream.

The apparatus according to claims 14 to 20, wherein the first chip and the second chip are located in the same data transmission device, the first chip is an electrical chip, and the second chip is a chip using an ethernet interface.

A data transmission apparatus, wherein the apparatus is a first chip, comprising:

the receiver is used for receiving a second data stream sent by the second chip; the second data stream is a cascade FEC code stream coded by at least adopting a first FEC code type and a second FEC code type;

a decoder for decoding the second data stream at least once to form a first data stream; the first data stream is a data stream coded by the first FEC code pattern;

a transmitter to transmit the first data stream to a third chip.

The apparatus of claim 22, wherein the first FEC code pattern is specifically: RS codes, BCH codes, Staircase codes, LDPC codes, Turbo codes, or TPC.

The apparatus according to claim 22 or 23, wherein the second FEC code pattern is specifically: BCH codes, RS codes, Staircase codes, LDPC codes, Turbo codes, or TPC.

The apparatus of claims 22-24, wherein the first data stream is for decoding by the third chip according to the first FEC pattern.

The apparatus according to claims 22 to 25, wherein the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, the second module is a chip, and the third chip is a chip using an ethernet interface.

A communication system comprising a data transmission device according to any one of claims 14 to 21 and a data transmission device according to any one of claims 22 to 26.

A network device comprising a data transmission arrangement according to any one of claims 14 to 21.

A network device comprising a data transmission arrangement according to any of claims 22-26.