阅读说明：本技术 回音抵消系统以及回音抵消方法 (Echo cancellation system and echo cancellation method ) 是由 陈昀泽 何轩廷 黄亮维 吕奎颖 于 2020-05-28 设计创作，主要内容包括：一种回音抵消系统包含数据传输电路以及回音抵消电路。数据传输电路用以接收第一传输信号。第一传输信号具有第一取样频率。回音抵消电路用以依据第一传输信号产生第二传输信号。第二传输信号具有第二取样频率。第二取样频率大于第一取样频率。回音抵消电路还用以依据第二传输信号产生回音抵消信号。数据传输电路还用以依据接收信号以及回音抵消信号产生输出信号。(An echo cancellation system includes a data transmission circuit and an echo cancellation circuit. The data transmission circuit is used for receiving a first transmission signal. The first transmission signal has a first sampling frequency. The echo cancellation circuit is used for generating a second transmission signal according to the first transmission signal. The second transmission signal has a second sampling frequency. The second sampling frequency is greater than the first sampling frequency. The echo cancellation circuit is further configured to generate an echo cancellation signal according to the second transmission signal. The data transmission circuit is further used for generating an output signal according to the received signal and the echo cancellation signal.)

1. An echo cancellation system, comprising:

a data transmission circuit for receiving a first transmission signal, wherein the first transmission signal has a first sampling frequency; and

the echo cancellation circuit is used for generating a second transmission signal according to the first transmission signal, wherein the second transmission signal has a second sampling frequency, and the second sampling frequency is greater than the first sampling frequency, wherein the echo cancellation circuit is further used for generating an echo cancellation signal according to the second transmission signal, and the data transmission circuit is further used for generating an output signal according to a received signal and the echo cancellation signal.

2. The echo cancellation system of claim 1 wherein the second sampling frequency is more than twice the first sampling frequency.

3. The echo cancellation system according to claim 1, wherein the data transmission circuit comprises:

a first oversampling circuit for generating a third transmission signal according to the first transmission signal, wherein the third transmission signal has a third sampling frequency, and the third sampling frequency is greater than the second sampling frequency;

a first shaping circuit for generating a first shaped signal according to the third transmission signal;

a first digital-to-analog converter for generating an analog signal according to the first shaping signal;

an analog front-end processing circuit for generating a processing signal according to the analog signal, the echo cancellation signal and the received signal, wherein the processing signal has the third sampling frequency; and

the analog-digital conversion circuit is used for generating at least one digital signal according to the processing signal, wherein the output signal is generated based on the at least one digital signal.

4. The echo cancellation system of claim 3 wherein the second sampling frequency is half of the third sampling frequency.

5. The echo cancellation system of claim 3, wherein the echo cancellation circuit comprises:

the second oversampling circuit is used for generating the second transmission signal according to the first transmission signal;

a first filter circuit for performing a filtering process on the second transmission signal to generate a first filtered signal;

a third oversampling circuit for generating a fourth transmission signal according to the first filtered signal and a random number, wherein the fourth transmission signal has the third sampling frequency;

a second shaping circuit for generating a second shaped signal according to the fourth transmission signal;

an adder for generating an operation signal according to the first shaping signal and the second shaping signal; and

the second digital-to-analog converter is used for generating the echo cancellation signal according to the operation signal.

6. The echo cancellation system of claim 5 wherein the echo cancellation circuit further comprises:

a random number generating circuit for generating the random number; and

a second filter circuit for generating a second filter signal according to the inverted random number corresponding to the random number,

wherein the first filter circuit is updated based on the at least one digital signal and the second filter circuit.

7. An echo cancellation system, comprising:

a data transmission circuit for receiving a first transmission signal; and

an echo cancellation circuit, comprising:

the first filter is used for generating a first filtering signal according to the first transmission signal, wherein the first filtering signal and a random number are combined into a first digital signal;

a second filter for generating a second filtered signal according to the first transmission signal; and

a digital-to-analog converter to generate an echo cancellation signal based on the first transmission signal and a shaped signal corresponding to the first digital signal and the second filtered signal;

the data transmission circuit is further used for generating an output signal according to the received signal and the echo cancellation signal.

8. The echo cancellation system according to claim 7, wherein the data transmission circuit comprises:

an analog front-end processing circuit for generating a processing signal according to the analog signal corresponding to the first transmission signal, the echo cancellation signal and a received signal;

the first analog-digital conversion circuit corresponds to the first filter, and is used for generating a first digital signal according to the processing signal; and

a second analog-to-digital conversion circuit corresponding to the second filter, wherein the second analog-to-digital conversion circuit is configured to generate a second digital signal according to the processing signal, and wherein the output signal is generated based on the first digital signal and the second digital signal.

9. The echo cancellation system of claim 8 wherein the first filter corresponds to a first phase and is coupled to the first analog-to-digital converter by a first adder, wherein the second filter corresponds to a second phase and is coupled to the second analog-to-digital converter by a second adder.

10. An echo cancellation method, comprising:

receiving a first transmission signal by a data transmission circuit, wherein the first transmission signal has a first sampling frequency;

generating a second transmission signal by an echo cancellation circuit according to the first transmission signal, wherein the second transmission signal has a second sampling frequency, and the second sampling frequency is greater than the first sampling frequency;

generating an echo cancellation signal according to the second transmission signal through the echo cancellation circuit; and

and generating an output signal according to the received signal and the echo cancellation signal through the data transmission circuit.

Technical Field

Embodiments described in the present disclosure relate to communication technologies, and in particular, to an echo cancellation system (echo cancellation system) and an echo cancellation method.

Background

As communication technologies have evolved, various communication systems have been developed and used in many different applications. In a communication system using Full-Duplex (Full-Duplex) technology, there are transmission signals and reception signals on a pair of transmission lines. When the impedances of the two transmission lines are not matched or the hybrid architecture of the receiving device is not matched, the transmission signal may be introduced into the reception signal. This can cause Echo (Echo) and can affect the signal-to-noise ratio (SNR) of the communication system.

Disclosure of Invention

Some embodiments of the present disclosure relate to an echo cancellation system. The echo cancellation system includes a data transmission circuit and an echo cancellation circuit. The data transmission circuit is used for receiving a first transmission signal. The first transmission signal has a first sampling frequency. The echo cancellation circuit is used for generating a second transmission signal according to the first transmission signal. The second transmission signal has a second sampling frequency. The second sampling frequency is greater than the first sampling frequency. The echo cancellation circuit is further configured to generate an echo cancellation signal according to the second transmission signal. The data transmission circuit is further used for generating an output signal according to the received signal and the echo cancellation signal.

Some embodiments of the present disclosure relate to an echo cancellation system. The echo cancellation system includes a data transmission circuit and an echo cancellation circuit. The data transmission circuit is used for receiving a first transmission signal. The echo cancellation circuit comprises a first filter, a second filter and a digital-to-analog converter. The first filter is used for generating a first filtering signal according to the first transmission signal. The first filtered signal is combined with a random number to form a first digital signal. The second filter is used for generating a second filtering signal according to the first transmission signal. The digital-to-analog converter is used for generating an echo cancellation signal based on the first transmission signal and a shaping signal corresponding to the first digital signal and the second filtering signal. The data transmission circuit is further used for generating an output signal according to the received signal and the echo cancellation signal.

Some embodiments of the present disclosure relate to an echo cancellation method. The echo cancellation method comprises the following steps: receiving a first transmission signal through a data transmission circuit, wherein the first transmission signal has a first sampling frequency; generating a second transmission signal according to the first transmission signal through an echo cancellation circuit, wherein the second transmission signal has a second sampling frequency, and the second sampling frequency is greater than the first sampling frequency; generating an echo cancellation signal according to the second transmission signal through an echo cancellation circuit; and generating an output signal according to the received signal and the echo cancellation signal through a data transmission circuit.

In summary, in the echo cancellation system and the echo cancellation method of the present disclosure, the echo cancellation circuit generates the echo cancellation signal according to the signal with the higher sampling frequency. In this way, more noise can be eliminated to improve the signal-to-noise ratio of the echo cancellation system.

Drawings

The foregoing and other objects, features, advantages and embodiments of the disclosure will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic diagram of an echo cancellation system, according to some embodiments of the present disclosure;

fig. 2 is a schematic diagram of an echo cancellation system, according to some embodiments of the present disclosure; and

fig. 3 is a flow chart of an echo cancellation method according to some embodiments of the present disclosure.

Detailed Description

The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected," may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.

Refer to fig. 1. Fig. 1 is a schematic diagram of an echo cancellation system S1, drawn in accordance with some embodiments of the present disclosure. In some embodiments, the echo cancellation system S1 is applied to an Ethernet (Ethernet) system.

In some embodiments, the echo cancellation system S1 employs full duplex technology. That is, there is a pair of transmission lines in the system, and the two transmission lines have transmission signals and reception signals, respectively. For the example of fig. 1, the transmission signal of the echo cancellation system S1 is the transmission signal TX 1. The received signal of the echo cancellation system S1 is the received signal RXC. In some embodiments, the transmission signal TX1 may be generated by encoding a signal from a media access control layer (MAC layer), but the disclosure is not limited thereto.

Taking the example of fig. 1 as an example, the echo cancellation system S1 includes a data transmission circuit 100, an echo cancellation circuit 200, and an echo cancellation circuit 300. In some embodiments, the echo cancellation circuit 200 is used to generate an echo cancellation signal EC1 to cancel most of the echo in the analog end cancellation system. The echo cancellation circuit 300 is used to generate an echo cancellation signal EC2 to cancel the remaining echo at the digital end.

In particular, the data transmission circuit 100 receives a transmission signal TX1, wherein the transmission signal TX1 has a first sampling frequency (e.g., 400 megahertz (MHz)). The echo cancellation circuit 200 receives the transmission signal TX1 and performs an oversampling (oversampling) procedure on the transmission signal TX1 to generate the transmission signal TX2, wherein the transmission signal TX2 has a second sampling frequency (e.g., 800 mhz) greater than the first sampling frequency. The echo cancellation circuit 200 generates an echo cancellation signal EC1 according to the transmission signal TX 2. Then, the data transmission circuit 100 generates the output signal DO according to the analog signal TXC, the receiving signal RXC, the echo cancellation signal EC1 and the echo cancellation signal EC 2. The echo cancellation signal EC1 and the echo cancellation signal EC2 can cancel the influence of the echo on the signal, thereby improving the signal-to-noise ratio of the echo cancellation system S1.

In some embodiments, the data transmission circuit 100 includes a memory 102, an oversampling circuit 104, a shaping circuit 106, a digital-to-analog converter 108, an analog front-end processing circuit 110, an analog-to-digital conversion circuit 112, a parallel-to-serial conversion circuit 114, an adder AD1, a serial-to-parallel conversion circuit 116, a filtering circuit 118, and an adder AD 2. The analog-to-digital conversion circuit 112 includes an analog-to-digital converter 1121 and an analog-to-digital converter 1122. The filter circuit 118 includes a filter 1181 and a filter 1182.

In some embodiments, the echo cancellation circuit 200 includes an oversampling circuit 202, a filter circuit 204, an adder AD3, a random number generation circuit 206, a filter circuit 208, an oversampling circuit 210, a shaping circuit 212, an adder AD4, and a digital-to-analog converter 214.

In operation, memory 102 receives a transmit signal TX 1. In some embodiments, the memory 102 is implemented as a register capable of executing a first-in-first-out (FIFO) program, but the disclosure is not limited thereto. The memory 102 then passes the transmission signal TX1 to the oversampling circuit 104 and the oversampling circuit 202.

The oversampling circuit 104 performs an oversampling procedure on the transmission signal TX1 to generate the transmission signal TX3, wherein the transmission signal TX3 has a third sampling frequency (e.g., 1.6 gigahertz) greater than the second sampling frequency. Then, the shaping circuit 106 generates a shaping signal SD1 according to the transmission signal TX 3. The digital-to-analog converter 108 converts the shaped signal SD1 in digital form to an analog signal TXC in analog form. The analog signal TXC can be processed by a transformer and then output to a network cable or other electronic elements.

On the other hand, the oversampling circuit 202 performs an oversampling process on the transmission signal TX1 to generate the transmission signal TX 2. As previously mentioned, the transmission signal TX2 has the second sampling frequency. Then, the filter circuit 204 may perform a filtering process on the TX signal TX2 with a filtered least mean square (FxLMS) mechanism to generate the filtered signal AEC _ O. The random number generation circuit 206 generates a random number PN. In some embodiments, the random number PN is a pseudo-noise sequence (pseudo-noise sequence), but the disclosure is not limited thereto. The adder AD3 combines the filtered signal AEC _ O and the random number PN to generate the operation signal CD 1. The oversampling circuit 210 performs an oversampling process on the operation signal CD1 to generate the transmission signal TX 4. The transmission signal TX4 also has a third sampling frequency. That is, the sampling frequency of the transmission signal TX4 is set to be equal to the sampling frequency of the transmission signal TX 3. Shaping circuit 212 generates shaped signal SD2 according to transmission signal TX 4. Adder AD4 combines shaped signal SD2 and shaped signal SD1 to generate operation signal CD 2. The digital-to-analog converter 214 converts the digital operation signal CD2 into an analog echo cancellation signal EC 1.

In some embodiments, if the analog signal TXC is introduced into the receive transmission line, it will cause echo. That is, analog front-end processing circuit 110 receives analog signal TXC. The analog front-end processing circuit 110 generates a processing signal AFE _ O according to the analog signal TXC, the echo cancellation signal EC1 from the echo cancellation circuit 200, and the reception signal RXC. The processing signal AFE _ O also has a third sampling frequency. The analog-to-digital conversion circuit 112 generates the digital signal D _ ODD and the digital signal D _ EVEN according to the processing signal AFE _ O. In some embodiments, the digital signal D _ ODD is generated by the adc 1121 operating according to a first sampling frequency and sampling the processing signal AFE _ O with a first phase (e.g., ODD phase), and the digital signal D _ EVEN is generated by the adc 1122 operating according to the first sampling frequency and sampling the processing signal AFE _ O with a second phase (e.g., EVEN phase). Next, the parallel-serial conversion circuit 114 converts the digital signal D _ ODD and the digital signal D _ EVEN in the parallel form into the serial signal SRD in the serial form.

In addition, the random number PN is subjected to an inversion procedure to generate an inverted random number-PN. The filter circuit 208 generates a filter signal FO according to the inverted random number-PN. The adder AD1 combines the filtered signal FO and the serial signal SRD in serial form to generate the serial form of the operation signal CD 3. The serial-parallel conversion circuit 116 converts the operation signal CD3 in serial form into a parallel signal PD in parallel form. Filter 1181 operates according to a first sampling frequency and samples parallel signal PD in a first phase (e.g., an odd phase) to generate filtered signal DLF 1. The filter 1182 operates according to the first sampling frequency and samples the parallel signal PD in the second phase (e.g., even phase) to generate the filtered signal DLF 2. In some embodiments, the filters 1181 and 1182 are implemented as low-pass filters, but the disclosure is not limited thereto. Summer AD2 combines filtered signal DLF1, filtered signal DLF2, and echo cancellation signal EC2 to produce output signal DO.

In some embodiments, the filtering lms mechanism of the filtering circuit 204 is updated based on the transmission signal TX2, the serial signal SRD (which may reflect an error), and the filtering circuit 208 (e.g., filter coefficients), so that the echo cancellation circuit 200 generates the echo cancellation signal EC1 that can more effectively cancel the echo, thereby improving the snr of the echo cancellation system S1.

In some related art techniques, an echo cancellation circuit generates an echo cancellation signal based on a signal having a lower sampling frequency. In these related arts, the echo cancellation signal cannot effectively cancel the echo, and thus the signal-to-noise ratio of the communication system cannot be effectively improved.

In the present disclosure, the echo cancellation circuit 200 generates the echo cancellation signal EC1 according to the transmission signal TX2 with a higher sampling frequency (a second sampling frequency, e.g., 800 mhz). Thus, the echo cancellation signal EC1 can effectively cancel the echo, so that the signal-to-noise ratio of the echo cancellation system S1 is effectively improved.

In addition, the sampling frequency of the transmission signal TX2 may be determined according to the sampling frequency of the processing signal AFE _ O output by the analog front-end processing circuit 110. In some embodiments, if the processing signal AFE _ O has the third sampling frequency, the second sampling frequency of the transmission signal TX2 output by the oversampling circuit 202 may be set to be half of the third sampling frequency or less. In this way, system cost can be avoided from being prohibitive with most echoes already cancelled. In some other embodiments, the second sampling frequency may be set equal to the third sampling frequency to eliminate more echo.

Refer to fig. 2. Fig. 2 is a schematic diagram of an echo cancellation system S2, drawn in accordance with some embodiments of the present disclosure. The echo cancellation system S2 of fig. 2 is a multi-phase (poly-phase) system.

Specifically, the main difference between the echo cancellation system S2 in fig. 2 and the echo cancellation system S1 in fig. 1 is that the data transmission circuit 1000 of the echo cancellation system S2 includes a memory 1131 and a memory 1132. The echo cancellation circuit 2000 of the echo cancellation system S2 includes a filter circuit 2041 (which may be included in the filter circuit 204 of fig. 1), a filter circuit 2042 (which may be included in the filter circuit 204 of fig. 1), a memory 207, a filter circuit 2081 (which may be included in the filter circuit 208 of fig. 1), a filter circuit 2082 (which may be included in the filter circuit 208 of fig. 1), a memory 216, a filter 2181, and a filter 2182. In some embodiments, the memory 1131, the memory 1132, the memory 207 and the memory 216 are implemented by registers capable of executing a first-in first-out program, but the disclosure is not limited thereto.

The filter circuits 2041 and 2042 receive the transmission signal TX1, wherein the filter circuit 2041 performs a filtering process on the transmission signal TX1 according to a first phase (e.g., an odd phase) to output a filtered signal F1. The filter circuit 2042 performs a filtering process on the TX1 according to the second phase (e.g., even phase) to output a filtered signal F2. The random number generation circuit 206 generates a random number PN. The adder AD5 combines the filtered signal F1 and the random number PN to generate the digital signal DD 1. The shaping circuit 212 generates a shaped signal SD3 according to the digital signal DD1 and the filtered signal F2. The digital-to-analog converter 214 generates the echo cancellation signal EC1 based on the combination of the shaped signal SD3 and the transmission signal TX 1. The analog front-end processing circuit 110 generates a processing signal AFE _ O1 according to an analog signal TXC1 corresponding to the transmission signal TX1, an echo cancellation signal EC1 and a reception signal RXC. The analog-to-digital conversion circuit 1121 samples the processing signal AFE _ O1 at a first phase (e.g., ODD phase) to generate the digital signal D _ ODD 1. Analog-to-digital conversion circuit 1122 samples the processing signal AFE _ O1 at a second phase (e.g., EVEN phase) to generate digital signal D _ EVEN 1.

On the other hand, the memory 207 outputs the inverted random number-PN to the filter 2081 and the filter 2082. The filter 2081 is coupled to the adc 1131 through the adder AD 6. The filter 2082 is coupled to the analog-to-digital converter 1132 through the adder AD 7. The filter 2081, the adc 1131, and the adc 1121 correspond to a first phase (e.g., an odd phase). Filter 2082, analog-to-digital converter 1132, and analog-to-digital converter 1122 correspond to a second phase (e.g., an even phase). In some embodiments, filter 2081 may be updated according to the output of adder AD6, and filter 2082 may be updated according to the output of adder AD 7.

In addition, the memory 216 transmits the transmission signal TX1 to the filter circuit 2181 and the filter circuit 2182. The output of the filter circuit 2181 and the output of the filter circuit 2182 are changed according to the filter coefficients of the filter circuit 2081 and the filter circuit 2082, respectively (for example, signals can be transmitted through the path connecting the filter circuit 208 to the filter circuit 204 in fig. 1). The combining circuit COM updates the filtering least mean square mechanism of the filtering circuit 2041 and the filtering circuit 2042 through the updating circuit 220 according to the output of the adc 1131, the output of the adc 1132, the output of the filtering circuit 2181 and the output of the filtering circuit 2182.

As mentioned previously, the echo cancellation system S2 of fig. 2 employs a multi-phase system. That is, the echo cancellation system S2 separately processes signals of different phases. In this case, all the devices can be operated at a lower frequency to achieve power saving. In addition, since the echo cancellation system S2 adopts a multi-phase system, the flexibility of circuit design is greater. For example, it will be more convenient to remove the path of one phase (e.g., odd phase or even phase) in the future.

Refer to fig. 3. Fig. 3 is a flow chart of an echo cancellation method 3000 according to some embodiments of the present disclosure. The echo cancellation method 3000 includes operations S310, S320, S330, and S340.

In some embodiments, the echo cancellation method 3000 is applied to the echo cancellation system S1 in fig. 1, but the disclosure is not limited thereto. For ease of understanding, the echo cancellation method 3000 will be discussed in conjunction with the echo cancellation system S1 of fig. 1.

In operation S310, a transmission signal TX1 is received by the data transmission circuit 100, wherein the transmission signal TX1 has a first sampling frequency.

In operation S320, a transmission signal TX2 is generated by the echo cancellation circuit 200 according to the transmission signal TX1, wherein the transmission signal TX2 has a second sampling frequency, and the second sampling frequency is greater than the first sampling frequency. In some embodiments, an oversampling procedure is performed on the transmission signal TX1 by the oversampling circuit 202 to generate the transmission signal TX 2. The sampling frequency of the transmission signal TX2 may be more than twice the sampling frequency of the transmission signal TX 1.

In operation S330, an echo cancellation signal EC1 is generated by the echo cancellation circuit 200 according to the transmission signal TX 2. Since the transmission signal TX2 has the higher second sampling frequency, the echo cancellation circuit 200 generates the echo cancellation signal EC1 that more effectively cancels the echo.

In operation S340, an output signal DO is generated by the data transmission circuit 100 according to the received signal RXC and the echo cancellation signal EC 1. In some embodiments, the echo cancellation signal EC1 may cancel most of the echo in the analog end cancellation system to improve the signal-to-noise ratio of the echo cancellation system S1.

In the present disclosure, echoes in a system can be more effectively cancelled. Accordingly, the signal-to-noise ratio of the system can be improved. In addition, the precision of Effective number of bits (ENOB) of the system can be reduced, so as to save the cost. Furthermore, the requirement for jitter (jitter) can be reduced, and the operation can be performed in any interval.

In summary, in the echo cancellation system and the echo cancellation method of the present disclosure, the echo cancellation circuit generates the echo cancellation signal according to the signal with the higher sampling frequency. In this way, more noise can be eliminated to improve the signal-to-noise ratio of the echo cancellation system.

Various functional elements and blocks have been disclosed herein. It will be apparent to those of ordinary skill in the art that functional blocks may be implemented by circuits (whether dedicated circuits or general purpose circuits that operate under the control of one or more processors and coded instructions), which generally comprise transistors or other circuit elements for controlling the operation of the electrical circuits corresponding to the functions and operations described herein. It is further understood that the specific structure and interconnections of circuit elements in general may be determined by a compiler, such as a Register Transfer Language (RTL) compiler. A register transfer language compiler operates on scripts (scripts) that are fairly similar to assembly language code (assembly language code) and compiles the scripts into a form for layout or fabrication of the final circuit.

Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that of the appended claims.

Description of the reference numerals

100,1000 data transmission circuit

102,1131,1132,207,216 memory

104 oversampling circuit

106 shaping circuit

108 digital-to-analog converter

110 analog front end processing circuit

112 analog-to-digital conversion circuit

1121,1122 analog-to-digital converter

114 parallel-serial converting circuit

116 serial-to-parallel conversion circuit

118 filter circuit

1181,1182 Filter

200,300,2000 echo cancellation circuit

202 oversampling circuit

204,208,2181,2182 Filter circuit

206 random number generating circuit

2041,2042,2081,2082 Filter

210 oversampling circuit

212 shaping circuit

214 digital-to-analog converter

220 refresh circuit

S1, S2 echo cancellation system

AD1, AD2, AD3, AD4, AD5, AD6, AD7 adder

TX1, TX2, TX3 and TX4

Parallel signals of PD

Serial signal of SRD

RXC receiving signal

SD1, SD2, SD3 shaped signal

TXC, TXC1 analog signals

EC1, EC2 echo cancellation signals

DO output signal

AEC _ O, FO, DLF1, DLF2, F1, F2 filtered signals

PN random number

-PN inverse random number

CD1, CD2, CD3 operational signals

AFE _ O, AFE _ O1 processing signals

D _ ODD, D _ EVEN, DD1, D _ ODD1, D _ EVEN1 digital signals

COM combining circuit

3000 echo cancellation method

S310, S320, S330, S340 operation