阅读说明：本技术 具有极窄带通数字滤波的模数转换电路 (Analog-to-digital conversion circuit with very narrow bandpass digital filtering ) 是由 G·H·麦克吉布尼 P·T·格雷 G·D·莫里森 D·K·凡·奥斯特兰德 于 2020-03-23 设计创作，主要内容包括：模数转换电路包括模数转换器(ADC)电路,其可操作以将具有振荡频率的模拟信号转换为具有第一数据速率频率的第一数字信号,其中所述模拟信号包括一组纯音分量。ADC电路还包括数字抽取滤波电路,可操作以将第一数字信号转换为具有第二数据速率频率的第二数字信号。ADC电路还包括数字带通滤波器电路,可操作以将第二数字信号转换成具有第三数据速率频率的出站数字信号。数字带通滤波器电路被设置为产生带通区域,该带通区域的带宽被调谐以对所需纯音进行滤波。ADC电路还包括可操作以计算多个系数的系数处理器和可操作以选择所需纯音的处理模块。(The analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency to a first digital signal having a first data rate frequency, wherein the analog signal includes a set of pure tone components. The ADC circuit also includes a digital decimation filtering circuit operable to convert the first digital signal to a second digital signal having a second data rate frequency. The ADC circuit also includes a digital band-pass filter circuit operable to convert the second digital signal to an outbound digital signal having a third data rate frequency. The digital band pass filter circuit is arranged to produce a band pass region having a bandwidth tuned to filter the desired pure tone. The ADC circuit also includes a coefficient processor operable to calculate a plurality of coefficients and a processing module operable to select a desired pure tone.)

1. An analog-to-digital conversion circuit comprising:

an analog-to-digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency to a first digital signal having a first data rate frequency, wherein the analog signal includes a set of pure tone components;

a digital decimation filtering circuit operable to convert the first digital signal to a second digital signal having a second data rate frequency;

a digital Band Pass Filter (BPF) circuit comprising a plurality of taps having a plurality of coefficients, wherein the digital BPF circuit is operable to convert the second digital signal to an outbound digital signal having a third data rate frequency, wherein the plurality of coefficients for the plurality of taps are set to produce a band pass region approximately centered on an oscillation frequency of an analog signal and the band pass region has a bandwidth tuned to filter a desired pure tone of the set of pure tone components, wherein the first data rate frequency is a first integer multiple of the third data rate frequency, wherein the second data rate frequency is a second integer multiple of the third data rate frequency, and wherein the first data rate frequency is greater than the second data rate frequency;

a coefficient processor operable to calculate the plurality of coefficients based on the desired pure tone; and

a processing module operable to:

selecting the desired pure tone;

providing said desired pure tone to said digital BPF circuit and said coefficient processor; and

determining an impedance value from the outbound digital signal, wherein the outbound digital signal is a vector having a real component and an imaginary component.

2. The analog-to-digital conversion circuit of claim 1, further comprising:

the first data rate frequency is a third integer multiple of the second data rate frequency.

3. The analog-to-digital conversion circuit of claim 1, wherein the ADC circuit comprises an oversampling modulator and the digital decimation filtering circuit, wherein the oversampling modulator comprises:

a 1-bit sigma-delta modulator operable to convert the analog signal to a first digital signal of a 1-bit digital data stream having the first data rate frequency.

4. The analog-to-digital conversion circuit of claim 1, wherein the digital decimation filtering circuit comprises:

an anti-aliasing filter; and

an extractor.

5. The analog-to-digital conversion circuit of claim 1, wherein the digital BPF circuit further comprises:

a first BPF circuit for a first signal component of the analog signal; and

a second BPF circuit for a second signal component of the analog signal.

6. The analog-to-digital conversion circuit of claim 1, further comprising:

the first data rate frequency is 2 of the third data rate frequency¹⁷Doubling; and

the second data rate frequency is 2 of the third data rate frequency¹²And (4) doubling.

7. The analog-to-digital conversion circuit of claim 1, further comprising:

the first data rate frequency comprises a first bit rate for each interval;

the second data rate frequency comprises a second bit rate for each interval; and

the third data rate frequency comprises a third bit rate for each interval.

8. The analog-to-digital conversion circuit of claim 1, wherein the processing module is operable to select a desired pure tone based on one of:

one or more known desired pure tones in the set of pure tones; and

one or more regions of interest.

9. The analog-to-digital conversion circuit of claim 1, wherein a bandwidth tuned to filter the desired pure tone is less than a channel spacing of 0.05, and wherein the channel spacing is a bandwidth between two pure tones of the set of pure tone components.

10. A drive sensing system, comprising:

a comparator operable to generate an analog comparison signal by comparing a sense drive signal with a reference signal, wherein the analog comparison signal comprises an oscillation frequency and a set of pure tone components;

a drive circuit operable to:

generating a driving signal according to the feedback signal; and

providing the drive signal to a sensor, wherein a change in an electrical characteristic of the sensor causes a change in the drive signal, producing the sense drive signal;

an analog-to-digital converter (ADC) circuit operable to convert the analog comparison signal to a first digital signal having a first data rate frequency;

a digital-to-analog converter operable to convert the first digital signal to the feedback signal;

a digital decimation filtering circuit for converting the first digital signal to a second digital signal having a second data rate frequency;

a digital Band Pass Filter (BPF) circuit comprising a plurality of taps having a plurality of coefficients, wherein the digital BPF circuit is operable to convert the second digital signal to an outbound digital signal having a third data rate frequency, wherein the plurality of coefficients for the plurality of taps are set to produce a band pass region centered about an oscillation frequency of the analog comparison signal and having a bandwidth tuned to filter a desired pure tone of the set of pure tone components, wherein the first data rate frequency is a first integer multiple of the third data rate frequency, wherein the second data rate frequency is a second integer multiple of the third data rate frequency, and wherein the first data rate frequency is greater than the second data rate frequency;

a coefficient processor operable to calculate the plurality of coefficients based on the desired pure tone; and

a processing module operable to:

selecting the desired pure tone;

providing said desired pure tone to said digital BPF circuit and said coefficient processor; and

determining an impedance value from the outbound digital signal, wherein the outbound digital signal is a vector having a real component and an imaginary component.

11. The drive sensing system of claim 10, wherein the ADC circuit comprises an oversampling modulator and the digital decimation filter circuit, wherein the oversampling modulator comprises:

a 1-bit sigma-delta modulator operable to convert the analog comparison signal to a first digital signal of a 1-bit digital data stream having the first data rate frequency.

12. The drive sensing system of claim 10, wherein the digital decimation filter circuit comprises:

an anti-aliasing filter; and

an extractor.

13. The drive sensing system of claim 10, further comprising:

the first data rate frequency comprises a first bit rate for each interval;

the second data rate frequency comprises a second bit rate for each interval; and

the third data rate frequency comprises a third bit rate for each interval.

14. The drive sensing system of claim 10, wherein the processing module is operable to select the desired pure tone based on one of:

one or more known desired pure tones in the set of pure tones; and

one or more regions of interest.

15. The drive sensing system of claim 10, wherein the bandwidth tuned to filter the desired pure tone is less than a channel spacing of 0.05, wherein the channel spacing is the bandwidth between two pure tones of the set of pure tone components.

Technical Field

The present invention relates generally to data communication systems, and more particularly to sensory data collection and/or communication.

Background

Sensors are used in a wide variety of applications, from home automation, to industrial systems, to healthcare, to transportation, and so forth. For example, sensors are placed in bodies, cars, airplanes, boats, ships, trucks, motorcycles, cell phones, televisions, touch screens, factories, appliances, motors, cash registers, and the like for various applications.

Typically, sensors convert physical quantities into electrical or optical signals. For example, sensors convert physical phenomena, such as biological conditions, chemical conditions, electrical conditions, electromagnetic conditions, temperature, magnetic conditions, mechanical motion (position, velocity, acceleration, force, pressure), optical conditions, and/or radioactive conditions, into electrical signals.

The sensor includes a transducer for converting one form of energy (e.g., force) into another form of energy (e.g., an electrical signal). There are a variety of sensors that can support various applications of sensors. For example, the transducer is a capacitor, a piezoelectric transducer, a piezoresistive transducer, a thermal transducer, a thermocouple, a photoconductive transducer, such as a photoresistor, a photodiode, and/or a phototransistor.

Sensor circuitry is coupled to the sensor to provide power to the sensor and to receive signals from the sensor representative of the physical phenomenon. The sensor circuit includes at least three electrical connections to the sensor: one for the power supply; the other for a common voltage reference (e.g., ground); and a third for receiving signals representing physical phenomena. As the physical phenomenon changes from one extreme to the other (for the range of sensing physical phenomena), the signal representing the physical phenomenon will change with the supply voltage to ground.

The sensor circuitry provides the received sensor signals to one or more computing devices for processing. Computing devices are known for transferring data, processing data, and/or storing data. The computing device may be a cellular phone, laptop, tablet, Personal Computer (PC), workstation, video game device, server, and/or data center that supports millions of network searches, stock exchanges, or hourly online purchases.

The computing device processes the sensor signals for various applications. For example, the computing device processes the sensor signals to determine the temperature of various items in the refrigerated truck during transport. As another embodiment, the computing device processes the sensor signals to determine a touch on the touch screen. As yet another embodiment, the computing device processes the sensor signals to determine various data points in the product line.

Drawings

Fig. 1 is a schematic block diagram of an embodiment of a communication system according to the present invention;

FIG. 2 is a schematic block diagram of an embodiment of a computing device according to the present invention;

FIG. 3 is a schematic block diagram of another embodiment of a computing device in accordance with the present invention;

FIG. 4 is a schematic block diagram of another embodiment of a computing device in accordance with the present invention;

FIG. 5A is a schematic depiction of a computing subsystem according to the present invention;

FIG. 5B is a schematic block diagram of another embodiment of a compute subsystem in accordance with the present invention;

FIG. 5C is a schematic block diagram of another embodiment of a compute subsystem in accordance with the present invention;

FIG. 5D is a schematic block diagram of another embodiment of a compute subsystem in accordance with the present invention;

FIG. 5E is a schematic block diagram of another embodiment of a compute subsystem in accordance with the present invention;

FIG. 6 is a schematic block diagram of an embodiment of a drive sense circuit according to the present invention;

FIG. 6A is a schematic block diagram of another embodiment of a drive sense circuit according to the present invention;

FIG. 7 is an embodiment of a power signal diagram according to the present invention;

FIG. 8 is an embodiment of a sensor map according to the present invention;

FIG. 9 is a schematic block diagram of another embodiment of a power signal diagram in accordance with the present invention;

FIG. 10 is a schematic block diagram of another embodiment of a power signal diagram in accordance with the present invention;

FIG. 11 is a schematic block diagram of another embodiment of a power signal diagram in accordance with the present invention;

FIG. 11A is a schematic block diagram of another embodiment of a power signal diagram in accordance with the present invention;

FIG. 12 is a schematic block diagram of an embodiment of a power signal change detection circuit in accordance with the present invention;

FIG. 13 is a schematic block diagram of another embodiment of a drive sense circuit in accordance with the present invention;

FIG. 14 is a schematic block diagram of an embodiment of a drive sense circuit with a programmed reference generator in accordance with the present invention;

FIG. 15 is a schematic block diagram of an embodiment of a data sensing circuit according to the present invention;

FIG. 16 is a schematic block diagram of another embodiment of a data sensing circuit in accordance with the present invention;

FIG. 17 is a schematic block diagram of an embodiment of a data circuit in accordance with the present invention;

FIG. 18 is a schematic block diagram of an embodiment of an analog-to-digital conversion circuit in accordance with the present invention;

FIG. 19 is a schematic block diagram of another embodiment of an analog-to-digital conversion circuit in accordance with the present invention;

FIGS. 20A-20B are exemplary graphs plotting condition versus capacitance according to the present invention;

FIG. 21 is an exemplary graph plotting input impedance versus frequency according to the present invention;

FIG. 22 is an embodiment of an impact value according to the present invention;

fig. 23 is a schematic block diagram of an embodiment of a sigma-delta analog-to-digital (ADC) circuit according to the present invention;

fig. 24 is an embodiment of the quantization noise of a sigma-delta oversampling modulator according to the present invention;

FIG. 25 is a schematic block diagram of exemplary outputs of different stages of an analog-to-digital conversion circuit in accordance with the present invention;

FIG. 26 is an embodiment of sampling an analog signal to produce a digitized signal in accordance with the invention;

FIG. 27 is a schematic block diagram of a digital filter implementing a multiply-accumulate function according to the present invention;

FIG. 28 is a schematic block diagram of a digital filter implementing a multiply-accumulate function in accordance with the present invention;

FIG. 29 is an embodiment of a digitized signal according to the invention;

FIG. 30 is an embodiment of generating a digitally filtered output in accordance with the present invention;

FIG. 31 is a schematic block diagram of an embodiment of a digital decimation filter circuit according to the present invention;

FIG. 32 is an exemplary frequency response H (z) of the anti-aliasing filter according to the invention;

FIG. 33 is a schematic block diagram of an embodiment of an anti-aliasing filter according to the present invention;

FIG. 34 is a schematic block diagram of an embodiment of a decimator in accordance with the present invention;

FIG. 35 is an embodiment of a frequency band with frequency channels in accordance with the present invention;

FIG. 36 is a schematic block diagram of another embodiment of a digital decimation filter circuit according to the present invention;

FIG. 37 is a schematic block diagram of another embodiment of a digital decimation filter circuit according to the present invention;

FIG. 38 is a schematic block diagram of an embodiment of a polyphase filter of the digital decimation filter circuit according to the present invention;

FIG. 39 is a schematic block diagram of another embodiment of a digital decimation filter circuit according to the present invention;

FIG. 40 is a schematic block diagram of an embodiment of a shift register memory in accordance with the present invention;

FIG. 41 is a schematic block diagram of another embodiment of a digital decimation filter circuit according to the present invention;

fig. 42 is an embodiment of a frequency band having n frequency channels in accordance with the present invention;

FIG. 43 is a schematic block diagram of an embodiment of a digital Band Pass Filter (BPF) circuit according to the present invention;

FIG. 44 is an exemplary frequency response H (z) of a digital Band Pass Filter (BPF) circuit according to the present invention;

FIG. 45 is an exemplary frequency response H (z) of a digital Band Pass Filter (BPF) circuit according to the present invention;

46A-46D are embodiments of processing signals through a digital Band Pass Filter (BPF) circuit according to the present invention;

FIGS. 47A-47D are embodiments of processing signals by a digital Band Pass Filter (BPF) circuit according to the present invention;

FIG. 48 is a schematic block diagram of an embodiment of a digital Band Pass Filter (BPF) circuit in accordance with the present invention;

FIG. 49 is a schematic block diagram of another embodiment of an analog to digital conversion circuit in accordance with the present invention;

FIG. 50 is a schematic block diagram of an embodiment of a first Band Pass Filter (BPF) circuit in accordance with the present invention;

FIG. 51 is a schematic block diagram of an embodiment of a second Band Pass Filter (BPF) circuit according to the present invention;

FIG. 52 is a schematic block diagram of an embodiment of a coefficient processor in accordance with the present invention;

FIG. 53 is a schematic block diagram of another embodiment of an analog to digital conversion circuit in accordance with the present invention; and

FIG. 54 is a schematic block diagram of an embodiment of processing module control within an analog-to-digital conversion circuit.

Detailed Description

FIG. 1 is a schematic block diagram of an embodiment of a communication system 10 including a plurality of computing devices 12-10, one or more servers 22, one or more databases 24, one or more networks 26, a plurality of drive sensing circuits 28, a plurality of sensors 30, and a plurality of actuators 32. The computing device 14 includes a touch screen 16 having sensor and drive sensor circuitry, and the computing device 18 includes a touch and haptic screen 20 including sensors, actuators, and drive sensing circuitry.

The sensor 30 is used to convert a physical input into an electrical output and/or an optical output. The physical input of the sensor may be one of a variety of physical input conditions. For example, physical conditions include, but are not limited to, one or more of the following: acoustic waves (e.g., amplitude, phase, polarization, frequency spectrum, and/or wave velocity); biological and/or chemical conditions (e.g., fluid concentration, level, composition, etc.); electrical conditions (e.g., charge, voltage, current, conductivity, permittivity, electric field, including amplitude, phase, and/or polarization); magnetic conditions (e.g., flux, permeability, magnetic field, including amplitude, phase, and/or polarization); optical conditions (e.g., refractive index, reflectivity, absorptivity, etc.); thermal conditions (e.g., temperature, flux, specific heat, thermal conductivity, etc.); and mechanical conditions (e.g., position, velocity, acceleration, force, strain, stress, pressure, torque, etc.). For example, piezoelectric sensors convert force or pressure into an electrical signal. As another example, a microphone converts audible sound waves into electrical signals.

There are many types of sensors to sense various types of physical conditions. Sensor types include, but are not limited to, capacitive sensors, inductive sensors, accelerometers, piezoelectric sensors, light sensors, magnetic field sensors, ultrasonic sensors, temperature sensors, Infrared (IR) sensors, touch sensors, proximity sensors, pressure sensors, liquid level sensors, smoke sensors, and gas sensors. In many aspects, the sensors serve as an interface between the physical world and the digital world by converting real world conditions into digital signals that are then processed by a computing device for a number of applications including, but not limited to, medical applications, production automation applications, home environmental control, public safety, and the like.

Each type of sensor has a variety of sensor characteristics that are factors in providing power to the sensor, receiving signals from the sensor, and/or interpreting signals from the sensor. Sensor characteristics include resistance, reactance, power requirements, sensitivity, range, stability, repeatability, linearity, error, response time, and/or frequency response. For example, resistance, reactance, and/or power requirements are factors that determine the requirements of the drive circuit. As another example, sensitivity, stability, and/or linearity are factors used to interpret a measure of a physical condition (e.g., a measure of temperature, pressure, etc.) based on a received electrical and/or optical signal.

The actuator 32 converts an electrical input into a physical output. The physical output of the actuator may be one of a variety of physical output conditions. For example, physical output conditions include, but are not limited to, one or more acoustic waves (e.g., amplitude, phase, polarization, spectrum, and/or wave speed); magnetic conditions (e.g., flux, permeability, magnetic field, including amplitude, phase, and/or polarization); thermal conditions (e.g., temperature, flux, specific heat, thermal conductivity, etc.); and mechanical conditions (e.g., position, velocity, acceleration, force, strain, stress, pressure, torque, etc.). As an example, a piezoelectric actuator converts a voltage into a force or pressure. As another example, a speaker converts electrical signals into audible sound waves.

The actuator 32 may be one of a variety of actuators. For example, the actuator 32 is a comb drive, a digital micromirror device, an electric motor, an electroactive polymer, a hydraulic cylinder, a piezoelectric actuator, a pneumatic actuator, a screw jack, a servo mechanism, a solenoid, a stepper motor, a shape memory alloy, a thermal bimorph, and a hydraulic actuator.

Each type of actuator has a variety of actuator characteristics that are factors in powering and signaling the actuator to achieve the desired performance. The actuator characteristics include resistance, reactance, power requirements, sensitivity, range, stability, repeatability, linearity, error, response time, and/or frequency response. For example, resistance, reactance, and power requirements are factors that determine the requirements of the drive circuit. As another example, sensitivity, stability, and/or linearity are factors for generating a signal that is sent to the actuator to obtain the desired physical output condition.

Computing devices 12, 14, and 18 may each be a portable computing device and/or a stationary computing device. The portable computing device may be a social networking device, a gaming device, a cell phone, a smart phone, a digital assistant, a digital music player, a digital video player, a laptop computer, a handheld computer, a tablet computer, a video game controller, and/or any other portable device that includes a computing core. The stationary computing device may be a computer (PC), a computer server, a cable set-top box, a satellite receiver, a television, a printer, a facsimile machine, a home entertainment appliance, a video game console, and/or any type of home or office computing device. Computing devices 12, 14, and 18 will be discussed in more detail with reference to one or more of fig. 2-4.

The server 22 is a special type of computing device optimized for processing large data requests in parallel. Server 22 includes similar components to those of computing devices 12, 14, and/or 18, with more robust processing modules, more main memory, and/or more hard drive storage (e.g., solid state, hard drive, etc.). In addition, the server 22 is typically accessed remotely; thus, it typically does not include user input means and/or user output means. Further, the server may be a stand-alone separate computing device and/or may be a cloud computing device.

Database 24 is a special type of computing device that is optimized for large-scale data storage and retrieval. Database 24 includes components similar to those of computing devices 12, 14, and/or 18, with more hard drive storage (e.g., solid state, hard drive, etc.) and possibly more processing modules and/or main memory. In addition, the database 24 is typically accessed remotely; thus, it typically does not include user input means and/or user output means. Further, the database 24 may be a stand-alone, separate computing device and/or may be a cloud computing device.

The network 26 includes one or more Local Area Networks (LANs) and/or one or more Wide Area Networks (WANs), which may be public and/or private networks. The LAN may be a wireless LAN (e.g., Wi-Fi access point, bluetooth, ZigBee, etc.) and/or a wired network (e.g., Firewire, ethernet, etc.). The WAN may be a wired and/or wireless WAN. For example, a LAN may be a wireless network of an individual home or business, while a WAN is the Internet, cellular telephone infrastructure, and/or satellite communications infrastructure.

In an embodiment of operation, the computing device 12-1 is in communication with a plurality of drive sensing circuits 28, which plurality of drive sensing circuits 28 are in turn in communication with a plurality of sensors 30. The sensor 30 and/or the drive sensing circuit 28 are located within and/or external to the computing device 12-1. For example, sensor 30 may be external to computing device 12-1 and drive sensing circuitry within computing device 12-1. As another example, sensor 30 and drive sense circuit 28 are both external to computing device 12-1. When the drive sense circuits 28 are external to the computing device, they are coupled to the computing device 12-1 via a wired and/or wireless communication link, as will be discussed in more detail with reference to one or more of fig. 5A-5C.

Computing device 12-1 communicates with drive sense circuitry 28 to: (a) turn them on, (b) acquire data from the sensors (individually and/or collectively), (c) instruct the drive sensing circuitry how to communicate the sensed data to computing device 12-1, (d) provide signal attributes for use with the sensors (e.g., direct current level, alternating current level, frequency, power level, regulated current signal, regulated voltage signal, impedance adjustments, frequency patterns of various sensors, different frequencies for different sensing applications, etc.), and/or (e) provide other commands and/or instructions.

As a particular embodiment, sensors 30 are distributed along the pipe to measure flow rate and/or pressure within a section of the pipe. The drive sensing circuits 28 have their own power source (e.g., battery, power supply, etc.) and are located proximal to their respective sensors 30. At desired time intervals (milliseconds, seconds, minutes, hours, etc.), drive sensing circuit 28 provides a regulated source signal or power signal to sensor 30. The electrical characteristics of the sensor 30 affect the conditioned source signal or power signal, which reflects the condition (e.g., flow rate and/or pressure) that the sensor is sensing.

The drive sense circuit 28 detects the effect on the conditioned source signal or power signal as a result of the electrical characteristics of the sensor. Drive sense circuit 28 then generates a signal representing a change to the adjusted source signal or power signal based on the detected effect on the power signal. Changes in the conditioned source signal or power signal are representative of the conditions sensed by sensor 30.

Drive sense circuit 28 provides a signal representative of the condition to computing device 12-1. The representative signal may be an analog signal or a digital signal. In either case, the computing device 12-1 interprets the representative signals to determine the pressure and/or flow rate at each sensor location along the pipeline. The computing device may then provide the information to server 22, database 24, and/or another computing device for storage and/or further processing.

As another embodiment of operation, computing device 12-2 is coupled to drive sense circuitry 28, which drive sense circuitry 28 is in turn coupled to sensor 30. The sensor 30 and/or the drive sensing circuit 28 may be internal and/or external to the computing device 12-2. In this embodiment, sensor 30 is sensing a condition specific to computing device 12-2. For example, the sensor 30 may be a temperature sensor, an ambient light sensor, an ambient noise sensor, or the like. As described above, when instructed by the computing device 12-2 (which may be a default setting for continuous sensing or a periodic interval), the drive sense circuitry 28 provides the adjusted source signal or power signal to the sensor 30 and detects the effect on the adjusted source signal or power signal based on the electrical characteristics of the sensor. The drive sense circuit generates and sends a signal representative of this effect to computing device 12-2.

In another embodiment of operation, the computing device 12-3 is coupled to a plurality of drive sensing circuits 28, the plurality of drive sensing circuits 28 coupled to a plurality of sensors 30 and to a plurality of drive sensing circuits 28, the plurality of drive sensing circuits 28 coupled to a plurality of actuators 32. The general function of the drive sense circuit 28 coupled to the sensor 30 is in accordance with the description above.

Since the actuator 32 is essentially the inverse of the sensor, the drive sensing circuit 28 may be used to power the actuator 32 because the actuator converts electrical signals to physical conditions and the sensor converts physical conditions to electrical signals. Thus, in this embodiment, the computing device 12-3 provides an actuation signal to the drive sensing circuit 28 of the actuator 32. The drive sense circuit modulates the actuation signal into a power signal or a regulated control signal that is provided to the actuator 32. The actuator 32 is powered by a power signal or a regulated control signal and produces the desired physical condition from the modulated actuation signal.

As another embodiment of operation, computing device 12-x is coupled to drive sensing circuitry 28 coupled with sensors 30 and to drive sensing circuitry 28 coupled with actuators 32. In this embodiment, the sensor 30 and actuator 32 are used by the computing device 12-x. For example, the sensor 30 may be a piezoelectric microphone and the actuator 32 may be a piezoelectric speaker.

FIG. 2 is a schematic block diagram of an implementation of computing device 12 (e.g., any of 12-1 through 12-x). Computing device 12 includes a core control module 40, one or more processing modules 42, one or more main memories 44, a cache memory 46, a video graphics processing module 48, a display 50, an input-output (I/O) peripheral device control module 52, one or more input interface modules 56, one or more output interface modules 58, one or more network interface modules 60, and one or more memory interface modules 62. The processing module 42 is described in more detail at the end of the detailed description of the present section, and in an alternative embodiment, the processing module 42 has a directed connection to the main memory 44. In alternative embodiments, core control module 40 and I/O and/or peripheral control module 52 are one module, such as a chipset, a Quick Path Interconnect (QPI), and/or a hyper path interconnect (UPI).

Each main memory 44 includes one or more Random Access Memory (RAM) integrated circuits or chips. For example, the main memory 44 includes four DDR4 (fourth generation double data Rate) RAM chips, each operating at a rate of 2,400 MHz. In general, main memory 44 stores data and operating instructions most relevant to processing module 42. For example, the core control module 40 coordinates the transfer of data and/or operating instructions from the main memory 44 and the memories 64-66. The data and/or operating instructions retrieved from memories 64-66 are the data and/or operating instructions requested by the processing module or most likely required by the processing module. When the processing module completes the data and/or operational instructions in main memory, the core control module 40 coordinates the sending of updated data to the memories 64-66 for storage.

The memories 64-66 include one or more hard disk drives, one or more solid state memory chips, and/or one or more other mass storage devices that are relatively inexpensive with respect to the amount of data stored compared to cache memory and main storage devices. Memories 64-66 are coupled to core control module 40 via I/O and/or peripheral control module 52 and via one or more memory interface modules 62. In one embodiment, I/O and/or peripheral control module 52 includes one or more Peripheral Component Interface (PCI) buses via which peripheral components are connected to core control module 40. Memory interface module 62 includes software drivers and hardware connectors for coupling memory devices to I/O and/or peripheral control module 52. For example, the memory interface 62 conforms to a Serial Advanced Technology Attachment (SATA) port.

The core control module 40 coordinates data communications between the processing module 42 and the network 26 through the I/O and/or peripheral control modules 52, the network interface module 60, and the network cards 68 or 70. The network card 68 or 70 includes a wireless communication unit or a wired communication unit. The wireless communication unit includes a Wireless Local Area Network (WLAN) communication device, a cellular communication device, a bluetooth device, and/or a ZigBee communication device. The wired communication unit includes a gigabit LAN connection, a firewire connection, and/or a proprietary computer wired connection. The network interface module 60 includes software drivers and hardware connectors for coupling a network card to the I/O and/or peripheral control module 52. For example, network interface module 60 conforms to one or more versions of IEEE 802.11, a cellular telephone protocol, 10/100/1000 gigabit LAN protocol, and the like.

Core control module 40 coordinates data communication between processing module 42 and input device 72 through input interface module 56 and I/O and/or peripheral control module 52. The input device 72 includes a keypad, keyboard, control switches, touch pad, microphone, camera, and the like. Input interface module 56 includes software drivers and hardware connectors for coupling input devices to I/O and/or peripheral control module 52. In one embodiment, the input interface module 56 conforms to one or more Universal Serial Bus (USB) protocols.

Core control module 40 coordinates data communications between processing module 42 and output device 74 via output interface module 58 and I/O and/or peripheral control module 52. The output device 74 includes a speaker or the like. The output interface module 58 includes software drivers and hardware connectors for coupling output devices to the I/O and/or peripheral control module 52. In one embodiment, output interface module 56 conforms to one or more audio codec protocols.

The processing module 42 communicates directly with the video graphics processing module 48 to display data on the display 50. The display 50 includes an LED (light emitting diode) display, an LCD (liquid crystal display), and/or other types of display technologies. The display has resolution, aspect ratio and other characteristics that affect the quality of the display. Video graphics processing module 48 receives data from processing module 42, processes the data according to characteristics of the display to generate rendering data, and provides the rendering data to display 50.

Fig. 2 further illustrates the sensor 30 and actuator 32 coupled to the drive sensing circuit 28, the drive sensing circuit 28 being coupled to an input interface module 56 (e.g., a USB port). Alternatively, one or more of the drive sense circuits 28 are coupled to the computing device via a wireless network card (e.g., WLAN) or a wired network card (e.g., gigabit LAN). Although not shown, the computing device 12 also includes a BIOS (basic input output System) memory coupled to the core control module 40.

FIG. 3 is a schematic block diagram of another embodiment of computing device 14, which includes a core control module 40, one or more processing modules 42, one or more main memories 44, a cache memory 46, a video graphics processing module 48, touchscreen 16, an input-output (I/O) peripheral control module 52, one or more input interface modules 56, one or more output interface modules 58, one or more network interface modules 60, and one or more memory interface modules 62. The touch screen 16 includes a touch screen display 80, a plurality of sensors 30, a plurality of Drive Sensing Circuits (DSCs), and a touch screen processing module 82.

Computing device 14 operates similarly to computing device 12 of fig. 2, with the addition of a touch screen as an input device. The touch screen includes a plurality of sensors (e.g., electrodes, capacitor sensing units, capacitor sensors, inductance sensors, etc.) to detect a near-side touch of the screen. For example, when one or more fingers touch the screen, the capacitance of the sensor(s) proximate to the touch may be affected (e.g., impedance changes). Drive Sensing Circuitry (DSC) coupled to the affected sensors detects the changes and provides a representation of the changes to the touch screen processing module 82, and the touch screen processing module 82 may be a separate processing module or integrated into the processing module 42.

The touch screen processing module 82 processes the representative signals from the Drive Sensing Circuit (DSC) to determine the location of the touch. This information is input to the processing module 42 for processing as input. For example, the touch indicates selection of a button on the screen, a scroll function, a zoom-in and zoom-out function, and the like.

FIG. 4 is a schematic block diagram of another embodiment of computing device 18, which includes a core control module 40, one or more processing modules 42, one or more main memories 44, a cache memory 46, a video graphics processing module 48, a touch and haptic screen 20, an input-output (I/O) peripheral control module 52, one or more input interface modules 56, one or more output interface modules 58, one or more network interface modules 60, and one or more memory interface modules 62. The touch and tactile screen 20 includes a touch and tactile screen display 90, a plurality of sensors 30, a plurality of actuators 32, a plurality of Drive Sensing Circuits (DSCs), a touch screen processing module 82, a touch screen processing module 92.

Computing device 18 operates similarly to computing device 14 of fig. 3, with the addition of a tactile aspect to screen 20 as an output device. The haptic portion of the screen 20 includes a plurality of actuators (e.g., piezoelectric transducers that generate vibrations, solenoids that generate motion, etc.) to provide a tactile sensation to the screen 20. To this end, the processing module generates haptic data, which is provided to a suitable Drive Sensing Circuit (DSC) by a touch screen processing module 92, which touch screen processing module 92 may be a separate processing module or integrated into the processing module 42. Drive Sensing Circuitry (DSC) converts the haptic data into drive signals and provides them to the appropriate actuators to produce the desired haptic sensation on the screen 20.

FIG. 5A is a schematic depiction of a computing subsystem 25, the computing subsystem 25 including a sensing data processing module 65, a plurality of communication modules 61A-x, a plurality of processing modules 42A-x, a plurality of drive sensing circuits 28, and a plurality of sensors 1-x, which sensors 1-x may be the sensors 30 of FIG. 1. Sensed data processing module 65 is one or more processing modules within one or more servers 22 and/or one or more processing modules in one or more computing devices different from the computing device in which processing modules 42A-x are located.

The drive sense circuit 28 (or drive sense circuits), the processing module (e.g., 41A), and the communication module (e.g., 61A) are within a common computing device. Each group of drive sensing circuitry, processing module, and communication module is in a separate computing device. The communication modules 61A-x are constructed in accordance with one or more wired communication protocols and/or one or more wireless communication protocols that conform to one or more of the Open Systems Interconnection (OSI) model, the transmission control protocol/internet protocol (TCP/IP) model, and other communication protocol modules.

In an embodiment of operation, a processing module (e.g., 42A) provides control signals to its corresponding drive sense circuit 28. Processing module 42A may generate a control signal, receive it from sensing data processing module 65, or receive an indication from sensing data processing module 65 to generate a control signal. The control signals enable the drive sense circuit 28 to provide drive signals to its corresponding sensor. The control signal may also include a reference signal having one or more frequency components to facilitate creation of the drive signal and/or to interpret the sense signal received from the sensor.

Based on the control signal, the drive sense circuit 28 provides a drive signal to its corresponding sensor (e.g., 1) on the drive & sense line. While receiving the drive signal (e.g., power supply signal, conditioned source signal, etc.), the sensor senses a physical condition 1-x (e.g., acoustic wave, biological condition, chemical condition, electrical condition, magnetic condition, optical condition, thermal condition, and/or mechanical condition). As a result of the physical conditions, electrical characteristics of the sensor (e.g., impedance, voltage, current, capacitance, inductance, resistance, reactance, etc.) change, thereby affecting the drive signal. Note that if the sensor is an optical sensor, it will convert the sensed optical condition into an electrical characteristic.

Drive sense circuitry 28 detects the effect on the drive signal via the drive & sense lines and processes the effect to produce a signal representative of the power change, which may be an analog or digital signal. The processing module 42A receives the signal representative of the power change, interprets it, and generates a value representative of the sensed physical condition. For example, if the sensor senses pressure, the value representing the sensed physical condition is a measure of pressure (e.g., x PSI).

In accordance with the sensed data processing function (e.g., algorithm, application, etc.), the sensed data processing module 65 collects values from the processing module that are representative of the sensed physical condition. Since sensors 1-x may be the same type of sensor (e.g., pressure sensor), each sensor may be a different sensor, or a combination thereof; the physical conditions sensed may be the same, may each be different, or a combination thereof. The sensed data processing module 65 processes the collected values to produce one or more desired results. For example, if the computing subsystem 25 is monitoring pressure along a pipeline, processing of the collected values indicates that the pressures are all within normal limits or that one or more of the sensed pressures are not within normal limits.

As another example, if computing subsystem 25 is used in a manufacturing facility, the sensors sense various physical conditions, such as sound waves (e.g., for sound insulation, sound generation, ultrasonic monitoring, etc.), biological conditions (e.g., bacterial contamination, etc.), chemical conditions (e.g., composition, gas concentration, etc.), electrical conditions (e.g., current levels, voltage levels, electromagnetic interference, etc.), magnetic stripe pieces (e.g., induced current, magnetic field strength, magnetic field orientation, etc.), optical conditions (e.g., ambient light, infrared, etc.), thermal conditions (e.g., temperature, etc.), and/or mechanical conditions (e.g., physical location, force, pressure, acceleration, etc.).

Computing subsystem 25 may also include one or more actuators in place of and/or in addition to one or more sensors. When computing subsystems 25 include actuators, the respective processing modules provide actuation control signals to the respective drive sensing circuits 28. The actuation control signals enable the drive sense circuitry 28 to provide drive signals to the actuators (e.g., similar to the drive and sense lines, but for the actuators) through the drive and actuation lines. The drive signal includes one or more frequency components and/or amplitude components to facilitate desired actuation of the actuator.

Further, the computing subsystem 25 may include cooperating actuators and sensors. For example, the sensor is sensing a physical condition of the actuator. In this embodiment, the drive sense circuit provides a drive signal to the actuator, while the other drive sense signal provides the same drive signal or a scaled version thereof to the sensor. This allows the sensor to provide near instantaneous and continuous sensing of the physical condition of the actuator. This further allows the sensor to operate at a first frequency and the actuator to operate at a second frequency.

In one embodiment, the computing subsystem is a stand-alone system for a variety of applications (e.g., manufacturing, plumbing, testing, monitoring, security, etc.). In another embodiment, computing subsystem 25 is one of a plurality of subsystems forming a larger system. For example, different subsystems are employed based on geographic location. As a specific example, a compute subsystem 25 is deployed in one part of a plant and another compute subsystem is deployed in another part of the plant. As another example, different subsystems may be employed based on their functionality. As a specific example, one subsystem monitors traffic light operation in a city and another subsystem monitors sewage treatment plants in the city.

Regardless of the use and/or deployment of the computing system, the physical conditions it senses, and/or the physical conditions it is actuating, each sensor and each actuator (if included) is driven and sensed by a single line, as opposed to separate drive and sense lines. This provides a number of advantages including, but not limited to, lower power requirements, better ability to drive high impedance sensors, lower line-to-line interference, and/or concurrent sensing functionality.

FIG. 5B is a schematic block diagram of another embodiment of computing subsystem 25, which includes a sensed data processing module 65, a communication module 61, a plurality of processing modules 42A-x, a plurality of drive sensing circuits 28, and a plurality of sensors 1-x, which sensors 1-x may be sensors 30 of FIG. 1. Sensed data processing module 65 is one or more processing modules in one or more servers 22 and/or one or more processing modules in one or more computing devices different from the computing device in which processing modules 42A-x are located.

In one embodiment, the drive sensing circuit 28, the processing module, and the communication module are within a common computing device. For example, a computing device includes a central processing unit that includes a plurality of processing modules. The functions and operations of the sensed data processing module 65, the communication module 61, the processing modules 42A-x, the drive sensing circuit 28, and the sensors 1-x are as discussed with reference to fig. 5A.

FIG. 5C is a schematic block diagram of another embodiment of computing subsystem 25, computing subsystem 25 including sensed data processing module 65, communication module 61, processing module 42, plurality of drive sensing circuits 28, and plurality of sensors 1-x, which may be sensors 30 of FIG. 1. Sensed data processing module 65 is one or more processing modules within one or more servers 22 and/or one or more processing modules in one or more computing devices different from the computing device in which processing module 42 is located.

In one embodiment, the drive sensing circuit 28, the processing module, and the communication module are within a common computing device. The functions and operations of the sensed data processing module 65, the communication module 61, the processing module 42, the drive sensing circuit 28, and the sensors 1-x are as discussed with reference to fig. 5A.

FIG. 5D is a schematic block diagram of another embodiment of the compute subsystem 25, which includes a processing module 42, a reference signal circuit 100, a plurality of drive sense circuits 28, and a plurality of sensors 30. The processing module 42 includes a drive sense processing block 104, a drive sense control block 102, and a reference control block 106. Each of the blocks 102, 106 of the process module 42 may be implemented by a separate module of the process module, may be a combination of software and hardware within the process module, and/or may be a field programmable module within the process module 42.

In an embodiment of operation, the drive sense control block 104 generates one or more control signals to activate one or more drive sense circuits 28. For example, drive sense control block 102 generates a control signal that enables drive sense circuit 28 for a given period of time (e.g., 1 second, 1 minute, etc.). As another embodiment, the drive sense control block 102 generates control signals to sequentially enable the drive sense circuits 28. As yet another embodiment, the drive sense control block 102 generates a series of control signals to periodically enable the drive sense circuit 28 (e.g., once per second, per minute, per hour, etc.).

Continuing the operational embodiment, the reference control block 106 generates a reference control signal that is provided to the reference signal circuit 100. The reference signal circuit 100 generates one or more reference signals for driving the sensing circuit 28 according to the control signal. For example, the control signal is an enable signal and, in response, the reference signal circuit 100 generates a preprogrammed reference signal that provides the preprogrammed reference signal to the drive sense circuit 28. In another embodiment, the reference signal circuit 100 generates a unique reference signal for each of the drive sense circuits 28. In yet another embodiment, the reference signal circuit 100 generates a first unique reference signal for each of the drive sense circuits 28 in the first group and a second unique reference signal for each of the drive sense circuits 28 in the second group.

The reference signal circuit 100 may be implemented in a variety of ways. For example, the reference signal circuit 100 includes a DC (direct current) voltage generator, an AC voltage generator, and a voltage combining circuit. The DC voltage generator generates a DC voltage of a first level, and the AC voltage generator generates an AC voltage of a second level, the second level being less than or equal to the first level. The voltage combining circuit combines the DC voltage and the AC voltage to generate a reference signal. As an example, reference signal circuit 100 generates a reference signal similar to the signal shown in fig. 7, which will be discussed later.

As another embodiment, the reference signal circuit 100 includes a DC current generator, an AC current generator, and a current combining circuit. The DC current generator generates a DC current at a first current level and the AC current generator generates an AC current at a second current level, the second current level being less than or equal to the first current level. The current combining circuit combines the DC and AC currents to generate a reference signal.

Returning to the operational embodiment, the reference signal circuit 100 provides one or more reference signals to the drive sense circuit 28. When the drive sense circuit 28 is enabled via a control signal from the drive sense control block 102, it provides a drive signal to its corresponding sensor 30. As a result of the physical condition, the electrical characteristics of the sensor change, which affects the drive signal. Based on the detected effects on the drive signal and the reference signal, the drive sense circuit 28 generates a signal representative of the effect on the drive signal.

The drive sense circuit provides a signal representative of the effect on the drive signal to the drive sense processing block 104. Drive sense processing block 104 processes the representative signal to generate a sensed value 97 of the physical condition (e.g., a digital value representative of a particular temperature, a particular pressure level, etc.). Processing module 42 provides sensed value 97 to another application running on the computing device, another computing device, and/or server 22.

FIG. 5E is a schematic block diagram of another embodiment of compute subsystem 25 including processing module 42, a plurality of drive sense circuits 28, and a plurality of sensors 30. This embodiment is similar to the embodiment of FIG. 5D, showing the functionality of the drive sense processing block 104, the drive sense control block 102, and the reference control block 106 in more detail. For example, the drive sense control block 102 includes separate enable/disable blocks 102-1 through 102-y. The enable/disable block is used to enable or disable the corresponding drive sense circuit in the manner as discussed above with reference to FIG. 5D.

Drive sense processing block 104 includes variance determination blocks 104-1a through y and variance interpretation blocks 104-2a through y. For example, variance determination module 104-1a receives signals from the corresponding drive sense circuit 28 that are representative of the physical condition sensed by the sensor. The variance determination module 104-1a is used to determine the difference between the signal representative of the sensed physical condition and the signal representative of a known or reference physical condition. Variance interpretation module 104-1b interprets the difference to determine a particular value of the sensed physical condition.

As a specific example, the variance determination module 104-1a receives a digital signal 10010110 (150 decimal) from the corresponding drive sense circuit 28 that is representative of the sensed physical condition (e.g., temperature) sensed by the sensor. For 8 bits, there are 28(256) possible signals representing the sensed physical condition. Assuming the temperature units are degrees celsius, the numerical value 01000000 (64 decimal) represents a known value of 25 degrees celsius. The variance determination module 104-b1 determines the difference between the digital signal representing the sensed value (e.g., 10010110, 150 decimal) and the known signal value (e.g., 01000000, 64 decimal), i.e., 00110000 (86 decimal). The variance determination module 104-b1 then determines a sensed value based on the difference and the known value. In this embodiment, the sensed value is equal to 25+86 (100/256) ═ 25+33.6 ═ 58.6 degrees celsius.

FIG. 6 is a schematic block diagram of drive center circuit 28-a coupled to sensor 30. The drive sensing circuit 28 includes a power supply circuit 110 and a power supply signal change detection circuit 112. The sensor 30 includes one or more transducers having varying electrical characteristics (e.g., capacitance, inductance, impedance, current, voltage, etc.) based on varying physical conditions 114 (e.g., pressure, temperature, biological, chemical, etc.), and vice versa (e.g., actuators).

The power circuit 110 is operatively coupled to the sensor 30 and provides a power signal 116 to the sensor 30 when enabled (e.g., based on a control signal from the processing module 42, applying power, closing a switch, receiving a reference signal, etc.). The power supply circuit 110 may be a voltage supply circuit (e.g., a battery, a linear regulator, an unregulated DC-DC converter, etc.) that generates a voltage-based power signal, a current source circuit (e.g., a current source circuit, a current mirror circuit, etc.) that generates a current-based power signal, or a circuit that provides a desired power level to the sensor and substantially matches the impedance of the sensor. The power supply circuit 110 generates a power signal 116 that includes a DC (direct current) component and/or an oscillating component.

When the power signal 116 is received and when exposed to the condition 114, the electrical characteristics of the sensor affect 118 the power signal. When the power signal change detection circuit 112 is enabled, it detects the effect 118 on the power signal as a result of the electrical characteristics of the sensor. For example, the power signal is a 1.5 voltage signal, and under a first condition, the sensor consumes 1 milliamp of current, which corresponds to an impedance of 1.5K ohms. In the second condition, the power supply signal is held at 1.5 volts and the current is increased to 1.5 milliamps. Therefore, from condition 1 to condition 2, the impedance of the sensor changes from 1.5K ohms to 1K ohms. The power signal change detection circuit 112 determines the change and generates a representative signal 120 of the change in the power signal.

As another example, the power signal is a 1.5 voltage signal and under a first condition, the sensor consumes 1 milliamp of current, which corresponds to an impedance of 1.5K ohms. In the second condition, the power supply signal drops to 1.3 volts and the current increases to 1.3 milliamps. Therefore, from condition 1 to condition 2, the impedance of the sensor changes from 1.5K ohms to 1K ohms. The power signal change detection circuit 112 determines the change and generates a representative signal 120 of the change in the power signal.

As shown in fig. 7, the power signal 116 includes a DC component 122 and/or an oscillating component 124. The oscillating component 124 includes a sinusoidal signal, a square wave signal, a triangular wave signal, a multilevel signal (e.g., having a time-varying amplitude relative to the DC component), and/or a polygonal signal (e.g., having a symmetrical or asymmetrical polygonal shape relative to the DC component). Note that the power signal is not affected by the sensor as a result of conditions or changes in conditions.

In one embodiment, the power generation circuit 110 changes the frequency of the oscillating component 124 of the power signal 116 so that it can be tuned to the impedance of the sensor and/or offset in frequency from other power signals in the system. For example, the impedance of a capacitive sensor decreases with frequency. Therefore, if the frequency of the oscillating component is too high relative to the capacitance, the capacitor looks like a short circuit and the change in capacitance will be ignored. Similarly, if the frequency of the oscillating component is too low relative to the capacitance, the capacitor appears to be an open circuit and the change in capacitance will be ignored.

In one embodiment, power generation circuit 110 varies the amplitude of DC component 122 and/or oscillating component 124 to increase the resolution of sensing and/or adjust the power consumption of sensing. Further, the power generation circuit 110 generates the drive signal 110 such that the amplitude of the oscillating component 124 is less than the amplitude of the DC component 122.

FIG. 6A is a schematic block diagram of drive center circuit 28-a1 coupled to sensor 30. The drive sensing circuit 28-a1 includes a signal source circuit 111, a signal change detection circuit 113, and a power supply 115. A power source 115 (e.g., a battery, a power supply, a current source, etc.) generates a voltage and/or current that is combined with a signal 117, which signal 117 is generated by the signal source circuit 111. The combined signal is provided to the sensor 30.

The signal source circuit 111 may be a voltage supply circuit (e.g., a battery, a linear regulator, an unregulated DC-DC converter, etc.) that generates a voltage-based signal 117, a current supply circuit (e.g., a current source circuit, a current mirror circuit, etc.) that generates a current-based signal 117, or a circuit that provides a desired power level to the sensor and substantially matches the impedance of the sensor. The signal source circuit 111 generates a signal 117 that includes a DC (direct current) component and/or an oscillating component.

When the combined signal (e.g., signal 117 and power from the power source) is received and when exposed to condition 114, the electrical characteristics of the sensor affect 119 the signal. When the signal change detection circuit 113 is enabled, it detects the effect 119 on the signal as a result of the electrical characteristics of the sensor.

FIG. 8 is an embodiment of a sensor map plotting electrical characteristics versus conditions. The sensor has a substantially linear region in which incremental changes in conditions produce corresponding incremental changes in the electrical characteristic. The graph shows two types of electrical characteristics: one increasing as the conditions increase and the other decreasing as the conditions increase. As a first type of embodiment, the resistance of the temperature sensor increases and the temperature increases. As a second type of embodiment, the capacitance of a capacitive touch sensor decreases as a touch is sensed.

FIG. 9 is a schematic block diagram of another embodiment of a power signal plot in which a change in an electrical characteristic or an electrical characteristic of a sensor is affecting the power signal. In this embodiment, the influence of the electrical characteristic or the change in the electrical characteristic of the sensor reduces the direct current component, but has little influence on the oscillation component. For example, the electrical characteristic is resistance. In this embodiment, the resistance or change in resistance of the sensor reduces the power signal, inferring an increase in resistance relative to a constant current.

FIG. 10 is a schematic block diagram of another embodiment of a power signal plot in which a change in an electrical characteristic or an electrical characteristic of a sensor is affecting the power signal. In this embodiment, the influence of the electrical characteristic or the change in the electrical characteristic of the sensor reduces the amplitude of the oscillation component, but has little influence on the dc component. For example, the electrical characteristic is the impedance of a capacitor and/or an inductor. In this embodiment, the impedance or impedance change of the sensor reduces the amplitude of the oscillating signal component, thereby inferring an increase in impedance for a relatively constant current.

FIG. 11 is a schematic block diagram of another embodiment of a power signal plot in which a change in an electrical characteristic or an electrical characteristic of a sensor is affecting the power signal. In this embodiment, the influence of the electrical characteristic or the change in the electrical characteristic of the sensor changes the frequency of the oscillation component, but has little influence on the DC component. For example, the electrical characteristic is the reactance of a capacitor and/or an inductor. In this embodiment, the reactance of the sensor or a change in the reactance changes the frequency of the oscillating signal component, thereby inferring an increase in reactance (e.g., the sensor acts as an integrator or phase shift circuit).

FIG. 11A is a schematic block diagram of another embodiment of a power signal plot in which a sensor electrical characteristic or change in an electrical characteristic is affecting the power signal. In this embodiment, the influence of the electrical characteristic or the change in the electrical characteristic of the sensor changes the frequency of the oscillation component, but has little influence on the DC component. For example, the sensor includes two transducers that oscillate at different frequencies. The first transducer receives a power signal having a frequency f1 and converts it to a first physical condition. The second transducer is excited by the first physical condition to produce an electrical signal of a different frequency f 2. In this embodiment, the first and second transducers of the sensor change the frequency of the oscillating signal component, which allows for finer-grained sensing and/or a wider sensing range.

Fig. 12 is a schematic block diagram of one embodiment of a power signal change detection circuit 112 that receives an affected power signal 118 and a resulting power signal 116 to thereby produce a signal 120 indicative of a change in the power signal. The effect 118 on the power signal is a result of the electrical characteristic and/or a change in the electrical characteristic of the sensor; figures 8-11A show some embodiments of the influence.

In one embodiment, the power signal change detection circuit 112 detects a change in the DC component 122 and/or the oscillating component 124 of the power signal 116. The power signal change detection circuit 112 then generates a signal 120 representative of the change in the power signal based on the change in the power supply signal. For example, the change in the power signal results from a change in the impedance of the sensor and/or a change in the impedance of the sensor. The representative signal 120 reflects changes in the power signal and/or changes in the sensor impedance.

In one embodiment, the power signal change detection circuit 112 is operable to detect a change in the oscillating component at a frequency, which change may be a phase shift, a frequency change, and/or an amplitude change of the oscillating component. The power signal change detection circuit 112 is also operable to generate a signal representative of the change in the power signal based on the change in the oscillating component at the frequency. The power signal change detection circuit 112 is also used to provide feedback to the power supply circuit 110 regarding the oscillation component. The feedback allows the power supply circuit 110 to adjust the oscillating component at a desired frequency, phase and/or amplitude.

FIG. 13 is a schematic block diagram of another embodiment of a drive sense circuit 28-b, the drive sense circuit 28-b including a change detection circuit 150, a conditioning circuit 152, and a power supply circuit 154. Drive sensing circuitry 28-b is coupled to sensor 30, which includes a transducer having varying electrical characteristics (e.g., capacitance, inductance, impedance, current, voltage, etc.) based on varying physical conditions 114 (e.g., pressure, temperature, biological, chemical, etc.). .

The power circuit 154 is operatively coupled to the sensor 30 and provides a power signal 158 to the sensor 30 when enabled (e.g., based on a control signal from the processing module 42, applying power, closing a switch, receiving a reference signal, etc.). The power supply circuit 154 may be a voltage supply circuit (e.g., a battery, a linear regulator, an unregulated DC-DC converter, etc.) that generates a voltage-based power signal or a current supply circuit (e.g., a current source circuit, a current mirror circuit, etc.) that generates a current-based power signal. The power supply circuit 154 generates a power signal 158 that includes a DC (direct current) component and an oscillating component.

When receiving the power signal 158 and when exposed to the condition 114, the electrical characteristics of the sensor affect 160 the power signal. When the change detection circuit 150 is enabled, it detects the effect 160 on the power signal as a result of the electrical characteristics of the sensor 30. The change detection circuit 150 is further operable to generate a signal 120 representative of the change to the power signal based on the detected effect on the power signal.

The adjustment circuit 152, when enabled, generates an adjustment signal 156 to adjust the DC component to a desired DC level and/or to adjust the oscillating component to a desired oscillation level (e.g., amplitude, phase, and/or frequency) based on the signal 120 representative of the power signal variation. The power supply circuit 154 utilizes the conditioning signal 156 to maintain the power signal at a desired setting 158 regardless of the electrical characteristics of the sensor. In this way, the adjustment amount represents the influence of the electrical characteristic on the power signal.

In one embodiment, the power supply circuit 158 is a DC-DC converter operable to provide a regulated power signal having a DC component and an AC component. The change detection circuit 150 is a comparator and the adjustment circuit 152 is a pulse width modulator that generates an adjustment signal 156. The comparator compares the power signal 158 affected by the sensor with a reference signal that includes both DC and AC components. When the electrical characteristic is at a first level (e.g., a first impedance), the power signal is adjusted to provide a voltage and a current such that the power signal is substantially similar to the reference signal.

When the electrical characteristic changes to a second level (e.g., a second impedance), the change detection circuit 150 detects a change in the DC and/or AC component of the power signal 158 and generates the representative signal 120, the representative signal 120 indicating the change. The conditioning circuit 152 detects changes in the representative signal 120 and generates a conditioning signal to substantially eliminate the effect on the power signal. The adjustment of the power signal 158 may be accomplished by adjusting the amplitude of the DC and/or AC components, by adjusting the frequency of the AC component, and/or by adjusting the phase of the AC component.

It should be noted that terms such as bitstream, stream, signal sequence, etc. (or their equivalents) that may be used herein interchangeably have been used to describe digital information (e.g., data, video, voice, text, graphics, audio, etc., any of which may be generally referred to as "data") whose content corresponds to any of a variety of desired types.

FIG. 14 is a schematic block diagram of an embodiment for providing a reference signal waveform for driving a sense circuit. In one embodiment, a sinusoidal waveform, such as the oscillating component 124, is generated by a reference signal generator 149, the reference signal generator 149 being coupled to a change detection circuit 150. The reference signal generator 149 may be a Phase Locked Loop (PLL), a crystal oscillator, a digital frequency synthesizer, and/or any other signal source that may provide a sinusoidal signal of a desired frequency, phase shift, and/or amplitude.

In general, the power supply circuit 154 generates a source signal 158 that is adjusted to substantially match the sinusoidal reference signal 157. For example, the sinusoidal signal generated by the reference signal generator 149 is useful when the sensor 30 is one of a plurality of sensors that sense changes in capacitance of a touch screen display. In such environments, the use of a sinusoidal reference signal is easy to generate and does not introduce harmonics that may adversely affect the operation of the drive sensing circuit, the touch screen operation of the display, and/or the display operation of the display.

The output of the power supply circuit 154 (source signal 158) and a reference signal generator output (e.g., reference signal 157) are coupled to the inputs of an operational amplifier 151, the outputs of which are coupled to an analog-to-digital converter (ADC) 212. The signal 120 representative of the source signal variation is output by the ADC 212, which is also input to the conditioning circuit 152 and converted by the digital-to-analog converter (DAC) 214; an output of the conditioning circuit 152 is coupled to a power supply circuit 154 to provide a conditioning signal 156 to the power supply circuit 154. The sinusoidal signal generated by the reference signal generator 149 is a non-linear signal and thus has a non-linear resolution.

FIG. 15 is a schematic block diagram of an embodiment of a data sensing circuit 200 that includes an analog time domain circuit 202, an analog-to-digital circuit 204, and a digital frequency domain circuit 206. The data sensing circuit 200 operates in the time domain according to information in the frequency domain. In general, the data sensing circuit 200 generates digital data 216 based on an analog frequency domain signal 210 (e.g., an analog signal having data in the frequency domain) and a reference signal 208. The resulting digital data 216 may be the desired output data or may require further processing to obtain the desired data output.

In an embodiment of operation, the analog time domain circuit 202 outputs a signal component of the analog frequency domain signal 210 to the device 218. The analog time domain circuit 202 includes adjusting a source circuit to generate a signal component. In one embodiment, the adjustment source circuit is an associated current source that is adjusted to a particular current value based on the reference signal 208. In another embodiment, the regulated source circuit is a voltage circuit (e.g., a linear regulator, a DC-DC converter, a battery, etc.) that generates a regulated voltage based on the reference signal 208.

The means 218 alters the signal components to produce the analog frequency domain signal 210, wherein the signal components are altered at a particular rate to represent the input data. The inverse of the data rate corresponds to the frequency of the analog frequency domain signal 210; thus, the signal is in the analog domain and the data is in the frequency domain. By way of example, the signal component produced by the analog time domain circuit 202 is a DC voltage (e.g., 0.25 volts to 5 volts or more) corresponding to the reference signal 208. The means 218 alters the signal component by changing the load on the signal component to affect the voltage and/or current of the signal component, thereby creating the analog frequency domain signal 210 (e.g., the signal component plus the effect of the alteration).

As a particular embodiment, the device 218 changes its resistance at a particular rate (e.g., 10Hz to 100MHz or higher) to represent the input data. The increase in resistance reduces the voltage of the constant current, reduces the current of the constant voltage, or reduces the voltage and current of the signal component. The decrease in resistance increases the voltage of the constant current, increases the current of the constant voltage, or increases the voltage and current of the signal component. The increase and decrease in device resistance at a particular rate represents the input data. The number of different resistance levels corresponds to a data level, where N is equal to the number of unique data values per cycle of the data rate, where N is an integer of 2 or more. For example, when N is 2, there are two data levels (e.g., a logic "0" of the first resistor and a logic "1" of the second resistor), and when N is 10, there are ten data levels (e.g., 0 to 9).

As another embodiment of generating the analog frequency domain signal 210, the signal components generated by the analog time domain circuit 202 include oscillating components (e.g., sine waves, triangular waves, square waves, sawtooth waves, etc., with peak-to-peak voltages of a few millivolts to 5 volts or more, with frequencies of 100Hz to 1MHz or more) that correspond to the reference signal 208. In this embodiment, the device changes its impedance (e.g., capacitance, inductance, and/or resistance) at a particular rate (e.g., fx at 10Hz to 100MHz or higher) to represent the input data. The increase in impedance decreases the voltage of the constant current, decreases the current of the constant voltage, or decreases the voltage and current of the signal component. The decrease in impedance may increase the voltage of the constant current, increase the current of the constant voltage, or increase the voltage and current of the signal component. The increase and decrease of the impedance of the device at a particular rate represents the input data.

Continuing with the operational embodiment, the analog time domain circuit 202 uses the reference signal 208 to compare with the analog frequency domain signal 210 to create the analog frequency domain error correction signal 212. The analog frequency-domain error correction signal 212 is indicative of the error correction required to maintain the signal component and thus maintain the analog frequency-domain signal 210 substantially matching the reference signal. The error correction represents frequency domain data embedded in the change of the signal component.

Analog-to-digital circuitry 204 (e.g., an "n" bit analog-to-digital converter, where n is an integer equal to or greater than 1) converts the analog frequency-domain error correction signal 212 to a digital frequency-domain error correction signal 214. The error correction representing the frequency domain data remains substantially in the digital domain.

The digital frequency domain circuit 206 operates in the frequency domain to recover digital data 216. For example, the digital frequency domain circuitry 206 includes one or more Finite Impulse Response (FIR) filters, one or more Cascaded Integrated Comb (CIC) filters, one or more infinite impulse response (FIR) filters, one or more decimation stages, one or more Fast Fourier Transform (FFT) filters, and/or one or more Discrete Fourier Transform (DFT) filters.

FIG. 16 is a schematic block diagram of another embodiment of a data sensing circuit 200, which includes an analog time domain circuit 202-1, an analog-to-digital circuit 204, a digital frequency domain circuit 206; and a digital-to-analog feedback circuit 220. The data sensing circuit 200 operates similarly to the data sensing circuit 200 of fig. 10, with the following differences. Feedback for adjusting signal components via the adjustment source circuit within the analog time domain circuit 201-1 comes from a digital-to-analog feedback circuit 220 (e.g., an "n" bit-to-digital-to-analog converter when n is an integer equal to or greater than 1).

FIG. 17 is a schematic block diagram of another embodiment of a data circuit 230, the data circuit 230 including a drive sense circuit 28, a plurality of digital Band Pass Filter (BPF) circuits 232 and 236, and a plurality of data sources (1 through n). As previously described, drive sense circuit 28 generates drive signal components of drive and sense signal 238 (e.g., the drive portion of signal 238) based on reference signal 208. The data sources operate at different frequencies to embed frequency domain data into the drive and sense signals 238 (e.g., the sense portion of the signals 238). Each data source operates similarly to the device 218 of fig. 10 to embed data into the signal 238 by varying the load on the drive component of the signal 238.

In an embodiment of operation, data source 1 varies the drive signal component of the drive and sense signal 238 at a first frequency fl; the data source 2 varies the drive signal component of the drive and sense signal 238 at the second frequency f 2; and the data source n varies the drive signal component of the drive and sense signal 238 at the "nth" frequency fn. Drive sense circuit 28 conditions drive and sense signals 238 to substantially match reference signal 208, which may be similar to reference signal 157 of FIG. 14.

Drive sense circuit 28 outputs a signal 120 representative of changes to drive and sense signal 238 based on the adjustment of drive and sense signal 238. Each of the digital BPF circuits 232 receives the signal 120 and is tuned to extract therefrom data corresponding to one of the data sources. For example, the digital BPF circuit 232 is tuned to extract data from the data source 1 at the frequency f1 to generate one or more digital values representing the first data 240. The second digital BPF circuit 234 is tuned to extract data from the data source 2 at the frequency f2 to generate one or more digital values representing the second data 242. The nth digital BPF circuit 236 is tuned to extract data from the data source n at the frequency fn to generate one or more digital values representing the nth data 244. Each of the digital BPF circuits 232-236 includes one or more Finite Impulse Response (FIR) filters, one or more Cascaded Integrated Comb (CIC) filters, one or more Infinite Impulse Response (IIR) filters, one or more decimation stages, one or more Fast Fourier Transform (FFT) filters, and/or one or more Discrete Fourier Transform (DFT) filters.

Fig. 18 is a schematic block diagram of an embodiment of an analog-to-digital conversion circuit 246, the analog-to-digital conversion circuit 246 including an analog-to-digital converter (ADC)258, a digital decimation filter circuit 248, a digital Band Pass Filter (BPF) circuit 250, and a processing module 252. The ADC258 may be implemented in a variety of ways. For example, ADC258 is ADC converter 212 of the previous figure that drives sensing circuit 28. As another example, the ADC258 is implemented as a fast ADC, a successive approximation ADC, a ramp comparison ADC, a Wilkinson ADC, an integrating ADC, and/or a delta-coded ADC. As yet another embodiment, ADC258 is implemented as a sigma-delta ADC.

The digital decimation filtering circuit 248 includes one or more Finite Impulse Response (FIR) filters, one or more Cascaded Integrated Comb (CIC) filters, one or more infinite impulse response (FIR) filters, one or more decimation stages, one or more Fast Fourier Transform (FFT) filters, and/or one or more Discrete Fourier Transform (DFT) filters, one or more polyphase filters, and one or more decimation stages. Digital Band Pass Filter (BPF) circuitry 250 includes one or more Finite Impulse Response (FIR) filters, one or more Cascaded Integrated Comb (CIC) filters, one or more infinite impulse response (FIR) filters, one or more decimation stages, one or more Fast Fourier Transform (FFT) filters, and/or one or more Discrete Fourier Transform (DFT) filters, and one or more polyphase filters. The BPF250 includes a plurality of taps whose coefficients are set to produce a band pass region approximately centered on the oscillation frequency of the analog input signal and having a bandwidth tuned to filter pure tones (e.g., s 1).

The sampling frequency of the stages of the analog-to-digital conversion circuit 246 is set to a multiple of the data output rate. For example, the rate of data output 256 is 300Hz, so the sampling frequency is a multiple of 300 Hz. For example, ADC circuit 258 is numbered 2¹⁷The analog input signal is oversampled at a sampling frequency (fs) of 300Hz (about 39.32 MHz). When the sampling frequency is greater than the nyquist sampling frequency (e.g., 40KHz-400KHz when the oscillation frequency is 20KHz-200KHz), the analog input signal is referred to as being oversampled. Setting the sampling frequency much higher than the nyquist sampling frequency results in significant oversampling of the analog signal. Oversampling of the analog signal allows for narrower bandpass filtering and improves the signal-to-noise ratio (SNR).

In an embodiment of operation, the ADC258 converts an analog signal including a set of pure tone components (e.g., one or more pure tone components each having an oscillation frequency) into a digital signal of the one or more pure tone components. For example, the input analog signal has a pure tone (e.g., a sinusoidal signal, a DC signal, a repeating signal, and/or combinations thereof) with a DC component and/or an oscillating frequency (e.g., a frequency in the audio frequency range, in the range of 20KHz-200KHz) at f1Internal, or more). As a specific example, the ADC is a sigma-delta ADC operating at about 39.32MHz (e.g., 300 x 2)¹⁷) The clock rate of (a) oversamples the analog input signal, thus boosting the low frequency noise to higher frequencies outside the band of interest. An embodiment of a sigma-delta ADC will be discussed in more detail with reference to fig. 23.

Continuing with the specific embodiment, ADC258 produces a 1-bit digital output of approximately 39.32MHz that represents the analog signal. In one embodiment, the analog signal includes an error correction signal s1 of frequency f1 that represents frequency domain data embedded in the analog input signal and that remains substantially in the digital domain (e.g., as discussed in fig. 14-15).

The digital decimation filter circuit 248 takes the output from the ADC circuit 258 (e.g., a 1-bit digital output at about 39.32MHz) and converts it to another digital signal having another data rate frequency that is a multiple of the data output rate (e.g., 300 Hz). In this embodiment, the digital decimation filter circuit 248 has 2¹²An output rate (fd) of 300HZ (about 1.23 MHz).

As a more specific example, the digital decimation filter circuit 248 converts a 1-bit digital output at approximately 39.32MHz to 2 of the error correction signal sl representing the frequency fl¹²An 18 bit output of 300HZ (about 1.23 MHz). The ratio (e.g., fs/fd) between the sampling rate (fs) and the output rate (fd) of the digital decimation filter circuit 248 is equal to the number of ADC258 samples per output of the digital decimation filter circuit 248. For example, 39.32MHz/1.23 MHz-32. Thus, the digital decimation filter circuit 248 has a decimation rate of 32. The digital decimation filter circuit 248 produces 1 output of 18 bits in the time required for the ADC258 to output 32 samples of 1 bit. The digital decimation filter circuit 248 will be discussed in more detail with reference to fig. 31-41.

The digital BPF circuit 250 takes the output of the digital decimation filter circuit 248 (e.g., an 18-bit output at about 1.23MHz) and band-pass filters it. The digital BPF circuit 250 applies a narrow bandpass filter centered at f1 and outputs an influence value 254 having a real component and an imaginary component. Because the data (e.g., error correction signal) is embedded in a sinusoid (e.g., pure tone), the required information is at frequency f1 and is based on amplitude and/or phase. Thus, the band pass filter may be very narrow (e.g., 1% to 20% of the channel spacing, and as a specific example, about 5% of the channel spacing 255 (e.g., a 10Hz band pass filter may be used for a 300Hz channel spacing)) to capture the desired signal. In one implementation, the digital BPF circuit 250 has a tap length of 4096 (e.g., the digital BPF circuit outputs 1 48-bit impact value at a 300Hz output rate in the time it takes for the digital decimation filter circuit 248 to output 4096 18-bit outputs at approximately 1.23 MHz). The digital BPF circuit 250 will be discussed in more detail with reference to fig. 42-53.

The processing module 252 interprets the imaginary and real components of the impact values 254 to produce a data output 256. The influence value 254 is a vector (i.e., phasor complex) having real and imaginary components representing a sinusoidal function having a peak magnitude (i.e., amplitude) and direction (i.e., phase). For example, the impact value 254 is a 48-bit value having a 24-bit real component and a 24-bit imaginary component. In the complex domain, voltage and current are phasors, while resistance, capacitance and inductance are replaced by complex impedances (e.g., ZR R, ZL jfL and ZC 1/(jfC) — j/(fC)). Since voltage (V) is current (I) impedance (Z), processing module 252 determines a capacitance or other impedance value based on the voltage and current vectors affecting value 254 (e.g., a decrease in impedance increases voltage by a constant current, increases current by a constant voltage, or increases voltage and current of a signal component). Increasing and decreasing the impedance at a particular rate represents the input data. The determined impedance value or change in impedance value is output as data output 256 at an example output rate of 300 Hz.

Fig. 19 is a schematic block diagram of another embodiment of an analog-to-digital conversion circuit 246, which includes an analog-to-digital converter (ADC)258, a digital decimation filtering circuit 248, a plurality of digital Band Pass Filter (BPF) circuits 250, and a processing module 252. The operation of the analog-to-digital conversion circuit 246 of fig. 19 is similar to the embodiment of fig. 18, except that a plurality of digital BPF circuits are included for filtering a plurality of pure tones.

In an embodiment of operation, the ADC258 converts an analog signal having a set of pure tone components (e.g., the signal sl-sn) to a set of digital signals sl-sn at an oscillation frequency (e.g., fl-fn). For example, the first tone of the input analog signal has an oscillation frequency of f1 (e.g., 100KHz), e.g., for a first self capacitance measurement on the touch screen display, the second tone of the input analog signal has an oscillation frequency of f2 (e.g., 100.3KHz), e.g., for a first mutual capacitance measurement on the touch screen display, and the nth tone of the input analog signal has an oscillation frequency of fn (e.g., 100KHz +300nHz), e.g., for an nth mutual capacitance measurement on the touch screen display. Frequencies f1-fn span n channels and are equally spaced by channel spacing 255. For example, the channel spacing 255 is equal to the output data rate of 300 Hz.

The digital decimation filter circuit 248 takes the output from the ADC258 (e.g., via an n-line parallel bus) and converts the signal to another digital signal (e.g., 300Hz) having another data rate frequency that is a multiple of the data output rate. In this embodiment, the digital decimation filter circuit 248 has 2¹²An output rate (fd) of 300HZ (about 1.23 MHz). For example, the digital decimation filter circuit 248 converts a 1-bit ADC output at approximately 39.32MHz representing a digital signal s1-sn of frequency f1-fn to 2 representing a signal s1-sn of frequency f1-fn^12*An 18-bit output of 300HZ (about 1.23 MHz).

Each of the digital BPF circuits 1-n250 includes a plurality of taps whose coefficients are set to produce a band pass region approximately centered on the oscillation frequency of the analog input signal, and the band pass region has a bandwidth tuned to filter pure tones. For example, digital BPF circuit 1250 has a bandwidth tuned for filter f1, digital BPF circuit 2250 has a bandwidth tuned for filter f2, and digital BPF circuit n250 has a bandwidth tuned for filter fn. The digital BPF circuits 1-n250 take the output of the digital decimation filter circuit 248 (e.g., the n 18-bit outputs at approximately 1.23MHz via the bus and the error correction signal s1-sn at frequency f1-fn) and shift each signal to a bandpass of frequencies f 1-fn.

The digital BPF circuits 1-n250 each apply a very narrow bandpass filter and output corresponding impact values 1-n 254 having real and imaginary components. Because data is embedded in each sinusoidal signal (s1-sn) (e.g., pure tones), the required information is at the frequency f1-fn and is based on amplitude and/or phase. Thus, the band pass filter can be very narrow (e.g., less than 0.05 times the channel spacing (e.g., 10Hz)) to capture the desired signal.

The processing module 252 interprets the imaginary and real components of the impact values 1-n 254 to produce data outputs 1-n 256. The influence values 1-n 254 are vectors (i.e., phasor complex numbers) each having a real component and an imaginary component representing a sinusoidal function having a peak magnitude (i.e., amplitude) and direction (i.e., phase). For example, the impact value is a 48-bit value having a 24-bit real component and a 24-bit imaginary component. In the complex domain, voltage and current are phasors, while resistance, capacitance and inductance are replaced by complex impedances (e.g., ZR R, ZL jfL and ZC 1/(jfC) — j/(fC)). Since voltage (V) — current (I) × impedance (Z), processing module 252 determines capacitance or other impedance values from the voltage and/or current vectors represented by influence values 1-n 254. The determined impedance values or changes in impedance values are output as data outputs 1-n 256. The data outputs 256 are output individually or in parallel at an output data rate (e.g., 300 Hz).

20A-20B are exemplary diagrams depicting conditions versus capacitance (e.g., electrodes of a touch screen display). In a touch screen display embodiment, the electrodes have a self capacitance and a mutual capacitance. Finger capacitance or pen capacitance (e.g., touch) can increase the self-capacitance of the electrode, thereby lowering the impedance for a given frequency. As shown in FIG. 20A, the mutual capacitance decreases with touch, while the self capacitance and pen capacitance increase with touch. As shown in fig. 20B, the mutual, pen, and self capacitances in the no-touch condition are shown to be about the same magnitude, but different from when in the touch condition. For example, mutual capacitance is reduced by touch, while self capacitance and pen capacitance are increased by touch.

Fig. 21 is an exemplary graph plotting impedance of an input with a dominant capacitive load versus frequency. Based on capacitance (self, pen, and/or mutual), as the frequency of the fixed capacitance increases, the impedance decreases based on 1/2 π fC, where f is the frequency and C is the capacitance.

FIG. 22 is an example of impact values 254-1 and 254-2. When the DC component embedded in the analog input signal represents a constant current voltage, the influence value represents a voltage vector having an imaginary component and a real component. The processing module 252 determines a capacitance change (e.g., self, pen, and/or mutual capacitance, etc.) from a voltage vector (e.g., impedance (Z) ═ voltage (V)/current (I) and ZC ═ 1/(jfC) ═ j/(fC)) and interprets whether the change represents a touch or no-touch condition.

Fig. 23 is a schematic block diagram of an embodiment of a sigma-delta analog-to-digital (ADC) circuit. Sigma-delta (ADC) circuit 258 is an embodiment of ADC258 of fig. 18 and 19 and includes oversampling modulator 260 and digital decimation filter circuit 248. In an embodiment of operation, the ADC circuit 258 converts an analog input signal 262 having an oscillation frequency and a set of pure tone components to an 18-bit output at a rate of approximately 1.23 MHz. For example, the input analog signal 262 has an oscillation frequency of f1 (e.g., 20KHz-200KHz) and a pure tone component s 1.

In this embodiment, the oversampling modulator 260 is a 1-bit ADC sigma-delta modulator. In this embodiment, oversampling modulator 260 is equal to 2¹⁷The analog input signal 262 is oversampled at a sampling frequency (fs) of 300Hz (about 39.32 MHz). The oversampling modulator 260 produces a 1-bit ADC output of 39.32MHz, representing the error correction signal s1 embedded in the sinusoidal signal at frequency f 1. The error correction signal s1 represents the frequency domain data embedded in the analog input signal and remains substantially in the digital domain.

The digital decimation filtering circuit 248 includes one or more Finite Impulse Response (FIR) filters, one or more Cascaded Integrated Comb (CIC) filters, one or more infinite impulse response (FIR) filters, one or more decimation stages, one or more Fast Fourier Transform (FFT) filters and/or one or more Discrete Fourier Transform (DFT) filters, one or more polyphase filters, and one or more decimation stages. The digital decimation filtering circuit 248 takes the output from the oversampling modulator 260 (e.g., a 1-bit ADC output of approximately 39.32MHz of the error correction signal s1 representing frequency f1) and filters and downconverts it to another digital signal having another data rate frequency. In this embodiment, the digital decimation filter circuit 248 has 2¹²An output rate (fd) of 300HZ (about 1.23 MHz).

For example, the digital decimation filter circuit 248 converts a 1-bit ADC output at approximately 39.32MHz representing the error correction signal sl at frequency fl to 2 representing the error correction signal s1 at frequency f1¹²An 18 bit output of 300HZ (about 1.23 MHz). The ratio (e.g., fs/fd) between the sampling rate (fs) and the output rate (fd) of the digital decimation filter circuit 248 is equal to the number of samples taken by the oversampling modulator 260 for each output of the digital decimation filter circuit 248. For example, 39.32MHz/1.23 MHz-32. Therefore, the decimation rate of the digital decimation filter circuit 248 is 32.

Fig. 24 is an example of quantization noise of the sigma-delta oversampling modulator 260 of fig. 23. Sigma-delta ADCs implement noise shaping (i.e., the function of effectively boosting low frequency noise to higher frequencies outside of the band of interest) making them suitable for high precision, high resolution applications. The oversampling modulator 260 of fig. 23 shifts the quantization noise 264 to a higher frequency. The order of the sigma-delta oversampling modulator changes the noise shaping.

As shown, the quantization noise 264 starts low at zero Hz, rises at the sampling frequency (fs) of the oversampling modulator, and then tends to level off. The multi-order sigma-delta modulator shapes the quantization noise 264 to a higher frequency than the low-order sigma-delta modulator. For example, the third order sigma-delta modulator embodiment shows much more noise near the frequency fs, but much less noise near low frequencies, compared to the first order sigma-delta modulator. The output of the digital decimation filter circuit 248 of fig. 23 includes frequencies from 0 to fd, so a significant portion of the quantization noise 264 is present in the output of all three embodiments. However, very narrow bandpass filtering (e.g., by the digital BPF circuit 250 discussed in the previous figures) isolates the signal of interest at lower frequencies, so that noise near fd is also removed.

Fig. 25 is a schematic block diagram of example outputs of different stages of the analog-to-digital conversion circuit 246 of fig. 18 and 19. In this embodiment, analog-to-digital (ADC) circuit 258 generates 2¹⁷1-bit ADC output at 300Hz (about 39.32 MHz). Thus, each data outputThe clock period (e.g., 300Hz in this embodiment) has a value of 2¹⁷(or 131,072) 1-bit analog input signal samples. Digital decimation filter circuit 248 by 2¹²300Hz (about 1.23MHz) produces an 18 bit output. 2¹⁷/2¹²Is equal to 2⁵Or 32; thus, over time, the ADC circuit 258 outputs 32 1-bit samples and the digital decimation filter circuit 248 is able to output an 18-bit value, as shown.

The BPF circuit 250 outputs a 48-bit impact value having a 24-bit real component and a 24-bit imaginary component at a data output clock rate of 300 Hz. Thus, each data output clock cycle has 2¹²And 18 bit values (or 4096) (e.g., 300Hz in this embodiment). In other words, during the time that the digital decimation filter circuit 248 outputs 4096 18-bit values, the one or more digital BPF circuits 250 output one 48-bit contribution value having a 24-bit real component and a 24-bit imaginary component at a data output clock rate of 300 Hz.

Fig. 26 is an embodiment of sampling the analog signal 262 to produce a digitized signal 270. In this embodiment, analog signal 262 is sampled at 8 points (s0-s7) per cycle to create a digitized signal representing 8 discrete points of analog signal 262.

Fig. 27 is a schematic block diagram of a digital filter implementing a multiply-accumulate function. The digital filter design shown is designed with 8 stages (e.g., taps) to capture 8 discrete points of the digitized signal of fig. 26. When the 8 stages capture a point in the pattern shown in fig. 26, the digital filter produces a filtered output 272 (e.g., a pulse representing an n-bit digital logic value). The input signal (e.g., digitized signal 270) enters a digital filter at stage 0 where it is multiplied by a coefficient h0 and also input to stage 1. Stages 1-7 each include a unit delay Z in the Z transformed symbol^-1To provide a delayed input (tap) to each stage of multiplication (i.e., the input signal is at delay Z)^-1And then multiplied by the next coefficient (e.g., h1-h 6)). The multiplication results of each stage are added (i.e., accumulated) to create a filtered output. A series of multiply-accumulate functions is also known as a moving average line. The more taps the filter, the more computation the output.

Fig. 28 is a schematic block diagram of a digital filter implementing a multiply-accumulate function. The digital filter operates in a similar manner to the digital filter of fig. 27, and is shown here for convenience.

Fig. 29 is an example of a digitized signal 270. At some point in time, the digitized signal 270 has a particular pattern. For example, the pattern shown is one sinusoidal signal period. The coefficients h0-h7 of the digital filter of fig. 28 may be set so that only things near the desired pattern produce a viable output.

Fig. 30 is an embodiment of generating a digitally filtered output 272. As the digitized signal 270 of fig. 29 moves through the stages of the digital filter (e.g., the stages of fig. 27 and 28), the coefficients h0-h7 at stages 0-7 are set to look up the pattern shown in fig. 29 (i.e., the coefficients set the center frequency of the bandpass filter, the bandwidth of the bandpass filter, and the roll-off of the bandpass filter). When the pattern shown in fig. 29 is identified (or a pattern that is relatively close to the pattern), the band pass filter may produce an output (e.g., amplitude and/or phase of the sinusoidal signal) that indicates the presence of a signal. As shown, at stage 7 and time t7, the filter recognizes that the pattern shown in FIG. 29 has moved through stages 0-7, thus producing filtered output 272 at time t 7.

Filtered output 272 may be a pulse representing an n-bit digital logic value. For example, a digitized sinusoidal signal of a first amplitude may produce pulses representing 1-bit digital logic of 0, while a digitized sinusoidal signal of a second amplitude may produce pulses representing 1-bit digital logic of 1. Thus, digital data (e.g., signal s1 in fig. 18-19) may be embedded in the analog signal and extracted by digital filtering.

Fig. 31 is a schematic block diagram of one embodiment of a digital decimation filter circuit 248. The digital decimation filter circuit 248 includes an anti-aliasing filter 274 and a decimator 276. In general, the digital decimation filter circuit 248 filters high frequency components of the input signal and reduces the sampling rate so that the next stage analog-to-digital conversion circuit 246 can operate more efficiently.

When the ADC258 is the sigma-delta ADC258 of fig. 23, the digital decimation filter circuit 248 receives a 1-bit ADC output stream from the ADC258 or the oversampling modulator 260 at approximately 39.32 MHz. By oversampling the analog input signal, the quantization noise 264 is distributed over a wider bandwidth. When ADC258 is a first order sigma-delta ADC, the output from oversampling modulator 260 includes quantization noise 264 shaped to be maximum at the sampling frequency (fs) of oversampling modulator 260 (e.g., 39.32MHz), as shown.

Anti-aliasing filter 274 is a low-pass filtered averaging filter (e.g., one or more Finite Impulse Response (FIR) filters, one or more comb filters, one or more raised cosine filters, one or more Cascaded Integrated Comb (CIC) filters, one or more Infinite Impulse Response (IIR) filters, one or more decimation stages, one or more Fast Fourier Transform (FFT) filters, and/or one or more Discrete Fourier Transform (DFT) filters, etc.) that samples the 1-bit ADC output and provides a cutoff frequency to remove or attenuate higher frequency signals (e.g., quantization noise 264). The anti-aliasing filter 274 has a frequency response H (z).

The decimator 276 reduces the output rate of the anti-aliasing filter 274 by discarding portions of the output data of the anti-aliasing filter 274. In this embodiment, the decimator 276 reduces the output rate of the anti-aliasing filter 274 (e.g., 39.32MHz) by 32 to produce an output rate of the 18-bit digital decimation filtering circuit 248 of about 1.23MHz (e.g., 39.32 MHz/32-1.23 MHz). As shown, applying a low pass anti-aliasing filter 274 with a cutoff frequency fd and decimating the signal 32 removes a portion of the quantization noise between fd and fs.

FIG. 32 is an example frequency response H (z) of the anti-aliasing filter 274. For example, the anti-aliasing filter 274 is a Finite Impulse Response (FIR) that cuts frequencies above 1.23MHz (i.e., the output rate of the digital decimation filter circuit 248). As shown, the FIR filter has a sinx/x (e.g., or "sinc") frequency response. The sinc frequency response has a "notch" response (e.g., it can reject the line frequency when set to that frequency). The notch position is also directly related to the output data rate. As shown, the first notch position in fig. 32 is at the output rate of the digital decimation filter circuit 248, which is approximately the output rate of 1.23MHz (e.g., cutoff frequency). The sinc frequency response is zero at integer multiples of the data rate (e.g., 2.46MHz, 3.69MHz, etc.). According to the nyquist sampling theorem, at a sampling rate of 39.32MHz, the signal may contain frequency components up to 39.32 MHz/2-19.66 MHz.

Fig. 33 is a schematic block diagram of an implementation of anti-aliasing filter 274. In this embodiment, anti-aliasing filter 274 implements a multiply-accumulate function as discussed in FIG. 27. For example, anti-aliasing filter 274 is a low-pass Finite Impulse Response (FIR) filter having N taps. The number of taps selected in the anti-aliasing filter 274 is related to the sampling frequency (e.g., 39.32MHz), the desired cutoff or stop band frequency (e.g., 1.23MHz), and several other desired filter characteristics. For example, increasing the number of taps in an FIR filter reduces noise, reduces the transition bandwidth between the stop-band frequency and the pass-band frequency, and increases attenuation in the stop-band. However, the more taps an FIR filter, the more it is computationally intensive (e.g., more multiply-accumulate is required).

In a particular embodiment, the anti-aliasing filter 274 is a 128-tap FIR filter (e.g., FIR filter has 128 frequency coefficients h0-h127) that cuts frequencies above 1.23MHz (i.e., the output rate of the digital decimation filter circuit 248) and operates at a 1-bit ADC output frequency of 39.32 MHz. The 1-bit ADC output at 39.32MHz is a 1-bit code stream in the time domain, shown here as the input signal x [ n ], where x [ n ] includes n discrete points. The analog signal shown as a dashed line on the 1-bit code stream shows a simplified example of how the 1-bit input stream represents an analog signal. As discussed in the previous figures, the digital decimation filter circuit 248 filters 32 samples of the input at a time. To accommodate the 128 taps, the 32-bit input may be padded with zeros.

The input signal enters the anti-aliasing filter 274 at stage 0 where it is multiplied by a coefficient h0 and input to stage 1. Stages 1-127 each include a unit delay Z in the Z transformed symbol^-1To provide a delayed input (tap) to each stage of the multiplication operation (i.e., the input signal is at delay Z)^-1And then multiplied by the next coefficient (e.g., h1-h 127)). The multiplication results of each stage are added (i.e. addedAccumulated) to create a filtered output. A series of multiply-accumulate functions is also known as a moving average line. The more taps, the more computation the output.

The output signal of the anti-aliasing filter 274 is equal toWhere N is 128 in this embodiment. The output equation is the sum of the convolutions of the input signal and the filter coefficients. In the time domain, the 128-bit code sequence is similar to the original analog signal (only 20 bits are shown here for convenience) and is responsible for high resolution. However, in the frequency domain, the anti-aliasing filter 274 applies only a low-pass filter to the signal to attenuate the quantization noise. Thus, the output signal is now a high resolution digital version of the analog input signal.

Fig. 34 is a schematic block diagram of one embodiment of decimator 276. Decimator 276 takes the output from a 128-tap anti-aliasing filter 274, here denoted as y [ n ] ═ y [0] + y [1] + … + y [127] (note that for convenience the inset shows only 20 samples) and discards each M calculation (e.g., where M is the decimation factor). For example, where the decimation factor is 32 and 128 samples are input from a 128 tap anti-aliasing filter 274, the decimator 276 outputs 4 outputs y [0] + y [1] (formerly y [31]), + y [2] (formerly y [63]) + y [3] (formerly y [95 ]). From the sum of the four outputs, an 18-bit output is produced at an output rate of about 1.23 MHz.

Fig. 35 is an embodiment of a frequency band with frequency channels. The band of interest 280 begins at f1 and ends at fn. The frequency band of interest 280 includes channels 282f1-fn spaced at a desired channel spacing 255 (e.g., a data output rate of 300Hz or another frequency). As a specific example, the frequency band of interest 280 includes 128 channels, where each channel contains pure tone components s1-s128 having frequencies f1-f 128. At a channel spacing of 300Hz (e.g., data output rate), the frequency bandwidth of interest is 128x300Hz — 38.4KHz (i.e., n x channel spacing of 200 Hz). If f1 is 100KHz, the band of interest 280 spans from 100KHz to 138.4 KHz.

Fig. 36 is a schematic block diagram of another embodiment of a digital decimation filter circuit 248. The digital decimation filtering circuit 248 includes anti-aliasing filters 274-1 to 274-n and decimators 276-1 to 276-n, where n corresponds to n channels of a 1-bit ADC output. As an example, anti-aliasing filters 274-1 to 274-n are 128-tap Finite Impulse Response (FIR) filters. The n channels of ADC output are transferred to the digital decimation filter circuit 248 via an n-line parallel bus 284. Each channel of 1-bit data from the ADC is filtered with a corresponding anti-aliasing filter 274-1 to 274-n and decimated by a factor of 32 by a respective decimator 276-1 to 276-n to produce n outputs at the output rate of the digital decimation filter circuit 248.

For example, the digital decimation filter circuit 248 takes 128 channels of 1-bit output at 39.32MHz from the ADC and filters each channel with an anti-aliasing filter with a decimation factor of 32 to produce 128 18-bit outputs at a sampling rate of about 1.23 MHz. For example, 128 18-bit outputs are multiplexed onto a single bus (i.e., 128 (2) operating at about 157.29MHz⁷) One channel x output rate 1.23MHz (2)¹²x300 Hz) or 2¹⁹x300 Hz-about 157.29 MHz). As a specific example, the output bus is a 16-bit bus with 8 free slots (e.g., 128 channels multiplexing 8-bit binary numbers require 8 bits). The output bus operates at 128 times the output rate to allow each channel to pass through each anti-aliasing filter 274-1 to 274-n and out onto a single bus. Alternatively, 128 18-bit outputs may be output in parallel.

Fig. 37 is a schematic block diagram of another embodiment of a digital decimation filter circuit 248. In contrast to the 128-tap Finite Impulse Response (FIR) anti-aliasing filter 274 and the decimator 276 of FIGS. 31-36, the digital decimation filter circuit 248 shown here includes 32 4-tap polyphase filters E₀(z)-E₃₁(z) coefficients e (n) ═ h (32n + l), n ═ 0 … 3, and l ═ 0 … 31. Each polyphase filter comprising a delay (z)^-1) And decimator (↓32), the resulting results are added by the summing network 278 to compute the final output.

In the embodiments of fig. 31-36, the filter response is convolved with the complete signal and many points that have just been calculated are discarded (e.g., the signal is filtered and then decimated). The polyphase filter is a more efficient implementation of the digital decimation filtering circuit 248 because the signal can be decimated before filtering and the computation is not wasted. In addition, each polyphase filter in the digital decimation filter circuit operates at the slower digital decimation filter circuit 248 output rate of 1.23MHz (as compared to a 128FIR filter operating at 39.32 MHz).

In this embodiment, 32 polyphase filters are required because the decimation rate is 32. Each sample on the input of the digital decimation filter circuit 248 is passed to only one of the polyphase filters. The 32 1-bit input samples (e.g., 1-bit ADC output stream from 39.32MHz) are loaded into the 32 polyphase filters, starting at the bottom (at stage 0) and working up. After loading 32 1-bit samples, the polyphase filter operates to generate a single output point (e.g., 18-bit output at 1.23 MHz). The process is repeated for the next 32 samples.

Fig. 38 is a schematic block diagram of an embodiment of a polyphase filter of the digital decimation filter circuit 248 shown in fig. 37. Each polyphase filter E₀(z)-E₃₁(z) includes 4 coefficients (e.g., 4 taps). The frequency response of the 128-tap FIR filter discussed in the previous figures may be rewritten for each filter E₀(z)-E₃₁(z) sum of the frequency responses. Based on the decimation factor, the taps that produce the output may be included in a filter (e.g., E)₀(z) includes a tap h [0]]、h[32]Z^-1、h[64]Z^-2And h [96]]Z^-3Data is extracted from the input signal every 32 points. The input signal x n may then be decomposed]So as to be input to a filter E₀(z)-E₃₁(z) the signal is decimated before. For example, x [ n ]]Value x [0]]、x[32]、x[64]And x [96]]Is inputted to a filter E₀(z) it produces the values required for extraction. The other inputs are multiplied by zero in order not to waste the computations done by the filter. Summing network 278 filters E₀(z)-E₃₁(z) results (e.g., y [0]]、y[1]、y[2]And y 3]) Add to produce an 18-bit output at an output rate of 1.23 MHz.

Fig. 39 is a schematic block diagram of another embodiment of a digital decimation filter circuit 248. In this embodiment, the digital decimation filter circuit 248 passes throughThe illustrated architecture filters and decimates (by a factor of 32) the 128 channels of the 1-bit ADC output at 39.32 MHz. In contrast to the embodiment shown in fig. 36, where each input channel requires n (e.g., 128) separate anti-aliasing filters and decimators, where each channel is processed by the same filter structure. To filter and decimate 128 channels by one configuration, the digital decimation filter circuit 248 includes 32 shift register memories 286, 32 bit-shifting 288, 32 4-tap polyphase filters E₀-E₃₁(e.g., fig. 37) as 32 look-up tables (LUTs) 290 and a summing tree 292.

Each shift register memory 286 contains a 5-bit register for each of the 128 channels. In each 5-bit register, one of the bits is reserved for new inputs, while the other 4 bits contain the previous 4 binary inputs. The memory writes each shift memory register 286 column at a time at the same frequency as the output sampling rate (e.g., 1.23Mz), however, the memory reads out into the filter structure one row at a time at a rate of 128 times the output sampling rate (e.g., 128 × 1.23mz ═ 157.29 MHz). As shown, by the time 128 bits are input to each of the shift memory registers 286 at the output rate, 4 bits are input to each LUT 290 per cycle. In this embodiment, every 128 bits outputs 4 bits with a decimation factor of 32. The structure of the transpose memory registry 286 will be discussed in more detail with reference to FIG. 40.

Bit shift 288 removes the input bit and rearranges the other 4 bits into the correct address lines of the look-up table (LUT) 290. The polyphase filters E0-E31 are implemented as a set of look-up tables (LUTs) 290. The LUT 290 stores pre-computed product values corresponding to possible input values. The pre-computed product value is stored in a memory location whose address location is the same as the binary value of the input value to which the product value corresponds. For example, for each polyphase filter E0-E31, the outputs of 16 possible combinations of 4 binary input taps are pre-computed and stored in a table. Each LUT takes a 4-bit input from the bit shift 288 and determines a pre-computed value based on the address. The output of each LUT is 16 bits (e.g., 1 bit per input (4) per tap (4 taps)) representing 4 bits of input data. The 16 bits representing the 4 bits of input data are passed through a summing tree 292 to calculate an 18 bit final result.

The digital decimation filter circuit 248 operates at a rate that is 128 times the output rate (e.g., 128x1.23 MHz — 157.29MHz), so that all 128 channels can be processed through the same structure and all output data can be processed on the same output bus. The digital decimation filter circuit 248 processes 4 bits at a time representing 128 bits per 128 channels. In the polyphase filters of fig. 36-37, 32 1-bit input samples (e.g., 1-bit ADC output stream from 39.32MHz) are loaded into the 32 polyphase filters from the bottom and work upwards. After loading 32 samples, the polyphase filter operates to generate a single output point. Here, 1-bit samples from each of the 128 channels are loaded into 32 polyphase filters. Thus, the filter structure of fig. 39 operates at 128 times the data output rate of the digital decimation filter circuit 248.

The summing tree 292 adds the results of the polyphase filter (LUT 290) (e.g., 16 bits from E0 added to 16 bits from E1 to produce a 17-bit value, etc.) to obtain the final result of the 128-bit output of 1.23MHz multiplexed on the 157.29MHz bus.

FIG. 40 is a schematic block diagram of an embodiment of a shift register memory 286. For example, the shift register memory 286 is a dual port 5-bit x 128-bit device (e.g., a static access random memory (SRAM) device), writing one column (128 bits) at a time, reading one row (5 bits) at a time. Port a is a write-only port with an input of data a (128 bits) and an address a (3 bits) to address the row. Port B is a read-only port having an output for data B (5 bits) and an input for address B (7 bits) for addressing the column. The shift register memory 286 has a latch output.

Each row of shift register memory 286 is a shift register of one of the 128 1-bit ADC output channels. Of the 5 taps in each row, 4 taps are active data read into the filter structure and the fifth tap retains input data for the next output sample. When the data of the filter structure of fig. 39 arrives at the input bus, all 128 channels are sampled during this period.

The memory is written to each shift memory register 286 at the same frequency as the output sample rate (e.g., 1.23Mz), however, the memory is read out into the filter structure at 128 times the output sample rate (e.g., 128 × 1.23mz ═ 157.29 MHz). This allows all 128 channels to be processed by the same filter structure and all output data can be multiplexed onto the same output bus.

Fig. 41 is a schematic block diagram of another embodiment of a digital decimation filter circuit 248. Fig. 41 shows a detailed embodiment of the digital decimation filter circuit 248 of fig. 39. The input signal for each 128 channels is sequentially decomposed to extract each channel at a decimation rate of 32 (e.g., as discussed with reference to fig. 38). For example, shift register memory 1286 writes the first bit (x [0]) of each channel, then writes the 32 th bit (x [32]) of each channel, then writes the 64 th bit (x [64]) of each channel, then writes the 96 th bit (x [96]) of each channel. Shift register memory 1286 reads a row of data containing x [0], x [32], x [64], and x [96] in turn from each channel at a rate 128 times the write rate (1.23MHz), thereby filtering the 128 channels through a filter structure.

The four bits of data from each channel of shift register memory 1286 are filtered by filter E0 (look-up table (LUT)290) to produce 128 16-bit outputs. E.g. E₀The filter includes a tap h [0]]、h[32]Z^-1、h[64]Z^-2And h [96]]Z^-3。x[0]、x[32]、x[64]And x [96]]Generates 16-bit filter outputs y 0 representing these inputs]. Shift register memories 2 through 128 operate similarly to shift register memory 1286. Each 16-bit output from each filter E0-E31 is passed through a summing tree 292 to produce an 18-bit output. Thus, at the output of the digital decimation filter circuit 128, 128 18-bit values are output at the rate of 1.23MHz multiplexed on the 157.29MHz bus (e.g., 128 × 1.23 MHz).

Fig. 42 is an embodiment of a frequency band having n frequency channels 282. Fig. 42 is similar to the embodiment of fig. 35, except that the band of interest 280 is now compared to the decimation frequency fd of 1.23MHz after passing through the digital decimation filter circuit 248 (e.g., the digital decimation filter circuit 248 cuts off noise at frequencies above 1.23MHz and reduces the sampling rate to 1.23 MHz). The band of interest 280 begins at f1 and ends at fn. The frequency band of interest 280 includes channels 282f1-fn spaced at a desired channel spacing 255 (e.g., a data output rate of 300Hz or another frequency). The frequency bandwidth of interest is 128x300Hz ═ 38.4KHz (i.e., n x channel spacing 300Hz) at a channel spacing of 300Hz (e.g., data output rate). If f1 is 100KHz, the band of interest 280 spans from 100KHz to 138.4 KHz.

Fig. 43 is a schematic block diagram of an embodiment of a digital Band Pass Filter (BPF) circuit 250. Digital Band Pass Filter (BPF) circuitry 250 includes one or more Finite Impulse Response (FIR) filters, one or more Cascaded Integrated Comb (CIC) filters, one or more infinite impulse response (FIR) filters, one or more decimation stages, one or more Fast Fourier Transform (FFT) filters, one or more Discrete Fourier Transform (DFT) filters, and/or one or more polyphase filters. The BPF250 includes a plurality of taps whose coefficients are set to produce a band pass region approximately centered at the oscillation frequency of the analog reference signal (e.g., 100KHz) and having a bandwidth tuned to filter a pure tone (e.g., f 1). The BPF250 has a frequency response h (z).

The digital BPF circuit 250 takes the output of the digital decimation filter circuit 248 (e.g., an 18-bit output of approximately 1.23MHz representing the signal sl at frequency fl) and shifts to a bandpass of frequency fl (e.g., 100 KHz). When the output of the digital decimation filter circuit 248 includes n 18-bit outputs from different channels (e.g., the analog input signal includes the pure tone components f1-fn of fig. 42), each output requires a digital BPF circuit to isolate each pure tone component.

The digital BPF circuit 250 applies a very narrow bandpass filter and outputs an influence value 254(si) having real and imaginary components at an output frequency of 300 Hz. Because the embedded data is sinusoidal (e.g., pure tones), the required information is at frequency f1 and is based on amplitude and/or phase. Thus, the band pass filter can be very narrow (e.g., less than 0.05 times the channel spacing (e.g., 10Hz)) to capture the desired signal.

Fig. 44 is an exemplary frequency response h (z) of the digital band-pass filter (BPF) circuit 250. As an embodiment, the digital BPF circuit 250 is a Discrete Fourier Transform (DFT) filter having a length N. For example, the digital BPF circuit 250 has a length of 4096 to filter 4096 18-bit inputs to produce 1 48-bit output. A sinx/x (e.g., or "sinc") frequency response is shown. The sinc frequency response has a "notch" response (e.g., it can reject the line frequency when set to that frequency). The sampling frequency is 1.23MHz, the length is 4096, and the frequency interval (i.e. the interval between samples in the frequency domain) resolution is 1.23 MHz/4096-300 Hz. The notch position is also directly related to the output data rate. As shown, the sinc frequency response is equal to zero at integer multiples of the 300Hz output data rate (e.g., 600Hz, 900Hz, 1200Hz, etc.).

Fig. 45 is an exemplary frequency response h (z) of a digital Band Pass Filter (BPF) circuit 250. Finite Impulse Response (FIR) filters have a sinx/x (e.g., or "sinc") frequency response as shown. The sinc frequency response has a "notch" response (e.g., it can reject the line frequency when set to that frequency). As signal s1 moves to the bandpass, a very narrow bandpass filter may be applied. For example, a 10Hz band pass filter centered at 5Hz is used to isolate pure tones. As shown, the first notch position in FIG. 45 is at 10Hz, with a center frequency of 5 Hz.

Fig. 46A-46D are examples of signal processing by digital Band Pass Filter (BPF) circuit 1250. The BPF circuit 1250 includes a plurality of taps whose coefficients are set to produce a band pass region approximately centered on the oscillation frequency (e.g., 100KHz) of the analog reference signal s1, and the band pass region has a bandwidth tuned to filter digital signals having frequency components at f1, f2, and f 3. In fig. 46A, the digital BPF circuit 1250 receives the output of the digital decimation filter circuit 248 (e.g., an 18-bit output of approximately 1.23MHz representing the signal s1 at frequency f1, the signal s2 at frequency f2, and the signal s3 at frequency f 3).

In fig. 46B, the digital BPF circuit 1250 shifts the 18-bit output of approximately 1.23MHz representing the signal sl at frequency fl, the signal s2 at frequency f2, and the signal s3 at frequency f3 to a bandpass at frequency fl (e.g., 100 KHz). For example, s1 is now at 0Hz, while s2 and s3 are evenly spaced from s1 (e.g., at 300Hz and 600 Hz).

In fig. 46C, the digital BPF circuit 1250 applies a very narrow band-pass filter to isolate sl. Because the embedded data is a sine wave (e.g., pure tone), the desired information is at a frequency f1 (e.g., 0Hz) and is based on amplitude and/or phase. Thus, the band pass filter can be very narrow (e.g., less than 0.05 times the channel spacing (e.g., 10Hz)) to capture the desired signal.

In fig. 46D, the digital BPF circuit 1250 outputs an influence value 254(sl) having a real component and an imaginary component at an output frequency of 300 Hz. The impact value 254(s1) is 48 bits with a 24 bit real part and a 24 bit imaginary part.

Fig. 47A-47D are examples of signals processed by digital Band Pass Filter (BPF) circuit 2250. The BPF circuit 2250 includes a plurality of taps with coefficients set to produce a band pass region approximately centered at the oscillation frequency of the analog reference signal s2 (e.g., 100.3KHz), and the band pass region has a bandwidth tuned to filter pure tones (e.g., f 2). In fig. 47A, a digital BPF circuit 2250 receives the output of the digital decimation filter circuit 248 (e.g., an 18-bit output of approximately 1.23MHz representing the signal s1 at frequency f1, the signal s2 at frequency f2, and the signal s3 at frequency f 3).

In fig. 47B, the digital BPF circuit 2250 shifts the 18-bit output representing the signal s1 at frequency fl, the signal s2 at frequency f2, and the signal s3 at frequency f3 to a bandpass at frequency f2 (e.g., 100.3 KHz). For example, s2 is now 0Hz and s3 is 300 Hz. S1 may be folded and aligned with S3 or other frequencies.

In fig. 47C, digital BPF circuit 2250 applies a very narrow bandpass filter to isolate s 2. Because the embedded data is sinusoidal (e.g., pure tones), the required information is at frequency f2 (e.g., 0Hz) and is based on amplitude and/or phase. Thus, the band pass filter can be very narrow (e.g., less than 0.05 times the channel spacing (e.g., 10Hz)) to capture the desired signal.

In fig. 47D, the digital BPF circuit 2250 outputs the influence value 254 having real and imaginary components at the output frequency of 300Hz (s 2). The impact value 254(s2) is 48 bits with a 24 bit real part and a 24 bit imaginary part.

Fig. 48 is a schematic block diagram of an embodiment of a digital Band Pass Filter (BPF) circuit 250. Digital BPF circuitry 250 includes one or more Finite Impulse Response (FIR) filters, one or more Cascaded Integrated Comb (CIC) filters, one or more infinite impulse response (FIR) filters, one or more decimation stages, one or more Fast Fourier Transform (FFT) filters, one or more Discrete Fourier Transform (DFT) filters, and/or one or more polyphase filters.

Using the DFT filter embodiment, the BPF circuit 250 receives the N-channel outputs from the digital decimation filter circuit 248 (e.g., 128 18-bit outputs at about 1.23MHz on a 16-bit bus running at about 157.29MHz) and performs a discrete fourier transform calculation of length N (e.g., a frequency response with synchronized outputs) at two frequencies (e.g., the self-capacitance frequency and the pen frequency) at a time on each channel. The digital BPF circuit 250 is at twice the speed of the input bus (e.g., 2)²⁰X300 Hz-314.57 MHz) to calculate two frequencies per input.

A Discrete Fourier Transform (DFT) transforms a sequence of complex numbers into another sequence of complex numbers. Each 18-bit input received represents a complex number of one frequency. An 18-bit input is fed to two separate multipliers where the input is multiplied by the real or imaginary coefficients of the DFT. The coefficient processor pre-computes the real and imaginary parts of the DFT for each frequency. The coefficient processor will be discussed in more detail with reference to fig. 52.

For each real and imaginary part of the input, the BPF circuit 250 applies a multiply-accumulate function. For example, the real part coefficients 294 are multiplied by the input and accumulated by accumulator 302. When the final result is computed for all outputs (e.g., 128 channels x 2 frequency 256 outputs), the final result is shifted to the output buffer 304 and the real component value 298 (e.g., 24 bits) is output at 300 Hz. Likewise, the imaginary coefficient 296 is multiplied by the input and accumulated by the accumulator 302. When the final result is calculated for all outputs (128 channels x 2 frequency 256 outputs), the final result is shifted to the output buffer 304 and the imaginary component value 300 (e.g., 24 bits) is output at 300 Hz. Thus, the BPF circuit filters the N outputs from the digital decimation filtering circuit 248 to produce 1 output having a real component value 298 and an imaginary component value 300, and operates at twice the speed of the input to output a two frequency result for each channel.

Fig. 49 is a schematic block diagram of another embodiment of an analog-to-digital conversion circuit 246, which includes analog-to-digital converter (ADC) circuits 1-n 258, a digital filter decimation circuit 248, a first Band Pass Filter (BPF) circuit 250, a second BPF circuit 250, a coefficient processor 306, and a processing module 252.

The ADC circuits 1-n 258 may be the ADC converter 212 of the drive sensing circuit 28 of the previous figures and/or any conventional ADC (e.g., a flash ADC, a successive approximation ADC, a ramp comparison ADC, a Wilkinson ADC, an integrating ADC, and/or a delta-coded ADC). The ADC circuit 258 may be implemented by a combination of a 1-bit ADC sigma-delta modulator and a digital decimation filter circuit 248 (e.g., a sigma-delta ADC). Fig. 49 operates in accordance with the previous embodiment except that the first BPF circuit 250 is operable to process the output from the digital filter decimation circuit 248, where the frequency is known, and the second BPF circuit 250 is operable to process the output from the digital filter decimation circuit 248, where the frequency is selectable by the processing module 252 according to a region of interest (ROI).

For example, the mutual capacitance is measured at two points every n channels (e.g., 256 frequencies, where n equals 128). The processing module 252 selects which intersections to sample at a particular point based on a given intersection or based on the results of its own frequency and pen frequency being always on. The processing module 252 inputs the selected frequency 310 into the second BPF250 and the coefficient processor 306 pre-computes coefficients for the second BPF250 based on the selected frequency. The second BPF250 will be discussed in more detail with reference to fig. 51.

The self-capacitance is measured at one point (e.g., one frequency) every n electrodes (e.g., 128 electrodes, where n equals 128) of the touch screen and the pen capacitance is measured at one point (e.g., one frequency) (one frequency on the same n electrodes). These frequencies are known to the system, so the processing module 252 inputs the known frequencies 308 to the coefficient processor 306 to pre-compute the coefficients of the first BPF 250. The first BPF250 will be discussed in more detail with reference to fig. 50.

The first BPF250 outputs a first influence value 254 that represents the self-capacitance and pen capacitance values (e.g., the first BPF250 operates at twice the speed of the input bus to filter two frequencies per channel, as discussed in fig. 48). The second BPF250 outputs a second influence 254 representing the mutual capacitance. The processing module 252 interprets the imaginary and real components of the impact values 254 to produce a data output 256. The influence values 254 are vectors (i.e., phasor complex numbers) having a function representing a sine wave having a peak magnitude (i.e., amplitude) and direction (i.e., phase). For example, the impact values 254 are 48-bit values, each having a 24-bit real component and a 24-bit imaginary component. In the complex domain, voltage and current are phasors, all resistors, capacitors and inductors are replaced with complex impedances (e.g., Z_R＝R、Z_LjfL, and ZC 1/(jfC) — j/(fC)).

Since the impedance of a channel is based primarily on its capacitance (self-, pen-, and/or mutual), as the frequency of the fixed capacitance increases, the impedance decreases according to 1/2 π fC, where f is the frequency and C is the capacitance. Since voltage (V) ═ current (I) × impedance (Z), processing module 252 determines capacitance or other impedance values from the voltage and current vectors affecting value 254 (e.g., a decrease in impedance increases the voltage of the constant current, increases the current of the constant voltage, or increases the voltage and current of the signal components). The increase and/or decrease in impedance represents the input data. The determined impedance value or change in impedance value is output as data output 256 at an example output rate of 300 Hz.

Fig. 50 is a schematic block diagram of an embodiment of a first Band Pass Filter (BPF) circuit 250. The first BPF circuit 250 is one or more Discrete Fourier Transform (DFT) or Fast Fourier Transform (FFT) filters that receive N (e.g., 128) output channels from the digital decimation filter circuit 248 (e.g., 128 18-bit outputs at about 1.23MHz on a 16-bit bus running at about 157.29MHz), and calculates a discrete fourier transform (e.g., self-capacitance frequency and pen frequency) of length N4096 on each channel two frequencies at a time. The digital BPF circuit 250 is at twice the speed of the input bus (e.g., 2)²⁰×300Hz-314.57 MHz) to calculate two frequencies per input.

Discrete fourier transform transforms N complex sequences (e.g., { x })_n}＝x₀,x₁,…,x_N-1) Conversion to another complex sequence (e.g., { X })_k}＝X₀,X₁,…,X_N-1) Wherein According to the Euler formula, can also be expressed as

For each 18-bit input, it is pre-computed by the coefficient processor 306 for each frequencyReal and imaginary parts of (c). The coefficient processor 306 will be discussed in more detail with reference to fig. 52.

For example, the real part coefficient w_ncos(2πω_sn) (for self-frequency (fs) input ω_sWherein) And w_ncos(2πω_pn) (for pen frequency (fp) input ω_pWherein) Is pre-computed by the coefficient processor 306 and multiplexed to be multiplied with the correct 18-bit output from the digital decimation filter circuit 248 shown on the left. Imaginary part coefficient-w_nsin(2πω_sn) (for self-frequency (fs) input ω_sWherein) And-w_nsin(2πω_pn) (for pen frequency (fp)) input ω_pWherein) Is pre-computed by the coefficient processor 306 and multiplexed to be multiplied with the correct 18-bit output from the digital decimation filter circuit 248 shown on the right.

The first BPF circuit 250 includes 4 18 x 18 multipliers (e.g., 2 per side per frequency) for multiplying 18 bits from the digital decimation filter circuit 248 with 18 bits from the coefficient processor. The first BPF circuit 250 includes 4 30-bit signed accumulators 302 (e.g., 2 per side per frequency) with 256 output registers for summing the multiplied values. The first BPF circuit 250 also includes 4 256 x 24 bit output buffers 304 (e.g., 2 per side per frequency). For example, the output buffer 304 is a two-port static access random access memory (SRAM) having a write-only port and a read-only port.

The first BPF circuit 250 calculates the final product of all 256 received 18-bit values (e.g., 128 channels x 2 frequencies) and shifts the final result to the output buffer 304. The output buffer 304 outputs the 24-bit real component value 298 and the 24-bit imaginary component value 300 to the processing module 252 at 300 Hz.

Fig. 51 is a schematic block diagram of an embodiment of a second Band Pass Filter (BPF) circuit 250. The second BPF circuit 250 is one or more Discrete Fourier Transform (DFT) or Fast Fourier Transform (FFT) filters that receive N (e.g., 128) output channels (e.g., 128 18-bit outputs at about 1.23MHz on a 16-bit bus running at about 157.29MHz) from the digital decimation filter circuit 248 and compute a discrete fourier transform of length N4096 on each channel two frequencies at a time (e.g., two mutual frequencies per channel). The digital BPF circuit 250 is at twice the speed of the input bus (e.g., 2)²⁰X300 Hz-314.57 MHz) to calculate two frequencies per input.

The second BPF circuit 250 is operable to process the output from the digital filter decimation circuit 248, wherein the frequency is selectable according to a region of interest (ROI). For example, the mutual capacitance is measured at two points every n channels (e.g., 256 frequencies, where n equals 128). The processing module 252 selects which intersections to sample at a particular point based on a given intersection or based on the results of its own frequency and pen frequency being always on. The processing module 252 inputs the selected frequency into the output map 316 of the second BPF 250.

For example, the output map 316 is a 256 × 12 bit two-port static access random access memory (SRAM) having a write-only port and a read-only port that interface with the processing module. The processing module populates the 256 entry output map 316 with 12-bit addresses for each frequency (e.g., 7-bit address 326 for channel number and 5-bit address 328 for frequency index). The input buffer 312 is double buffered (compared to the first BPF circuit 250) so that the channels can be sequentially loaded and randomly clocked out. For example, the input buffer 312 is a 256 × 18 bit two-port SRAM with a write only port and a read only port. Because the inputs are double buffered, the second BPF circuit 250 will have one cycle more delay (e.g., at 300Hz) than the first BPF circuit 250.

At each summing step, the counter 314 clocks through 256 cross points. Each intersection selects a line and a coefficient corresponding to one of the frequencies calculated by the coefficient processor 306. The coefficient processor 306 pre-computes coefficients for the second BPF250 based on the selected frequency. For example, there are 34 possible frequency values for the cross frequency. Thus, the coefficient processor 306 calculates real and imaginary coefficients for each of the 34 possibilities and stores these values in a look-up table.

Coefficient processor 306 inputs real coefficients into coefficient lookup table (LUT)318 and imaginary coefficients into coefficient LUT 320. Each coefficient LUT 318 and 320 is a 34x 18 bit two-port SRAM having a read-only port and a write-only port. A 5-bit address 328 corresponding to the selected frequency is input to each coefficient LUT 318 and 320 and used to select the correct coefficient for the input. The coefficient LUT 318 inputs the 18-bit real coefficient to the multiplier to multiply the 18-bit input value from the digital filter decimation circuit 248. Coefficient LUT 320 multiplies the 18-bit imaginary coefficient input to the second multiplier on the right side of the schematic by the 18-bit input value from digital filter decimation circuit 248.

The rest of the second BPF250 operates similarly to the first BPF circuit 250. The second BPF circuit 250 includes 4 18 x 18 multipliers (e.g., 2 per side per frequency) for multiplying 18 bits from the digital decimation filter circuit 248 with 18 bits from the coefficient LUTs 318 and 320. The second BPF circuit 250 includes 4 30-bit signed accumulators 302 (e.g., 2 per side per frequency) with 256 output registers for summing the multiplied values. The second BPF circuit 250 also includes 4 256 x 24 bit output buffers 304 (e.g., 2 per side per frequency). For example, the output buffer 304 is a two-port SRAM having a write-only port and a read-only port. The second BPF circuit 250 calculates the final product of all 256 received 18-bit values (e.g., 128 channels x 2 frequencies) and shifts the final result to the output buffer 304. The output buffer 304 outputs a 24-bit real component value 322 and a 24-bit imaginary component value 324 to the processing module at 300 Hz.

Fig. 52 is a schematic block diagram of an embodiment of coefficient processor 306. Coefficient processor 306 includes a "nk" latch, +1024, a function multiplexer, a cosine lookup table 330, a frequency lookup table 332, 0.5-0.5x, "w_n"latch, counter 334, two multiplexers, and coefficient processor multiplier 336. The frequency lookup table 332 is a 34x 12 bit two-port static access random access memory (SRAM) that is populated with 34 possible frequency options by the processing module. The cosine lookup table 330 is a 1.17 fixed point 4096 x 16 bit lookup table (e.g., Read Only Memory (ROM)). Coefficient processor multiplier 336 is an 18 x 18 bit signed multiplier.

As previously described, the Discrete Fourier Transform (DFT) transforms N complex sequences (e.g., { x }_n}＝x₀,x₁,…,x_N-1) Conversion to another complex sequence (e.g., { X })_k}＝X₀,X₁,…,X_N-1) WhereinAccording to the Euler formula, can also be expressed as

For each 18-bit input, the coefficient processor 306 pre-computes for each frequencyReal and imaginary parts of (c).

For example, there may be 34 possible frequency options for each input of the BPF circuit 250. For each of the 34 frequency options, each real part coefficient w is pre-computed_ncos (2 π ω n) (for frequency input ω, where) And each imaginary coefficient-w_nsin (2 π ω n) (for frequency input ω, where) By the coefficient processor 306.

The coefficient processor 306 operates at a rate of n that is 1 greater than the BPF circuit 250 so that it is always one cycle ahead of the BPF circuit 250. For each value of n, (which runs at an input sample rate of 1.23MHz), coefficient processor 306 performs the following calculations: 1) w is a_n0.5-0.5cos (2N/N), and for each of the 34 frequency possibilities (k): 1) kn mod 4096, 2) w_ncos (2 π kn/N), and 3) -w_nsin (2 π kn/N). To accomplish this, coefficient processor multiplier 336 operates at n times the input sample rate (e.g., when n is 128, 128 × 1.23MHz is 157.29 MHz).

The counter 334, from 0 to 4095, inputs the value of "n" to the functional multiplexer and the AND w_nA multiplexer to which the latches are connected. The kn latch inputs the kn value to a function multiplexer of cos (2 π kn/N) and sin (2 π kn/N) functions. kn plus 1024 values are also input to the functional multiplexer. Depending on the clock period, a function (e.g., cos (2 π kn/N), -sin (2 π kn/N), or cos (2 π N/N)) is selected. The selected function is input into the cosine lookup table 330 to look up a particular value of the function.

If the selected function does not include k, then a particular value of the cosine lookup table 330 is fed to 0.5-0.5x, where w_nA value of 0.5-0.5cos (2N/N) is calculated and output to w_nA latch. w is a_nThe latch outputs a value and is multiplexed with the counter 334 output. When the function does include k, the selected function is input into the cosine lookup table 330 to look up a particular value of the function. The particular value is then input into the multiplexer along with the output (k) from the frequency lookup table 332. On one clock cycle, a particular value of cos (2 π kn/N) or-sin (2 π kn/N) is input to the coefficient processor multiplier 336 and w_nThe values are multiplied. The calculated coefficient is converted into 18 bits and then output to the BPF circuit 250.

At different clock cycles, the value of k from the frequency lookup table 332 is input to the coefficient processor multiplier 336 to be multiplied by the value n from the counter 334. The kn values are input into kn latches for the next set of calculations.

Fig. 53 is a schematic block diagram of another embodiment of an analog-to-digital conversion circuit 246, which includes analog-to-digital converter (ADC) circuits 1-n 258, a digital filter decimation circuit 248, a pen Band Pass Filter (BPF) circuit 338, a self BPF circuit 340, a coefficient processor 306, a cross BPF circuit 342, and a processing module 252.

The operation of fig. 53 is similar to the embodiment of fig. 49, except that two BPF filters (e.g., pen BPF circuit 338 and slave BPF circuit 340) running at the speed of the input bus, instead of one BPF circuit 250 (e.g., first BPF circuit 250), run at twice the speed of the input bus to calculate two frequencies at a time. The pen BPF circuit 338 and the self BPF circuit 340 process the output from the digital filter decimation circuit 248, where the frequency is known (e.g., self-measure and pen measure are always on), and the mutual BPF circuit 342 is operable to process the output from the digital filter decimation circuit 248, where the frequency is selectable according to a region of interest (ROI).

For example, the mutual capacitance is measured at two points every n electrodes (e.g., 256 frequencies, where n equals 128). The processing module 252 selects which intersections to sample at a particular point based on a given intersection or based on the results of the pen frequency and the self-frequency being always on. The processing module 252 inputs the selection of the frequency 310 into the mutual BPF circuit 342, and the coefficient processor 306 pre-computes the coefficient of the mutual BPF circuit 342 based on the selected frequency.

The self-capacitance is measured at one point (e.g., frequency) every n electrodes, and the pen capacitance is measured at one point every n electrodes (e.g., frequency). These frequencies are known to the system, so the processing module 252 inputs the known frequencies 308 into the coefficient processor 306 to pre-calculate the coefficients from the BPF circuit 338 and BPF circuit 340.

The pen BPF circuit 338 outputs a pen influence value representing the pen capacitance value. A self-influence value representing the self-capacitance value is output from the BPF circuit 340. The mutual BPF circuit 342 outputs a mutual influence value representing the mutual capacitance value. The processing module 252 interprets the imaginary and real components of the impact values to produce a 300Hz data output 256. The influence value 254 is a vector (i.e., phasor complex) having a real component and an imaginary component, representing a sinusoidal function having a peak magnitude (i.e., amplitude) and direction (i.e., phase). For example, the impact values 254 are 48-bit values, each having a 24-bit real component and a 24-bit imaginary component. In the complex domain, voltage and current are phasors, all resistors, capacitors and inductors are replaced with complex impedances (e.g., Z_R＝R、Z_LjfL and Z_C＝1/(jfC)＝-j/(fC))。

Since the impedance of a channel is based primarily on its capacitance (self-, pen-, and/or mutual), as the frequency of the fixed capacitance increases, the impedance decreases based on 1/2 π fC, where f is the frequency and C is the capacitance. Since voltage (V) ═ current (I) × impedance (Z), processing module 252 determines capacitance or other impedance values from the voltage and current vectors that affect the values (e.g., a decrease in impedance increases the voltage of the constant current, increases the current of the constant voltage, or increases the voltage and current of the signal components). The increase and/or decrease in impedance represents the input data. The determined impedance value or change in impedance value is output as data output 256 at an example output rate of 300 Hz.

Figure 54 is a schematic block diagram of one embodiment of the processing module 252 controlling the analog-to-digital conversion circuitry 246. The analog-to-digital conversion circuit 246 is a limited data communication system in which all variables are set by the processing module 252 and controlled for the required data processing. The processing module 252 is operable to control each stage of the analog-to-digital conversion circuit 246 to produce a desired output 256.

For example, the processing module 252 sets the frequency and waveform for each oscillating reference signal via the reference generation circuit 344 (e.g., the reference signal generator 149) to produce the analog reference signal 346. DC component input data 348 is embedded in each analog reference signal 346. The processing module 252 also sets the sampling rate of the ADC 258. ADC258 processes the analog signal including the analog reference signal and the DC component and outputs representative signal 350 to digital filter stage 352 (e.g., digital decimation filter circuit 248 and digital BPF circuit 250).

The processing module 252 determines the stage (e.g., taps) of each filter, the sampling frequency, the filter bandwidth, and any other desired filter parameters. The processing module 252 determines digital filter parameters based on the desired output rate, the desired linearity, and other factors. The processing module 252 inputs the known frequency and the mutual frequency selection into a coefficient processor for the digital BPF filter.

Digital filter stage 352 produces impact values 254 that are interpreted by processing module 252 at data processing 354. The processing module 252 sets data interpretation parameters based on the data output rate and the nature of the input data 348.

For example, the input data 348 may convey one or more of a current (I), a voltage (V), or a change in impedance (Z). For example, if the input is a voltage measurement with a constant current, the processing module 252 may analyze the voltage change to determine an impedance change value. Based on the data interpretation parameters, the processing module 252 interprets the impact values 254 and generates processed output data 256.

As may be used herein, the terms "substantially" and "approximately" provide an industry-accepted tolerance for the relatedness of their corresponding terms and/or items. For some industries, the industry accepts tolerances of less than 1%, while for other industries, the industry accepts tolerances of 10% or higher. Other examples of industry accepted tolerances range from less than 1% to 50%. Industry-accepted tolerances correspond to, but are not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, thermal noise, dimensions, signal errors, packet loss, temperature, pressure, material composition, and/or performance metrics. Within the industry, tolerance differences of acceptable tolerances may be greater or less than a percentage level (e.g., a dimensional tolerance of less than +/-1%). Some correlations between items may range from less than a percentage level to a few percent difference. Other correlations between items may vary from a difference of a few percent to the magnitude of the difference.

As also used herein, the terms "configured to," "operatively coupled to," "coupled to," and/or "coupled" include direct couplings between items and/or indirect couplings between items via intermediate items (e.g., items include, but are not limited to, components, elements, circuits, and/or modules), where, for example, indirect couplings do not modify information of a signal but may adjust its current level, voltage level, and/or power level. As further used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as "coupled to".

As may be further used herein, the terms "configured to," "operable to," "coupled to," or "operably coupled to" indicate that an item includes one or more of a power connection, input(s), output(s), etc., to perform its corresponding function(s) when activated, and may also include inferred coupling to one or more other items. As may be further used herein, the term "associated with" includes direct and/or indirect coupling of separate items and/or embedding of one item in another item.

As may be used herein, the term "compares favorably", indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that the magnitude of signal 1 is greater than the magnitude of signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than the magnitude of signal 2 or the magnitude of signal 2 is less than the magnitude of signal 1. As used herein, the term "disadvantageously compares" means that a comparison between two or more items, signals, etc., fails to provide a desired relationship.

As may be used herein, one or more claims may include the phrase "at least one of a, b, and c" or "at least one of a, b, and c" in the generic form, in a particular form of the generic form, with more or less elements than "a", "b", and "c". In any of these words, the interpretation of the phrases is the same. In particular, "at least one of a, b and c" is equivalent to "at least one of a, b or c" and shall denote a, b and/or c. For example, it means: only "a", only "b", only "c", "a" and "b", "a" and "c", "b" and "c", and/or "a", "b" and "c".

As also used herein, the terms "processing module," "processing circuit," "processor," "processing circuitry," and/or "processing unit" may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, microcontroller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of circuits and/or operational instructions. The processing module, processing circuit, processing circuitry, and/or processing unit may be or further include a memory and/or integrated memory element, which may be a single memory device, multiple memory devices, and/or embedded circuitry of another processing module, processing circuit, processing circuitry, and/or processing unit. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, processing circuit, processing circuitry, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together by a wired and/or wireless bus structure) or may be distributively located (e.g., via indirectly coupled cloud computing via a local area network and/or a wide area network). It is further noted that if the processing module, processing circuit, processing circuitry, and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory elements storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. It is further noted that the memory elements may store hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the figures, and the processing modules, processing circuits, processing circuitry, and/or processing units execute hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the figures. Such storage or memory elements may be included in an article of manufacture.

One or more embodiments have been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. Boundaries and sequences of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences may be defined so long as the specified functions and relationships are appropriately performed. Accordingly, any such alternate boundaries or sequences are within the scope and spirit of the claims. Further, boundaries of these functional building blocks have been arbitrarily defined for the convenience of the description. Alternate boundaries may be defined so long as some important functions are properly performed. Similarly, flow diagram blocks may be arbitrarily defined herein to illustrate certain important functions.

To the extent used, flow diagram block boundaries and sequences may be otherwise defined and still perform some significant function. Such alternative definitions of functional building blocks and flow diagram blocks and sequences are, therefore, within the scope and spirit of the claims. Those of ordinary skill in the art will also appreciate that the functional building blocks, as well as other illustrative blocks, modules, and components herein, may be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software, etc., or any combination thereof.

Further, the flow chart may include a "start" and/or "continue" indication. The "start" and "continue" indications reflect that the presented steps may optionally be incorporated into or otherwise used in conjunction with one or more other routines. Further, the flow chart may include an "end" and/or "continue" indication. The "end" and/or "continue" indications reflect that the presented steps may end as described and illustrated or optionally be incorporated or otherwise used in conjunction with one or more other routines. In this context, "start" means the beginning of the first step presented, and may precede other activities not specifically shown. Further, the "continue" indication reflects that the presented step may be performed multiple times and/or may be continued by other activities not specifically shown. Further, while the flow diagrams indicate a particular order of steps, other orders are equally possible, as long as the principles of causality are maintained.

One or more embodiments are used herein to illustrate one or more aspects, one or more features, one or more concepts, and/or one or more examples. Physical embodiments of devices, articles, machines and/or processes may include one or more aspects, features, concepts, examples, etc., described with reference to one or more embodiments discussed herein. Furthermore, in the various figures, embodiments may include the same or similarly named functions, steps, modules, etc. which may use the same or different reference numbers, and thus the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different functions, steps, modules, etc.

Although the transistors in the above figures are shown as Field Effect Transistors (FETs), as will be appreciated by one of ordinary skill in the art, the transistors may be implemented using any type of transistor structure, including, but not limited to, bipolar Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), N-well transistors, P-well transistors, enhancement, depletion, and zero Voltage Threshold (VT) transistors.

Unless specifically stated to the contrary, signals to, from, and/or between elements in the figures of any of the figures presented herein may be analog or digital, continuous-time or discrete-time, and single-ended or differential. For example, if the signal path is shown as a single ended path, it also represents a differential signal path. Likewise, if the signal path is shown as a differential path, it also represents a single-ended signal path. Although one or more particular architectures are described herein, other architectures using one or more data buses not explicitly shown, direct connections between elements, and/or indirect couplings between other elements as recognized by one of ordinary skill in the art may likewise be implemented.

The term "module" is used in the description of one or more embodiments. A module implements one or more functions by a device such as a processor or other processing device or other hardware, which may include or operate in association with a memory storing operational instructions. The modules may operate independently and/or in conjunction with software and/or firmware. As also used herein, a module may contain one or more sub-modules, each of which may be one or more modules.

As may be further used herein, computer-readable memory includes one or more storage elements. The memory element may be a single memory device, multiple memory devices, or a group of memory locations within a memory device. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. The memory device may be in the form of solid state memory, hard drive memory, cloud memory, thumb drive, server memory, computing device memory, and/or other physical media for storing digital information.

Although specific combinations of features and functions are described herein for one or more embodiments, other combinations of features and functions are also possible. The present disclosure is not limited by the specific embodiments disclosed herein and explicitly incorporates such other combinations.