阅读说明：本技术 一种基于Verilog减法运算的CPLD平台除法实现方法 (CPLD platform division implementation method based on Verilog subtraction operation ) 是由 刘运录 罗阳 杜俊 于 2021-08-03 设计创作，主要内容包括：本发明公开了一种基于Verilog减法运算的CPLD平台除法实现方法,包括如下步骤：CPLD寄存器接收并转换无刷电机转速信息数据,二进制保存以得到二进制的转速信息结果；将转速信息结果进行二分法的减法算法,并将二分法减法算法转换为二进制除法运算；利用移位方式在CPLD逻辑芯片中,实现PI控制算法中的乘除积分运算,实现CPLD平台的除法算法形成除法器。本发明在CPLD平台上,通过二分法的减法转换方式实现除法运算,进而实现在CPLD平台的无刷直流电机的PI控制,其CPLD为逻辑芯片能进行PI的乘、除、积分的逻辑运算,实现CPLD平台的除法计算,可实现高速计算从而满足在CPLD平台上的PI控制。(The invention discloses a CPLD platform division implementation method based on Verilog subtraction operation, which comprises the following steps: the CPLD register receives and converts the brushless motor rotating speed information data, and binary storage is carried out to obtain a binary rotating speed information result; carrying out a dichotomy subtraction algorithm on the rotating speed information result, and converting the dichotomy subtraction algorithm into a binary division operation; and a shifting mode is utilized in the CPLD logic chip to realize multiplication and division integral operation in the PI control algorithm and realize division algorithm of the CPLD platform to form a divider. The invention realizes division operation on the CPLD platform by a subtraction conversion mode of dichotomy, further realizes PI control of the brushless DC motor on the CPLD platform, and the CPLD is a logic chip which can carry out the logic operation of multiplication, division and integration of PI, realizes the division operation of the CPLD platform, and can realize high-speed calculation so as to meet the PI control on the CPLD platform.)

1. A CPLD platform division implementation method based on Verilog subtraction operation is characterized by comprising the following steps:

the CPLD register receives and converts the rotating speed information data of the brushless motor, and further stores the rotating speed information data in a binary manner to obtain a binary rotating speed information result;

carrying out a dichotomy subtraction algorithm on the rotating speed information result, and converting the dichotomy subtraction algorithm into a binary division operation;

and a displacement mode is utilized in the CPLD logic chip to realize multiplication and division integral operation in the PI control algorithm, and the division algorithm of the CPLD platform is realized to form a divider so as to meet the requirement that a PI controller on the CPLD platform converts and updates the rotating speed information of the brushless motor.

2. The CPLD platform division implementation method based on Verilog subtraction operation according to claim 1, wherein the PI controller is implemented as follows:

wherein, n actual rotating speeds, e is the rotating speed difference, the proportional parameter Kp and the integral parameter Ki are both integer powers of two, and nref is the feedback rotating speed.

3. The CPLD platform division implementation method based on Verilog subtraction operation according to claim 1 or 2, characterized in that: the proportional parameter Kp and the integral parameter Ki in the PI controller are fractions in actual use, and need to be divided.

4. The CPLD platform division implementation method based on Verilog subtraction operation according to claim 1, characterized in that: the divider, when enabled, begins to compute:

firstly, the highest position of a quotient is found, the quotient has N bits, the divisor is shifted to the left by N bits, the N is large enough, the divisor is shifted to the left by N bits and then is larger than the dividend, the highest position of the quotient is zero, the divisor is shifted to the left by one bit continuously, namely the N bits are subtracted by one, when the divisor is smaller than the dividend, the highest position of the quotient is one, otherwise, the highest position of the quotient is zero, when the divisor is smaller than the dividend, the dividend is subtracted by the divisor, the dividend is continued to be the dividend, and the operation is circulated until the N is one, namely the divisor is multiplied by 2^ N to be used as the divisor to carry out the above subtraction operation.

5. The CPLD platform division implementation method based on Verilog subtraction operation according to claim 4, characterized in that: when the divider is enabled, judging whether the quotient is one from the high order, if so, subtracting a corresponding numerical value from the dividend; this operation is cycled through until N is zero and the division is complete.

6. The CPLD platform division implementation method based on Verilog subtraction operation according to claim 1, wherein the divider is implemented by the following functions:

wherein, the function description: speed =100M/speed _ reg is realized; speed represents the actual rotating speed of the brushless motor;

num = 100000000: the 100M denominator used for calculating the speed, speed _ reg represents the speed feedback.

7. The CPLD platform division implementation method based on Verilog subtraction operation according to claim 1, characterized in that: in the divider, a divider operation flag is set to be one in the calculation, and the divider is cleared when the division is completed.

8. The CPLD platform division implementation method based on Verilog subtraction operation according to claim 1, characterized in that: the code characteristics of the divider comprise a character string, a derived function, a character string array, a global constant array, a global enumeration array, a complex Switch/Case structure and a complex If/Else structure.

9. The CPLD platform division implementation method based on Verilog subtraction operation according to claim 1, characterized in that: when the divider is used for calculation, the maximum value of the rotation speed calculation is 2^14=16384 r/min.

10. The CPLD platform division implementation method based on Verilog subtraction operation according to claim 1, characterized in that: the conversion link of the brushless motor rotating speed information data of the CPLD register comprises the steps of utilizing a subtracter to realize a division function to obtain rotating speed information and carrying out subtraction to obtain rotating speed error information.

Technical Field

The invention relates to the field of brushless direct current motor control, in particular to a CPLD platform division implementation method based on Verilog subtraction operation, which realizes division operation on a CPLD platform by a subtraction conversion mode of a dichotomy and further realizes PI control of a brushless direct current motor on the CPLD platform.

Background

The CPLD complex programmable logic device is developed from PAL and GAL devices, has relatively large scale and complex structure, and belongs to the large-scale integrated circuit range; the digital integrated circuit is a digital integrated circuit which is used by a user to construct logic functions according to respective needs and is frequently applied to brushless motors.

In the brushless motor, the CPLD is a logic chip that can only perform simple logic operations, and cannot directly perform multiplication, division, and integration operations of the PI.

Disclosure of Invention

The invention aims to provide a CPLD platform division implementation method based on Verilog subtraction operation, so as to solve the problems in the background technology.

In order to achieve the purpose, the invention provides the following technical scheme:

a CPLD platform division implementation method based on Verilog subtraction operation comprises the following steps:

the CPLD register receives and converts the rotating speed information data of the brushless motor, and further stores the rotating speed information data in a binary manner to obtain a binary rotating speed information result;

carrying out a dichotomy subtraction algorithm on the rotating speed information result, and converting the dichotomy subtraction algorithm into a binary division operation;

and a displacement mode is utilized in the CPLD logic chip to realize multiplication and division integral operation in the PI control algorithm, and the division algorithm of the CPLD platform is realized to form a divider so as to meet the requirement that a PI controller on the CPLD platform converts and updates the rotating speed information of the brushless motor.

Preferably, the PI controller is implemented as follows:

wherein, n actual rotating speeds, e is the rotating speed difference, the proportional parameter Kp and the integral parameter Ki are both integer powers of two, and nref is the feedback rotating speed.

Preferably, the proportional parameter Kp and the integral parameter Ki in the PI controller are fractional in actual use, and need to be divided.

Preferably, the divider, when enabled, begins to calculate:

firstly, the highest position of a quotient is found, the quotient has N bits, the divisor is shifted to the left by N bits, the N is large enough, the divisor is shifted to the left by N bits and then is larger than the dividend, the highest position of the quotient is zero, the divisor is shifted to the left by one bit continuously, namely the N bits are subtracted by one, when the divisor is smaller than the dividend, the highest position of the quotient is one, otherwise, the highest position of the quotient is zero, when the divisor is smaller than the dividend, the dividend is subtracted by the divisor, the dividend is continued to be the dividend, and the operation is circulated until the N is one, namely the divisor is multiplied by 2^ N to be used as the divisor to carry out the above subtraction operation.

Preferably, when the divider is enabled, whether the quotient digit is one is judged from the quotient digit, and if the quotient digit is one, the corresponding numerical value is subtracted from the dividend; this operation is cycled through until N is zero and the division is complete.

Preferably, the divider is implemented as follows:

wherein, the function description: speed =100M/speed _ reg is realized; speed represents the actual rotating speed of the brushless motor;

num = 100000000: the 100M denominator used for calculating the speed, speed _ reg represents the speed feedback.

Preferably, in the divider, a divider operation flag is set to be one in the calculation, and the divider is cleared when the division is completed.

Preferably, the code features of the divider include a string, a derived function, a string array, a global constant array, a global enumeration array, a complex Switch/Case structure, and a complex If/Else structure.

Preferably, the maximum value of the rotation speed calculation of the divider in the calculation is 2^14=16384 r/min.

Preferably, the conversion step of the brushless motor rotation speed information data of the CPLD register includes using a subtractor to implement a division function to obtain rotation speed information, and performing a difference to obtain rotation speed error information.

The invention has the beneficial effects that: the invention realizes division operation on the CPLD platform by a subtraction conversion mode of dichotomy, further realizes PI control of the brushless DC motor on the CPLD platform, and the CPLD is a logic chip which can carry out the logic operation of multiplication, division and integration of PI, realizes the division operation of the CPLD platform, and can realize high-speed calculation so as to meet the PI control on the CPLD platform.

Drawings

FIG. 1 is a schematic diagram of a PI controller according to the present invention;

FIG. 2 is a functional diagram of a divider according to the present invention;

FIG. 3 is a code diagram of a divider according to the present invention;

FIG. 4 is a diagram of an implementation model of the PI controller of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1

Referring to fig. 1-4, the present invention provides a technical solution: a CPLD platform division implementation method based on Verilog subtraction operation is characterized by comprising the following steps:

the CPLD register receives and converts the rotating speed information data of the brushless motor, and further stores the rotating speed information data in a binary manner to obtain a binary rotating speed information result; the conversion link of the brushless motor rotating speed information data of the CPLD register comprises the steps of utilizing a subtracter to realize a division function to obtain rotating speed information and carrying out subtraction to obtain rotating speed error information;

carrying out a dichotomy subtraction algorithm on the rotating speed information result, and converting the dichotomy subtraction algorithm into a binary division operation;

and a displacement mode is utilized in the CPLD logic chip to realize multiplication and division integral operation in the PI control algorithm, and the division algorithm of the CPLD platform is realized to form a divider so as to meet the requirement that a PI controller on the CPLD platform converts and updates the rotating speed information of the brushless motor.

A CPLD platform division implementation method based on Verilog subtraction operation comprises the following functions and implementation methods:

the functions are as follows: in the PI controller, Kp, Ki are integer powers of 2, which are fractional numbers in practical use, and a division calculation is required. The multiplication and division integral operation in the PI control algorithm is realized in the CPLD logic chip by using a shifting mode, the division calculation of the CPLD platform is realized, and the high-speed calculation can be realized so as to meet the PI control on the CPLD platform;

the realization is as follows: the divider and the bisection method are realized through software, the efficiency of the divider using a displacement mode is low, and the updating of the rotating speed cannot be completed in time under the condition of high rotating speed. After improvement, judging whether the quotient is 1 from the high order, if so, subtracting a corresponding numerical value from the dividend, namely multiplying the divisor by 2^ N, namely, shifting the divisor by N orders, namely N-1; this operation is cycled through until N is 0 and the division is complete.

It should be noted that, in the present invention, on the CPLD platform, the division operation is realized by the subtraction conversion of the dichotomy, and then the PI control of the brushless dc motor on the CPLD platform is realized, and the CPLD is a logic chip capable of performing the logical operations of multiplication, division and integration of the PI, so as to realize the division calculation on the CPLD platform, and realize the high-speed calculation, thereby satisfying the PI control on the CPLD platform.

Example 2

Referring to fig. 4, in a CPLD platform division implementation method based on Verilog subtraction, a PI controller is implemented as follows:

wherein n actual rotating speeds, e is a rotating speed difference, the proportional parameter Kp and the integral parameter Ki are both integer powers of two, and nref is a feedback rotating speed; the proportional parameter Kp and the integral parameter Ki in the PI controller are fractional numbers in actual use, and need to be divided.

Referring to fig. 2 and 3, when the divider is enabled, the divider starts to calculate: firstly, the highest position of a quotient is found, the quotient has N bits, the divisor is shifted to the left by N bits, the N is large enough, the divisor is shifted to the left by N bits and then is larger than the dividend, the highest position of the quotient is zero, the divisor is shifted to the left by one bit continuously, namely the N bits are subtracted by one, when the divisor is smaller than the dividend, the highest position of the quotient is one, otherwise, the highest position of the quotient is zero, when the divisor is smaller than the dividend, the dividend is subtracted by the divisor, the dividend is continued to be the dividend, and the operation is circulated until the N is one, namely the divisor is multiplied by 2^ N to be used as the divisor to carry out the above subtraction operation.

When the divider is enabled, judging whether the quotient is one from the high order, if so, subtracting a corresponding numerical value from the dividend; this operation is cycled through until N is zero and the division is complete.

Note that the proportional parameter Kp =1/4=0.25 and the integral parameter Ki = 1/256.

Referring to fig. 2, the divider is implemented as follows:

wherein, the function description: speed =100M/speed _ reg is realized; speed represents the actual rotating speed of the brushless motor;

num = 100000000: the 100M denominator used for calculating the speed, speed _ reg represents the speed feedback.

During the calculation of the divider, setting a running mark of the divider as one, and resetting when the division is completed; the code characteristics of the divider comprise a character string, a derivation function, a character string array, a global constant array, a global enumeration array, a complex Switch/Case structure and a complex If/Else structure; when the divider is used for calculation, the maximum value of the rotation speed calculation is 2^14=16384 r/min.

The selected code characteristics of the divider and the explanation thereof accord with the method for realizing the division of the invention: as shown in Table 1 below

Table 1: divider code usage feature type

Example 3

A CPLD platform division implementation method based on Verilog subtraction operation is characterized in that data in a CPLD register are stored in a binary mode to obtain a binary result. In the added rotation speed conversion step, a subtractor running at high speed is used for realizing the function of division, so that rotation speed information is obtained, and difference is made to obtain rotation speed error information; when the divider is enabled, the calculation is started, when the dividend is larger than the divisor, the quotient is added with 1, the dividend subtracts the divisor to obtain a new dividend, the dividend is known to be smaller than the divisor, in the calculation, the operation mark of the divider is set to be 1, the clear 0 of the division rule is completed, and the purpose is to clear an enabling signal for an enabling divider module. The updating of the rotation speed may not be completed in time in case of a fast rotation speed.

The method comprises the steps of using a subtraction algorithm of a dichotomy, regarding the division as a binary division, firstly finding the highest bit of a quotient, assuming that the quotient has N bits, the divisor is shifted to the left by N bits, wherein N is enough, the divisor is shifted to the left by N bits and then is larger than a dividend, the highest bit of the quotient is 0, the divisor continues to be shifted to the left by N-1 bits, when the divisor is smaller than the dividend, the highest bit of the quotient is 1, otherwise, the divisor is 0, when the divisor is smaller than the dividend, the dividend is subtracted from the divisor, and repeating the above steps until N is 1, namely multiplying the divisor by 2^ N as the divisor to perform the above subtraction operation, so that the efficiency of the divider can be greatly improved, and the PI control of a brushless motor running at high speed is satisfied.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.