阅读说明：本技术 具有扩大栅极垫的半导体封装及其制造方法 (Semiconductor package having enlarged gate pad and method of manufacturing the same ) 是由 薛彦迅 何约瑟 王隆庆 张晓天 牛志强 于 2021-05-28 设计创作，主要内容包括：本发明公开了一种半导体封装制造方法,包括提供一个晶圆、采用一个种子层、形成一个光致抗蚀剂层、电镀一个铜层、去除光致抗蚀剂层、去除种子层、施加研磨工艺、形成金属化和施加分离工艺等步骤。本发明还公开了一种半导体封装,包括一个硅层、一个铝层、一个钝化层、一个聚酰亚胺层、一个铜层和一个金属化。在一个示例中,栅极夹片的接触区域的面积小于栅极铜表面的面积,栅极夹片的接触面积大于栅极铝表面。在另一示例中,栅极引脚的接触区域的面积大于栅极铜表面的面积,栅极引脚的接触区域的面积大于栅极铝表面。(The invention discloses a semiconductor packaging manufacturing method which comprises the steps of providing a wafer, adopting a seed layer, forming a photoresist layer, electroplating a copper layer, removing the photoresist layer, removing the seed layer, applying a grinding process, forming metallization, applying a separation process and the like. The invention also discloses a semiconductor package comprising a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer and a metallization. In one example, the contact area of the gate clip is smaller than the area of the gate copper surface and the contact area of the gate clip is larger than the gate aluminum surface. In another example, the contact area of the gate lead is larger in area than the gate copper surface and the contact area of the gate lead is larger in area than the gate aluminum surface.)

1. A method for preparing a plurality of power semiconductor chips, the method comprising the steps of:

preparing a wafer comprising

A plurality of power semiconductor devices, wherein each power semiconductor device of the plurality of power semiconductor devices comprises

A first metal layer, which is positioned on the front surface of the wafer and forms the pattern of a first source electrode metal pad and a first grid electrode metal pad; and

a passivation layer covering the first source metal pad and the first gate metal pad, the passivation layer being patterned to expose a top surface of the first source metal pad through one or more source passivation opening portions of the passivation layer and to expose a top surface of the first gate metal pad through a gate passivation opening portion of the passivation layer;

depositing a seed layer onto the front side of the wafer;

arranging a photoresist layer above the seed layer and forming a pattern;

plating a second metal layer onto the front side of the wafer in the region exposed by the photoresist layer;

removing the photoresist layer;

removing the remaining part of the seed layer which is not covered by the second metal layer;

grinding the back of the wafer to form a thin wafer;

forming a metallization on a back side of the thin wafer; and

and forming the plurality of power semiconductor chips by applying a separation process.

2. The method for manufacturing a plurality of power semiconductor chips of claim 1 wherein the step of electroplating the second metal layer forms a second gate metal pad and a second source metal pad separated by the photoresist; wherein the second gate metal pad covers the first gate metal pad; wherein the second source metal pad covers the first source metal pad; and wherein an area of the top surface of the second gate metal pad is larger than the gate passivation opening of the passivation layer.

3. The method for preparing a plurality of power semiconductor chips of claim 2 wherein said wafer further has a polyimide layer overlying said passivation layer; wherein the polyimide layer is patterned to expose a top surface portion of the first source metal pad through one or more source passivation opening portions of the passivation layer and to expose a top surface portion of the first gate metal pad through a gate passivation opening of the passivation layer.

4. The method for fabricating a plurality of power semiconductor chips of claim 3 wherein the second gate metal pad fills the gate passivation opening over the first gate metal pad; and wherein the second gate metal pad further extends above a top surface of the passivation layer and a top surface of the polyimide layer.

5. The method for preparing a plurality of power semiconductor chips as defined in claim 4, wherein the first metal layer comprises an aluminum layer and the step of electroplating the second metal layer comprises a substep of electroplating a copper layer.

6. The method for manufacturing a plurality of power semiconductor chips of claim 5 wherein each power semiconductor device in the plurality of power semiconductor devices further comprises a metal-oxide semiconductor field effect transistor; and is

Wherein the second gate metal pad in the sub-step of electroplating the copper layer is electrically connected to a gate contact region of the metal-oxide semiconductor field effect transistor through the first gate metal pad.

7. A power semiconductor chip, comprising:

a semiconductor substrate including a power semiconductor device;

a first metal layer overlying the semiconductor substrate, the first metal layer being patterned to include a larger area first source metal pad and a smaller area first gate metal pad spaced apart, the first source metal pad being electrically connected to a source contact region of the power semiconductor device, the first gate metal pad being electrically connected to a gate contact region of the power semiconductor device;

a passivation layer overlying the first metal layer, the passivation layer patterned to expose a top portion of the first source metal pad through one or more source passivation openings of the passivation layer and to expose a top portion of the first gate metal pad through a gate passivation opening of the passivation layer, wherein each of the one or more source passivation openings is at least ten times the area of the gate passivation opening; and

a second metal layer overlying the passivation layer and the first metal layer, the second metal layer including a second source metal pad and a second gate metal pad separated by the second source metal pad, the second source metal pad filling the one or more source passivation openings of the passivation layer and being electrically connected to the first source metal pad, the second gate metal pad filling the gate passivation openings of the passivation layer and being electrically connected to the first gate metal pad;

wherein the top surface area of the second gate metal pad is larger than the gate passivation opening of the passivation layer.

8. The power semiconductor chip of claim 7, further comprising a polyimide layer overlying the passivation layer, the polyimide layer patterned to expose a top portion of the first source metal pad through the one or more source passivation openings of the passivation layer and to expose a top portion of the first gate metal pad through the gate passivation opening of the passivation layer.

9. The power semiconductor chip of claim 8, wherein the first metal layer comprises an aluminum layer.

10. The power semiconductor chip of claim 9, wherein the second metal layer comprises a copper layer.

11. The power semiconductor chip of claim 10, wherein the gate passivation opening of the passivation layer is less than 0.3mm x 0.3mm, and wherein the top surface area of the second gate metal pad is greater than 0.3mm x 0.3 mm.

12. The power semiconductor chip of claim 10, wherein the semiconductor device comprises a metal-oxide semiconductor field effect transistor, and wherein the second gate metal pad is electrically connected to a gate contact region of the metal-oxide semiconductor field effect transistor through the first gate metal pad.

13. A semiconductor package, comprising:

a lead frame,

a semiconductor chip on the lead frame, the semiconductor chip comprising:

a semiconductor substrate including a power semiconductor device;

an aluminum layer covering the front surface of the semiconductor substrate, the aluminum layer being patterned and including a first source metal pad of a larger area and a first gate metal pad of a smaller area spaced apart from each other, the first source metal pad being electrically connected to the source contact region of the power semiconductor device, the first gate metal pad being electrically connected to the gate contact region of the power semiconductor device;

a passivation layer covering the aluminum layer;

a polyimide layer over the passivation layer;

a copper electroplating layer; and

a back metal on a back side opposite to the front side of the semiconductor substrate;

wherein the passivation layer and the polyimide layer are patterned to expose a top portion of the first source metal pad through one or more source passivation openings and to expose a top portion of the first gate metal pad through a gate passivation opening;

wherein the electroplated copper layer includes a first source metal pad and a second gate metal pad spaced apart from the second source metal pad;

wherein the second source metal pad fills the one or more source passivation openings of the passivation layer and is electrically connected to the first source metal pad;

wherein the second gate metal pad fills the gate passivation opening of the passivation layer and is electrically connected to the first gate metal pad; and is

Wherein the top surface area of the second gate metal pad is larger than the gate passivation opening of the passivation layer.

14. The semiconductor package of claim 13, wherein the lead frame includes a die pad, a gate lead, and a source lead spaced apart from each other; and wherein the semiconductor chip is located on the wafer pad with its backside metallization electrically connected to the wafer pad.

15. The semiconductor package of claim 14, wherein a gate conductive element electrically connects the second gate metal pad on the semiconductor chip to the gate lead of the lead frame; and one of the source conductive elements electrically connects the second source metal pad of the semiconductor chip to the source lead of the lead frame.

16. The semiconductor package of claim 15, wherein a contact area between the gate conductive element and the second gate metal pad is greater than a top surface area of the first gate metal pad exposed through the gate passivation opening.

17. The semiconductor package of claim 16, wherein the gate conductive element comprises a gate clip; and wherein the source conductive element comprises a source clip.

18. The semiconductor package according to claim 13, wherein the lead frame includes a source substrate, a gate substrate and a drain lead spaced apart from each other; wherein the semiconductor chip is placed on the lead frame in an inverted state, the second source metal pad is electrically connected to the source substrate, and the second gate metal pad is electrically connected to the gate substrate; and one of the drain conductive elements electrically connects the backside metallization to the drain lead.

19. The semiconductor package of claim 18, wherein a contact area between the gate substrate and the second gate metal pad is greater than an area of a top surface of the first gate metal pad exposed through the gate passivation opening.

20. The semiconductor package of claim 13, wherein the semiconductor device comprises a metal-oxide semiconductor field effect transistor, and wherein the second gate metal pad is electrically connected to the gate contact region of the metal-oxide semiconductor field effect transistor through the first gate metal pad.

Technical Field

The present invention generally relates to a semiconductor package and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor package having an enlarged gate pad and a method of manufacturing the same.

Background

With the progress of semiconductor manufacturing technology, the size of a power semiconductor chip is continuously reduced without affecting its power processing capability. As the size of power semiconductor chips continues to shrink, the size of their gate pads also correspondingly decreases. For applications requiring smaller physical dimensions, such as mobile applications, power semiconductor chips are packaged to 3.3mm x 3.3mm, or even smaller package sizes. Clip bonding techniques offer the advantages of higher current handling and lower resistance for power semiconductor devices, but result in a larger area in the process compared to wire bonding techniques. In order to fully utilize the chip size, it is necessary to maximize the size of the source pad and minimize the size of the gate pad. A hybrid bonding process, i.e., clip bonding of the source pad and wire bonding of the gate pad, has been proposed. However, such hybrid bonding processes add complexity to the process, increase manufacturing costs, and increase contamination. Generally, gate pads of 0.3mm x 0.3mm or larger are suitable for clip bonding. Smaller gate pads of 0.1mm x 0.1mm must use wire bonding. Wire bonding of the gate pad after clip bonding of the source pad typically has reliability issues including the wire not sticking to the gate pad. During reflow, the solder paste solvent used in the clip bonding for the source pad contaminates the gate pad.

Disclosure of Invention

An object of the present invention is to provide a method of manufacturing a plurality of semiconductor packages. The method includes the steps of providing a wafer, applying a seed layer, forming a photoresist layer, applying an electroplated copper layer, removing the photoresist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a separation process.

It is another object of the present invention to provide a semiconductor package comprising a semiconductor layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer and metallization. In one example, the area of the contact region of the gate clip is less than the area of the gate copper surface. The contact area of the gate clip is larger than the gate aluminum surface. In another example, the area of the contact region of the gate lead is greater than the area of the gate copper surface. The contact area of the gate lead is larger than the gate aluminum surface. The invention simplifies the process flow, reduces the manufacturing cost and reduces the pollution.

In order to achieve the above object, the present invention provides a method for preparing a plurality of power semiconductor chips, the method comprising the steps of:

preparing a wafer comprising

A plurality of power semiconductor devices, wherein each power semiconductor device of the plurality of power semiconductor devices comprises

A first metal layer, which is positioned on the front surface of the wafer and forms the pattern of a first source electrode metal pad and a first grid electrode metal pad; and

a passivation layer covering the first source metal pad and the first gate metal pad, the passivation layer being patterned to expose a top surface of the first source metal pad through one or more source passivation opening portions of the passivation layer and to expose a top surface of the first gate metal pad through a gate passivation opening portion of the passivation layer;

depositing a seed layer onto the front side of the wafer;

arranging a photoresist layer above the seed layer and forming a pattern;

plating a second metal layer onto the front side of the wafer in the region exposed by the photoresist layer;

removing the photoresist layer;

removing the remaining part of the seed layer which is not covered by the second metal layer;

grinding the back of the wafer to form a thin wafer;

forming a metallization on a back side of the thin wafer; and

and forming the plurality of power semiconductor chips by applying a separation process.

Optionally, a step of electroplating the second metal layer to form a second gate metal pad and a second source metal pad separated by the photoresist; wherein the second gate metal pad covers the first gate metal pad; wherein the second source metal pad covers the first source metal pad; and wherein an area of the top surface of the second gate metal pad is larger than the gate passivation opening of the passivation layer.

Optionally, the wafer further has a polyimide layer covering the passivation layer; wherein the polyimide layer is patterned to expose a top surface portion of the first source metal pad through one or more source passivation opening portions of the passivation layer and to expose a top surface portion of the first gate metal pad through a gate passivation opening of the passivation layer.

Optionally, the second gate metal pad fills the gate passivation opening above the first gate metal pad; and wherein the second gate metal pad further extends above a top surface of the passivation layer and a top surface of the polyimide layer.

Optionally, the first metal layer comprises an aluminum layer and the step of electroplating the second metal layer comprises a copper layer electroplating sub-step.

Optionally, each power semiconductor device in the plurality of power semiconductor devices further comprises a metal-oxide semiconductor field effect transistor; and is

Wherein the second gate metal pad in the sub-step of electroplating the copper layer is electrically connected to a gate contact region of the metal-oxide semiconductor field effect transistor through the first gate metal pad.

The present invention also provides a power semiconductor chip comprising:

a semiconductor substrate including a power semiconductor device;

a first metal layer overlying the semiconductor substrate, the first metal layer being patterned to include a larger area first source metal pad and a smaller area first gate metal pad spaced apart, the first source metal pad being electrically connected to a source contact region of the power semiconductor device, the first gate metal pad being electrically connected to a gate contact region of the power semiconductor device;

a passivation layer overlying the first metal layer, the passivation layer patterned to expose a top portion of the first source metal pad through one or more source passivation openings of the passivation layer and to expose a top portion of the first gate metal pad through a gate passivation opening of the passivation layer, wherein each of the one or more source passivation openings is at least ten times the area of the gate passivation opening; and

a second metal layer overlying the passivation layer and the first metal layer, the second metal layer including a second source metal pad and a second gate metal pad separated by the second source metal pad, the second source metal pad filling the one or more source passivation openings of the passivation layer and being electrically connected to the first source metal pad, the second gate metal pad filling the gate passivation openings of the passivation layer and being electrically connected to the first gate metal pad;

wherein the top surface area of the second gate metal pad is larger than the gate passivation opening of the passivation layer.

Optionally, the power semiconductor chip further comprises a polyimide layer covering the passivation layer, the polyimide layer being patterned to expose a top surface portion of the first source metal pad through one or more source passivation openings of the passivation layer and to expose a top surface portion of the first gate metal pad through a gate passivation opening of the passivation layer.

Optionally, the first metal layer comprises an aluminum layer.

Optionally, the second metal layer comprises a copper layer.

Optionally, the gate passivation opening of the passivation layer is smaller than 0.3mm × 0.3mm, and the top surface area of the second gate metal pad is larger than 0.3mm × 0.3 mm.

Optionally, the semiconductor device comprises a metal-oxide semiconductor field effect transistor, and wherein the second gate metal pad is electrically connected to a gate contact region of the metal-oxide semiconductor field effect transistor through the first gate metal pad.

The present invention also provides a semiconductor package, comprising:

a lead frame,

a semiconductor chip on the lead frame, the semiconductor chip comprising:

a semiconductor substrate including a power semiconductor device;

an aluminum layer covering the front surface of the semiconductor substrate, the aluminum layer being patterned and including a first source metal pad of a larger area and a first gate metal pad of a smaller area spaced apart from each other, the first source metal pad being electrically connected to the source contact region of the power semiconductor device, the first gate metal pad being electrically connected to the gate contact region of the power semiconductor device;

a passivation layer covering the aluminum layer;

a polyimide layer over the passivation layer;

a copper electroplating layer; and

a back metal on a back side opposite to the front side of the semiconductor substrate;

wherein the passivation layer and the polyimide layer are patterned to expose a top portion of the first source metal pad through one or more source passivation openings and to expose a top portion of the first gate metal pad through a gate passivation opening;

wherein the electroplated copper layer includes a first source metal pad and a second gate metal pad spaced apart from the second source metal pad;

wherein the second source metal pad fills the one or more source passivation openings of the passivation layer and is electrically connected to the first source metal pad;

wherein the second gate metal pad fills the gate passivation opening of the passivation layer and is electrically connected to the first gate metal pad; and is

Wherein the top surface area of the second gate metal pad is larger than the gate passivation opening of the passivation layer.

Optionally, the lead frame comprises a die pad, a gate lead and a source lead which are spaced apart from each other; and wherein the semiconductor chip is located on the wafer pad with its backside metallization electrically connected to the wafer pad.

Optionally, a gate conductive element electrically connects the second gate metal pad on the semiconductor chip to the gate lead of the lead frame; and one of the source conductive elements electrically connects the second source metal pad of the semiconductor chip to the source lead of the lead frame.

Optionally, a contact area between the gate conductive element and the second gate metal pad is larger than a top surface area of the first gate metal pad exposed through the gate passivation opening.

Optionally, the gate conductive element comprises a gate clip; and wherein the source conductive element comprises a source clip.

Optionally, the lead frame includes a source substrate, a gate substrate and a drain lead which are spaced apart from each other; wherein the semiconductor chip is placed on the lead frame in an inverted state, the second source metal pad is electrically connected to the source substrate, and the second gate metal pad is electrically connected to the gate substrate; and one of the drain conductive elements electrically connects the backside metallization to the drain lead.

Optionally, a contact area between the gate substrate and the second gate metal pad is larger than a top surface area of the first gate metal pad exposed through the gate passivation opening.

Optionally, the semiconductor device comprises a metal-oxide semiconductor field effect transistor, wherein the second gate metal pad is electrically connected to the gate contact region of the metal-oxide semiconductor field effect transistor through the first gate metal pad

Compared with the prior art, the invention has the beneficial effects that:

the copper plating of the invention replaces the traditional NiPdAu plating. The clamping piece joint of the grid electrode pad and the clamping piece joint of the source electrode pad replace the traditional mixed joint process, simplify the process flow, reduce the manufacturing cost and reduce the pollution.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are an embodiment of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts according to the drawings:

fig. 1Ai and 1Fi illustrate top views of process steps for fabricating a plurality of semiconductor packages in an example of the present invention;

FIGS. 1Aii, 1B, 1C, 1D, 1E and FIG. 1Fii show cross-sectional views of this process step;

FIG. 1Aii shows a cross-sectional view of FIG. 1Ai taken along line AA';

FIG. 1Fii shows a cross-sectional view of FIG. 1Fi along line BB';

fig. 2Ai shows a top view of a semiconductor package in an example of the invention;

fig. 2Aii shows a cross-sectional view of the semiconductor package of fig. 2 Ai;

FIG. 2B illustrates a cross-sectional view of another semiconductor package in an example of the present invention;

fig. 3 shows a process flow diagram for preparing a plurality of semiconductor packages in an example of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In an example of the present invention, fig. 3 shows a flow chart of a process 300 of preparing a plurality of semiconductor packages.

The process 300 may begin at block 302. In an example of the present invention, fig. 1Ai and 1Fi represent top views, and fig. 1Aii, 1B, 1C, 1D, 1E and 1Fii represent cross-sectional views of a process of preparing a plurality of semiconductor packages. For simplicity, only one semiconductor chip is shown in each of fig. 1Ai and 1Fi and fig. 1Aii, 1B, 1C, 1D, and 1E. In fig. 1Fii, a part of the adjacent semiconductor chip 193 is indicated by a dotted line.

In block 302, referring to fig. 1Ai and 1Aii, wafer 100 includes a plurality of power semiconductor chips. Each power semiconductor chip on wafer 100 includes a semiconductor substrate layer 110 on which the power semiconductor device is formed, a first metal layer 120, preferably an aluminum layer, a passivation layer 130, and a polyimide layer 140. In one example, first metal layer 120 is disposed over front surface 114 of semiconductor substrate layer 110. In another example, the first metal layer 120 is patterned into a larger area of the first source metal pad 120S, and a smaller area of the first gate metal pad 120G separated from the first source metal pad. In an example of the present invention, the area of the first source metal pad 120S is at least fifty times larger than the area of the first gate metal pad 120G. The first source metal pad 120S is electrically connected to one source contact region (not shown) of the power semiconductor device formed on top of the semiconductor substrate layer 110, and the top of the first gate metal pad 120G is electrically connected to a gate contact region (not shown) of the power semiconductor device formed on top of the semiconductor substrate layer 110. The passivation layer 130 is positioned on the first metal layer 120 and partially fills the first gap separating the first source metal pad 120S and the first gate metal pad 120G. The polyimide layer 140 is located over the passivation layer 130 and is much thicker than the passivation layer 130. Polyimide layer 140 fills the remainder of the gap to provide a substantially flat top surface across the gap separating first source metal pad 120S and first gate metal pad 120G.

The passivation layer 130 and the polyimide layer 140 have a pattern of one or more source passivation openings 124 on the first source metal pad 120S and a pattern of one gate passivation opening 126 on the first gate metal pad 120G. In an example of the present invention, each of the one or more source passivation openings 124 is at least ten times the area of the gate passivation opening 126. The first gate metal pad 120G includes an exposed gate aluminum surface 125 through a gate passivation opening 126. The center of the gate passivation opening 126 is substantially aligned with the center of the first gate metal pad 120G, and the area of the gate passivation opening 126 is smaller than the entire top surface area of the first gate metal pad 120G. The first source metal pad 120S also includes a first exposed source aluminum surface 127 and a second exposed source aluminum surface 129 through the one or more source passivation openings 124. In another example, the polyimide layer 140 is optional and the passivation layer 130 fills the gap to provide a substantially flat top surface over the gap separating the first source metal pad 120S and the first gate metal pad 120G. Block 302 may be followed by block 304.

In block 304, referring now to fig. 1B, a seed layer 150 is applied to the front surface of the wafer 100. In an example of the invention, the seed layer is applied by a Physical Vapor Deposition (PVD) process. Seed layer 150 includes a first portion 152 and a second portion 154. The first portion 152 of the seed layer 150 will diffuse into the second metal layer 180 of fig. 1D (in one example, the second metal layer 180 is a copper layer). In block 312, the second portion 154 of the seed layer 150 is removed. In examples of the present disclosure, the seed layer 150 includes TiCu. Block 304 may be followed by block 306.

In block 306, referring to fig. 1C, a photoresist layer 170 is formed over the seed layer 150. The photoresist layer 170 has one or more source photoresist openings 174 on the first source metal pad 120S and a gate photoresist opening 176 on the first gate metal pad 120G. In an example of the present invention, the area of each of the one or more source photoresist openings 174 is at least ten times the area of the gate photoresist opening 176. In one example, the edges of the one or more source photoresist openings 174 are substantially aligned with the edges of the one or more source passivation openings 124 such that the one or more source photoresist openings 174 are substantially the same shape and size as the one or more source passivation openings 124. In another example, the edges of the gate photoresist opening 176 are recessed from the edges of the gate passivation opening 126 such that the area of the gate photoresist opening 176 is greater than the area of the gate passivation opening 126. The photoresist layer 170 covers the second portion 154 of the seed layer 150. Block 306 may be followed by block 308.

In block 308, referring to fig. 1D, a second metal layer 180, preferably a copper layer, is plated on the first portion 152 of the seed layer 150 not covered by the photoresist layer 170. In this process, the first portion 152 of the seed layer 150 diffuses into the copper layer. Second metal layer 180 includes a second source metal pad 180S having a top surface area defined by one or more source photoresist openings 174 and a second gate metal pad 180G having a top surface area defined by gate photoresist opening 176. The photoresist layer 170 separates the second gate metal pad 180G from the second source metal pad 180S. Block 308 may be followed by block 310.

In block 310, referring to fig. 1E, the photoresist layer 170 shown in fig. 1D is removed using a lift-off process. Block 310 may be followed by block 312.

In block 312, still referring to fig. 1E, the second portion 154 of the seed layer 150 shown in fig. 1B is removed by an etching process. A portion of the front surface 142 of the polyimide layer 140 is exposed through a second gap separating the second source metal pad 180S and the second gate metal pad 180G. The second gap is at least as wide as the first gap separating the first source metal pad 120S and the first gate metal pad 120G. In one example, the top surface edge of the second gate metal pad extends beyond the first edge of the passivation layer 130, and the polyimide layer 140 bonded to the second gate metal pad faces the second edge of the passivation layer 130 and the polyimide layer 140 bonded to the second source metal pad. In another example, an edge of the second source metal pad 180S is substantially aligned with a second edge of the passivation layer 130 and the polyimide layer 140, the exposed front surface 142 of the polyimide layer being between the first edge and the second edge. Block 312 may be followed by block 314.

In block 314, referring to fig. 1Fi and 1Fii, a grinding process is applied to the wafer backside 112 of fig. 1Aii of the semiconductor substrate layer 110 of fig. 1Aii to form a thin wafer 190. In an embodiment of the present invention, the thickness of the wafer before the grinding process is in the range of 700 μm to 800 μm. The thickness of the thinned wafer 190 is in the range of 80 μm to 120 μm. Block 314 may be followed by block 316.

In block 316, referring to fig. 1Fii, metallization 194 is formed on the back side 192 of the thinned wafer 190. In the present example, the metallization 194 includes a titanium layer, a nickel layer, and a silver layer. Metallization 194 forms the bottom drain of the power semiconductor device. Block 316 may be followed by block 318.

In block 318, still referring to fig. 1Fii, the singulation process 198 singulates the semiconductor chip 191 from adjacent semiconductor chips 193 (shown in phantom) of the wafer 100 to form a plurality of semiconductor chips, each of which includes a power semiconductor device.

Fig. 1Fii shows a semiconductor chip 191 comprising a power semiconductor device. Semiconductor chip 191 includes a semiconductor substrate layer 110', a first metal layer 120, a passivation layer 130, a polyimide layer 140, and a second metal layer 180 formed on the front side of semiconductor substrate layer 110', and a back side metallization 194 formed on the back side of semiconductor substrate layer 110 '. In one example, the first metal layer 120 includes one aluminum layer. In another example, the first metal layer 120 is patterned into a first source metal pad 120S and a first gate metal pad 120G that are separate from the first source metal pad 120S. The first source metal pad 120S is electrically connected to a source contact region (not shown) of the power semiconductor device, and the first gate metal pad 120G is electrically connected to a gate contact region (not shown) of the power semiconductor device. The passivation layer 130 is located over the first metal layer 120. A polyimide layer 140 is over the passivation layer 130. The passivation layer 130 and the polyimide layer 140 have one or more source passivation openings 124 on the first source metal pad 120S and one gate passivation opening 126 on the first gate metal pad 120G.

Second metal layer 180 fills one or more source passivation openings 124 on first source metal pad 120S and gate passivation openings 126 on first gate metal pad 120G. Second metal layer 180 further extends over the top surface of passivation layer 130 and polyimide layer 140. The second metal layer 180 includes a second gate metal pad 180G and a second source metal pad 180S, and the second gate metal pad 180G is disposed above the first gate metal pad 120G. The second gate metal pad 180G has a substantially planar top surface with an area larger than the gate passivation opening 126, which defines the exposed gate aluminum surface 125 of the first gate metal pad 120G. In another example, second metal layer 180 comprises a copper plated layer.

The second gate metal pad 180G includes a bare gate copper surface 185 on the front surface 184 of the semiconductor die that provides the gate electrode of the power semiconductor device. The second gate metal pad 180G is electrically connected to a gate contact region (not shown) of the power semiconductor device through the first gate metal pad 120G. The area of the exposed gate copper surface 185 of the second gate metal pad 180G, which is larger than the area of the exposed gate aluminum surface 125 of the first gate metal pad 120G, is exposed through the gate passivation opening 126. In an alternative embodiment, the top surface area of the second gate metal pad 180G is greater than the entire top surface area of the first gate metal pad 120G.

The second source metal pad 180S is electrically connected to a source contact region (not shown) of the power semiconductor device through the first source metal pad 120S, providing a source of the power semiconductor device. As shown in fig. 1Fi, the second source metal pad 180S further includes a first exposed source copper surface 187 and a second exposed source copper surface 189 on the front surface of the semiconductor die that cover the first exposed source aluminum surface 127 and the second exposed source aluminum surface 129, respectively.

In an example of the invention, the exposed gate copper surface 185 of block 308 (fig. 1Fi) is a first rectangle. The area of exposed gate aluminum surface 125 of block 302 (fig. 1Ai) is a second rectangular shape.

The back side metallization 194 formed on the back side of the semiconductor substrate layer 110 'extends substantially over the entire back side of the semiconductor substrate layer 110'. In one example, the semiconductor chip includes one vertical power semiconductor device, and the back surface metallization 194 is provided as a drain. The voltage applied to the gate controls the current between the source and drain.

In an example of the present invention, fig. 2Ai shows a top view of the semiconductor package 200, and fig. 2Aii shows a cross-sectional view of the semiconductor package 200 along line CC'.

In an example of the invention, a semiconductor chip 191 containing a power semiconductor device is deposited on a leadframe 201, and the bottom drain electrode (metallization 194) of the leadframe 201 is electrically connected to the leadframe die pad 203. A source conductive element 210 electrically and mechanically connects the first exposed source copper surface 187 and the second exposed source copper surface 189 to the source lead 212 of the lead frame 201 and a gate conductive element 220 electrically and mechanically connects the exposed gate copper surface 185 to the gate lead 222 of the lead frame 201. Gate lead 222, source lead 212, and die pad 203 are separated from each other. An optional drain lead may be electrically connected to die pad 203. At least a portion of the bottom surfaces of gate lead 222, source lead 212, and die pad 203 or the optional drain lead are exposed through the bottom of a molded package (not shown) encapsulating lead frame 201, semiconductor chip 191, source conductive element 210, and gate conductive element 220.

In the present example, the semiconductor chip 191 includes a semiconductor transistor, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The exposed gate copper surface 185 (fig. 1Fi) of block 308 is electrically connected to the exposed gate aluminum surface 125 (fig. 1Ai) of block 302. A voltage applied to the gate lead controls the current flow between the source lead and the drain lead.

In a preferred example of the present invention, the gate conductive element 220 may be a metal clip connected to the exposed gate copper surface 185 of the second gate metal pad 180G by a conductive adhesive (e.g., solder or conductive epoxy). In another preferred example, the gate conductive element 220 comprises a metal strip connected to the exposed gate copper surface 185 with or without an adhesive. The contact area 225 between the conductive element 220 and the exposed gate copper surface 185 is less than the area of the exposed gate copper surface 185. The contact area 225 between the gate conductive element 220 and the exposed gate copper surface 185 is larger than the exposed gate aluminum surface 125 (fig. 1Ai) through the gate passivation opening 126 of block 302.

In an example of the present invention, fig. 2B shows a cross-sectional view of a semiconductor package 250.

In an example of the present invention, a semiconductor chip 191 including one power semiconductor device is flipped and disposed on a lead frame 251, a second source metal pad 180S is electrically connected to a source pad 260 of the lead frame 251, and a second gate metal pad 180G is electrically connected to a gate pad 240 of the lead frame 251. The drain conductive element 253 electrically and mechanically connects the bottom drain electrode (metallization 194) of the semiconductor chip 191 to a drain lead (not shown) of the leadframe 251. The gate pad 240, the source pad 260, and the drain lead are separated from each other. The gate pad 240 may be connected to a gate lead (not shown), and the source pad 260 may be connected to a source lead. Bottom surfaces of at least portions of the gate, source and drain leads are exposed through a bottom of a mold package (not shown) encapsulating the lead frame 251, the semiconductor chip 191 and the drain conductive member 253.

In an example of the present invention, the semiconductor chip 191 includes a semiconductor transistor, such as a MOSFET. The exposed gate copper surface 185 is electrically connected to the exposed gate aluminum surface 125 of block 302 (fig. 1 Ai). A voltage applied to the gate base controls the current flow between the source lead and the drain lead.

In a preferred example of the present invention, the exposed gate copper surface 185 of the second gate metal pad 180G may be connected to the gate pad 240 by a conductive adhesive (e.g., solder or conductive epoxy). The contact area 245 between the gate pedestal 240 and the exposed gate copper surface 185 is larger than the exposed gate aluminum surface 125 through the gate passivation opening 126 (fig. 1Ai) of block 302.

In an example of the present invention, the semiconductor chip 191 includes a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a gate and a source disposed on a front surface and a drain on a back surface. The semiconductor chip 191 may include other types of vertical semiconductor devices having control electrodes disposed on a major surface of the semiconductor chip to control current flowing through an opposite major surface of the semiconductor chip, such as insulated gate control transistors (IGBTs).

One of ordinary skill in the art will recognize that modifications to the disclosed embodiments are possible. For example, the size of the area of exposed gate copper surface 185 may vary. Other modifications may occur to those skilled in the art and all such modifications are considered to be within the scope of the present invention as defined by the claims.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.