阅读说明：本技术 半导体封装装置及其制造方法 (Semiconductor package device and method of manufacturing the same ) 是由 黃文宏 于 2021-09-07 设计创作，主要内容包括：本公开涉及半导体封装装置及其制造方法。半导体封装装置包括：基板,所述基板具有第一通孔；以及重布线层,下表面接触所述基板,所述重布线层具有第二通孔,所述第一通孔的孔径由所述基板向所述重布线层的方向逐渐缩小,所述第二通孔的孔径由所述重布线层向所述基板的方向逐渐缩小。(The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: a substrate having a first via; and the lower surface of the rewiring layer is in contact with the substrate, the rewiring layer is provided with a second through hole, the aperture of the first through hole is gradually reduced from the substrate to the direction of the rewiring layer, and the aperture of the second through hole is gradually reduced from the rewiring layer to the direction of the substrate.)

1. A semiconductor package device, comprising:

a substrate having a first via; and

the lower surface of the rewiring layer is in contact with the substrate, the rewiring layer is provided with a second through hole, the aperture of the first through hole is gradually reduced from the substrate to the direction of the rewiring layer, and the aperture of the second through hole is gradually reduced from the rewiring layer to the direction of the substrate.

2. The semiconductor package device of claim 1, wherein a side surface of the redistribution layer contacts the substrate.

3. The semiconductor package device of claim 1, wherein the semiconductor package device further comprises:

and the solder mask layer is arranged on the upper surface of the rewiring layer.

4. The semiconductor package device of claim 1, wherein the semiconductor package device further comprises:

and the bare chip is arranged on the upper surface of the redistribution layer.

5. The semiconductor package device of claim 1, wherein the substrate comprises a first dielectric layer comprising fiberglass.

6. The semiconductor package device of claim 5, wherein the redistribution layer comprises a second dielectric layer of a different material than the first dielectric layer.

7. The semiconductor package device of claim 1, wherein the semiconductor package device further comprises:

at least two connecting through holes are arranged between the redistribution layer and the substrate and are respectively electrically connected with the redistribution layer and the substrate, and the aperture of each connecting through hole is the same or different.

8. A method of manufacturing a semiconductor package device, comprising:

providing a rewiring layer structure and a core carrier plate, wherein the rewiring layer structure comprises a carrier plate and a rewiring layer arranged on the carrier plate, the rewiring layer is provided with a second through hole, the hole diameter of the second through hole is gradually reduced from the rewiring layer to the direction of the carrier plate, and a release film is arranged on the surface of the core carrier plate;

taking the rewiring layer structure to the surface of the core carrier plate, wherein the rewiring layer faces the core carrier plate;

removing the carrier plate in the rewiring layer structure;

manufacturing a substrate on the rewiring layer; and

and stripping the redistribution layer and the substrate from the core carrier plate.

9. The method of claim 8, wherein the fabricating a substrate on the redistribution layer comprises:

laminating a first dielectric layer on the rewiring layer;

drilling a hole on the outer surface of the first dielectric layer towards the direction of the rewiring layer to form a first through hole, wherein the hole diameter of the first through hole is gradually reduced from the first dielectric layer towards the direction of the rewiring layer; and

and forming a conductive structure in the first through hole.

10. The method of claim 8, further comprising:

and arranging a solder mask on the surface of the rewiring layer away from the substrate.

11. The method of claim 8, further comprising:

providing a bare chip; and

bonding the die to a surface of the redistribution layer remote from the substrate.

12. The method of claim 9, wherein the first dielectric layer comprises glass fibers.

13. The method of claim 12, wherein the redistribution layer comprises a second dielectric layer of a different material than the first dielectric layer.

Technical Field

The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.

Background

Due to the limitations of the exposure machine capability, the photoresist resolution capability, the etching capability and other processing capabilities of the existing substrate, the Line width/Line spacing (L/S, Line/Space) of the existing mass-produced substrate is about 8/10 micrometers (um), which makes it difficult to move to a thinner Line. The small amount of sample produced for proofing can achieve an L/S of 7/9um, but the yield is low, so that the mass production is difficult.

To implement thinner wires, one solution employs fanout RDLs (Redistribution Layer) to implement thin wire portions. In order to realize such a scheme, a thin circuit portion is realized by mainly attaching a redistribution layer to a Substrate through an adhesive layer in a conventional Fan-Out Substrate (fosb), and a through hole is formed by performing laser drilling on the surface of the redistribution layer toward the Substrate, and the through hole needs to penetrate through the adhesive layer, thereby realizing electrical connection between the redistribution layer and the Substrate. However, in the process of forming the via hole, the AR ratio (aspect ratio) 1 of the via hole due to the difference in laser energy in laser drilling: 3 or so, that is, the via hole will eventually have a small hole diameter when reaching the vicinity of the substrate, which will cause an electrical abnormality problem when plating the small hole diameter portion.

For example, fig. 1 schematically shows the structure of a conventional FOSUB. The AR ratio in the structure shown in fig. 1 is about 1: 3(20 um: 60um), which is likely to cause abnormal electroplating of the fine holes of the through holes and cause electrical problems.

Disclosure of Invention

The present disclosure provides a semiconductor package device and a method of manufacturing the same.

In a first aspect, the present disclosure provides a semiconductor package device, comprising: a substrate having a first via; and the lower surface of the rewiring layer is in contact with the substrate, the rewiring layer is provided with a second through hole, the aperture of the first through hole is gradually reduced from the substrate to the direction of the rewiring layer, and the aperture of the second through hole is gradually reduced from the rewiring layer to the direction of the substrate.

In some alternative embodiments, a side surface of the redistribution layer contacts the substrate.

In some optional embodiments, the semiconductor package device further includes: and the solder mask layer is arranged on the upper surface of the rewiring layer.

In some optional embodiments, the semiconductor package device further includes: and the bare chip is arranged on the upper surface of the redistribution layer.

In some alternative embodiments, the substrate comprises a first dielectric layer comprising glass fibers.

In some optional embodiments, the redistribution layer comprises a second dielectric layer of a different material than the first dielectric layer.

In some optional embodiments, the semiconductor package device further includes: at least two connecting through holes are arranged between the redistribution layer and the substrate and are respectively electrically connected with the redistribution layer and the substrate, and the aperture of each connecting through hole is the same or different.

In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, comprising: providing a rewiring layer structure and a core carrier plate, wherein the rewiring layer structure comprises a carrier plate and a rewiring layer arranged on the carrier plate, the rewiring layer is provided with a second through hole, the hole diameter of the second through hole is gradually reduced from the rewiring layer to the direction of the carrier plate, and a release film is arranged on the surface of the core carrier plate; taking the rewiring layer structure to the surface of the core carrier plate, wherein the rewiring layer faces the core carrier plate; removing the carrier plate in the rewiring layer structure; manufacturing a substrate on the rewiring layer; and peeling the redistribution layer and the substrate from the core carrier.

In some optional embodiments, the fabricating a substrate on the redistribution layer includes:

laminating a first dielectric layer on the rewiring layer; drilling a hole on the outer surface of the first dielectric layer towards the direction of the rewiring layer to form a first through hole, wherein the hole diameter of the first through hole is gradually reduced from the first dielectric layer towards the direction of the rewiring layer; and forming a conductive structure in the first through hole.

In some optional embodiments, the method of manufacturing a semiconductor package device further includes: and arranging a solder mask on the surface of the rewiring layer away from the substrate.

In some optional embodiments, the method of manufacturing a semiconductor package device further includes: providing a bare chip; and bonding the die to a surface of the redistribution layer remote from the substrate.

In some alternative embodiments, the first dielectric layer comprises fiberglass.

In some optional embodiments, the redistribution layer comprises a second dielectric layer of a different material than the first dielectric layer.

In order to solve the problems that the line width/line distance capability of a substrate is limited, and electroplating of a connecting through hole between the substrate and a rewiring layer is abnormal, the semiconductor packaging device and the manufacturing method thereof provided by the disclosure have the advantages that a fan-out process is utilized to heterogeneously integrate a high-yield fine line rewiring layer (L/S can reach 2/2um) and the substrate, a good-quality rewiring layer is taken and placed on a core carrier plate attached with a release film, then the substrate is formed on the basis of the rewiring layer through a line embedding substrate process, the substrate and the rewiring layer are laminated and electrically connected, and finally the core carrier plate is removed, and the buried rewiring layer is positioned on the outer layer of a product. Thus, the production capacity can be improved while the line width/line distance of the product is reduced. It has been proved that the line width/line distance L/S can be reduced to 2/2 um. Moreover, compared with the prior art that the adhesive layer is adopted, the thickness of the product is reduced because the adhesive layer is not adopted. In addition, since the rewiring layer is in direct contact with the substrate, the AR ratio of the connection through-hole between the rewiring layer and the substrate is relatively large compared to the conventional fosb, thereby also solving the problem of plating abnormality of the connection through-hole.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 schematically shows the structure of a conventional FOSUB;

fig. 2A, 2B and 2C are schematic longitudinal cross-sectional structural views of one embodiment of a semiconductor package device 2A, 2B and 2C, respectively, according to the present disclosure;

fig. 3 is a partially enlarged schematic view of a second via hole 221 corresponding to a dotted rectangular frame in the rewiring layer 22 in the semiconductor package device 2A shown in fig. 2A;

fig. 4A, 4B, 4C, 4D, 4E, 4F and 4G are schematic longitudinal sectional structural views of a semiconductor package device 1a according to the present disclosure at various stages of fabrication.

Reference numerals:

21-a substrate; 211 — a first via; 212-a first dielectric layer; 22-a rewiring layer; 221-a second via; 222-a second dielectric layer; 23-a solder mask layer; 24-connecting vias; 25-a bare chip; 26-solder balls; 27-underfill; 28-a bond pad; 41-rewiring layer structure; 42-core carrier plate; 411-a carrier plate; 43-Release film.

Detailed Description

The following description of the embodiments of the present invention will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present invention through the description of the present invention. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined by the claims and the appended claims, and therefore, they are not technically essential, and any structural modification, proportion change, or size adjustment should be within the scope of the present disclosure without affecting the function and achievement of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be regarded as the scope of the present invention without substantial technical changes.

It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Referring to fig. 2A, fig. 2A shows a longitudinal cross-sectional structural schematic of one embodiment 2A of a semiconductor package device according to the present disclosure.

As shown in fig. 2A, the semiconductor package device 2A includes a substrate 21 and a rewiring layer 22, and the lower surface of the rewiring layer 22 contacts the substrate 21.

The substrate 21 may be various types of substrates, and the present disclosure is not particularly limited thereto.

The substrate 21 may include organic and/or inorganic substances, wherein the organic substances may be, for example: polyamide fiber (PA), Polyimide (PI), Epoxy resin (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fiber, FR-4 Epoxy glass cloth laminate, PP (preprg, PrePreg or so-called PrePreg, PrePreg), ABF (Ajinomoto Build-up Film), etc., and inorganic matter may be, for example, silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc.

The substrate 21 may also be, for example, a printed circuit board such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate, or the like.

The rewiring layer 22 may be a rewiring layer composed of a conductive material and a Dielectric material (Dielectric). It should be noted that, currently known or future developed redistribution layer forming techniques may be adopted in the manufacturing process, and the disclosure is not limited thereto, and for example, the redistribution layer may be formed by using techniques including but not limited to photolithography, electroplating (plating), Electroless plating (electroplating), and the like. Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fiber (PA), Polyimide (PI), Epoxy resin (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fiber, FR-4 Epoxy glass cloth laminate, PP (preprg, PrePreg or so-called PrePreg, PrePreg), ABF (Ajinomoto Build-up Film), etc., and inorganic matter may be, for example, silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), or the like, and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The substrate 21 has a first via hole 211, and the rewiring layer 22 has a second via hole 221. The substrate 21 and the rewiring layer 22 may each be a single-layer or multi-layer structure.

In some alternative embodiments, as shown in fig. 2A, the substrate 21 includes a first dielectric layer 212, and the first dielectric layer 212 may include glass fibers to enhance the rigidity of the substrate 21.

In some optional embodiments, rewiring layer 22 includes a second dielectric layer 222. The material of the second dielectric layer 222 and the first dielectric layer 212 may be different for reasons of photoresist resolution and economy.

As shown in fig. 2A, the aperture of the first through hole 211 in the substrate 21 is gradually reduced from the substrate 21 toward the redistribution layer 22. Referring further to fig. 3, fig. 3 is a partially enlarged schematic view of a second via 221 corresponding to a dotted rectangular frame in the rewiring layer 22 in the semiconductor packaging apparatus 2A shown in fig. 2A. As shown in fig. 3, the aperture of the second via hole 221 is gradually reduced from the rewiring layer 22 toward the substrate 21. Such design of the aperture of the first via hole 211 and the aperture of the second via hole 221 is determined by the process for directly contacting the substrate 21 with the redistribution layer 22.

In some alternative embodiments, as shown in fig. 2A, the semiconductor package device 2A may further include a solder resist layer 23. The solder resist layer 23 is provided on a part of the upper surface of the rewiring layer 22. In this way, the solder resist layer 23 can protect the portion of the upper surface of the rewiring layer 22 that is not exposed for external connection. In addition, as shown in fig. 2A, the solder resist layer 23 may also be provided on the lower surface of the substrate 21. Thus, the solder resist layer 23 can protect the portion of the lower surface of the substrate 21 that is not exposed to the external connection.

In some alternative embodiments, as shown in fig. 2A, the semiconductor package device 2A may further include a connection via 24 disposed between the redistribution layer 22 and the substrate 21 for electrically connecting the redistribution layer 22 and the substrate 21. In the case where the semiconductor package device 2A includes at least two connection through-holes 24, the aperture of each connection through-hole 24 may be the same (as shown in fig. 2A). The hole diameter of the connection through hole 24 may be the same as or different from the hole diameter of the first through hole 211. In the case where the diameters of the connecting through hole 24 and the first through hole 211 are the same, the opening process is relatively simple.

Technical effects that the semiconductor package device 2a provided by the above embodiments provided by the present disclosure can achieve include but are not limited to: by forming the substrate 21 on the redistribution layer 22 and bringing them into direct contact, the line width/pitch of the substrate can be significantly reduced. Moreover, compared with the conventional scheme in which the redistribution layer is attached to the substrate through the adhesive layer, since there is no adhesive layer, the product thickness is reduced and the AR ratio of the connection through-hole 24 between the redistribution layer 22 and the substrate 21 can be made relatively large, and the problem of plating abnormality of the connection through-hole is also solved.

With further reference to fig. 2B, fig. 2B shows a schematic longitudinal cross-sectional structure of another embodiment 2B of a semiconductor package device according to the present disclosure.

The semiconductor package device 2B is substantially similar to the semiconductor package device 2a except that, as shown in fig. 2B, the redistribution layer 22 contacts not only the lower surface but also the side surface of the substrate 21, i.e., the redistribution layer 22 is smaller than the substrate 21 in lateral length.

In some alternative embodiments, as shown in fig. 2B, since the uppermost surface has not only the rewiring layer 22 but also a part of the substrate 21, the solder resist layer 23 in the semiconductor package device 2B is provided not only on a part of the upper surface of the rewiring layer 22 but also on the upper surface of the substrate 21 around the rewiring layer 22.

In some alternative embodiments, as shown in fig. 2B, in the case where the semiconductor package device 2B includes at least two connection through-holes 24, the aperture of each connection through-hole 24 may be different, which may make the aperture design of each connection through-hole 24 more flexible.

With further reference to fig. 2C, fig. 2C shows a schematic longitudinal cross-sectional structure of another embodiment 2C of a semiconductor package device according to the present disclosure.

The semiconductor package 2C is substantially similar to the semiconductor package 2b except that, as shown in fig. 2C, the semiconductor package 2C may further include a Die (Die)25 disposed above the upper surface of the redistribution layer 22. The die 25 and the redistribution layer 22 are electrically connected by solder balls 26, and are filled with an Underfill (Underfill) 27. Also, the bottom of the substrate 21 may be provided with a pad 28 to be electrically connected with an external device.

Referring now to fig. 4A-4G, fig. 4A, 4B, 4C, 4D, 4E, 4F and 4G are schematic longitudinal cross-sectional structural views of a semiconductor package device according to the present disclosure at various stages of manufacture, thereby schematically illustrating a flow of a method of manufacturing a semiconductor package device of the present disclosure. The figures have been simplified for a better understanding of various aspects of the disclosure.

Referring to fig. 4A, a redistribution layer structure 41 and a core carrier 42 are provided.

The redistribution layer structure 41 includes a carrier 411 and a redistribution layer 22 disposed on the carrier 411. The rewiring layer 22 has a second via hole 221 for connecting the wires of the layers in the rewiring layer 22. It is understood that the second via 221 formed in the redistribution layer 22 is formed by laser drilling, which is generally performed from the redistribution layer 22 toward the carrier 411, and the energy of the laser decreases with the distance, so that the hole diameter of the second via 221 decreases, and thus the hole diameter decreases from the redistribution layer 22 toward the carrier 411. Rewiring layer 22 may also include a second dielectric layer 222.

The surface of the core carrier 42 may be provided with a release film 43 to facilitate later peeling of the redistribution layer structure 41 from the core carrier 42. Referring to fig. 4B, the redistribution layer structure 41 is picked and placed on the surface of the core carrier 42, wherein the redistribution layer 22 faces the core carrier 42. It should be noted that, in order to improve the production capacity, two redistribution layer structures 41 are respectively disposed on the upper surface and the lower surface of the core carrier 42 in fig. 4B, but this does not limit the disclosure, and the disclosure also contemplates that only one redistribution layer structure 41 is disposed on the upper surface of the core carrier 42.

Referring to fig. 4C, the carrier 411 in the redistribution layer structure 41 is removed.

Referring to fig. 4D, a substrate 21 is fabricated on the rewiring layer 22.

In some alternative embodiments, fabricating the substrate 21 on the redistribution layer 22 may include: laminating a first dielectric layer 212 on the rewiring layer 22; drilling a hole on the outer surface of the first dielectric layer 212 towards the direction of the redistribution layer 22 to form a first through hole 211, wherein the aperture of the first through hole 211 is gradually reduced from the first dielectric layer 212 towards the direction of the redistribution layer 22; and forming a conductive structure within the first via hole 211.

The first dielectric layer 212 may include glass fibers to enhance the rigidity of the substrate 21. The second dielectric layer 222 may be a different material than the first dielectric layer 212.

In some optional embodiments, fabricating the substrate 21 on the redistribution layer 22 may further include: a connecting via 24 is formed between the rewiring layer 22 and the substrate 21 for electrically connecting the rewiring layer 22 and the substrate 21. The number of the connecting through holes 24 is at least one, and when there are at least two connecting through holes 24, the hole diameters of the connecting through holes 24 may be the same or different. The hole diameter of the connection through hole 24 may be the same as or different from the hole diameter of the first through hole 211. In the case where the diameters of the connecting through hole 24 and the first through hole 211 are the same, the opening process is relatively simple.

Referring to fig. 4E, the redistribution layer 22 and the substrate 21 are peeled off from the core carrier 42.

In some alternative embodiments, referring to fig. 4F, the method of manufacturing a semiconductor package device according to the present disclosure may further include: a solder resist layer 23 is provided on the surface of the rewiring layer 22 remote from the substrate 21, and a solder resist layer 23 is provided on the surface of the substrate 21 remote from the rewiring layer 22.

In some alternative embodiments, referring to fig. 4G, the method of manufacturing a semiconductor package device according to the present disclosure may further include: providing a die 25; and bonding a die 25 onto the face of the redistribution layer 22 remote from the substrate 21. Solder balls 26 may be provided between the die 25 and the redistribution layer 22 to electrically connect the two, and an underfill 27 may be filled therebetween. Also, a pad (not shown) may be further provided at the bottom of the substrate 21 to be electrically connected to an external device.

In some optional embodiments, as an example, the thicknesses of the substrate 21 and the redistribution layer 22 may be set as follows: if the thickness of the substrate 21 is H and the thickness of the redistribution layer 22 is H, H can be greater than H, where H is greater than or equal to 2 and less than or equal to 25um, and H is greater than or equal to 6 and less than or equal to 40 um. In a particular embodiment, 2.5 ≦ H ≦ 4um, 12 ≦ H ≦ 18um may be set.

In some alternative embodiments, as an example, the lateral length ratio of the redistribution layer 22 to the substrate 21 in the longitudinal cross-sectional structural diagram may be set as follows: assuming that the lateral length of the rewiring layer 22 is A and the lateral length of the substrate 21 is B, A.ltoreq.B may be set, for example, 0.1. ltoreq.A/B.ltoreq.1 may be set. In particular embodiments, 0.6 ≦ A/B ≦ 0.7 may be set.

In some alternative embodiments, as an example, the line width/line distance L/S of the substrate 21 and the redistribution layer 22 may be set as follows: if the line width/line distance L/S of the redistribution layer 22 is R and the line width/line distance L/S of the substrate 21 is R, R > R may be set, where R is greater than or equal to 0.3 and less than or equal to 10um, and R is greater than or equal to 10 and less than or equal to 100 um. In a particular embodiment, 2 ≦ R ≦ 6um, 13 ≦ R ≦ 25um may be set.

The manufacturing method of the semiconductor package device provided in this embodiment can achieve the corresponding technical effects of the semiconductor package device described above, and will not be described herein again.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.