阅读说明：本技术 Led阵列驱动器系统 (LED array driver system ) 是由 M·F·塞米纳拉 S·R·穆萨梅西 于 2021-06-07 设计创作，主要内容包括：本公开的实施例涉及LED阵列驱动器系统。一种实施例LED驱动器系统包括：功率晶体管,被配置为被选择性地启动以供生成用于LED阵列的驱动电流,所述功率晶体管具有被耦合到所述LED阵列的第一导电端子和被耦合到参考电阻器的第二导电端子；运算放大器,具有用于接收参考电压的非反相输入端、被耦合到所述功率晶体管的所述第二导电端子的反相输入端以及被耦合到传输门的第一导电端子的输出端子,所述传输门具有被耦合到所述功率晶体管的控制端子的第二导电端子和用于接收使能信号的控制端子；以及摆率控制单元,被配置为控制所述驱动电流的所述摆率。(Embodiments of the present disclosure relate to LED array driver systems. An embodiment LED driver system includes: a power transistor configured to be selectively activated for generating a drive current for an LED array, the power transistor having a first conducting terminal coupled to the LED array and a second conducting terminal coupled to a reference resistor; an operational amplifier having a non-inverting input for receiving a reference voltage, an inverting input coupled to the second conduction terminal of the power transistor, and an output terminal coupled to a first conduction terminal of a transmission gate having a second conduction terminal coupled to the control terminal of the power transistor and a control terminal for receiving an enable signal; and a slew rate control unit configured to control the slew rate of the driving current.)

1. A light emitting diode, LED, driver system configured to be coupled to and drive an LED array, the LED driver system comprising:

a power transistor configured to be selectively activated to generate a drive current for the LED array, the power transistor having a first conducting terminal coupled to the LED array and a second conducting terminal coupled to a reference resistor;

an operational amplifier having: a non-inverting input configured to receive a reference voltage, an inverting input coupled to the second conductive terminal of the power transistor, and an output terminal coupled to a first conductive terminal of a transmission gate, the transmission gate having a second conductive terminal coupled to a control terminal of the power transistor and a control terminal configured to receive an enable signal, the first and second conductive terminals of the transmission gate configured to be electrically connected to each other to cause activation of the power transistor when the enable signal is at an enable value, and the first and second conductive terminals of the transmission gate configured to be electrically isolated from each other to cause deactivation of the power transistor when the enable signal is at a disable value; and

a slew rate control unit configured to:

controlling a slew rate of the driving current;

selectively charging an equivalent capacitance at the control terminal of the power transistor by a charging current; and

selectively discharging the equivalent capacitance by a discharge current, the charge current and the discharge current depending at least in part on a target value of the drive current.

2. The LED driver system of claim 1, wherein the slew rate control unit is configured to:

setting the charging current to a first charging value different from zero and independent of the target value during a first phase of operation of the slew rate control unit;

setting the charging current to a second charging value different from zero and dependent on the target value during a second operating phase following the first operating phase of the slew rate control unit;

setting the charging current to zero during a third phase of operation of the slew rate control unit subsequent to the second phase of operation;

setting the discharge current to a discharge value different from zero and dependent on the target value during a fourth operating phase following the third operating phase of the slew rate control unit; and

setting the discharge current to zero during a fifth operational phase following the fourth operational phase of the slew rate control unit.

3. The LED driver system of claim 2, wherein:

the second charge value corresponds to the target value multiplied by a first scaling factor; and

the slew rate control unit is further configured to set a duration of a rising edge of the drive current to a value corresponding to a second scaling factor multiplied by a ratio between the target value and the second charge value during the second phase of operation.

4. The LED driver system of claim 3, wherein:

the discharge value corresponds to the target value multiplied by a third scaling factor; and

the slew rate control unit is further configured to set a duration of a falling edge of the drive current to a value corresponding to a fourth scaling factor multiplied by a ratio between the target value and the discharge value during the fourth phase of operation.

5. The LED driver system of claim 2, wherein the slew rate control unit is configured to:

setting the enable signal to the disable value during the first, second, fourth, and fifth phases of operation; and

setting the enable signal to the enable value during the third phase of operation.

6. The LED driver system of claim 1, further comprising: a first current mirror configured to output a reference current and a control current according to an external current, the reference voltage depending on the reference current, and the charging current and the discharging current depending on the control current.

7. The LED driver system of claim 4, further comprising: a first current mirror configured to output a reference current and a control current according to an external current, the reference voltage depending on the reference current, and the charging current and the discharging current depending on the control current;

wherein the slew rate control unit comprises:

a second current mirror configured to generate the discharge current during the fourth operation phase in accordance with the control current; and

a third current mirror configured to generate the charging current during the second phase of operation in accordance with the control current.

8. The LED driver system of claim 7, wherein the first and third scaling coefficients depend on mirror ratios of the first, second, and third current mirrors.

9. The LED driver system of claim 3, wherein:

the discharge value corresponds to the target value multiplied by a third proportionality coefficient;

the slew rate control unit is further configured to set a duration of a falling edge of the drive current to a value corresponding to a fourth scaling factor multiplied by a ratio between the target value and the discharge value during the fourth phase of operation; and

the second scaling factor and the fourth scaling factor depend on the reference resistor.

10. The LED driver system of claim 2, wherein during the first and fifth phases of operation, the power transistor is off, and the slew rate control unit is configured to:

switching from the first phase of operation to the second phase of operation when the voltage at the control terminal of the power transistor rises to such an extent that the power transistor is switched on; and

switching from the fourth operating phase to the fifth operating phase when the voltage at the control terminal of the power transistor decreases to such an extent that the power transistor is switched off.

11. The LED driver system of claim 10, wherein the slew rate control unit is configured such that:

during the first phase of operation, the charging current increases the voltage at the control terminal of the power transistor from a first voltage value to a second voltage value, the second voltage value corresponding to a threshold voltage of the power transistor;

during the second phase of operation, the charging current increases the voltage at the control terminal of the power transistor from the second voltage value to a third voltage value;

during the third phase of operation, the voltage at the control terminal of the power transistor is held at the third voltage value;

during the fourth phase of operation, the discharge current reduces the voltage at the control terminal of the power transistor from the third voltage value to the second voltage value; and

during the fifth phase of operation, the voltage at the control terminal of the power transistor is held at the first voltage value.

12. The LED driver system of claim 11, wherein the third voltage value is configured to cause the power transistor to generate the drive current at the target value.

13. An electronic system, comprising:

one or more Light Emitting Diode (LED) driver systems, each LED driver system comprising:

a power transistor configured to be selectively activated to generate a drive current, the power transistor having a first conduction terminal and a second conduction terminal coupled to a reference resistor;

an operational amplifier having: a non-inverting input configured to receive a reference voltage, an inverting input coupled to the second conductive terminal of the power transistor, and an output terminal coupled to a first conductive terminal of a transmission gate, the transmission gate having a second conductive terminal coupled to a control terminal of the power transistor and a control terminal configured to receive an enable signal, the first and second conductive terminals of the transmission gate configured to be electrically connected to each other to cause activation of the power transistor when the enable signal is at an enable value, and the first and second conductive terminals of the transmission gate configured to be electrically isolated from each other to cause deactivation of the power transistor when the enable signal is at a disable value; and

a slew rate control unit configured to:

controlling a slew rate of the driving current;

selectively charging an equivalent capacitance at the control terminal of the power transistor by a charging current; and

selectively discharging the equivalent capacitance by a discharge current, the charge current and the discharge current depending at least in part on a target value of the drive current; and

a respective LED array coupled to the one or more LED driver systems via the first conducting terminal of the power transistor of each LED driver system.

14. The electronic system of claim 13, wherein the slew rate control unit is configured to:

setting the charging current to a first charging value different from zero and independent of the target value during a first phase of operation of the slew rate control unit;

setting the charging current to a second charging value different from zero and dependent on the target value during a second operating phase following the first operating phase of the slew rate control unit;

setting the charging current to zero during a third phase of operation of the slew rate control unit subsequent to the second phase of operation;

setting the discharge current to a discharge value different from zero and dependent on the target value during a fourth operating phase following the third operating phase of the slew rate control unit; and

setting the discharge current to zero during a fifth operational phase following the fourth operational phase of the slew rate control unit.

15. The electronic system of claim 14, wherein:

the second charge value corresponds to the target value multiplied by a first scaling factor; and

the slew rate control unit is further configured to set a duration of a rising edge of the drive current to a value corresponding to a second scaling factor multiplied by a ratio between the target value and the second charge value during the second phase of operation.

16. The electronic system of claim 15, wherein:

the discharge value corresponds to the target value multiplied by a third scaling factor; and

the slew rate control unit is further configured to set a duration of a falling edge of the drive current to a value corresponding to a fourth scaling factor multiplied by a ratio between the target value and the discharge value during the fourth phase of operation.

17. The electronic system of claim 14, wherein the slew rate control unit is configured to:

setting the enable signal to the disable value during the first, second, fourth, and fifth phases of operation; and

setting the enable signal to the enable value during the third phase of operation.

18. The electronic system of claim 13, wherein each LED driver system further comprises: a first current mirror configured to output a reference current and a control current according to an external current, the reference voltage depending on the reference current, and the charging current and the discharging current depending on the control current.

19. The electronic system of claim 15, wherein:

the discharge value corresponds to the target value multiplied by a third proportionality coefficient;

the slew rate control unit is further configured to set a duration of a falling edge of the drive current to a value corresponding to a fourth scaling factor multiplied by a ratio between the target value and the discharge value during the fourth phase of operation; and

the second scaling factor and the fourth scaling factor depend on the reference resistor.

20. The electronic system of claim 14, wherein during the first and fifth phases of operation, the power transistor is off, and the slew rate control unit is configured to:

switching from the first phase of operation to the second phase of operation when the voltage at the control terminal of the power transistor rises to such an extent that the power transistor is switched on; and

switching from the fourth operating phase to the fifth operating phase when the voltage at the control terminal of the power transistor decreases to such an extent that the power transistor is switched off.

Technical Field

The present invention relates generally to the field of electronic devices, and more particularly to an LED driver system.

Background

For driving Light Emitting Diodes (LEDs), LED driver systems are known which are configured to control the current through the LEDs.

Different kinds of LED driver system architectures are known in the art.

For example, fig. 1 illustrates an LED driver system 100 having a V2I ("voltage to current") architecture, which is configured to drive an LED array 102.

LED driver system 100 includes: an operational amplifier 104 having a non-inverting input configured to receive a voltage Vbuf; an output terminal connected to a control terminal (e.g., a gate) of a transistor 108 (e.g., an n-type Metal Oxide Semiconductor (MOS) transistor); and an inverting input terminal connected to a conductive terminal (e.g., source) of transistor 108. The inverting input terminal of the operational amplifier 104 is also connected to a first terminal of an external resistor Rext, a second terminal of which is connected to a reference terminal (GND terminal) to which a ground voltage is supplied.

The other conducting terminal (e.g., drain) of transistor 108 is connected to the input terminal of current mirror 120. The current mirror 120 has an output terminal connected to an input terminal of a resistor ladder digital-to-analog converter (DAC)125 for providing a high precision reference current Iref that is a mirrored version of an external current Iext through an external resistor Rext, which in turn is a function of the external resistor Rext and a voltage Vbuff.

The DAC125 has an output terminal for providing a reference voltage Vref to a non-inverting input terminal of the operational amplifier 130 based on the reference current Iref. The operational amplifier 130 has an output terminal connected to a first conduction terminal of the transmission gate TG1 for providing the voltage Vi. The transmission gate TG1 has a second conductive terminal connected to a control terminal (e.g., gate) of a power transistor N1 (e.g., an N-type power MOS transistor) for providing the voltage Vo.

Power transistor N1 has a conductive terminal (e.g., a source) connected to the non-inverting terminal of operational amplifier 130 and to a first conductive terminal of reference resistor Rset, thereby defining circuit node 135. The reference resistor Rset has a second conductive terminal connected to the ground terminal GND. Power transistor N1 has another conductive terminal (e.g., drain) connected to LED array 102.

The transmission gate TG1 has a control terminal for receiving a Pulse Width Modulated (PWM) control signal CTRL that pulses between high and low values.

When the control signal CTRL is at a high value, the first and second conduction terminals of the transmission gate TG1 are electrically connected to each other so that the voltage Vo reaches the voltage Vi, the feedback voltage FDB at the circuit node 135 reaches the reference voltage Vref, and the LED array 102 is crossed by a driving current Iset having a value Iset (h) corresponding to the reference voltage Vref divided by the resistance of the reference resistor Rset.

When the control signal CTRL is at a low value, the first conductive terminal of the transmission gate TG1 is electrically isolated from the second conductive terminal of the transmission gate TG1, and the drive current Iset is at a value Iset (l) equal to zero.

In this way, it is possible to deliver the drive current Iset in the form of current pulses, the duty cycle of which is based on the duty cycle of the control signal CTRL. By varying the duty cycle of the control signal CTRL (e.g. at a frequency higher than 100 Hz), the intensity of the light emitted by the LED can thus be adjusted. This LED control technique is referred to as digital dimming.

To avoid or at least reduce control errors when driving the LED array 102 at low duty cycles, the drive current Iset should have fast rising/falling edges (i.e. low slew rate).

According to solutions known in the art, the fast rising/falling edge is obtained by keeping the voltage Vi output by the operational amplifier 130 close to the target voltage Vo at the gate of the power transistor N1 by providing a scaled copy of the power transistor N1 and the reference resistor Rset, connected in such a way as to form a copy of the feedback loop between the operational amplifier 130 and the power transistor N1, and connected to a transmission gate controlled by a negative version of the control signal CTRL (i.e. a version thereof with a phase difference of 180 °).

Disclosure of Invention

The applicant has found that the above known solutions for controlling LEDs with currents having a reduced slew rate suffer from several drawbacks.

First, according to the known solutions, although the slew rate is reduced, the actual speed/duration of the rising/falling edge cannot be controlled, which is always fixed for a given current value and therefore cannot be scaled to meet the requirements of a particular application, regardless of the actual value of the current.

Furthermore, the fast current rising/falling edges obtained using known solutions may lead to unwanted electromagnetic interference (EMI).

In view of the above, the applicant has devised a solution for solving or at least reducing the above drawbacks.

An aspect of the invention relates to a LED driver system adapted to be coupled to a LED array for driving the LED array, the LED driver system comprising:

-a power transistor configured to be selectively activated for generating a drive current for the LED array, the power transistor having a first conducting terminal coupled to the LED array and a second conducting terminal coupled to a reference resistor;

-an operational amplifier having a non-inverting input for receiving a reference voltage, an inverting input coupled to a second conduction terminal of the power transistor, and an output terminal coupled to a first conduction terminal of a transmission gate, the transmission gate having a second conduction terminal coupled to the control terminal of the power transistor and a control terminal for receiving an enable signal, the first and second conduction terminals of the transmission gate being electrically connected to each other to cause activation of the power transistor when the enable signal is at an enable value and being electrically isolated from each other to cause deactivation of the power transistor when the enable signal is at a disable value; and

-a slew rate control unit configured to control a slew rate of the drive current, the slew rate control unit being configured to selectively charge the equivalent capacitance at the control terminal of the power transistor by a charging current and to selectively discharge the equivalent capacitance by a discharging current, the charging current and the discharging current being at least partially dependent on a target value of the drive current.

According to an embodiment of the invention, the slew rate control unit is configured in this way to perform the following operations:

-setting the charging current to a first charging value different from zero and independent of the target value during a first operational phase of the slew rate control unit,

-during a second operating phase following the first operating phase of the slew rate control unit, setting the charging current to a second charging value different from zero and depending on the target value;

-setting the charging current to zero during a third operating phase following the second operating phase of the slew rate control unit;

-during a fourth operating phase following the third operating phase of the slew rate control unit, setting the discharge current to a discharge value different from zero and depending on the target value; and

-setting the discharge current to zero during a fifth operating phase following the fourth operating phase of the slew rate control unit.

According to an embodiment of the present invention, the second charge value corresponds to a multiplication of the target value by the first scaling factor.

According to an embodiment of the invention, the slew rate control unit is further configured to set the duration of the rising edge of the drive current during the second operation phase to a value corresponding to the second scaling factor multiplied by the ratio between the target value and the second charge value.

According to an embodiment of the invention, the discharge value is multiplied by a third scaling factor to the target value.

According to an embodiment of the invention, the slew rate control unit is further configured to set the duration of the falling edge of the drive current during the fourth operational phase to a value corresponding to the fourth scaling factor multiplied by the ratio between the target value and the discharge value.

According to an embodiment of the invention, the slew rate control unit is configured to set the enable signal to the disable value during the first, second, fourth and fifth operation phases.

According to an embodiment of the invention, the slew rate control unit is configured to set the enable signal to the enable value during the third phase of operation.

According to an embodiment of the invention, the LED driver system further comprises a first current mirror configured to output the reference current and the control current according to the external current.

According to an embodiment of the invention, the reference voltage depends on the reference current.

According to an embodiment of the invention, the charging current and the discharging current depend on the control current.

According to an embodiment of the invention, the slew rate control unit comprises a second current mirror configured to generate the discharge current during the fourth operation phase in dependence of the control current.

According to an embodiment of the invention, the slew rate control unit comprises a third current mirror configured to generate the charging current during the second operation phase in dependence of the control current.

According to an embodiment of the invention, the first scaling factor and the third scaling factor depend on mirror ratios of the first current mirror, the second current mirror and the third current mirror.

According to an embodiment of the invention, the second scaling factor and the fourth scaling factor depend on the reference resistor.

According to an embodiment of the invention, the power transistor is turned off during the first and fifth operation phases.

According to an embodiment of the invention, the slew rate control unit is configured to perform the following operations:

-switching from the first to the second operation phase when the voltage at the control terminal of the power transistor rises to such an extent that the power transistor is switched on, and

switching from the fourth operating phase to the fifth operating phase when the voltage at the control terminal of the power transistor decreases to such an extent that the power transistor is switched off.

According to an embodiment of the invention, the slew rate control unit is configured such that the charging current increases the voltage at the control terminal of the power transistor from a first voltage value to a second voltage value, the second voltage value corresponding to a threshold voltage of the power transistor during the first operation phase.

According to an embodiment of the invention, the slew rate control unit is configured such that the charging current increases the voltage at the control terminal of the power transistor from the second voltage value to the third voltage value during the second operation phase.

According to an embodiment of the invention, the slew rate control unit is configured such that during the third operation phase the voltage at the control terminal of the power transistor is maintained at the third voltage value.

According to an embodiment of the invention, the slew rate control unit is configured such that the discharge current reduces the voltage at the control terminal of the power transistor from the third voltage value to the second voltage value during the fourth operation phase.

According to an embodiment of the invention, the slew rate control unit is configured such that during the fifth operational phase the voltage at the control terminal of the power transistor is maintained at the first voltage value.

According to an embodiment of the invention, the third voltage is such as to cause the power transistor to generate a drive current having a target value.

Another aspect of the invention relates to an electronic system that includes one or more LED driver systems and respective LED arrays coupled to the one or more LED driver systems.

Drawings

These and other features and advantages of the solution according to the invention will be better understood on reading the following detailed description of an embodiment thereof, provided below by way of non-limiting example only, to be read in conjunction with the appended drawings. In this regard, the drawings are expressly intended to be simplified to conceptually illustrate the structures and procedures described. Specifically, the method comprises the following steps:

fig. 1 illustrates an LED driver system according to a solution known in the art;

fig. 2 illustrates an LED driver system according to an embodiment of the invention;

fig. 3A shows a simplified depiction of a slew rate control unit of the LED driver system illustrated in fig. 2 during a first set of operational phases according to an embodiment of the present invention;

fig. 3B illustrates a time diagram of voltage and current in an LED driver system during a first set of operating phases according to an embodiment of the present invention;

fig. 4A shows a simplified depiction of a slew rate control unit of the LED driver system illustrated in fig. 2 during a second set of operational phases in accordance with an embodiment of the present invention;

FIG. 4B illustrates a time diagram of voltage and current in the LED driver system during a second set of operational phases according to an embodiment of the present invention;

FIG. 5 illustrates in detail an exemplary implementation of a slew rate control unit according to an embodiment of the present invention;

6A-6E illustrate how the slew rate control unit of FIG. 5 operates during the operational stages illustrated in FIGS. 3A and 3B according to embodiments of the present invention;

FIG. 7A illustrates an exemplary simulation result of how the drive current generated by the LED driver system rises to two different target values, according to an embodiment of the present invention;

FIG. 7B illustrates an exemplary simulation result of how the drive current generated by the LED driver system drops from two different target values, according to an embodiment of the present invention;

FIGS. 8A and 8B illustrate exemplary simulation results of how the duration of a rising edge of a drive current and the duration of a falling edge of the drive current may be set, according to an embodiment of the present invention; and

fig. 9 illustrates, in simplified block form, an electronic system including an LED driver system for driving an LED array in accordance with an embodiment of the present invention.

Detailed Description

Fig. 2 illustrates an LED driver system 200 configured to drive the LED array 102 in accordance with an embodiment of the invention. Elements of the LED driver system 200 that are common with the LED driver system 100 of fig. 1 are identified by the same reference numerals, and descriptions thereof are omitted for the sake of brevity.

Compared to the known LED driver system 100 of fig. 1, the LED driver system 200 according to an embodiment of the present invention comprises a slew rate control unit 210 adapted to control a slew rate of the driving current Iset generated by the LED driver system 200 for driving the LED array 102.

According to an embodiment of the present invention, the slew rate control unit 210 has: an input for receiving a control signal CTRL; an input coupled to the non-inverting terminal of operational amplifier 130 for receiving a reference voltage Vref; and an inverting terminal input coupled to operational amplifier 130 for receiving feedback voltage FDB.

According to an embodiment of the present invention, the slew rate control unit 210 is configured to set the duration of the rising and falling edges of the drive current Iset independently of the value of the drive current Iset by appropriately charging/discharging an equivalent (e.g., parasitic) capacitance C at the gate terminal of the power transistor N1 with an appropriate charging current Ich and an appropriate discharging current Idsch. Therefore, according to an embodiment of the present invention, the slew rate control unit 210 has an output coupled to a gate terminal of the power transistor N1 and configured to selectively provide the charging current Ich and the discharging current Idsch. According to an embodiment of the present invention, and as will be described in detail below, the slew rate control unit 210 is configured to generate the charging current Ich and the discharging current Idsch from the control current Ic that is provided by the current mirror 120 and that depends on the target value of the drive current Iset.

According to an embodiment of the present invention, the slew rate control unit 210 is configured to generate an enable signal ENA to be used instead of the control signal CTRL for driving the opening and closing of the transmission gate TG 1.

According to an embodiment of the present invention, by referring to the simplified depiction of the slew rate control unit 210 illustrated in fig. 3A and the exemplary timing diagram illustrated in fig. 3B, the slew rate control unit 210 is configured to set the duration Tr of the rising edge of the drive current Iset by charging the equivalent capacitance C at the gate terminal of the power transistor N1 with the charging current Ich generated in the following manner:

during a first phase (identified by reference ph1 in fig. 3B), the charging current Ich is set by the slew rate control unit 210 to a value Ichc independent of the value of the target driving current Iset; and

during a second phase (identified by reference ph2 in fig. 3B), the charging current Ich is set by the slew rate control unit 210 to a value Ichv that depends on the target value Iset (h) of the driving current Iset.

According to an embodiment of the present invention, during the first phase ph1, the voltage Vo at the gate terminal of power transistor N1 rises from the ground voltage to the voltage difference Vgs across the gate and source terminals of power transistor N1 to the value of the threshold voltage Vth of power transistor N1 (i.e., rises until power transistor N1 turns on).

According to an embodiment of the invention, during the second phase ph2, the voltage Vo rises until it reaches a value that causes the drive current Iset to reach the value Iset (h).

According to an embodiment of the present invention, the slew rate control unit 210 sets the value Ichv taken by the charging current Ich in the second stage ph2 to a value depending on the (target) value iset (h).

As will be described in more detail in the following of the present description, according to an embodiment of the present invention, the slew rate control unit 210 is configured to set the value Ichv taken by the charging current Ich in the second stage ph2 to a value proportional to the (target) value iset (h), i.e.:

Ichv＝A×Iset(h) (I)

where A is a scaling factor.

According to an embodiment of the present invention, the higher the value of the drive current Iset (h), the higher the value Ichv of the charging current Ich in the second stage ph2, and thus the faster the charging of the equivalent capacitance C.

As will be described in more detail in the following of this description, according to an embodiment of the invention, the slew rate control 210 is configured to set the duration Tr of the rising edge of the drive current Iset (from the value Iset (l) to the value Iset (h)) to a value proportional to the (target) value Iset (h) and inversely proportional to the value Ichv taken by the charging current Ich in the second stage ph2, i.e.:

where B is a scaling factor.

Thus, according to an embodiment of the invention, the resulting duration Tr of the rising edge of the drive current Iset from the value Iset (l) to the value Iset (h) may advantageously be set independently of the value Iset (h) of the drive current Iset, i.e. by combining equations (1) and (2):

Tr＝B/A (3)

in other words, the slew rate control unit 210 according to an embodiment of the present invention allows obtaining the same duration Tr of the rising edge of the driving current Iset for different values Iset (h). It has to be understood that the duration Tr of the rising edge of the drive current Iset according to an embodiment of the invention is equal to the duration of the second phase ph 2.

In the exemplary time chart illustrated in fig. 3B, two exemplary cases are shown, namely, a first case where the drive current Iset rises from the value Iset (l) to the value Iset (h) (1), and a second case where the drive current Iset rises from the same value Iset (l) to a value Iset (h) (2) which is higher than Iset (h) (1). During the first phase ph1, the charging current Ich is set by the slew rate control unit 210 to the same value Ichc in both cases.

In the first case, during the second phase ph2, the charging current Ich is set by the slew rate control unit 210 to a value Ichv (1) that depends on the value Iset (h) (1) so that the voltage Vo reaches the value Vo (1) within a period of time equal to Tr, causing the driving current Iset to rise until Iset (h) (1).

In the second case, during the second phase ph2, the charging current Ich is set by the slew rate control unit 210 to a value Ichv (2) that depends on the value Iset (h) (2), so that the voltage Vo reaches the value Vo (2) (higher than Vo (1)) within the same period of time equal to Tr, causing the driving current Iset to rise until Iset (h) (2) (higher than Iset (h) (2)).

According to an embodiment of the present invention, the slew rate control unit 210 keeps the enable signal ENA at a low value during both the first phase ph1 and the second phase ph2, thereby keeping the transmission gate TG1 open. At the beginning of the third phase ph3 following the second phase ph2, i.e., once the voltage Vo at the gate terminal of the power transistor N1 reaches a value that causes the drive current Iset to reach the (target) value Iset (h), the slew rate control unit 210 switches the enable signal ENA to a high value, thereby closing the transmission gate TG 1.

In this way, with the voltage Vo very close to the voltage Vi, the transition between the open-loop condition (transmission gate TG1 open) and the closed-loop condition (transmission gate TG1 closed) is smoothly performed.

According to an embodiment of the present invention, by referring to the simplified depiction of the slew rate control unit 210 illustrated in fig. 4A and the exemplary timing diagram illustrated in fig. 4B, the slew rate control unit 210 is configured to set the duration Tf of the falling edge of the drive current Iset by discharging the equivalent capacitance C at the gate terminal of the power transistor N1 with the discharge current Idsch in the following manner:

during a fourth phase (identified by reference sign ph4 in fig. 4B), the discharge current Idsch is set by the slew rate control unit 210 to a value Idschv that depends on the (target) value Iset (h) of the drive current Iset.

According to an embodiment of the present invention, during the fourth phase ph4, the voltage Vo drops from a value that causes the drive current Iset to have a value Iset (h) to a value such that the voltage difference Vgs across the gate and source terminals of the power transistor N1 reaches the threshold voltage Vth of the power transistor N1, thereby turning off the power transistor N1.

According to an embodiment of the present invention, the slew rate control unit 210 sets the value Idschv to a value that depends on the (target) value iset (h).

As will be described in more detail in the following of the present specification, according to an embodiment of the present invention, the slew rate control unit 210 is configured to set the value Idschv taken by the discharge current Idsch in the fourth stage ph4 to a value proportional to the (target) value iset (h), that is:

Idschv＝A′×Iset(h) (4)

where A' is a scaling factor, e.g., a factor A equal to equation (1).

According to the embodiment of the present invention, the higher the value Iset (h) of the drive current Iset, the higher the value Idschv of the discharge current Idsch in the fourth stage ph4, and therefore, the faster the speed of discharge of the equivalent capacitance C.

As will be described in more detail in the following of this description, according to an embodiment of the invention, the slew rate control 210 is configured to set the duration Tf of the rising edge of the drive current Iset (from the value Iset (h) to the value Iset (l)) to a value proportional to the value Iset (h) and inversely proportional to the value Ichv taken by the discharge current Idsch in the fourth stage ph4, i.e.:

where B' is a scaling factor, e.g., a factor B equal to equation (2).

Thus, according to an embodiment of the invention, the resulting duration Tf of the falling edge of the drive current Iset from the value Iset (h) to the value Iset (l) may advantageously be set independently of the value Iset (h) of the drive current Iset, i.e. by combining equations (4) and (5):

Tr＝B′/A′ (6)

in other words, the slew rate control unit 210 according to an embodiment of the present invention allows obtaining the same duration Tf of the falling edge of the drive current Iset for different values Iset (h). It must be appreciated that the duration Tf of the falling edge of the drive current Iset according to an embodiment of the present invention is equal to the duration of the fourth phase ph 4. According to an embodiment of the invention, the duration Tf of the falling edge is equal to the duration Tr of the rising edge.

In the exemplary time chart illustrated in fig. 4B, two exemplary cases are shown, namely, a first case where the drive current Iset falls from the value Iset (h) (1) to the value Iset (l) and a second case where the drive current Iset falls from the value Iset (h) (2) (higher than Iset (h) (1)) to the value Iset (l).

In the first case, during the fourth phase ph4, the discharge current Idsch is set by the slew rate control unit 210 to a value Idschv (1) that depends on the value iset (h) (1) so that the voltage Vo falls from the value Vo (1) to the threshold voltage value Vth within a period of time equal to Tf.

In the second case, during the fourth phase ph4, the discharge current Idsch is set by the slew rate control unit 210 to a value Idschv (2) that depends on the value iset (h) (2) so that the voltage Vo falls from the value Vo (2) (higher than Vo (1)) to the threshold voltage value Vth within the same time period equal to Tf.

According to an embodiment of the present invention, the slew rate control unit 210 switches the enable signal ENA to a low value at the beginning of the fourth phase ph4, thereby opening the transmission gate TG 1.

In this way, the transition between the closed-loop condition (transmission gate TG1 closed) and the open-loop condition (transmission gate TG1 open) is smoothly performed at a voltage Vo very close to the voltage Vi.

According to an embodiment of the present invention, as soon as the power transistor N1 is turned off, the voltage Vo reaches the ground voltage by means of a pull-down circuit (not visible in fig. 4A) and is held to the ground voltage during the following fifth phase ph 5.

At this point, after expiration of phase ph5, the process is repeated and the first phase ph1 begins again.

The slew rate control unit 210 is re-assumed with respect to an embodiment of the present invention, and therefore, the resulting drive current Iset oscillates between:

low values of Iset (l) at stages ph1 and ph5, and

high value Iset (h) at stage ph3 (in the illustrated example, Iset (h) (1) or Iset (h (2)),

with the rising edge having a duration Tr corresponding to the duration of the phase ph2 and the falling edge having a duration Tf corresponding to the duration of the phase ph 4.

Fig. 5 illustrates an exemplary implementation of the slew rate control unit 210 in detail, according to an embodiment of the present invention.

According to an embodiment of the invention, the slew rate control unit 210 comprises a first current generator unit comprising a current mirror CM1 having: an input terminal connected to a bias current generator Ibias; and an output terminal providing a corresponding first operating charging current Ichc having a value corresponding to the value Ichc (which is independent of the drive current Iset) in dependence on the current generated by the bias current generator Ibias.

According to an embodiment of the present invention, the slew rate control unit 210 further comprises a second generator unit comprising a current mirror CM2 and a current mirror CM 3. According to an embodiment of the invention, the current mirror CM2 includes: an input terminal coupled to current mirror 120 for receiving control current Ic; a first output terminal for supplying a discharge current Idsch in accordance with the received control current Ic; and a second output terminal for providing a current Ix to the input terminal of the current mirror CM3 in dependence on the received control current Ic. According to an embodiment of the present invention, the current mirror CM3 has an output terminal for providing a second operating charging current Ichv having a value corresponding to the value Ichv according to the current Ix (depending on the target value Iset (h) of the drive current Iset).

According to an embodiment of the present invention, the current mirror 120, CM1, CM2, CM3 are configured in the following manner.

Current mirror 120:

current mirror CM 1:

Ichc＝p×Ibias

current mirror CM 2:

Idschv＝m×Ic，Ix＝Ic

current mirror CM 3:

Ichv＝m×Ix

where h, k, m, n, p are mirror parameters that form the mirror ratio of the current mirror.

According to an embodiment of the present invention, the slew rate control unit 210 comprises a current switching arrangement comprising four current switching elements M1 to M4 and a transmission gate TG 2.

According to an embodiment of the present invention, the current switching element M1 includes a transistor, such as a p-type MOS transistor, having: a first conduction terminal (e.g., source) coupled to an output terminal of the current mirror CM1 for receiving a first operating charging current Ichc; a second conduction terminal (e.g., drain) connected to the first conduction terminal of transmission gate TG2 (defining circuit node 505); and a control terminal (e.g., a gate) connected to the first charging current control unit 510.

According to an embodiment of the present invention, the current switching element M2 includes a transistor, such as a p-type MOS transistor, having: a first conduction terminal (e.g., source) coupled to an output terminal of the current mirror CM3 for receiving a second operational charging current Ichv; a second conductive terminal (e.g., drain) connected to circuit node 505; and a control terminal (e.g., a gate) connected to the second charging current control unit 520.

According to an embodiment of the present invention, the current switching element M3 includes a transistor, such as an n-type MOS transistor, having: a first conductive terminal (e.g., drain) connected to circuit node 505; a second conductive terminal (e.g., a source) connected to the output terminal of the current mirror CM2 for receiving the discharge current Idsch; and a control terminal (e.g., a gate) connected to the discharge current control unit 530.

According to an embodiment of the present invention, the current switching element M4 includes a transistor, such as an n-type MOS transistor, having: a first conductive terminal (e.g., drain) connected to circuit node 505; a second conductive terminal (e.g., a source) connected to the ground terminal GND; and a control terminal (e.g., a gate) connected to the discharge current control unit 530.

According to an embodiment of the present invention, the slew rate control unit 210 further comprises a reference power transistor N2, e.g. an N-type power MOS transistor, having the same or similar size as the power transistor N1 and comprising: a first conductive terminal (e.g., a source) connected to the ground terminal GND; a control terminal (e.g., a gate) coupled to the gate terminal of power transistor N1 for receiving voltage Vo; and a second conductive terminal (e.g., drain) coupled to the bias current generator Ibias'.

According to an embodiment of the present invention, the first charge current control unit 510, the second charge current control unit 520 and the discharge current control unit 530 have respective input terminals for receiving a voltage V2 at a drain terminal of the reference power transistor N2.

According to an embodiment of the present invention, the first charging current control unit 510, the second charging current control unit 520 and the discharging current control unit 530 have further respective input terminals for receiving the control signal CTRL.

According to an embodiment of the present invention, the transmission gate TG2 has: a second conduction terminal connected to the gate terminal of power transistor N1 (and thus to the second conduction terminal of transmission gate TG 1); and a control terminal for receiving a negative version of the enable signal ENA.

According to an embodiment of the present invention, the slew rate control unit 210 further comprises a comparator 540 having: a non-inverting input terminal connected to an inverting input terminal of the operational amplifier 130; an inverting input terminal connected to the non-inverting input terminal of the operational amplifier 130; and an output terminal connected to an input terminal of the second charging current control unit 520.

According to an embodiment of the present invention, the slew rate control unit 210 further comprises an enable signal generator 550 adapted to generate an enable signal ENA based on the output signal Va generated by the first charging current control unit 510, the output signal Vb generated by the second charging current control unit 520 and based on the output signal Vc generated by the discharging current control unit 530.

6A-6E illustrate how the slew rate control unit 210 of FIG. 5 operates during the phases ph 1-ph 5 illustrated in FIGS. 3A and 3B, in accordance with embodiments of the present invention;

according to an embodiment of the invention, the start condition provides that the control signal CTRL is at a low value, the enable signal ENA is at a low value, the power transistors N1 and N2 are turned off, the transmission gate TG1 is opened, the transmission gate TG2 is closed, the voltage V2 at the drain terminal of the reference power transistor N2 is high, and the feedback voltage FDB is lower than the reference voltage Vref, so that the output of the comparator 540 is at a low value. Further, the starting point condition specifies that the transistors M1, M2, M3, and M4 are off, and that the drive current Iset is at the value Iset (l) (zero).

According to an embodiment of the invention, the phase ph1 (see fig. 6A) is triggered by having the control signal CTRL switched to a high value to signal that the transmission gate TG1 is to be closed. However, according to an embodiment of the invention, instead of directly closing the transmission gate TG1 as soon as the control signal CTRL switches to a high value, a pre-charging of the equivalent capacitance C at the gate terminal of the power transistor N1 is performed, the first part of which corresponds to the phase ph 1.

Specifically, according to an embodiment of the present invention, when the control signal CTRL is switched to a high value and the voltage V2 is at a high value, the first charging current control circuit 510 turns on the transistor M1, thus causing the charging current Ich corresponding to the first operating charging current Ichc, i.e., to have a value corresponding to the value Ichc, which is independent of the driving current Iset, to flow from the current mirror CM1 to the equivalent capacitor C through the transistor M1 and the transmission gate TG 2. Accordingly, the equivalent capacitor C is charged, and the voltage Vo is increased at a rate corresponding to the value of the first operating charging current Ichc.

According to an embodiment of the present invention, phase ph2 (see fig. 6B) is triggered when voltage Vo reaches a value that causes the activation of power transistor N1 and reference power transistor N2. According to an embodiment of the present invention, as soon as the reference power transistor N2 turns on and the voltage V2 drops to a low value, the first charge current control circuit 510 turns off the transistor M1, and the second charge current control circuit 520 turns on the transistor M2. In this way, the charging current Ich corresponding to the second operation charging current Ichv, i.e., having a value corresponding to the value Ichv, which depends on the target value Iset (h) of the driving current Iset (see equation (1)), is caused to flow from the current mirror CM3 to the equivalent capacitance C through the transistor M2 and the transmission gate TG 2. Thus, the equivalent capacitance C is also charged and the voltage Vo is also increased, this time at a rate corresponding to the value of the second operating charging current Ichv, which in turn depends on the target value Iset (h) of the driving current Iset. During the second phase ph2, the drive current Iset begins to rise at a rate dependent on the second operating charge current Ichv.

According to an embodiment of the present invention, when the feedback voltage FDB becomes higher than the reference voltage Vref, the phase ph3 (see fig. 6C) is triggered so that the output of the comparator 540 becomes a high value. In this case, the second charge current control circuit 520 turns off the transistor M2, thus ending the precharge of the equivalent capacitance C, and the enable signal generator 550 is driven for switching the enable signal ENA to a high value, so that the transmission gate TG2 is opened and the transmission gate TG1 is closed, thereby establishing a feedback loop involving the operational amplifier 130 and the power transistor N1 and causing the drive current Iset to assume the target value Iset (h).

According to an embodiment of the invention, phase ph4 (see fig. 6D) is triggered by having control signal CTRL switched to a low value. In this case, the enable signal generator 550 is driven by the control signal CTRL for switching the enable signal ENA to a low value so that the transmission gate TG1 is opened and the transmission gate TG2 is closed, and the discharge current control unit 530 turns on the transistor M3. It is therefore the discharge current Idsch-i.e. having a value corresponding to the value Idschv, which depends on the (target) value Iset (h) of the drive current Iset (see equation (4)) -that flows from the equivalent capacitance C to the current mirror CM2 through the transfer gate TG2 and the transistor M3.

Thus, the equivalent capacitance C is discharged and the voltage Vo is lowered at a rate corresponding to the value of the discharge current Idsch, which in turn depends on the target value Iset (h) of the drive current Iset. During phase ph4, the drive current Iset begins to fall at a rate dependent on the discharge current Idsch.

According to an embodiment of the present invention, when the voltage Vo decreases to the extent that the power transistor N1 and the reference power transistor N2 are turned off, the phase ph5 (see fig. 6E) is triggered. In this case, the voltage V2 is at a low value, and the discharge current control unit 530 turns off the transistor M3 and turns on the transistor M4, thereby pulling down the voltage Vo to the ground voltage. Thus, the drive current Iset is at the value Iset (l) (zero).

According to an embodiment of the invention, the target value Iset (h) of the drive current Iset corresponds to the value Vref of the reference voltage Vref divided by the resistance Rset of the reference resistor Rset:

the value Vref of the reference voltage Vref in turn corresponds to the value Iref of the reference current Iref multiplied by the resistance Rd of the DAC 125:

Vref＝Iref×Rd (8)

the value Iref of the reference current Iref in turn corresponds to the value Vbuff of the mirror ratio h/n times the voltage Vbuff of the current mirror 120 divided by the resistance Rext of the external resistor Rext:

the value Ic of the control current Ic provided by the current mirror 120 corresponds to the value Vbuff of the mirror ratio k/n multiplied by the voltage Vbuff of the current mirror 120 divided by the resistance Rext of the external resistor Rext:

during the second phase ph2, the value Ichv of the second operational charging current Ichv provided by the slew rate control unit 210 corresponds to the mirror ratio m of the current mirror CM3 multiplied by the value Ic of the control current Ic

Ichv＝m×Ic (11)

By combining equations (10) and (11), the value Ichv of the second operating charging current Ichv provided by the slew rate control unit 210 during the second phase ph2 according to embodiments of the present invention may be expressed as a function of the reference current Iref:

by combining equations (8), (10) and (11), the target value Iset (h) of the drive current Iset may be expressed as a function of the value Ic of the control current Ic, or as a function of the value Ichv of the second operating charging current Ichv provided by the slew rate control unit 210 during the second phase ph 2:

thus, by combining equations (1) and (13), it can be derived:

that is, the proportionality coefficient A of equation (1) is equal to

To illustrate in more detail how the slew rate control unit 210 according to an embodiment of the present invention sets the duration Tr of the rising edge of the drive current Iset (from the value Iset (l) to the value Iset (h)), the following is considered.

During the first phase ph1, the voltage Vo at the gate terminal of power transistor N1 rises until reaching a value corresponding to the threshold voltage Vth of power transistor N1:

Vo＝Vgs＝Vth (15)

in the second phase ph2, the voltage Vo rises until reaching a value such that the drive current Iset reaches the target value Iset (h):

Vo＝Vgs+ΔV＝Vgs+(Rset×Iset(h)) (16)

thus, during the second phase ph2, the equivalent capacitance C is charged for a period of time corresponding to the duration Tr of the rising edge to undergo a voltage change Δ V — Rset × iset (h), in which:

thus, by combining equations (2) and (17), it can be derived:

that is, the scaling factor B of equation (2) is equal to (C × Rset).

As can be seen in equation (18), the duration Tr of the rising edge increases with decreasing value Ichv, and vice versa.

Further, by combining equations (14) and (18), it can be derived:

as shown in equation (19) (and in equation (3)), the slew rate control unit 210 according to an embodiment of the present invention allows the duration Tr of the rising edge of the drive current Iset to be advantageously set for different target values Iset (h) of the drive current Iset, because equation (19) (and equation (3)) does not provide dependency on the target values Iset (h).

Further, according to the embodiment of the present invention, the duration Tr of the rising edge of the drive current Iset can be easily set by appropriately varying the mirror parameters h, k and m.

Similarly, during the fourth phase ph4, the value Idschv of the discharge current Idsch provided by the slew rate control unit 210 corresponds to the mirror ratio m of the current mirror CM2 multiplied by the value Ic of the control current Ic

Idschv＝m×Ic (20)

By combining equations (10) and (20), the value Idschv of the discharge current Idschv provided by the slew rate control unit 210 during the fourth phase ph4 according to an embodiment of the present invention may be expressed as a function of the reference current Iref:

by combining equations (8), (20), and (21), the target value Iset (h) of the drive current Iset can be expressed as a function of the value Ic of the control current Ic or as a function of the value Idschv of the discharge current Idschv provided by the slew rate control unit 210 during the fourth phase ph 4:

thus, by combining equations (4) and (22), it can be derived:

that is, the proportionality coefficient A' of equation (4) is equal to

To illustrate in more detail how the slew rate control unit 210 according to an embodiment of the present invention sets the duration Tf of the falling edge of the drive current Iset (from the value Iset (h) to the value Iset (l)), the following is considered.

During the third phase ph3, the voltage Vo at the gate terminal of the power transistor N1 is at a value such that the drive current Iset has a value corresponding to the target value Iset (h):

Vo＝Vgs+ΔV＝Vgs+(Rset×Iset(h)) (24)

during the fourth phase ph4, the equivalent capacitance C is discharged for a period of time corresponding to the duration Tf of the falling edge to undergo a voltage change Δ V — Rset × iset (h) so that the voltage Vo reaches a value corresponding to the threshold voltage Vth of the power transistor. Thus, the following equation is obtained:

by combining equations (5) and (25), it can be derived:

that is, the scaling factor B' of equation (4) is equal to (C × Rset).

As can be seen in equation (26), the duration Tf of the falling edge increases with decreasing value Idschv, and vice versa.

Further, by combining equations (23) and (26), it can be derived:

as shown in equation (27) (and in equation (6)), the slew rate control unit 210 according to an embodiment of the present invention allows to set the duration Tf of the falling edge of the drive current Iset advantageously for different target values Iset (h) of the drive current Iset, since equation (27) (and equation (6)) does not provide a dependency on the target value Iset (h).

Further, according to the embodiment of the present invention, the duration Tf of the falling edge of the drive current Iset can be easily set by appropriately varying the mirror parameters h, k and m.

As can be seen by comparing equations (19) and (27), the slew rate control unit 210 is advantageously configured to allow symmetrical rising and falling edges, i.e., having Tr equal to Tf.

Fig. 7A illustrates an exemplary simulation result of how the drive current Iset rises from the value Iset (l) 0A to the value Iset (h) (1) 100mA or the value Iset (h) (2) 200mA using the slew rate control unit 210 according to an embodiment of the present invention, while fig. 7B illustrates how the drive current Iset falls from the value Iset (h) (1) 100mA or the value Iset (h) (2) 200mA to the value Iset (l) 0A using the slew rate control unit 210 according to an embodiment of the present invention. The portion corresponding to the rising edge of the phase ph1 during which the equivalent capacitance C is charged with a charging current Ich having a value independent of the drive current Iset is identified with reference numeral 710 in fig. 7A, the portion corresponding to the rising edge of the phase ph2 during which the equivalent capacitance C is charged with a charging current Ich having a value dependent on the value Iset (h) of the drive current Iset is identified with reference numeral 720 in fig. 7A, and the falling edge corresponding to the phase ph4 is identified with reference numeral 730 in fig. 7B.

As can be seen in the figure, even if the value Iset (h) (2) is twice the value Iset (h) (1), the duration Tr of the rising edge of the drive current Iset and the duration Tf of the falling edge of the drive current Iset are the same.

In other words, thanks to the proposed solution, the same duration Tr and/or Tf of the rising and/or falling edge of the drive current Iset can be set for different values Iset (h), i.e. the duration Tr and/or Tf of the rising and/or falling edge of the drive current Iset can be set independently of the actual value of the drive current Iset.

Furthermore, obtaining current rising/falling edges that may potentially lead to undesired electromagnetic interference (EMI) is avoided compared to known solutions.

Fig. 8A and 8B illustrate exemplary simulation results of how the duration Tr of the rising edge of the drive current Iset and the duration Tf of the falling edge of the drive current Iset vary with the variation of the mirror parameters h, k and m.

Fig. 9 illustrates, in simplified block form, an electronic system 900 (or a portion thereof) including at least one LED driver system 200 for driving an LED array 102 in accordance with embodiments of the invention described above.

According to embodiments of the present invention, the electronic system 900 is adapted to be used in electronic devices, such as, for example, personal digital assistants, computers, tablet computers, and smart phones.

According to an embodiment of the invention, in addition to the LED driver system 200, the electronic system 900 may further comprise a controller 905, such as, for example, one or more microprocessors and/or one or more microcontrollers.

In addition to LED driver system 200, electronic system 900 may include input/output devices 910 (such as, for example, a keyboard and/or a touch screen and/or a visual display) for generating/receiving messages/commands/data, and/or for receiving/transmitting digital and/or analog signals, according to embodiments of the present invention.

In addition to LED driver system 200, electronic system 900 may also include a wireless interface 915 for exchanging messages with a wireless communication network (not shown), e.g., via radio frequency signals, according to embodiments of the present invention. Examples of the wireless interface 915 may include an antenna and a wireless transceiver.

According to an embodiment of the invention, the electronic system 900 may further comprise a storage device 920, such as, for example, a volatile and/or non-volatile memory device, in addition to the LED driver system 200.

According to an embodiment of the present invention, in addition to the LED driver system 200, the electronic system 900 may also include a supply device, such as a battery 925, for supplying power to the electronic system 900.

According to embodiments of the present invention, electronic system 900 may include one or more communication channels (buses) for allowing data exchange between LED driver system 200 and controller 905 and/or input/output device 910 and/or wireless interface 915 and/or storage device 920 and/or battery 925 (when they exist).

Naturally, to satisfy local and specific requirements, a person skilled in the art may apply to the solution described above many logical and/or physical modifications and alterations. More specifically, although the present invention has been described with a certain degree of particularity with reference to preferred embodiments thereof, it should be understood that various omissions, substitutions and changes in the form and details as well as other embodiments are possible. In particular, various embodiments of the invention may be practiced even without the specific details set forth in the preceding description, in order to provide a more thorough understanding of the invention; rather, well-known features may have been omitted or simplified in order not to obscure the description with unnecessary detail. Moreover, it is expressly intended that certain elements and/or method steps described in connection with any disclosed embodiment of the invention may be incorporated in other embodiments.