阅读说明：本技术 分压装置 (Voltage divider ) 是由 山下裕也 伊泽文仁 石本圣又 阿知原雅人 于 2020-05-22 设计创作，主要内容包括：一种分压装置(3),对从电压电源输出的电压进行分压,分压装置具备利用在板状的基板的正面(5)中并联连接的电容器以及电阻将配置于基板的正面(5)的多个导体图案串联连接的多个电阻分压基板(2A～2D),电阻分压基板(2A～2D)经由连接构件(11)而被串联连接,并且相邻的电阻分压基板(2A～2D)彼此被配置成使一方的电阻分压基板的背面(6)与另一方的电阻分压基板的正面(5)相向、并且使配置于一方的电阻分压基板的正面(5)的导体图案与配置于另一方的电阻分压基板的正面(5)的导体图案隔着另一方的电阻分压基板而对置。(A voltage divider (3) for dividing a voltage output from a voltage power supply, the voltage divider comprising a plurality of resistance voltage dividing substrates (2A-2D) in which a plurality of conductor patterns disposed on the front surface (5) of a plate-shaped substrate are connected in series by capacitors and resistors connected in parallel on the front surface (5) of the substrate, wherein the resistance voltage dividing substrates (2A-2D) are connected in series via a connecting member (11), and adjacent resistance voltage dividing substrates (2A-2D) are arranged so that the back surface (6) of one resistance voltage dividing substrate faces the front surface (5) of the other resistance voltage dividing substrate, and the conductor pattern disposed on the front surface (5) of one resistance voltage dividing substrate faces the conductor pattern disposed on the front surface (5) of the other resistance voltage dividing substrate with the other resistance voltage dividing substrate interposed therebetween.)

1. A voltage divider device for dividing a voltage output from a voltage source,

the voltage divider includes a plurality of resistance voltage dividing substrates in which a plurality of conductor patterns disposed on the 1 st surface of a plate-shaped substrate are connected in series by a capacitor and a resistor connected in parallel to the 1 st surface of the substrate,

the plurality of resistance voltage dividing substrates are connected in series via a conductive member, and the adjacent resistance voltage dividing substrates are arranged such that a 2 nd surface of one resistance voltage dividing substrate and a 1 st surface of the other resistance voltage dividing substrate face each other, and the conductor pattern arranged on the 1 st surface of the one resistance voltage dividing substrate and the conductor pattern arranged on the 1 st surface of the other resistance voltage dividing substrate face each other with the other resistance voltage dividing substrate interposed therebetween.

2. A pressure dividing apparatus according to claim 1,

the adjacent resistance voltage dividing substrates are arranged in parallel with each other such that the 2 nd surface of the one resistance voltage dividing substrate faces the 1 st surface of the other resistance voltage dividing substrate.

3. A voltage dividing device according to claim 1 or 2,

each of the resistance voltage-dividing substrates is disposed so that a distance between the 2 nd surface of the one resistance voltage-dividing substrate and the 1 st surface of the other resistance voltage-dividing substrate is equal in each of the adjacent resistance voltage-dividing substrates.

4. A voltage dividing device according to any one of claims 1 to 3,

the resistance voltage-dividing substrate has a 1 st surface of a rectangular shape, and the resistance voltage-dividing substrates are arranged upright such that a side surface extending in a longitudinal direction among side surfaces of the resistance voltage-dividing substrate is in a horizontal direction.

5. A voltage dividing device according to any one of claims 1 to 3,

the resistance voltage-dividing substrates are stacked and arranged in layers in a direction parallel to a vertical direction.

6. A voltage dividing device according to any one of claims 1 to 5,

and filling the atmosphere environment in which the resistance voltage division substrate is arranged with dry air, nitrogen, hydrogen or sulfur hexafluoride.

7. A voltage dividing device according to any one of claims 1 to 6,

the resistance voltage-dividing substrate is a single-sided substrate in which the conductor pattern is disposed on the 1 st surface of the substrate and the conductor pattern is not disposed on the 2 nd surface of the substrate.

8. A voltage dividing device according to any one of claims 1 to 6,

the resistance voltage-dividing substrate is a double-sided substrate in which the conductor pattern is arranged on the 1 st surface of the substrate and the 2 nd surface of the substrate,

the conductor pattern disposed on the 1 st surface of the substrate and the conductor pattern disposed on the 2 nd surface of the substrate are connected via a via.

9. A pressure divider arrangement according to claim 8,

the conductor pattern disposed on the 1 st surface of the substrate and the conductor pattern disposed on the 2 nd surface of the substrate have the same shape and the same size, and are disposed so as to face each other.

10. A pressure dividing apparatus according to claim 8 or 9,

between the 2 nd surface of the one resistance voltage-dividing substrate and the 1 st surface of the other resistance voltage-dividing substrate, an insulating sheet is disposed in close contact with the 2 nd surface of the one resistance voltage-dividing substrate and the 1 st surface of the other resistance voltage-dividing substrate, opposed to the 2 nd surface of the one resistance voltage-dividing substrate, and opposed to the 1 st surface of the other resistance voltage-dividing substrate.

11. A voltage dividing device according to any one of claims 1 to 10,

a round as a round is added to a corner of the conductor pattern closest to the corner of the resistance voltage dividing substrate among the conductor patterns.

12. The voltage divider according to any one of claims 1 to 11, further comprising:

a connection terminal for electrically connecting the one resistance voltage-dividing substrate and the other resistance voltage-dividing substrate;

a 1 st cap nut for fixing the one resistance voltage-dividing substrate and the connection terminal;

a 2 nd cap nut for fixing the other resistance voltage-dividing board and the connection terminal; and

a fixing rod which penetrates through the 1 st hole of the one resistance voltage dividing substrate and the 2 nd hole of the other resistance voltage dividing substrate to mechanically fix the one resistance voltage dividing substrate and the other resistance voltage dividing substrate,

the connection terminal has:

a 1 st screw part penetrating a 3 rd hole of the one resistive voltage division substrate; and

a 2 nd screw part penetrating a 4 th hole provided in the other resistive voltage-dividing substrate,

the 1 st cap nut is screwed to the 1 st screw part penetrating the 3 rd hole,

the 2 nd cap nut is screwed to the 2 nd screw portion penetrating the 4 th hole.

Technical Field

The present invention relates to a voltage divider used for detecting a high voltage.

Background

A voltage divider is used to detect a voltage value of a voltage output from a high-voltage power supply as a high-voltage generation source. The voltage divider divides a voltage output from the high-voltage power supply, and the voltage divided by the voltage divider is used for detecting a voltage value.

The voltage divider includes a resistance voltage dividing substrate that divides a voltage output from a high-voltage power supply using a resistance, and a plurality of resistances and a plurality of capacitors are arranged on the resistance voltage dividing substrate. In the voltage detection device described in patent document 1, the 1 st resistor is disposed at the 1 st side of the triangle, the 2 nd resistor is disposed at the 2 nd side of the triangle, and the capacitor is disposed at the 3 rd side of the triangle, thereby reducing the size of the resistor-dividing substrate.

Documents of the prior art

Patent document 1: japanese laid-open patent publication No. 63-215970

Disclosure of Invention

However, in the technique of patent document 1, although the resistance voltage dividing substrate is miniaturized, miniaturization in the case where a plurality of resistance voltage dividing substrates are arranged to divide a high voltage is not considered. When a plurality of resistive voltage-dividing substrates are arranged, parasitic capacitance occurs between the resistive voltage-dividing substrates, and when the voltage excessively changes due to imbalance (immalance) in the parasitic capacitance, a voltage equal to or higher than a design value may be applied to the resistive voltage-dividing substrates to cause component damage, and thus it is necessary to suppress imbalance in the parasitic capacitance. In order to suppress the parasitic capacitance between the resistance voltage dividing substrates, it is necessary to increase the distance between the resistance voltage dividing substrates in terms of insulation design, and therefore, in the technique of patent document 1, there is a problem that the device structure becomes large when a plurality of resistance voltage dividing substrates are arranged.

The present invention has been made in view of the above circumstances, and an object thereof is to obtain a voltage dividing device capable of dividing voltage with a small device configuration even when a plurality of resistance voltage dividing substrates are arranged.

In order to solve the above-described problems and achieve the object, the present invention is a voltage divider that divides a voltage output from a voltage power supply, wherein the voltage divider includes a plurality of resistive voltage dividing substrates, and a plurality of conductor patterns disposed on the 1 st surface of a plate-shaped substrate are connected in series by a capacitor and a resistor connected in parallel on the 1 st surface of the substrate. The plurality of resistance voltage dividing substrates are connected in series via a conductive member, and adjacent resistance voltage dividing substrates are arranged such that the 2 nd surface of one resistance voltage dividing substrate and the 1 st surface of the other resistance voltage dividing substrate face each other, and such that the conductor pattern arranged on the 1 st surface of one resistance voltage dividing substrate and the conductor pattern arranged on the 1 st surface of the other resistance voltage dividing substrate face each other with the other resistance voltage dividing substrate interposed therebetween.

According to the present invention, even when a plurality of resistance voltage-dividing substrates are arranged, an effect of enabling voltage division to be achieved with a small device configuration is obtained.

Drawings

Fig. 1 is a diagram showing a configuration of a voltage detection system including a voltage divider device according to embodiment 1.

Fig. 2 is a diagram illustrating a structure of a resistance voltage-dividing substrate provided in the voltage-dividing device according to embodiment 1.

Fig. 3 is a diagram showing an equivalent circuit of the resistance voltage-dividing substrate shown in fig. 2.

Fig. 4 is a diagram for explaining the capacitance of the capacitor.

Fig. 5 is a diagram for explaining a mounting structure of the partial pressure device according to embodiment 1.

Fig. 6 is a diagram for explaining another example of mounting the resistance voltage dividing substrate according to embodiment 1.

Fig. 7 is a diagram for explaining an ideal circuit in the case where the resistive voltage-dividing substrates included in the voltage-dividing device according to embodiment 1 are connected in series.

Fig. 8 is a diagram for explaining an actual circuit when resistive voltage-dividing substrates included in the voltage-dividing device according to embodiment 1 are connected in series.

Fig. 9 is a diagram for explaining parasitic capacitance generated between the resistance voltage dividing substrates shown in fig. 8.

Fig. 10 is a diagram showing a simulation analysis result of parasitic capacitance in the voltage dividing device according to embodiment 1.

Fig. 11 is a graph showing the results of simulation analysis when the parasitic capacitances between the substrates are different.

Fig. 12 is a diagram illustrating a structure of a resistance voltage dividing substrate provided in the voltage dividing device of embodiment 2.

Fig. 13 is a diagram for explaining parasitic capacitance generated between the resistance voltage-dividing substrates included in the voltage-dividing device of embodiment 2.

Fig. 14 is a diagram showing another configuration example of the resistance voltage-dividing substrate provided in the voltage-dividing device according to embodiment 2.

Fig. 15 is a diagram showing another configuration example of the resistance voltage-dividing substrate provided in the voltage-dividing device according to embodiment 1.

Fig. 16 is a diagram for explaining a relationship between the thickness of the resistance voltage-dividing substrate and the discharge suppressing effect.

Fig. 17 is a diagram for explaining the capacitance generated between the resistance voltage-dividing substrates included in the voltage-dividing device of embodiment 3.

Fig. 18 is a perspective view showing the structure of the voltage dividing device when the resistance voltage dividing substrates shown in fig. 5 are arranged upright.

Fig. 19 is a front view of the voltage divider shown in fig. 18.

Fig. 20 is a plan view showing the structure of the voltage dividing device shown in fig. 18.

Fig. 21 is a diagram showing a structure of the resistance voltage-dividing substrate shown in fig. 18.

Fig. 22 is a diagram illustrating a structure of a screw portion of a connection terminal provided in the voltage divider shown in fig. 18.

Fig. 23 is a diagram showing a structure of a cap nut provided in the pressure divider shown in fig. 18.

(symbol description)

1: a high voltage power supply; 2A to 2D, 20A, 20B: a resistance voltage-dividing substrate; 3: a voltage divider; 4: detecting a resistance; 5. 50: a front side; 6. 60: a back side; 7: a copper pattern; 10: an electrode; 11: a connecting member; 15: an insulating sheet; 17: a via (via); 21: a connection terminal; 21a, 21 c: a threaded portion; 21 b: an insulating section; 22: a cap nut; 23: a fixing rod; 24: a hole for a fixing rod; 25. 25a to 25 d: a through-hole (via-hole); 40: the 1 st component; 45: a support member; 100: a voltage detection system; a to e: a connection point; C0-C16: a chip capacitor; R0-R16: and chip resistance.

Detailed Description

Hereinafter, embodiments of the voltage divider according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to these embodiments.

Embodiment 1.

Fig. 1 is a diagram showing a configuration of a voltage detection system including a voltage divider device according to embodiment 1. The voltage detection system 100 includes: a high voltage power supply (voltage power supply) 1 which is a high voltage generation source; a voltage divider (high voltage divider) 3 for dividing the high voltage generated by the high voltage power supply 1; and a detection resistor 4 that detects a voltage for controlling the high voltage power supply 1.

In the voltage detection system 100, the high-voltage power supply 1, the voltage divider 3, and the detection resistor 4 are connected in series. One end of the high-voltage power supply 1 is connected to one end of the voltage divider 3 via a connection point a, the other end of the voltage divider 3 is connected to one end of the detection resistor 4 via a connection point b, and the other end of the detection resistor 4 is connected to the other end of the high-voltage power supply 1. The connection line connecting the other end of the detection resistor 4 and the other end of the high voltage power supply 1 is grounded.

The high-voltage power supply 1 is a device that supplies a high voltage to a load (not shown). The high-voltage power supply 1 controls an output process of a voltage to a load based on a voltage value detected by using the voltage divider 3 and the detection resistor 4.

The voltage divider 3 has a plurality of resistance voltage dividing substrates for dividing a voltage. Hereinafter, a case where the voltage divider 3 has 4 resistive voltage dividing substrates 2A to 2D will be described, but the number of resistive voltage dividing substrates provided in the voltage divider 3 may be any number as long as it is 2 or more.

In the voltage divider 3, the resistive voltage dividing substrates 2A to 2D are connected in series. Specifically, one end of the resistance voltage-dividing substrate 2A is connected to the connection point a, one end of the resistance voltage-dividing substrate 2B is connected to the other end of the resistance voltage-dividing substrate 2A, one end of the resistance voltage-dividing substrate 2C is connected to the other end of the resistance voltage-dividing substrate 2B, one end of the resistance voltage-dividing substrate 2D is connected to the other end of the resistance voltage-dividing substrate 2C, and the connection point B is connected to the other end of the resistance voltage-dividing substrate 2D.

Examples of the circuit system of the high-voltage power supply 1 include a step-up system using a transformer and a voltage doubler circuit (voltage doubler circuit) system applied to a Cockcroft-Walton (Cockcroft-Walton) circuit, etc., but any circuit system may be applied to the high-voltage power supply 1 of the present embodiment.

For example, the output of the high voltage power supply 1 is a high voltage of 60kV, and it is necessary to detect 5V by the detection resistor 4. In this case, from the viewpoint of resistance voltage division, the detection resistor 4 needs 5k Ω, and the combined resistance of the voltage divider 3 needs 60M Ω. In the case of the voltage divider 3, since 4 resistive voltage divider substrates 2A to 2D are provided, the voltage is divided by about 15kV for each 1 resistive voltage divider substrate 2A to 2D. In describing the electrical connection of the present embodiment, the calculation and description will be made using 60kV, but 60kV is just an example, and there are no upper limit and lower limit to the applicable voltage range.

The voltage divider 3 may be disposed in the vicinity of the high-voltage power supply 1, and therefore may be disposed above, below, or on the side of the high-voltage power supply 1. Since there is no restriction on fixing, the pressure divider 3 may be fixed in any direction and at any angle. When the voltage divider 3 is fixed near the high-voltage power supply 1, the voltage divider 3 may be fixed by a structure that is electrically 0V or electrically floating.

Fig. 2 is a diagram illustrating a structure of a resistance voltage-dividing substrate provided in the voltage-dividing device according to embodiment 1. Fig. 3 is a diagram showing an equivalent circuit of the resistance voltage-dividing substrate shown in fig. 2. Since the resistance voltage-dividing substrates 2A to 2D have the same structure, the structure of the resistance voltage-dividing substrate 2A will be described here. Fig. 2 shows a structure of a front surface 5 as a 1 st surface of the resistance voltage dividing substrate 2A and a structure of a rear surface 6 as a 2 nd surface of the resistance voltage dividing substrate 2A. Further, the facing surface 5 is hatched.

In embodiment 1, the resistance voltage divider substrates 2A to 2D are single-sided substrates in which copper patterns 7 as an example of conductor patterns are arranged only on the front surface 5. On the front surface 5 of the resistance voltage-dividing substrate 2A, a plurality of copper patterns 7 are arranged so as to be regularly spread over the surface area of the front surface 5 as large as possible. In the present embodiment, it is important to form the copper pattern 7 as large and regular as possible with respect to the surface area of the front surface 5, and the parasitic capacitance with less error is generated by the copper pattern 7.

In the front surface 5 of the resistive voltage dividing substrate 2A, a plurality of (for example, 5) copper patterns 7 having a rectangular shape are connected in series along the longitudinal direction of the resistive voltage dividing substrate 2A. In the front surface 5 of the resistance voltage-dividing substrate 2A, chip capacitors C1 to C4 as an example of capacitors and chip resistors R1 to R4 as an example of resistors are arranged between the copper patterns 7.

In the following description, when the chip capacitors C1 to C4 included in the voltage divider 3 are not to be distinguished, the chip capacitors C1 to C4 may be referred to as chip capacitors C0. When the chip resistors R1 to R4 included in the voltage divider 3 do not need to be distinguished, the chip resistors R1 to R4 may be referred to as chip resistors R0.

Between the 1 st copper pattern 7 and the 2 nd copper pattern 7, a chip resistor R1 and a chip capacitor C1 are disposed so as to connect the 1 st copper pattern 7 and the 2 nd copper pattern 7. The chip resistance R1 and the chip capacitor C1 are connected in parallel between the 1 st copper pattern 7 and the 2 nd copper pattern 7.

Between the 2 nd copper pattern 7 and the 3 rd copper pattern 7, a chip resistor R2 and a chip capacitor C2 are disposed so as to connect the 2 nd copper pattern 7 and the 3 rd copper pattern 7. The chip resistance R2 and the chip capacitor C2 are connected in parallel between the 2 nd copper pattern 7 and the 3 rd copper pattern 7.

Between the 3 rd copper pattern 7 and the 4 th copper pattern 7, a chip resistor R3 and a chip capacitor C3 are disposed so as to connect the 3 rd copper pattern 7 and the 4 th copper pattern 7. The chip resistance R3 and the chip capacitor C3 are connected in parallel between the 3 rd copper pattern 7 and the 4 th copper pattern 7.

Between the 4 th copper pattern 7 and the 5 th copper pattern 7, a chip resistor R4 and a chip capacitor C4 are disposed so as to connect the 4 th copper pattern 7 and the 5 th copper pattern 7. The chip resistance R4 and the chip capacitor C4 are connected in parallel between the 4 th copper pattern 7 and the 5 th copper pattern 7.

In this way, the copper pattern 7 is connected in series via the chip capacitor C0 and the chip resistor R0 connected in parallel on the front surface 5 of the resistance voltage-dividing substrate 2A. In this embodiment, for convenience of explanation, a case will be described in which 4 chip resistors R1 to R4 and chip capacitors C1 to C4 are connected in series, but the number of series connections is not limited in the design of the resistance voltage-dividing substrate 2A.

The distance between the adjacent copper patterns 7 on the front surface 5 of the resistance voltage-dividing substrate 2A depends on the sizes of the chip capacitor C0 and the chip resistor R0. For example, if the size of the chip capacitor C0 and the size of the chip resistor R0 are 1.6mm × 0.8mm (1608 sizes), respectively, the distance between the adjacent copper patterns 7 may be 1.0 mm. In the front surface 5 of the resistance voltage-dividing substrate 2A, after the chip capacitor C0 and the chip resistor R0 are disposed, the copper pattern 7 is disposed as wide as possible with respect to the surface area of the front surface 5. For example, the gap between the upper side of the front surface 5 and the upper side of the copper pattern 7 is set to be close to 0, and the gap between the lower side of the front surface 5 and the lower side of the copper pattern 7 is set to be close to 0. Further, the gap between the left side of the front 5 and the left side of the copper pattern 7 disposed at the leftmost end among the copper patterns 7 is set to be close to 0, and the gap between the right side of the front 5 and the right side of the copper pattern 7 disposed at the rightmost end among the copper patterns 7 is set to be close to 0.

Since the resistance voltage-dividing substrates 2A to 2D are single-sided substrates, any of the copper pattern 7, the chip capacitor C0, and the chip resistor R0 are not disposed on the rear surface 6 of the resistance voltage-dividing substrates 2A to 2D.

Here, the capacitor capacitance Cc [ F ] of the capacitor is described. Fig. 4 is a diagram for explaining the capacitance of the capacitor. Fig. 4 shows a structure of a capacitor disposed in the chip capacitor C0 or the like. The capacitor disposed in the chip capacitor C0 or the like has a structure in which a dielectric having a dielectric constant ∈ is sandwiched by 2 pairs of electrodes (parallel plates) 10.

Dielectric constant ε [ F/m ]]Is ∈ ═ epsilon₀·ε_r，ε₀Is the dielectric constant in vacuum, ε_rIs the relative dielectric constant of each substance. Here, the capacitance of the capacitor is Cc [ F ]]The surface area of the electrode 10 is set to S [ mm ]²]D [ mm ] is the distance between the electrodes 10]Setting the dielectric constant epsilon to epsilon [ F/m [ ]]When Cc is equal to epsilon (S/d) [ F]The expression (1) holds. According to the formula, the dielectric constant ε [ F/m ] is obtained]When the surface area is constant, the surface area S [ mm ]²]The larger the capacitor capacitance Cc [ F ]]The larger, and in addition, the distance d [ mm ] between the electrodes 10]The closer the capacitor capacitance Cc [ F ]]The larger. In addition, if the surface area S [ mm ] can be set appropriately²]And the distance d [ mm ] between the electrodes 10]The capacitor capacitance Cc [ F ] can be set]The distance d [ mm ] is an arbitrary value]It is possible to make the capacitor capacitance Cc [ F ] large and small as desired]。

Fig. 5 is a diagram for explaining a mounting structure of the partial pressure device according to embodiment 1. The resistive voltage-dividing substrates 2A to 2D included in the voltage-dividing device 3 are connected in series by a connecting member 11 including a conductive member. As for the method of connecting the resistance voltage dividing substrates 2A to 2D, any member may be used as long as the resistance voltage dividing substrates 2A to 2D can be electrically connected to each other. For connection between the resistance voltage dividing substrates 2A to 2D, for example, a wiring material such as a cable or a metal conductor can be used.

The resistance voltage-dividing substrates 2A to 2D have the same plate-like shape. The front surface 5 and the back surface 6 of the resistance voltage-dividing substrates 2A to 2D are rectangular. The resistance voltage dividing substrates 2A to 2D are arranged upright such that a side surface extending in the longitudinal direction among the side surfaces becomes a bottom surface and a side surface in the width direction is parallel to the vertical direction. The resistive voltage-dividing substrates 2A to 2D are arranged upright such that the front surfaces 5 thereof are parallel to each other and the positions thereof in the in-plane direction are aligned. That is, the resistance voltage-dividing substrates 2A to 2D are vertically arranged so as not to be displaced in the in-plane direction of the resistance voltage-dividing substrates 2A to 2D.

The atmosphere in which the resistance voltage-dividing substrates 2A to 2D are disposed may be air, but when the substrates are filled with dry air, nitrogen, or hydrogen, the error in the parasitic capacitance can be suppressed more than in the case of air. Further, by filling the atmosphere in which the resistance voltage dividing substrates 2A to 2D are arranged with SF6 (sulfur hexafluoride), the error of the parasitic capacitance can be suppressed as in the case of dry air.

Fig. 6 is a diagram for explaining another example of mounting the resistance voltage dividing substrate according to embodiment 1. In fig. 6, the connecting member 11 is not shown. As shown in fig. 6, the resistance voltage-dividing substrates 2A to 2D may be stacked in layers in the vertical direction. Even in this case, as in the case of fig. 5 in which the resistive voltage-dividing substrates 2A to 2D are arranged upright, there is an effect of suppressing an error in parasitic capacitance. When the resistive voltage-dividing substrates 2A to 2D are stacked in layers, the resistive voltage-dividing substrates 2A to 2D are supported by the support member 45 and the like.

The resistance voltage-dividing substrate 2A is disposed such that the back surface 6 of the resistance voltage-dividing substrate 2A and the front surface 5 of the resistance voltage-dividing substrate 2B face each other with a distance d1 therebetween. The resistance voltage-dividing substrate 2B is disposed such that the back surface 6 of the resistance voltage-dividing substrate 2B and the front surface 5 of the resistance voltage-dividing substrate 2C face each other with a distance d2 therebetween. The resistance voltage-dividing substrate 2C and the resistance voltage-dividing substrate 2D are arranged such that the back surface 6 of the resistance voltage-dividing substrate 2C and the front surface 5 of the resistance voltage-dividing substrate 2D face each other with a distance D3 therebetween. In this way, the resistance voltage dividing substrates are arranged so that the back surface 6 of one resistance voltage dividing substrate and the front surface 5 of the other resistance voltage dividing substrate face each other, and the copper pattern 7 arranged on the front surface 5 of one resistance voltage dividing substrate and the copper pattern 7 arranged on the front surface 5 of the other resistance voltage dividing substrate face each other with the other resistance voltage dividing substrate interposed therebetween.

In the following description, the resistance voltage-dividing substrates 2A to 2D may be referred to as substrates. Therefore, in the following description, the space between the resistance voltage dividing substrates 2A to 2D, that is, the space between the resistance voltage dividing substrates 2A and 2B, the space between the resistance voltage dividing substrates 2B and 2C, and the space between the resistance voltage dividing substrates 2C and 2D may be referred to as a space between the substrates.

In the voltage divider 3, the resistive voltage dividing substrates 2A to 2D are arranged so that the distances D1, D2, and D3 between the substrates become equal. Therefore, the resistance voltage-dividing substrates 2A to 2D are fixed at equal intervals by using spacers such as resin, for example, and the substrates are electrically connected by using wiring materials. The resistance voltage dividing substrates 2A to 2D may be fixed at equal intervals only by metal conductors and may be electrically connected by metal conductors. The distances d1, d2, and d3 between the substrates affect the capacitor capacitance Cc [ F ] as described above, and therefore, it is preferable that the error is as small as possible, for example, the error is within ± 10%.

Here, an ideal circuit of the voltage divider 3 when the resistive voltage divider substrates 2A to 2D are connected in series will be described. Fig. 7 is a diagram for explaining an ideal circuit in the case where the resistive voltage-dividing substrates included in the voltage-dividing device according to embodiment 1 are connected in series. An ideal circuit is a circuit in which there is no parasitic capacitance between substrates, but in an actual circuit, parasitic capacitance occurs between substrates.

The resistance voltage-dividing substrate 2A includes chip capacitors C1 to C4 and chip resistors R1 to R4, and the resistance voltage-dividing substrate 2B includes chip capacitors C5 to C8 and chip resistors R5 to R8. The resistance voltage-dividing substrate 2C includes chip capacitors C9 to C12 and chip resistors R9 to R12, and the resistance voltage-dividing substrate 2D includes chip capacitors C13 to C16 and chip resistors R13 to R16. The chip capacitors C1 to C16 have the same characteristics, and the chip resistors R1 to R16 have the same characteristics, respectively.

In the voltage dividing device 3, chip capacitors CN (N is a natural number of 1 to 16) and chip resistors RN are connected in parallel, respectively. In the voltage divider 3, when the combination of the chip capacitor CN and the chip resistor RN is the element group XN, the element groups are connected in series in the order of the element group X1, the element group X2, the element group X3, the element group X4, the element group X5, the element group X6, the element group X7, the element group X8, the element group X9, the element group X10, the element group X11, the element group X12, the element group X13, the element group X14, the element group X15, and the element group X16.

In this way, in the resistance voltage-dividing substrates 2A to 2D, the chip capacitor C0 and the chip resistor R0 are connected in parallel, and the group of the chip capacitor C0 and the chip resistor R0 is connected in series between the groups.

The element group X1 of the resistance voltage-dividing substrate 2A is connected to the connection point a. The element group X4 of the resistance voltage dividing substrate 2A and the element group X5 of the resistance voltage dividing substrate 2B are connected via a connection point c. The element group X8 of the resistance voltage dividing substrate 2B and the element group X9 of the resistance voltage dividing substrate 2C are connected via a connection point d. The element group X12 of the resistance voltage dividing substrate 2C and the element group X13 of the resistance voltage dividing substrate 2D are connected via a connection point e. The element group X16 of the resistance voltage-dividing substrate 2D is connected to the connection point b.

In the voltage divider 3, the element groups X1 to X16 disposed on the resistive voltage dividing substrates 2A to 2D are connected in series. In an ideal circuit, no parasitic capacitance occurs between the substrates. Therefore, in an ideal circuit, the voltage applied from the connection point a to the connection point b is equally divided for each combination (each element group) of the chip capacitor C0 and the chip resistor R0. When a voltage of 60kV is applied from the connection point a to the connection point b, a voltage of 3.75kV is applied to each of the chip capacitor C0 and the chip resistor R0. Therefore, in the case of an ideal circuit, the voltage of 3.75kV may be considered in designing the substrate.

Between the connection points a to d, 30kV, which is a voltage several times (8 times in this case) the series connection of the chip capacitor C0 and the chip resistor R0 disposed therebetween, is applied. Similarly, 30kV is applied between the connection points d-b and c-e, respectively. Therefore, in the case of an ideal circuit, the mounting structure may be designed on the premise that a maximum of 30kV is applied between the substrates.

However, in the actual circuit of the voltage divider 3, parasitic capacitances (parasitic capacitances Cs1 to Cs12 described later) exist between the substrates. Here, an actual circuit of the voltage dividing device 3 in which the parasitic capacitance is taken into consideration will be described. Fig. 8 is a diagram for explaining an actual circuit when resistive voltage-dividing substrates included in the voltage-dividing device according to embodiment 1 are connected in series.

In the voltage dividing means 3, an unintended parasitic capacitance occurs. Here, a case where parasitic capacitances Cs1 to Cs12 exist between the substrates of the voltage divider 3 will be described. The parasitic capacitances Cs1 to Cs4 are parasitic capacitances between the resistance voltage-dividing substrates 2A and 2B, the parasitic capacitances Cs5 to Cs8 are parasitic capacitances between the resistance voltage-dividing substrates 2B and 2C, and the parasitic capacitances Cs9 to Cs12 are parasitic capacitances between the resistance voltage-dividing substrates 2C and 2D.

The capacitance values [ F ] of the parasitic capacitances Cs1 to Cs12 have different values for the respective parasitic capacitances Cs1 to Cs12 if the parasitic capacitances Cs1 to Cs12 are not appropriately controlled. If the capacitance values of the parasitic capacitances Cs1 to Cs12 are different, the voltage division ratio based on the parasitic capacitances Cs1 to Cs12 between the substrates changes when an excessive change in voltage occurs. Therefore, a high voltage equal to or higher than a design value may be applied between the connection points a to d, between the connection points d to b, and between the connection points c to e, and if the parasitic capacitances Cs1 to Cs12 are not appropriately controlled, the voltage divider 3 may malfunction. These parasitic capacitances Cs1 to Cs12 do not disappear in structure. Therefore, by controlling all the parasitic capacitances Cs1 to Cs12 to have a common value, the voltage division ratio between the substrates due to the parasitic capacitances Cs1 to Cs12 can be made close to a constant value. In the following description, when the parasitic capacitances Cs1 to Cs12 are not necessarily distinguished from each other, the parasitic capacitances Cs1 to Cs12 may be referred to as parasitic capacitances CsX.

Here, capacitance values [ F ] of the parasitic capacitances Cs1 to Cs12 when the resistive voltage-dividing substrates 2A to 2D, which are single-sided substrates, are mounted as shown in fig. 5 will be described.

Fig. 9 is a diagram for explaining parasitic capacitance generated between the resistance voltage dividing substrates shown in fig. 8. The capacitance value [ F ] of the parasitic capacitances Cs1 to Cs12 can be calculated from the same viewpoint, and therefore, the capacitance value [ F ] of the parasitic capacitance Cs1 will be described here.

Fig. 9 illustrates the 1 st component 40 as a part of the resistance voltage-dividing substrates 2A and 2B. The 1 st component 40 is disposed at a position where the parasitic capacitance Cs1 shown in fig. 8 occurs. As shown in fig. 9, in the present embodiment, the parasitic capacitance of the 1 st component 40 is formed by the series connection of the capacitance Cx of the substrate material and the parasitic capacitance Cs1 between the resistance voltage dividing substrates 2A and 2B. Now, the mounting structure of the present embodiment will be describedThe capacitance Cx of the substrate material in (B) and the parasitic capacitance Cs1 between the resistive voltage dividing substrates 2A, 2B. Relative dielectric constant ε of glass composite substrate (CEM-3) as a general substrate material_rIs 4.7, the relative dielectric constant ε of a glass epoxy substrate (FR-4)_rIs 4.73. Here, the capacitance value [ F ] when the substrate material is CEM-3 is described]。

The thicknesses of the resistance voltage-dividing substrates 2A and 2B were 1.6mm, respectively. The surface area of the copper pattern 7 is assumed to be S [ mm ]²]When, according to C ═ epsilon₀·ε_r(S/d), the capacitance Cx of the substrate material is 2.94 ε₀S[F]。

Next, a parasitic capacitance Cs1 between the substrates is described. In the mounting structure of the present embodiment, it is assumed that the distance between the substrates is 10mm to 20mm, and the environment in which the voltage divider 3 is disposed has a relative dielectric constant ∈_r1 atmosphere. In this case, the parasitic capacitance Cs1 between the substrates is 0.1 ε when the distance between the substrates is 10mm₀S[F]And 0.05 epsilon in the case that the distance between the substrates is 20mm₀S[F]. Therefore, when the parasitic capacitance of the 1 st component 40 is composed of the capacitance Cx of the substrate material and the parasitic capacitance Cs1 between the substrates, a voltage of about several% of the entire capacitance Cx of the substrate material is applied from the viewpoint of the partial pressure of the capacitor. Therefore, the remaining voltage is applied to the parasitic capacitance Cs1 between the substrates. That is, in embodiment 1, it can be said that the parasitic capacitance of the 1 st component 40 depends on the parasitic capacitance Cs1 between the substrates.

Next, a simulation analysis result of the parasitic capacitance in the circuit shown in fig. 8 will be described. Fig. 10 is a diagram showing a simulation analysis result of parasitic capacitance in the voltage dividing device according to embodiment 1. Fig. 10 shows simulation analysis results of the parasitic capacitances Cs1 to Cs12 between the substrates at the same time. Fig. 11 is a graph showing the results of simulation analysis when the parasitic capacitances between the substrates are different.

The simulation conditions here are such that a voltage of 60kV and 100Hz is applied between the connection points a-b shown in FIG. 8. In the upper part of fig. 10 and 11, the voltage waveforms between the connection points a-d shown in fig. 8 are shown. In addition, in the middle of fig. 10 and 11, voltage waveforms between the connection points c-e shown in fig. 8 are shown. In the lower stages of fig. 10 and 11, voltage waveforms between the connection points d-b shown in fig. 8 are shown.

The voltage waveform shown in fig. 10 is a voltage waveform in which all the parasitic capacitances Cs1 to Cs12 are common as in the voltage divider 3 of the present embodiment. As shown in fig. 10, when all the parasitic capacitances Cs1 to Cs12 are common, 30kV is equally applied to all the substrates. This is because the errors of the parasitic capacitances Cs1 to Cs12 are very small and have substantially common values, and the voltage division by the parasitic capacitances Cs1 to Cs12 is performed uniformly even with respect to an excessive change in voltage. Therefore, in the present embodiment, 3.75kV divided on the substrate is equally applied not only between the substrates but also to the chip capacitor C0 and the chip resistor R0 on the substrate. Therefore, malfunction of the voltage dividing device 3 can be prevented.

The voltage waveforms shown in fig. 11 are voltage waveforms shown in the voltage dividing device of the comparative example. In the voltage dividing device of the comparative example, the parasitic capacitances Cs1 to Cs4 between the connection points a to d were made larger than the parasitic capacitances Cs5 to Cs 12. Thus, in the voltage dividing device of the comparative example, the parasitic capacitances Cs1 to Cs4 are different from the parasitic capacitances Cs5 to Cs 12.

As shown in fig. 11, a maximum of 30kV is applied between the connection points a-d and between the connection points c-e, but a maximum of 58kV is applied between the connection points d-b. This is the result of the following structure: since the different parasitic capacitors CsX are connected in series to the voltage divider 3, the voltage division ratio by the parasitic capacitor CsX changes, and the voltage is biased to the side where the capacitance value of the parasitic capacitor CsX is small. As a result, in the voltage dividing device of the comparative example, it is necessary to design a mounting structure that withstands 58 kV. When the space insulation distance is assumed to be 1kV/mm, the voltage divider device of the comparative example needs to have a mounting structure in which the substrates are separated by 58 mm. Further, since a voltage equal to or higher than a design value is applied to the chip capacitor C0 and the chip resistor R0 on the substrate, the voltage may cause damage to components.

The simulation described in fig. 11 is merely an example in which only the parasitic capacitances Cs1 to Cs4 between the connection points a to d are changed to explain the simulation for easy understanding, and is merely an example of the simulation. In the actual substrate design for the voltage divider of the comparative example, the pattern design is not performed so that the parasitic capacitance between the substrates becomes a common value as in the present embodiment.

In addition, in the partial pressure device 3 of the present embodiment, the surface area S [ mm ] with the front surface 5 of the substrate²]The single-sided substrates on which the copper patterns 7 are uniformly arranged are arranged so that the distances d1, d2, and d3 between the substrates are equal to each other without being shifted from each other in the planar direction. This makes it possible to control the parasitic capacitance CsX between the substrates to a common value at all positions between the substrates in the voltage divider 3. Therefore, even when the voltage is excessively changed, the voltage between the substrates can be equally divided, so that the insulating distance between the substrates can be easily designed, and the voltage dividing device 3 can be downsized. That is, the voltage divider 3 can be miniaturized while securing the insulation distance between the components.

In addition, mechanical dimensional errors of the substrate occur during the manufacture of the substrate. Regarding the surface area S [ mm ] of the front side 5 of the substrate not considered²]The substrate with the designed pattern (the substrate with the small surface area of the copper pattern) of (1) has a large variation in parasitic capacitance due to a mechanical dimensional error. In addition, in the substrate having a small surface area of the copper pattern, the capacitance value of the parasitic capacitor itself is small. That is, in the case of a substrate having a small surface area of a copper pattern, the capacitance value of the parasitic capacitance has a very small value of several pF. Therefore, when a substrate having a small surface area of the copper pattern is used, and the number of substrates is increased in order to divide a high voltage, imbalance in parasitic capacitance is more likely to occur. Therefore, the voltage imbalance becomes large, and it is difficult to predict the voltage between the substrates.

In the partial pressure device 3 of the present embodiment, the surface area S [ mm ] of the front surface 5 of the substrate²]Since the surface area of the copper pattern 7 is increased as much as possible, the variation in the parasitic capacitance CsX due to the dimensional error (manufacturing error) of the copper pattern 7 can be tolerated.

As an example of the copper pattern, a case where a copper pattern having a width of 2mm is superimposed will be described. When the position of the copper pattern of the opposing substrate is shifted by 1mm in the width direction (lateral direction) due to a mechanical dimensional error of the substrate, the portion overlapping in the lateral direction is 1mm in the copper pattern having a width of 2 mm. In this case, the parasitic capacitance between the copper patterns becomes half of the design value. On the other hand, in the case of overlapping copper patterns having a width of 10mm with each other, if the position of the facing one of the copper patterns is shifted by 1mm in the width direction, the overlapping portion in the lateral direction is 9 mm. In this case, the parasitic capacitance between the copper patterns becomes 90% of the design value. As described above, the larger the surface area of the copper pattern is, the more tolerable the dimensional error (positional deviation) of the copper pattern can be.

In the present embodiment, a configuration in which the voltage of 60kV is divided by the series connection of the resistance voltage dividing substrates 2A to 2D is described, but the resistance voltage dividing substrates 2A to 2D are only an example. Therefore, the number of resistive voltage-dividing substrates can be changed in accordance with the target device, voltage, and the like. For example, when voltage division is performed for a voltage higher than 60kV, a resistive voltage dividing board connected in series may be added. In this case, the resistance voltage-dividing substrates are also arranged so that the distances between the resistance voltage-dividing substrates are equal without being shifted in the in-plane direction of the resistance voltage-dividing substrates.

In embodiment 1, the resistance voltage-dividing substrates 2A to 2D are connected in series by the connecting member 11, and the adjacent resistance voltage-dividing substrates are arranged in parallel with each other such that the back surface 6 of one resistance voltage-dividing substrate faces the front surface 5 of the other resistance voltage-dividing substrate. Each of the resistance voltage-dividing substrates 2A to 2D is disposed so that the distance between the back surface 6 of one of the resistance voltage-dividing substrates and the front surface 5 of the other resistance voltage-dividing substrate is equal in each of the adjacent resistance voltage-dividing substrates. Accordingly, all of the parasitic capacitances Cs1 to Cs12 can be controlled to have a common value, and the voltage division ratio between the parasitic capacitances Cs1 to Cs12 between the substrates can be made close to a constant value. Therefore, even when a plurality of resistance voltage-dividing substrates are arranged, the voltage-dividing device 3 can realize voltage division with a small device configuration.

In addition, the resistance voltage-dividing substrates 2A to 2D are uniformThe surface area S [ mm ] of the front surface 5 of the resistance voltage-dividing substrates 2A to 2D is arranged²]Copper pattern 7 of approximately the same area. Therefore, the heat dissipation performance of the resistance voltage-dividing substrates 2A to 2D is improved. Further, since the resistive voltage-dividing substrates 2A to 2D are arranged upright, the flow of air is improved, and the heat dissipation performance by natural convection is improved. Therefore, even in an environment in which the voltage divider 3 is installed in a sealed structure in which forced air cooling or water cooling is not possible, the temperature rise of the resistive voltage divider substrates 2A to 2D can be suppressed.

Embodiment 2.

Next, embodiment 2 of the present invention will be described with reference to fig. 12 to 16. In embodiment 2, the resistance voltage dividing substrate is a double-sided substrate in which copper patterns 7 are arranged on both sides.

Fig. 12 is a diagram illustrating a structure of a resistance voltage dividing substrate provided in the voltage dividing device of embodiment 2. In embodiment 2, a resistance voltage-dividing substrate 20A as a double-sided substrate is used instead of the resistance voltage-dividing substrate 2A as a single-sided substrate. The resistive voltage-dividing substrate other than the resistive voltage-dividing substrate 20A included in the voltage-dividing device 3 in embodiment 2 also has the same configuration as the resistive voltage-dividing substrate 20A.

The resistance voltage-dividing substrate 20A is a double-sided substrate having copper patterns 7 arranged on both sides. The front surface 50 of the resistance voltage-dividing substrate 20A has the same structure as the front surface 5 of the resistance voltage-dividing substrate 2A. That is, the surface area S [ mm ] of the front surface 50 of the resistance voltage-dividing substrate 20A is arranged on the front surface 50²]And a plurality of copper patterns 7 spread out as widely and regularly as possible. In the front surface 50 of the voltage-resistance-dividing substrate 20A, chip capacitors C1 to C4 and chip resistors R1 to R4 are arranged between the copper patterns 7, as in the front surface 5 of the voltage-resistance-dividing substrate 2A.

In the rear surface 60 of the resistance voltage dividing substrate 20A, the copper pattern 7 is arranged at a position in plane symmetry with the front surface 50 of the resistance voltage dividing substrate 20A. That is, in the rear surface 60 of the resistance voltage dividing substrate 20A, the copper pattern 7 having the same shape and the same size as the copper pattern 7 of the front surface 50 of the resistance voltage dividing substrate 20A is arranged so as to face the copper pattern 7 of the front surface 50. The copper patterns 7 disposed on the back surface 60 are electrically connected to the copper patterns 7 disposed on the front surface 50 at plane-symmetrical positions, respectively, via vias (vias 17 described later). Specifically, the copper pattern 7 disposed at the leftmost end of the front surface 50 and the copper pattern 7 disposed at the leftmost end of the rear surface 60 are connected by the via 17, and the 2 nd copper pattern 7 from the left disposed on the front surface 50 and the 2 nd copper pattern 7 from the left disposed on the rear surface 60 are connected by the via 17. The copper pattern 7 disposed on the rightmost end of the front surface 50 and the copper pattern 7 disposed on the rightmost end of the rear surface 60 are connected by a via 17, and the 2 nd copper pattern 7 disposed on the right of the front surface 50 and the 2 nd copper pattern 7 disposed on the right of the rear surface 60 are connected by a via 17.

The mounting structure of the pressure dividing device 3 of embodiment 2 is the same as that of the pressure dividing device 3 of embodiment 1 described with reference to fig. 5, and therefore, the description thereof is omitted. In addition, as for an actual circuit in the case where 4 resistive voltage dividing substrates in total, which are the same as the resistive voltage dividing substrate 20A, are connected in series, there are parasitic capacitances Cs1 to Cs12 between the substrates, as in the circuit of the voltage dividing device 3 of embodiment 1 described in fig. 8.

In the voltage divider device 3 according to embodiment 2, a resistance voltage dividing substrate 20A is disposed at a position of the resistance voltage dividing substrate 2A, and a resistance voltage dividing substrate 20B described later is disposed at a position of the resistance voltage dividing substrate 2B. A resistance voltage dividing substrate similar to the resistance voltage dividing substrate 20A is disposed at the position of the resistance voltage dividing substrate 2C, and a resistance voltage dividing substrate similar to the resistance voltage dividing substrate 20A is disposed at the position of the resistance voltage dividing substrate 2D.

As described in embodiment 1, since the voltage divider device 3 may malfunction when the capacitance values of the parasitic capacitances Cs1 to Cs12 are different, in embodiment 2 as well, the parasitic capacitances Cs1 to Cs12 are all controlled to have a common value, as in embodiment 1. The equivalent circuit of the resistance voltage-dividing substrate 20A shown in fig. 12 is the same as the equivalent circuits of the resistance voltage-dividing substrates 2A to 2D shown in fig. 2.

Here, capacitance values [ F ] of the parasitic capacitances Cs1 to Cs12 when 4 resistive voltage division substrates as the double-sided substrates are mounted as shown in fig. 5 will be described.

Fig. 13 is a diagram for explaining parasitic capacitance generated between the resistance voltage-dividing substrates included in the voltage-dividing device of embodiment 2. The capacitance value [ F ] of the parasitic capacitances Cs1 to Cs12 can be calculated from the same viewpoint, and therefore, the capacitance value [ F ] of the parasitic capacitance Cs1 will be described here.

The resistive voltage-dividing substrates 20A and 20B included in the voltage-dividing device 3 according to embodiment 2 are connected in series by a connecting member 11 (not shown in fig. 13). The voltage dividing device 3 according to embodiment 2 is different from the voltage dividing device 3 according to embodiment 1 in that the type of the substrate in the voltage dividing device 3 according to embodiment 2 is a double-sided substrate, and thus the copper patterns 7 are arranged on both sides of the substrate, and the copper patterns 7 on the front surface 50 and the copper patterns 7 on the rear surface 60 of the substrate are connected by the vias 17.

With this structure, the capacitance Cx of the substrate material disappears, and therefore, in embodiment 2, only the parasitic capacitance CsX between the substrates may be considered. The parasitic capacitance Cs100 between the substrates shown in fig. 13 can be obtained by the same calculation as the parasitic capacitance Cs1 between the substrates in embodiment 1. That is, it is assumed that the distance between the substrates is 10mm to 20mm, and the environment in which the voltage divider 3 is disposed has a relative dielectric constant ε_r1 atmosphere. In this case, the parasitic capacitance Cs100 between the substrates is 0.1 ε when the distance between the substrates is 10mm₀S[F]And 0.05 epsilon in the case that the distance between the substrates is 20mm₀S[F]。

As described above, according to embodiment 2, since the double-sided substrate is used for the voltage divider 3, the mounting structure of the voltage divider 3 may be designed in consideration of only the parasitic capacitance CsX between the substrates as the parasitic capacitance of the voltage divider 3. Therefore, the design of the mounting structure of the pressure dividing device 3 becomes easier than the pressure dividing device 3 of embodiment 1.

In embodiment 2, the front surface 50 and the back surface 60 of the substrate have a surface area S [ mm ] with respect to the substrate²]And the copper pattern 7 is regularly spread as large as possible, the surface area of the copper pattern 7 is 2 times as large as that of embodiment 1. Therefore, the heat dissipation performance of the substrate is improved as compared with the voltage divider 3 of embodiment 1.

Further, R (rounded) may be added to the corner portions of the copper pattern 7 closest to the corner portions of the resistance voltage dividing substrates 20A to 20D to reduce the electric field, thereby suppressing discharge from the resistance voltage dividing substrates 20A to 20D.

Fig. 14 is a diagram showing another configuration example of the resistance voltage-dividing substrate provided in the voltage-dividing device according to embodiment 2. Since the resistance voltage-dividing substrates 20A to 20D have the same configuration, another configuration example of the resistance voltage-dividing substrate 20A will be described here. As shown in fig. 14, R is added to the corner of the copper pattern 7 closest to the corner of the resistance voltage dividing substrate 20A to relax the electric field, thereby suppressing discharge from the resistance voltage dividing substrate 20A. R may be provided at the corner of all the copper patterns 7 of the resistance voltage-dividing substrate 20A. That is, R may be provided at the corner of all the copper patterns 7 of the resistance voltage dividing substrates 20A to 20D.

R may be added to the copper pattern 7 of the single-sided substrate. In this case, R is added to the corner of the copper pattern 7 closest to the corner of the resistance voltage dividing substrates 2A to 2D described in embodiment 1. Fig. 15 is a diagram showing another configuration example of the resistance voltage-dividing substrate provided in the voltage-dividing device according to embodiment 1. As shown in fig. 15, R is added to the corner of the copper pattern 7 closest to the corner of the resistance voltage dividing substrate 2A to relax the electric field, thereby suppressing discharge from the resistance voltage dividing substrate 2A. R may be provided at the corner of all the copper patterns 7 of the resistance voltage dividing substrates 2A to 2D.

The effect of suppressing discharge by adding R to the corner of the copper pattern 7 is greater in the case of the resistance voltage-dividing substrates 20A to 20D as the both-side substrates than in the case of the resistance voltage-dividing substrates 2A to 2D as the one-side substrates.

Fig. 16 is a diagram for explaining a relationship between the thickness of the resistance voltage-dividing substrate and the discharge suppressing effect. For example, the thicknesses of the resistance voltage-dividing substrates 2A and 20A are 1.6mm, respectively, and the thickness of the copper pattern 7 is 35 μm. In this case, in the resistive voltage-dividing substrate 20A as a double-sided substrate, the voltages of the facing copper patterns 7 on the front and back surfaces are the same. Therefore, the resistance voltage dividing substrate 20A has a characteristic of a block as a thick conductor according to the thickness of the resistance voltage dividing substrate 20A, and therefore the discharge suppressing effect is large. That is, the resistance voltage dividing substrate 2A has the same characteristics as a conductor having a thickness W1 of 35 μm, whereas the resistance voltage dividing substrate 20A has the same characteristics as a conductor having a thickness W2 of 1.67 mm. Therefore, the resistance voltage-dividing substrate 20A as a double-sided substrate has a greater effect of suppressing discharge from the substrate than the resistance voltage-dividing substrate 2A as a single-sided substrate.

Embodiment 3.

Next, embodiment 3 of the present invention will be described with reference to fig. 17. In embodiment 3, the resistance voltage dividing substrates are double-sided substrates, and an insulating sheet is attached between the resistance voltage dividing substrates.

Fig. 17 is a diagram for explaining the capacitance generated between the resistance voltage-dividing substrates included in the voltage-dividing device of embodiment 3. The mounting structure of the voltage divider 3 in embodiment 3 is different from the mounting structure of the voltage divider 3 in embodiment 2 in that an insulating sheet 15 is added between the substrates, and the insulating sheet 15 and the substrates are in close contact with each other. Therefore, the voltage divider 3 according to embodiment 3 has no capacitance of the substrate material, but only the capacitance Cs200 of the insulating sheet 15. Since the insulating sheets 15 between the substrates have the same thickness and the insulating sheets 15 are in close contact with the substrates, the distances d1, d2, and d3 between the substrates are equal to the thickness of the insulating sheets 15. The connection of the substrates is connected in series by the connecting member 11, similarly to the voltage divider 3 of embodiment 1.

As for an actual circuit in the case where 4 pieces in total are connected in series to the same resistance voltage-dividing substrates as the resistance voltage-dividing substrate 20A, there are parasitic capacitances Cs1 to Cs12 between the substrates, as in the circuit of the voltage-dividing device 3 of embodiment 1 described in fig. 8.

As described in embodiment 1, since there is a possibility that the voltage divider 3 may malfunction when the capacitance values of the parasitic capacitances Cs1 to Cs12 are different, in embodiment 3 as well, the parasitic capacitances Cs1 to Cs12 are all controlled to have a common value, as in embodiment 1.

In embodiment 3, only the insulating sheet 15 is provided between the substrates, and the relative dielectric constant ∈ is_rSince the parasitic capacitance CsX is not likely to change depending on temperature or humidity, the parasitic capacitance CsX is easily controlled to a common value.

Here, the capacitance Cs200 of the insulating sheet 15 is explained. The insulating sheet 15 has various thicknesses and relative dielectric constants ε depending on the material_rThe product of (1). For example, assuming that the thickness of the insulating sheet 15 is 0.5mm, the relative dielectric constant ε is measured_rAssuming that 3, the capacitance Cs200 of the insulating sheet 15 is 6.0 ε₀S[F]。

As described above, according to embodiment 3, the mounting structure of the voltage divider 3 can be designed in consideration of only the capacitance Cs200 of the insulating sheet 15 as the capacitance of the voltage divider 3, and therefore the design of the mounting structure of the voltage divider 3 is facilitated. In addition, in the voltage divider 3 of embodiment 3, the relative dielectric constant ∈ is used_rSpecific relative dielectric constant ε_rSince the insulating sheet 15 having a larger size than 1 insulates the substrates, the distance between the substrates can be made closer than the voltage divider 3 of embodiment 2, and the size can be further reduced than the voltage divider 3 of embodiment 2.

Embodiment 4.

Next, embodiment 4 of the present invention will be described with reference to fig. 18 to 23. In embodiment 4, a method of vertically arranging the resistive voltage-dividing substrates 2A to 2D will be described.

Fig. 18 is a perspective view showing the structure of the voltage dividing device when the resistance voltage dividing substrates shown in fig. 5 are arranged upright. Fig. 19 is a front view of the voltage divider shown in fig. 18. Fig. 20 is a plan view showing the structure of the voltage dividing device shown in fig. 18. Fig. 21 is a diagram showing a structure of the resistance voltage-dividing substrate shown in fig. 18. Fig. 22 is a diagram showing a structure of a screw portion of a connection terminal provided in the voltage divider shown in fig. 18, and fig. 23 is a diagram showing a structure of a cap nut provided in the voltage divider shown in fig. 18.

In fig. 18, 20, and 21, 2 axes orthogonal to each other in a plane parallel to the upper surfaces of the resistance voltage-dividing substrates 2A to 2D are defined as an X axis and a Y axis. An axis orthogonal to the X axis and the Y axis is a Z axis. The X-axis direction is a longitudinal direction of the front surfaces of the resistance voltage dividing substrates 2A to 2D, the Z-axis direction is a width direction of the front surfaces of the resistance voltage dividing substrates 2A to 2D, and the Y-axis direction is a thickness direction of the resistance voltage dividing substrates 2A to 2D. In fig. 18, a vertical direction parallel to the Z-axis direction is indicated by a top view direction D1, and a direction parallel to the X-axis direction is indicated by a front view direction D2.

The voltage divider 3 includes resistance voltage dividing substrates 2A to 2D, a connection terminal 21, a cap nut 22, and a fixing rod 23. The connection terminal 21 is a terminal for electrically connecting the resistance voltage-dividing substrates 2A to 2D. The cap nut 22 is a nut for fixing the resistance voltage dividing substrates 2A to 2D and the connection terminal 21. The fixing rod 23 is a rod-shaped member that mechanically fixes the resistance voltage dividing substrates 2A to 2D.

As shown in fig. 21, the resistive voltage dividing substrate 2A is provided with a hole 24 for a fixing rod and conductive through holes 25a to 25 d. The fixing rod hole 24 and the through holes 25a to 25d are holes that penetrate from the front surface to the back surface of the resistance voltage dividing substrate 2A. The fixing rod holes 24 and the through holes 25a to 25d are provided at both longitudinal ends of the front surface of the resistance voltage dividing substrate 2A.

Specifically, 2 through holes 25a and 25b and 1 fixing rod hole 24 are provided at one end in the longitudinal direction of the front surface of the resistance voltage dividing substrate 2A, and 2 through holes 25c and 25d and 1 fixing rod hole 24 are provided at the other end. The resistive voltage dividing substrates 2B to 2D are also provided with fixing rod holes 24 and through holes 25a to 25D at the same positions as the resistive voltage dividing substrate 2A.

For example, the through holes 25a and 25c have the same coordinates in the Z-axis direction, and the through holes 25b and 25d have the same coordinates in the Z-axis direction. The through holes 25a and 25b may have the same or different coordinates in the X-axis direction. The coordinates of the through holes 25c and 25d in the X axis direction may be the same or different. Fig. 20 shows a case where the through holes 25a and 25b have different coordinates in the X axis direction and the through holes 25c and 25d have different coordinates in the X axis direction. Fig. 21 shows a case where the coordinates in the X-axis direction of the through holes 25a and 25b are the same, and the coordinates in the X-axis direction of the through holes 25c and 25d are the same.

The coordinates in the XZ plane of the through holes 25a to 25d provided in the resistance voltage dividing substrates 2B to 2C are the same as the coordinates in the XZ plane of the through holes 25a to 25d provided in the resistance voltage dividing substrate 2A. In the following description, when it is not necessary to distinguish the through holes 25a to 25d, the through holes 25a to 25d may be referred to as through holes 25.

The fixing rod 23 penetrates all the resistive voltage dividing substrates 2A to 2D through the fixing rod holes 24 penetrating the resistive voltage dividing substrates 2A to 2D, and both ends thereof are fixed to other structures. When any 1 of the resistance voltage dividing substrates 2A to 2D is used as one resistance voltage dividing substrate and the resistance voltage dividing substrate adjacent to the one resistance voltage dividing substrate is used as the other resistance voltage dividing substrate, the fixing rod hole 24 provided in the one resistance voltage dividing substrate is the 1 st hole and the fixing rod hole 24 provided in the other resistance voltage dividing substrate is the 2 nd hole.

As shown in fig. 22, the connection terminal 21 includes screw portions 21a and 21c as conductors and a cylindrical insulating portion 21 b. The screw portions 21a and 21c are connected by a rod-shaped conductor member, and the rod-shaped conductor member is covered with an insulating portion 21 b. The rod-shaped conductor member and the screw portions 21a and 21c are integrally formed, and the integrally formed member penetrates the inside of the tube of the insulating portion 21 b. According to this configuration, the screw portion 21a is disposed on one end side of the insulating portion 21b, and the screw portion 21c is disposed on the other end side of the insulating portion 21 b. Since the screw portions 21a and 21c are connected to the insulating portion 21b via a rod-shaped conductor member, the screw portions 21a and 21c are electrically connected.

The resistance voltage-dividing substrates 2A and 2B are electrically connected via a connection terminal 21. Similarly, the resistance voltage dividing boards 2B and 2C are electrically connected through the connection terminal 21, and the resistance voltage dividing boards 2C and 2D are electrically connected through the connection terminal 21.

By changing the length of the insulating portion 21B of the connection terminal 21, the distance between the adjacent resistance voltage dividing substrates 2A and 2B can be adjusted. Similarly, the distance between the resistance voltage dividing boards 2B and 2C and the distance between the resistance voltage dividing boards 2C and 2D can be adjusted by changing the length of the insulating portion 21B of the connection terminal 21.

In the case of the voltage divider substrates 2A and 2B, the screw portion 21a of the connection terminal 21 is inserted into the through hole 25a of the voltage divider substrate 2A, and the cap nut 22 is screwed to the screw portion 21a from the opposite direction to the insertion side. Similarly, the screw portion 21c of the connection terminal 21 inserted into the through hole 25a of the voltage dividing resistor substrate 2A is inserted into the through hole 25a of the voltage dividing resistor substrate 2B, and the cap nut 22 is screwed to the screw portion 21c from the opposite direction to the insertion side.

Thus, the connection terminal 21 and the resistance voltage dividing board 2A are fixed by the cap nut 22, the connection terminal 21 and the resistance voltage dividing board 2B are fixed by the cap nut 22, and the resistance voltage dividing boards 2A and 2B are fixed by the connection terminal 21. In this case, the cap nut 22 is brought into contact with the through hole 25a, whereby the adjacent resistance voltage dividing substrates 2A and 2B are electrically connected.

For example, when the resistance voltage dividing substrate 2A is one resistance voltage dividing substrate and the resistance voltage dividing substrate 2B is the other resistance voltage dividing substrate, the cap nut 22 for fixing the resistance voltage dividing substrate 2A and the connection terminal 21 is the 1 st cap nut, and the cap nut 22 for fixing the resistance voltage dividing substrate 2B and the connection terminal 21 is the 2 nd cap nut. In this case, the through hole 25a provided in the resistance voltage dividing substrate 2A is the 3 rd hole, and the through hole 25a provided in the resistance voltage dividing substrate 2B is the 4 th hole. The screw portion 21a screwed into the through hole 25a provided in the resistance voltage dividing substrate 2A is a 1 st screw portion, and the screw portion 21c screwed into the through hole 25a provided in the resistance voltage dividing substrate 2B is a 2 nd screw portion.

The through hole 25a of the resistance voltage dividing substrate 2A and the through hole 25a of the resistance voltage dividing substrate 2B are used for connection of the resistance voltage dividing substrates 2A and 2B. The through hole 25d of the resistance voltage dividing substrate 2B and the through hole 25d of the resistance voltage dividing substrate 2C are used for connecting the resistance voltage dividing substrates 2B and 2C. The through hole 25b of the resistance voltage dividing substrate 2C and the through hole 25b of the resistance voltage dividing substrate 2D are used for connecting the resistance voltage dividing substrates 2C and 2D. In addition, when the resistance voltage dividing substrate 2A is connected to the resistance voltage dividing substrate on the opposite side of the resistance voltage dividing substrate 2B, the through hole 25c is used. In addition, when the resistance voltage dividing substrate 2D is connected to the resistance voltage dividing substrate on the side opposite to the resistance voltage dividing substrate 2C, the through hole 25C is used.

In this way, the position of the connection terminal 21 is arranged so as not to be close between the resistance voltage dividing substrates 2A to 2D. That is, the connection terminal 21 is disposed between the resistance voltage dividing substrates 2A to 2D so that the coordinates in the XZ plane of the connection terminal 21 connecting the resistance voltage dividing substrates 2A and 2B, the coordinates in the XZ plane of the connection terminal 21 connecting the resistance voltage dividing substrates 2B and 2C, and the coordinates in the XZ plane of the connection terminal 21 connecting the resistance voltage dividing substrates 2C and 2D are not the same. For example, when the 1 st through-hole 25 (the through-hole 25a in fig. 21) is used for connection on the front surface side of the resistance voltage dividing substrate 2B, the 2 nd through-hole 25 (the through-hole 25B in fig. 21) closest to the 1 st through-hole 25 is not used for connection on the back surface side of the resistance voltage dividing substrate 2B, but the 3 rd through-hole 25 (the through-hole 25d in fig. 21) on the opposite side in the longitudinal direction is used.

In addition, when the 3 rd through hole 25 (the through hole 25d in fig. 21) is used for the connection on the front surface side of the resistance voltage dividing substrate 2C, the 4 th through hole 25 (the through hole 25C in fig. 21) closest to the 3 rd through hole 25 is not used for the connection on the back surface side of the resistance voltage dividing substrate 2C, and the 1 st or 2 nd through hole 25 on the opposite side in the longitudinal direction is used. In this case, since the 1 st through hole 25 is used for connection on the front surface side of the resistance voltage dividing substrate 2B, the 2 nd through hole 25 is used for connection on the back surface side of the resistance voltage dividing substrate 2C.

This can lengthen the insulation distance L1 between the cap nuts 22 of the adjacent ones of the resistance voltage dividing substrates 2A to 2D. Further, the insulation distance between the front-side cap nut 22 and the rear-side cap nut 22 of the resistance voltage divider substrates 2A to 2D can be made longer.

In embodiment 4, the connection terminal 21 is disposed between the resistance voltage dividing substrates 2A to 2D so that the coordinates in the XZ plane of the connection terminal 21 to which the resistance voltage dividing substrates 2A and 2B are connected, the coordinates in the XZ plane of the connection terminal 21 to which the resistance voltage dividing substrates 2B and 2C are connected, and the coordinates in the XZ plane of the connection terminal 21 to which the resistance voltage dividing substrates 2C and 2D are connected are different from each other. This allows the resistive voltage-dividing substrates 2A to 2D to be electrically connected while securing the insulation distance between the cap nuts 22.

The configuration described in the above embodiment is an example of the content of the present invention, and may be combined with other known techniques, and a part of the configuration may be omitted or modified within a range not departing from the gist of the present invention.