阅读说明：本技术 具有多个裸片的ic封装 (IC package with multiple dies ) 是由 托马斯·戴尔·博尼菲尔德 于 2020-06-12 设计创作，主要内容包括：一种集成电路(IC)封装(100)包含具有覆盖衬底(116)的第一表面(108)的第一裸片(102)。所述第一裸片(102)包含在与所述第一表面(108)相对的第二表面(118)处的第一金属垫(130)。所述IC封装(100)还包含具有第一表面(119)的介电层(106),所述第一表面接触所述第一裸片(102)的所述第二表面(118)。所述IC封装(100)还包含具有接触所述介电层(106)的第二表面(121)的表面(120)的第二裸片(104)。所述第二裸片(104)包含与所述第一裸片(102)的所述第一金属垫(132)对准的第二金属垫(132)。垂直于所述第一裸片(102)的所述第二表面(118)的平面(136)与所述第一金属垫(130)和所述第二金属垫(132)相交。(An Integrated Circuit (IC) package (100) includes a first die (102) having a first surface (108) overlying a substrate (116). The first die (102) includes a first metal pad (130) at a second surface (118) opposite the first surface (108). The IC package (100) also includes a dielectric layer (106) having a first surface (119) that contacts the second surface (118) of the first die (102). The IC package (100) also includes a second die (104) having a surface (120) that contacts a second surface (121) of the dielectric layer (106). The second die (104) includes a second metal pad (132) aligned with the first metal pad (132) of the first die (102). A plane (136) perpendicular to the second surface (118) of the first die (102) intersects the first metal pad (130) and the second metal pad (132).)

1. An Integrated Circuit (IC) package, comprising:

a first die having a first surface overlying a substrate, wherein the first die includes a first metal pad at a second surface opposite the first surface;

a dielectric layer having a first surface contacting the second surface of the first die; and

a second die having a surface contacting a second surface of the dielectric layer, the second die including a second metal pad aligned with the first metal pad of the first die, wherein a plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

2. The IC package of claim 1, wherein the first and second metal pads form a capacitor, and the first and second dies communicate through the capacitor.

3. The IC package of claim 2, wherein the first die and the second die are galvanically isolated.

4. The IC package of claim 3, wherein the first die has a first ground potential and the second die has a second ground potential, wherein the first ground potential differs from the second ground potential by at least 40 volts.

5. The IC package of claim 1, wherein the surface of the second die is a first surface and the substrate is a first substrate, the IC package further comprising:

a second substrate contacting a second surface of the second die, wherein the second surface of the second die is opposite the first surface of the second die.

6. The IC package of claim 5, further comprising:

a recess in the second substrate and an insulating layer of the second die, the recess exposing a portion of a metal layer of the second die to provide a third metal pad, wherein the insulating layer of the second die separates the metal layer of the second die from the second substrate; and

a bonding wire coupled to the third metal pad.

7. The IC package of claim 1, wherein the dielectric layer comprises:

a first protective overcoat contacting the second surface of the first die;

a second protective overcoat contacting the surface of the second die; and

a non-conductive die adhesive sandwiched between the first protective overcoat and the second protective overcoat.

8. The IC package of claim 7, further comprising:

a recess in the first protective overcoat, the recess exposing a third metal pad formed at the second surface of the first die; and

a bonding wire coupled to the third metal pad.

9. The IC package of claim 7, wherein the surface of the second die is a first surface and the substrate is a first substrate, the IC package further comprising:

a second substrate contacting a second surface of the second die, wherein the second surface of the second die is opposite the first surface of the second die;

a first recess in the second substrate and an insulating layer of the second die, the first recess exposing a portion of a metal layer in the second die to provide a third metal pad, wherein the insulating layer of the second die separates the metal layer of the second die from the second substrate;

a first wire bond coupled to the third metal pad;

a second recess in the first protective overcoat, the second recess exposing a fourth metal pad formed at the second surface of the first die; and

a second wire bond coupled to the fourth metal pad.

10. The IC package of claim 9, wherein the second die has a smaller footprint than the first die.

11. The IC package of claim 1, wherein the dielectric layer further comprises:

a first protective overcoat contacting the second surface of the first die;

a second protective overcoat contacting the surface of the second die;

a spacer plate sandwiched between the first protective overcoat and the second protective overcoat;

a recess in the first protective overcoat, the recess exposing a third metal pad formed at the second surface of the first die;

a first non-conductive die adhesive (NCDA) layer sandwiched between the first protective overcoat and the first surface of the spacer plate, wherein the first NCDA layer covers a portion of the first protective overcoat that is spaced apart from the recess in the first protective overcoat; and

a second layer of NCDA sandwiched between the second protective overcoat and a second surface of the spacer plate, the second surface being opposite the first surface of the spacer plate.

12. The IC package of claim 11, wherein the surface of the second die is a first surface and the substrate is a first substrate, the IC package further comprising:

a second substrate contacting a second surface of the second die, wherein the second surface of the second die is opposite the first surface of the second die;

a first recess in the second substrate and an insulating layer of the second die, the first recess exposing a metal layer of the second die to provide a third metal pad, wherein the insulating layer of the second die separates the metal layer of the second die from the second substrate;

a first wire bond coupled to the third metal pad;

a second recess in the first protective overcoat, the second recess exposing a fourth metal pad formed at the second surface of the first die; and

a second wire bond coupled to the fourth metal pad.

13. The IC package of claim 12, wherein the spacer plate and the second die have a smaller footprint than the first die.

14. An Integrated Circuit (IC) package, comprising:

a first die having a first surface overlying a first substrate, wherein the first die includes a first metal pad at a second surface opposite the first surface;

a second die comprising a second metal pad aligned with the first metal pad;

a first protective overcoat contacting the second surface of the first die, wherein the first protective overcoat comprises a first recess exposing a third metal pad positioned at the second surface of the first die;

a second protective overcoat contacting a first surface of the second die;

a non-conductive die adhesive (NCDA) layer sandwiched between the first protective overcoat and the second protective overcoat, wherein the first metal pad and the second metal pad form a capacitor coupling the first die and the second die, wherein the NCDA layer covers a portion of the first protective overcoat, the portion being spaced apart from the first recess; and

a second substrate contacting a second surface of the second die, wherein a second recess extending through the second substrate and an insulating layer of the second die exposes a portion of the metal layer to provide a fourth metal pad.

15. The IC package of claim 14, further comprising:

a first wire bond coupled to the third metal pad positioned; and

a second wire bond coupled to the fourth metal pad.

16. The IC package of claim 14, wherein the first die and the second die are galvanically isolated.

17. The IC package of claim 14, wherein the NCDA layer is a first NCDA layer, the IC package further comprising:

a second NCDA layer between the second protective overcoat and the first protective overcoat; and

a spacer between the first and second NCDA layers.

18. A method for forming an Integrated Circuit (IC) package, the method comprising:

applying a protective overcoat to a first die wafer comprising a first die and a second die wafer comprising a second die, wherein a first surface of the first die covers a substrate and a second surface of the first die comprises a first metal pad, and the second surface of the first die is opposite the first surface of the first die; singulating the first die from the first die wafer and singulating the second die from the second die wafer;

applying a non-conductive die adhesive (NCDA) layer to the second surface of the first die;

aligning a second metal pad positioned on a surface of the second die with the first metal pad of the first die; and

bonding the second die to the NCDA layer to form a capacitor in combination with the first metal pad and the second metal pad, wherein the capacitor couples the first die with the second die.

19. The method for forming an IC package of claim 18, wherein the surface of the second die is a first surface, the method further comprising:

etching a first recess into the second die wafer, the first recess extending through a second substrate contacting a second surface of the second die and an insulating layer of the second substrate to expose a portion of a metal layer of the second substrate to provide a third metal pad, wherein the second surface of the second die is opposite the first surface of the second die, and the insulating layer of the second die separates the metal layer of the second metal pad from the second substrate;

etching a second recess in the first protective overcoat covering the first die wafer to expose a fourth metal pad positioned on the second surface of the first die, wherein the NCDA layer is applied to a portion of the first protective overcoat, the portion being spaced apart from the second recess; and

wire bonds are attached to the third and fourth metal pads.

20. The method for forming an IC package of claim 18, wherein the first die is galvanically isolated from the second die.

Technical Field

This description relates to Integrated Circuit (IC) packages, and more particularly, to IC packages having multiple dies.

Background

Galvanic isolation is the principle of isolating functional sections of an electrical system to prevent current flow so that no direct conductive path is permitted. Energy or information may still be exchanged between segments by other mechanisms, such as capacitive, inductive, or electromagnetic waves. Galvanic isolation is used where two or more circuits communicate but each such circuit has a ground that may be at a different potential. Galvanic isolation is an effective method of opening the ground loop by preventing undesirable current from flowing between two cells sharing a ground conductor. Galvanic isolation is also used for safety, preventing current from accidentally passing through a person's body to ground.

The capacitor may provide galvanic isolation by allowing Alternating Current (AC) to flow but blocking direct current. Thus, the capacitor may couple AC signals between circuits at different dc voltages.

Disclosure of Invention

A first example relates to an Integrated Circuit (IC) package including a first die having a first surface overlying a substrate. The first die includes a first metal pad at a second surface opposite the first surface, and a dielectric layer having a first surface contacting the second surface of the first die. The IC package also includes a second die having a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first and second metal pads.

A second example relates to an IC package. The IC package includes a first die having a first surface overlying a first substrate, wherein the first die includes a first metal pad at a second surface opposite the first surface. The IC package also includes a second die including a second metal pad aligned with the first metal pad. A first protective overcoat contacts the second surface of the first die. The first protective overcoat includes a first recess exposing a third metal pad positioned at the second surface of the first die. A second protective overcoat contacts the first surface of the second die. A non-conductive die adhesive (NCDA) layer is sandwiched between the first protective overcoat and the second protective overcoat. The NCDA layer covers a portion of the first protective overcoat, the portion being spaced apart from the first recess. The first metal pad and the second metal pad form a capacitor coupling the first die with the second die. The IC package also includes a second substrate contacting a second surface of the second die. A second recess extending through the second substrate and the insulating layer of the second die exposes a portion of the metal layer to provide a fourth metal pad.

A third example relates to a method for forming an IC package. The method includes applying a protective overcoat to a first die wafer including a first die and a second die wafer including a second die. A first surface of the first die covers a substrate and a second surface of the first die includes a first metal pad. The second surface of the first die is opposite the first surface of the first die. The method includes singulating the first die from the first die wafer and singulating the second die from the second die wafer. The method also includes applying an NCDA layer to the second surface of the first die and aligning a second metal pad positioned on a surface of the second die with the first metal pad of the first die. The method also includes bonding the second die to the NCDA layer to form a capacitor in conjunction with the first metal pad and the second metal pad. The capacitor couples the first die with the second die.

Drawings

Fig. 1 illustrates a diagram of an example of an Integrated Circuit (IC) package having a galvanically isolated first die and second die.

Fig. 2 illustrates another example of an IC package having a galvanically isolated first die and second die.

Figure 3 illustrates yet another example of an IC package having a galvanically isolated first die and second die.

Fig. 4 illustrates a flow diagram of an example method of forming an IC package.

Fig. 5 illustrates a first packaging stage of an IC package formed by the method of fig. 4.

Fig. 6 illustrates a second packaging stage of the IC package formed by the method of fig. 4.

Fig. 7 illustrates a third packaging stage of the IC package formed by the method of fig. 4.

Fig. 8 illustrates a fourth packaging stage of the IC package formed by the method of fig. 4.

Fig. 9 illustrates a flow diagram of another example method of forming an IC package.

Fig. 10 illustrates a first packaging stage of an IC package formed by the method of fig. 9.

Fig. 11 illustrates a second packaging stage of the IC package formed by the method of fig. 9.

Fig. 12 illustrates a third packaging stage of the IC package formed by the method of fig. 9.

Fig. 13 illustrates a fourth packaging stage of the IC package formed by the method of fig. 9.

Fig. 14 illustrates a fifth packaging stage of the IC package formed by the method of fig. 9.

Detailed Description

The present description relates to an Integrated Circuit (IC) package having a galvanically isolated and capacitively coupled first die and second die. The first die and the second die include embedded circuitry. Furthermore, because the first die and the second die are galvanically isolated, the ground of the circuitry embedded in the first die may be at a different potential than the ground of the circuitry embedded in the second die. The first die has a first surface overlying the first substrate, and the first die has a first metal pad at a second surface opposite the first surface. A first protective overcoat contacts the second surface of the first die. The second die has a first surface contacting the second protective overcoat. The second die includes a second metal pad aligned with the first metal pad. The first metal pad and the second metal pad form a node of a capacitor that couples the first die with the second die.

A non-conductive die adhesive (NCDA) layer is sandwiched between the first protective overcoat and the second protective overcoat. In some examples, a plurality of NCDA layers and/or spacers are sandwiched between the first protective overcoat layer and the second protective overcoat layer. The combination of the first protective overcoat, the second protective overcoat, the NCDA layer (and/or other layers) between the first metal pad of the first die and the second metal pad of the second die form a dielectric layer. The first metal pad of the first die and the second metal pad of the second die are separated by a dielectric layer, thereby forming a capacitor that capacitively couples the first die to the second die.

Additionally, wire bonds may be employed to couple the first die and the second die to other components, such as other dies of the IC package and/or external leads. More specifically, a first recess in the first protective overcoat exposes a third metal contact positioned on the second surface of the first die. Similarly, a second substrate (e.g., formed of silicon) contacts a second surface of the second die. The second substrate includes a second recess exposing a fourth metal pad positioned at the second surface of the second die. Wire bonds are coupled to the respective third and fourth metal pads to couple the first die and the second die to other components of the IC package.

By implementing the IC package in this manner, electrical isolation including functional isolation, basic isolation, or enhanced isolation may be achieved. Additionally, because the first die and the second die are galvanically isolated, the first die and the second die may be fabricated using different processing techniques, particularly where the maximum voltage of the first die is different than the maximum voltage of the second die.

Fig. 1 illustrates a diagram of an example of an IC package 100 in a condition for completing the package. The IC package 100 includes a first die 102 and a second die 104. The first die 102 and the second die 104 include respective embedded circuits. In one orientation, the second die 104 is stacked on the first die 102, and the first die 102 is separated from the second die 104 by the dielectric layer 106.

The first surface 108 of the first die 102 overlies the substrate 116. The substrate 116 may be formed of silicon. The second surface 118 of the first die 102 is opposite the first surface 108. In some examples, the second surface 118 of the first die 102 is referred to as a face of the first die 102. In one orientation, the second surface 118 of the first die 102 is positioned below the dielectric layer 106 such that the first surface 119 of the dielectric layer 106 contacts the second surface of the first die 102.

The second die 104 includes a first surface 120 and a second surface 122. The second surface 122 of the second die 104 is opposite the first surface 120 of the second die 104. In some examples, the second die 104 has a smaller footprint than the first die 102. The footprint of a die refers to the area of the surface of the respective die. In some examples, the first surface 120 of the second die 104 contacts the second surface 121 of the dielectric layer 106. The second surface 121 of the dielectric layer 106 is opposite the first surface 119 of the dielectric layer 106.

In some examples, the dielectric layer 106 implements a protective overcoat for the first and second dies and a single layer of homogeneous material, such as a non-conductive die adhesive (NCDA) layer, such as a layer formed from an epoxy. In other examples, the dielectric layer 106 may be implemented with multiple heterogeneous material layers, such as a protective overcoat for the first and second dies, multiple layers of NCDA, and spacers interposed between the multiple layers of NCDA.

The first die 102 and the second die 104 include embedded circuitry. The first die 102 and the second die 104 may be formed by different materials and/or processing techniques. In this manner, the materials and/or processing techniques used to fabricate the first and second dies 102, 104 individually may be selected based on the operating parameters (e.g., maximum voltage) of the first and second dies 102, 104.

In some examples, the arrangement of the first die 102 and the second die 104 is referred to as a face-to-face configuration. The first die 102 includes a first metal pad 130 (e.g., a connector) and the second die 104 includes a second metal pad 132. The first metal pad 130 and the second metal pad 132 are coincident and aligned. Thus, in one orientation, a plane, such as plane 136, extending perpendicular to the second surface 118 of the first die 102 intersects the first metal pad 130 and the second metal pad 132. The first metal pad 130 forms a first node of the capacitor 140 and the second metal pad 132 forms a second node of the capacitor 140.

The first die 102 and the second die 104 are galvanically isolated and capacitively coupled by the capacitor 140. In this manner, the circuitry embedded in the first die 102 communicates with the circuitry embedded in the second die 104 through the capacitors 140. Because the first die 102 and the second die 104 are galvanically isolated, in some examples, the first die 102 and the second die 104 have grounds that are at different potentials. In one example of a high voltage application, the ground of the first die 102 and the ground of the second die 104 have a high voltage difference (e.g., a voltage difference of about 40 volts (V) or greater). Indeed, in some examples, such as where the first die 102 includes circuitry for driving a motor and the second die 104 controls operations on the first die 102, the ground voltage of the first die 102 may be 1 kilovolt (kV) or more greater than the ground voltage of the second die 104.

The first die 102 includes a third metal pad 150 positioned on the second surface 118 of the first die 102. The first bonding wire 152 is coupled to the third metal pad 150. Further, a fourth metal pad 154 is positioned on the second surface 122 of the second die 104. The second bonding wire 156 is coupled to the fourth metal pad 154. The first wire bond 152 and the second wire bond 156 are coupled to other components of the IC package, such as other dies and/or leads of the IC package.

The IC package 100 provides a simple design that achieves galvanic isolation. Further, in some examples, the IC package 100 achieves base isolation, and in other examples, the IC package 100 achieves enhanced isolation. Additionally, as noted, the first die 102 and the second die 104 are embedded with circuits having different ground potentials. Wafer materials and processing techniques selected for a particular voltage range and/or other operating parameters of the first die 102 and the second die 104 may be employed. In contrast, in a scenario where the circuitry of the first die 102 and the second die 104 are integrated based on a particular technology that provides isolation, a designer would be limited to using that single particular type of material and processing technology.

Fig. 2 illustrates a detailed view of an example of an IC package 200 in conditions for completing the package. The IC package 200 may be used to implement the IC package 100 of fig. 1. The IC package 200 includes a galvanically isolated first die 202 and a second die 204.

The first surface 208 of the first die 202 overlies the first substrate 210. The first substrate 210 may be formed of silicon. A first protective overcoat 212 is applied to a second surface 214 of the first die 202, and the second surface 214 is opposite the first surface 208. In some examples, the second surface 214 of the first die 202 is referred to as a face of the first die 202.

The second die 204 includes a first surface 220 and a second surface 222. The second surface 222 of the second die 204 is opposite the first surface 220 of the second die 204. The first surface 220 of the second die 204 is referred to as a face of the second die 204. In some examples, the second die 204 has a smaller footprint than the first die 202. A second protective overcoat 224 is bonded to the first surface 220 of the second die 204.

The first die 202 and the second die 204 include embedded circuitry. The first die 202 and the second die 204 may be formed by different materials and/or processing techniques. In this manner, the materials and/or processing techniques used to fabricate the first and second dies 202 and 204, respectively, may be selected based on the operating parameters of the first and second dies 202 and 204.

The NCDA layer 226 is bonded to the first protective overcoat 212 and the second protective overcoat 224. In other words, the NCDA layer 226 is sandwiched between the first protective overcoat 212 and the second protective overcoat 224. In some examples, the NCDA layer 226 is implemented with epoxy.

In some examples, the arrangement of the first die 202 and the second die 204 is referred to as a face-to-face configuration. The first die 202 includes a first metal pad 230 (e.g., a connector) and the second die 204 includes a second metal pad 232. The first and second metal pads 230 and 232 may each have a diameter in the range of 40 to 200 micrometers (μm). The first metal pad 230 and the second metal pad 232 are consistent and aligned within manufacturing tolerances (e.g., ± 10 μm). Thus, in one orientation, a plane, such as plane 236, extending perpendicular to the second surface 214 of the first die 202 intersects the first and second metal pads 230 and 232. The first metal pad 230 forms a first node of the capacitor 240 and the second metal pad 232 forms a second node of the capacitor 240.

The first protective overcoat 212 and the second protective overcoat 224 can each be formed from a stack of materials. For example, the first protective overcoat 212 and the second protective overcoat 224 can be formed with: first layer of silicon dioxide (SiO)₂) At least about 1 μm (e.g., ± 0.7 μm) thick; a second layer of silicon oxynitride (SiON) that is at least about 1 μm (e.g., + -0.7 μm) thick; and a third layer of silicon dioxide (SiO)₂) And is at least about 10 μm (e.g., ± 8 μm) thick. Additionally, the thickness of the NCDA layer 226 can be at least about 6 μm (e.g., + -4 μm). The dielectric layer 106 of fig. 1 may be implemented with a combination of the first protective overcoat 212, the second protective overcoat 224, and the NCDA layer 226. In such cases, the first and second metal pads 230, 232 are separated by a distance of about 30 μm (e.g., ± 22.8 μm).

The first die 202 and the second die 204 are galvanically isolated and capacitively coupled by a capacitor 240. In this way, the circuitry embedded in the first die 202 may communicate with the circuitry embedded in the second die 204 through the capacitors 240, and vice versa. Because the first die 202 and the second die 204 are galvanically isolated, in some examples, the first die 202 and the second die 204 have grounds at different potentials. In one example of a high voltage application, the ground of the first die 202 and the ground of the second die 204 have a high voltage difference (e.g., a voltage difference of about 40V or greater). Indeed, in some examples, such as where the first die 202 includes circuitry for driving a motor and the second die 204 controls operations on the first die 202, the ground voltage of the first die 202 may be 1kV or more greater than the ground voltage of the second die 204.

In some examples, the first recess 242 is etched in the first protective overcoat 212. The first recess 242 in the first protective overcoat 212 exposes the third metal pad 250 positioned on the second surface 214 of the first die 202. The first recess 242 is spaced apart from the NCDA layer 226. In other words, in instances in which the first recess 242 is included, the first NCDA layer 226 is applied to a portion of the first protective overcoat 212 covering the first die 202 that is spaced apart from the first recess 242. Thus, the first NCDA layer 226 does not cover or otherwise cover the first recess 242. The first bonding wire 252 is coupled to the third metal pad 250. Additionally, a second substrate 254 (e.g., formed of silicon) contacts the second surface 222 of the second die 204. More specifically, the second surface 222 is proximate to the insulating layer 255 of the second die 205, and the second substrate 254 contacts the insulating layer 255 of the second die 205. A second recess 256 formed by a backside processing technique is etched in the second substrate 254 and the insulating layer 255 of the second die 204 to expose a portion of the metal layers within the second die 204, providing a fourth metal pad 260. Thus, in some examples, the opening in the second substrate 254 and the insulating layer 255 forming the recess 256 are self-aligned. In addition, the insulating layer 255 of the second die 204 separates the fourth metal pad 260 from the substrate 254. The second bonding wire 262 is coupled to the fourth metal pad 260. The first and second wire bonds 252, 262 may be coupled to other components of the IC package 200, such as other dies of the IC package 200 and/or external leads.

The IC package 200 provides a simple design that achieves galvanic isolation. Further, in some examples, the IC package 200 achieves base isolation, and in other examples, the IC package 200 achieves enhanced isolation. Additionally, as noted, in some examples, the first die 202 and the second die 204 are embedded with circuitry having different maximum voltages. Accordingly, wafer materials and processes selected for particular voltage ranges and/or other operating parameters of the first die 202 and the second die 204 may be employed. In contrast, in a scenario where the circuitry of the first die 202 and the second die 204 are integrated by a single technology, a designer would be limited to using a single type of material and processing technology.

Fig. 3 illustrates a detailed view of the IC package 300 in a condition for completing the package. The IC package 300 may be used to implement the IC package 100 of fig. 1. The IC package 300 includes a galvanically isolated first die 302 and a second die 304.

The first surface 308 of the first die 302 overlies the first substrate 310. The first substrate 310 may be silicon. A first protective overcoat 312 is applied to a second surface 316 of the first die 302, and the second surface 316 is opposite the first surface 308. In some examples, the second surface 316 of the first die 302 is referred to as a face of the first die 302.

The second die 304 includes a first surface 320 and a second surface 322. The second surface 322 of the second die 304 is opposite the first surface 320 of the second die 304. The first surface 320 of the second die 304 is referred to as a face of the second die 304. In some examples, the second die 304 has a smaller footprint than the first die 302. A second protective overcoat 324 is bonded to the first surface 320 of the second die 304.

The first die 302 and the second die 304 include embedded circuitry. The first die 302 and the second die 304 may be formed by different materials and/or processing techniques. In this manner, the materials and/or processing techniques used to fabricate the first and second dies 302, 304 individually may be selected based on the operating parameters of the first and second dies 302, 304.

The spacer plate 326 is sandwiched between the first protective overcoat 312 and the second protective overcoat 324. The spacer plate 326 is formed of a non-conductive material. In some examples, the spacer plate 326 is made of silicon dioxide (SiO), such as fused silica or quartz₂) The material is formed.

The first NCDA layer 328 is bonded to the first protective overcoat 312 and the spacer plate 326. Thus, the first NCDA layer 328 is sandwiched between the first protective overcoat 312 and the spacer plate 326. The second NCDA layer 330 is adhered to the second protective overcoat 324. Thus, the second NCDA layer 330 is sandwiched between the second protective overcoat 324 and the spacer plate 326. In some examples, the first NCDA layer 328 and the second NCDA layer 330 are formed of an epoxy.

In some examples, the arrangement of the first die 302 and the second die 304 is referred to as a face-to-face configuration. The first die 302 includes a first metal pad 332 (e.g., a connector) and the second die 304 includes a second metal pad 334. The first and second metal pads 332, 334 may each have a diameter of about 120 μm (e.g., ± 80 μm). The second die 304 is aligned with the first die 302 such that the first metal pads 332 and the second metal pads 334 are consistent and aligned within a manufacturing tolerance (e.g., ± 10 μm). Thus, in one orientation, a plane, such as plane 338, extending perpendicular to the second surface 316 of the first die 302 intersects the first metal pad 332 and the second metal pad 334. The first metal pad 332 forms a first node of the capacitor 340 and the second metal pad 334 forms a second node of the capacitor 340. The IC package 300 has a thinner first protective overcoat 312 and a thinner second protective overcoat 324 than the IC package 200 of fig. 2. The spacer plate 326 compensates for the reduced thickness of the first protective overcoat 312 and the second protective overcoat 324.

The first protective overcoat 312 and the second protective overcoat 324 can each be formed from a stack of materials. For example, the first protective overcoat 312 and the second protective overcoat 324 can be formed with: first layer of silicon dioxide (SiO)₂) At least about 1 μm (e.g., ± 0.7 μm) thick; and a second layer of silicon oxynitride (SiON) at least about 1 μm (e.g., ± 0.7 μm) thick. Additionally, the thickness of the first NCDA layer 328 and the second NCDA layer 330 is at least about 6 μm (e.g., ± 4 μm) thick. The spacer plate 326 has a thickness of at least about 20 μm (e.g., ± 10 μm). The combination of the first protective overcoat 312, the second protective overcoat 324, the first NCDA layer 328, the second NCDA layer 330, and the spacer plate 326 can be used to implement the dielectric layer 106 of fig. 1. In such cases, the first and second metal pads 332, 334 are separated by a distance of about 36 μm (e.g., ± 20.8 μm).

The first die 302 and the second die 304 are galvanically isolated and capacitively coupled by a capacitor 340. In this way, the circuitry embedded in the second die 304 can communicate with the circuitry embedded in the second die 304 through the capacitors 340, and vice versa. Because the first die 302 and the second die 304 are galvanically isolated, the first die 302 and the second die 304 have different ground potentials. In one example of a high voltage application, the ground of the first die 302 and the ground of the second die 304 have a high voltage difference (e.g., a voltage difference of about 40V or greater). Indeed, in some examples, such as where the first die 302 includes circuitry for driving a motor and the second die 304 controls operations on the first die 302, the ground voltage of the first die 302 may be 1kV or more greater than the ground voltage of the second die 304.

In one example, the first recess 342 is etched in the first protective overcoat 312. The first recess 342 in the first protective overcoat 312 exposes a third metal pad 350 positioned on the second surface 316 of the first die 302. The first recess 342 is spaced apart from the first NCDA layer 328. In other words, in examples in which the first recess 342 is included, the first NCDA layer 328 is applied to a portion of the first protective overcoat 312 covering the first die 302 that is spaced apart from the first recess 342. Thus, the first NCDA layer 342 does not cover or otherwise cover the first recess 342. The first bonding wire 352 is coupled to the third metal pad 350. Additionally, a second substrate 354 (e.g., formed of silicon) contacts the second surface 322 of the second die 304. More specifically, the second die 304 includes an insulating layer 355 proximate the second surface 322 of the second die 304. Thus, in some examples, the second substrate 354 contacts the insulating layer 355 of the second die 304. Etching the second recess 356 in the second substrate 354 and the insulating layer 355 of the second die 304 using backside processing techniques exposes a portion of the metal layer of the second die 304 to provide a fourth metal pad 360 within the second die 304. Thus, in some examples, the opening formed in the second substrate 354 and the insulating layer 355 of the second die 304 forming the second recess 356 are self-aligned. In addition, the insulating layer 355 of the second die 304 separates the fourth metal pad 360 from the substrate 354. The second bonding wire 362 is coupled to the fourth metal pad 360. The first wire bond 352 and the second wire bond 362 are coupled to other components of the IC package 300, such as other dies and/or external leads of the IC package 300.

The IC package 300 provides a simple design that achieves galvanic isolation. Further, in some examples, IC package 300 achieves substantial isolation, and in other examples, IC package 300 achieves enhanced isolation. Additionally, as noted, in some examples, the first die 302 and the second die 304 are embedded with circuitry having different maximum voltages. Accordingly, wafer materials and processing techniques selected for particular voltage ranges and/or other operating characteristics of the first and second dies 302, 304 may be employed. In contrast, in the case where the circuitry of the first and second dies 302, 304 is integrated on a single die, the designer will be limited to using a single type of material and processing technology.

Fig. 4 illustrates a method 400 for forming an IC package. The method 400 may be employed, for example, to form the IC package 100 of fig. 1 and/or the IC package 200 of fig. 2. Thus, the IC package includes a first die and a second die, such as the first die 202 and the second die 204 of fig. 2. Method 400 is shown by fig. 5 through 8. Fig. 5-8 illustrate stages in the manufacture of the IC package 200 of fig. 2. In addition, fig. 2 and 5 to 8 use the same reference numerals to denote the same structures.

At 405, a protective overcoat is applied to a die wafer including a first die and a second die, which may be referred to as a first die wafer and a second die wafer, respectively. More specifically, as illustrated in FIG. 5, the first protective overcoat 212 and the second protective overcoat 224 are applied to a first die wafer 280 including the first die 202 and a second die wafer 282 including the second die 204, respectively, as illustrated in FIG. 5. In addition, the first die 205 covers a first substrate, such as the first substrate 210, as illustrated in fig. 5.

Referring back to fig. 4, at 410, a first recess is patterned and etched in a first protective overcoat applied to the first die wafer. At 412, the back side of the second die wafer is patterned, wherein the pattern on the back side of the second die wafer is aligned with the pattern on the front side of the second die wafer. At 413, a second recess is etched in the second substrate and the insulating layer on the second die wafer backside at the area covering the second die. In some examples, the second substrate and the second recess in the insulating layer are formed by a backside processing technique. As illustrated in fig. 6, the first recess 242 exposes the third metal pad 250 of the first die 202, and the second recess 256 exposes a portion of the metal layer of the second die 204 to provide a fourth metal pad 260.

Referring back to fig. 4, at 414, the first die and the second die are singulated from the first die wafer and the second die wafer. In some examples, the first die and the second die may be singulated with a laser process or a dicing process. At 415, a layer of NCDA is applied to the first die, such as illustrated by NCDA layer 226 of fig. 7. As illustrated in fig. 7, the NCDA layer 226 is applied to a portion of the first protective overcoat 212 of the first die 202 spaced apart from the first recess 242. Referring back to fig. 4, at 420, the first metal pads of the first die and the second metal pads on the second die are aligned and the second die is mounted to the NCDA layer, and at 425, the second die is bonded to the NCDA layer. As illustrated in fig. 8, second metal pad 232 is aligned with first metal pad 230 such that plane 236 extends through first metal pad 230 and second metal pad 232 to form a capacitor. Referring back to fig. 4, at 430, wire bonds are attached to the metal pads exposed through the first and second recesses to form the IC package 200 illustrated in fig. 2.

Fig. 9 illustrates a method 1000 for forming an IC package. The method 1000 may be employed, for example, to form the IC package 100 of fig. 1 and/or the IC package 300 of fig. 3. Thus, the IC package includes a first die and a second die, such as the first die 302 and the second die 304 of fig. 2. The method 1000 is shown by fig. 10-14. Fig. 10-14 illustrate stages in the manufacture of the IC package 300 of fig. 3. In addition, the same reference numerals are used in fig. 3 and 10 to 14 to denote the same structures.

At 1005, a protective overcoat is applied to a die wafer including a first die and a second die, which can be referred to as a first die wafer and a second die wafer. More specifically, as illustrated in fig. 10, the first and second protective overcoats 312, 324 are applied to a first die wafer 380 including the first die 302 and a second die wafer 382 including the second die 304, respectively. Additionally, as illustrated in fig. 10, a first die covers the first substrate 310. Referring back to fig. 9, at 1010, a first recess is etched in a first protective overcoat applied to a first wafer containing a first die. At 1012, the back side of the second die wafer is patterned, where the pattern on the back side of the second die wafer is aligned with the pattern on the front side of the second die wafer 282. At 1013, a second recess is etched in the insulating layer in an area covering the second die on the second substrate and the second die wafer backside. In some examples, the second substrate and the second recess in the insulating layer are formed by a backside processing technique. As illustrated in fig. 11, the first recess 342 exposes the third metal pad 350 of the first die 302, and the second recess 356 exposes the metal layer of the second die 304 to provide a fourth metal pad 360.

Referring back to fig. 9, at 1014, a first die and a second die are singulated from the first die wafer and the second die wafer, respectively. In some examples, the first die and the second die may be singulated with a laser process or a dicing process. At 1015, a first NCDA layer is applied to the first die. Fig. 12 illustrates a first NCDA layer 328 applied to the second surface 316 of the first die 302. As illustrated in fig. 12, the first NCDA layer 328 is applied to a portion of the first protective overcoat 312 of the first die 302 that is spaced apart from the first recess 342.

Referring back to fig. 9, at 1020, a spacer plate is mounted on the first NCDA layer. At 1025, a second NCDA layer is applied to the spacer plate. Fig. 13 illustrates a spacer 326 mounted on a first NCDA layer 328 and a second NCDA layer 330 applied to the spacer 326. Referring back to fig. 9, at 1030, the first metal pad of the first die and the second metal pad of the second die are aligned. At 1035, the second die is mounted to the second NCDA layer. As illustrated in fig. 14, the second metal pad 334 is aligned with the first metal pad 332 such that the plane 338 extends through the first metal pad 332 and the second metal pad 334 to form a capacitor. Referring back to fig. 9, at 1040, wire bonds are attached to the metal pads exposed through the first and second recesses 342, 356 to form the IC package 300 illustrated in fig. 3.

The above description is an example. It is, of course, not possible to describe every conceivable combination of components or methodologies, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Accordingly, the present specification is intended to embrace all such alterations, modifications and variations that fall within the scope of this application, including the appended claims.