阅读说明：本技术 一种防止负载过大导致电压跌落的开关控制电路和方法 (Switch control circuit and method for preventing voltage drop caused by overlarge load ) 是由 叶青海 庄惠明 于 2021-09-01 设计创作，主要内容包括：本发明公开了一种防止负载过大导致电压跌落的开关控制电路和方法,包括开关电路和控制电路；开关电路包括PMOS管和第一电容,PMOS管的源极与供电输入端电连接,PMOS管的漏极同时与第一电容的一端和供电输出端电连接,控制电路包括开关三极管,开关三极管的基极与信号控制端电连接,开关三极管的集电极与PMOS管的栅极电连接,开关三极管的射极和第一电容的另一端均接地；信号控制端的开关控制信号为PWM信号,PWM信号的占空比随负载瞬间电流的增大而增大且频率随负载瞬间电流的增大而减小。本发明根据负载设备的负载瞬间电流来灵活控制PWM信号的频率和占空比,无需增加硬件且无需根据负载需求更换第一电容,从而能兼容不同的负载设备且降低硬件成本。(The invention discloses a switch control circuit and a method for preventing voltage drop caused by overlarge load, comprising a switch circuit and a control circuit; the control circuit comprises a switch triode, the base electrode of the switch triode is electrically connected with the signal control end, the collector electrode of the switch triode is electrically connected with the grid electrode of the PMOS tube, and the emitter electrode of the switch triode and the other end of the first capacitor are both grounded; the switch control signal of the signal control end is a PWM signal, the duty ratio of the PWM signal is increased along with the increase of the load instantaneous current, and the frequency is reduced along with the increase of the load instantaneous current. According to the invention, the frequency and the duty ratio of the PWM signal are flexibly controlled according to the load instantaneous current of the load equipment, hardware does not need to be added, and the first capacitor does not need to be replaced according to the load requirement, so that different load equipment can be compatible, and the hardware cost is reduced.)

1. A switch control circuit for preventing voltage drop caused by overlarge load is characterized by comprising a switch circuit and a control circuit;

the switch circuit comprises a PMOS (P-channel metal oxide semiconductor) tube and a first capacitor, wherein the source electrode of the PMOS tube is electrically connected with the power supply input end, the drain electrode of the PMOS tube is simultaneously electrically connected with one end of the first capacitor and the power supply output end, and the other end of the first capacitor is grounded;

the control circuit comprises a switching triode, the base electrode of the switching triode is electrically connected with the signal control end, the collector electrode of the switching triode is electrically connected with the grid electrode of the PMOS tube, and the emitter electrode of the switching triode is grounded;

the switch control signal of the signal control end is a PWM signal, the duty ratio of the PWM signal is increased along with the increase of the load instantaneous current, and the frequency is reduced along with the increase of the load instantaneous current.

2. The switching control circuit for preventing voltage drop due to overload according to claim 1, wherein the switching circuit further comprises a second capacitor, one end of the second capacitor is electrically connected to the power input terminal, and the other end of the second capacitor is grounded.

3. The switch control circuit for preventing voltage drop caused by overload according to claim 2, wherein the capacitance value of the second capacitor is between 5 μ F and 20 μ F.

4. The switching control circuit for preventing voltage drop due to overload according to claim 1, wherein the switching circuit further comprises a first resistor and a second resistor;

two ends of the first resistor are respectively and electrically connected with a collector electrode of the switching triode and a grid electrode of the PMOS tube;

one end of the second resistor is electrically connected with the power supply input end, the other end of the second resistor is electrically connected with the grid electrode of the PMOS tube, and the resistance value of the first resistor is smaller than that of the second resistor.

5. The switch control circuit for preventing voltage drop due to overload according to claim 4, wherein the first resistor has a resistance value of 50k Ω to 200k Ω, and the second resistor has a resistance value of 500k Ω to 2M Ω.

6. The switch control circuit for preventing voltage drop caused by overload according to claim 4, wherein the switch circuit further comprises a third capacitor, one end of the third capacitor is electrically connected to the power supply input terminal, and the other end of the third capacitor is electrically connected to the gate of the PMOS transistor.

7. The switch control circuit for preventing voltage drop due to overload according to claim 6, wherein the capacitance of the third capacitor is between 50nF and 200 nF.

8. The switch control circuit for preventing voltage drop caused by overload according to claim 1, wherein the control circuit further comprises a third resistor, one end of the third resistor is electrically connected to the base of the switching transistor, and the other end of the third resistor is electrically connected to the signal control terminal.

9. The switch control circuit for preventing voltage drop due to overload according to claim 8, wherein the third resistor has a resistance value between 10k Ω and 100k Ω.

10. A switching control method for preventing voltage drop caused by overload, which is characterized by applying a switching control circuit for preventing voltage drop caused by overload according to any one of the above claims 1 to 9, and comprising the following steps:

receiving an input voltage of a power supply input end and a PWM signal of a signal control end;

when the PWM signal is at a high level, the switching triode is switched on, so that the PMOS tube is switched on, the input voltage is output to load equipment connected with a power supply output end, otherwise, when the PWM signal is at a low level, the switching triode is switched off, so that the PMOS tube is switched off, the input voltage stops being output, and the cycle is repeated until the load instantaneous current of the load equipment reaches the working current, and the signal control end keeps a high level signal.

Technical Field

The invention relates to the technical field of circuit control, in particular to a switch control circuit and a method for preventing voltage drop caused by overlarge load.

Background

In the application of electronic products, in order to control the power-up and power-down sequence of each module, an electronic switch control circuit is often used for controlling the power-up and power-down of a power supply, and the instantaneous current of a switch is often larger than that of a heavy load at the moment of conduction, so that the input voltage is instantaneously reduced, the condition easily causes the operation failure of the module or the whole machine, and the power supply device of the system is damaged at serious time. To solve this problem, it is common practice to add a resistor and a capacitor at the control terminal of the switch, delay the switching speed by using a resistor-capacitor device, and reduce the load transient current, thereby avoiding pulling down the input voltage. The method increases the cost, is not flexible, and cannot be compatible in design.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: a switch control circuit and a method for preventing voltage drop caused by overlarge load are provided, so that different load devices can be compatible, and the hardware cost is reduced.

In order to solve the technical problems, the invention adopts the technical scheme that:

a switch control circuit for preventing voltage drop caused by overlarge load comprises a switch circuit and a control circuit;

the switch circuit comprises a PMOS (P-channel metal oxide semiconductor) tube and a first capacitor, wherein the source electrode of the PMOS tube is electrically connected with the power supply input end, the drain electrode of the PMOS tube is simultaneously electrically connected with one end of the first capacitor and the power supply output end, and the other end of the first capacitor is grounded;

the control circuit comprises a switching triode, the base electrode of the switching triode is electrically connected with the signal control end, the collector electrode of the switching triode is electrically connected with the grid electrode of the PMOS tube, and the emitter electrode of the switching triode is grounded;

the switch control signal of the signal control end is a PWM signal, the duty ratio of the PWM signal is increased along with the increase of the load instantaneous current, and the frequency is reduced along with the increase of the load instantaneous current.

In order to solve the technical problem, the invention adopts another technical scheme as follows:

the switch control circuit for preventing the voltage drop caused by the overlarge load is applied to the switch control method for preventing the voltage drop caused by the overlarge load, and comprises the following steps of:

receiving an input voltage of a power supply input end and a PWM signal of a signal control end;

when the PWM signal is at a high level, the switching triode is switched on, so that the PMOS tube is switched on, the input voltage is output to load equipment connected with a power supply output end, otherwise, when the PWM signal is at a low level, the switching triode is switched off, so that the PMOS tube is switched off, the input voltage stops being output, and the cycle is repeated until the load instantaneous current of the load equipment reaches the working current, and the signal control end keeps a high level signal.

The invention has the beneficial effects that: the switch control circuit and the method prevent voltage drop caused by overlarge load, the conduction and the cut-off of a switch triode are controlled through the height change of a PWM signal, so that the conduction and the cut-off of a PMOS (P-channel metal oxide semiconductor) tube are controlled, the load instantaneous current of load equipment is restrained, and the input voltage is prevented from being lowered.

Drawings

Fig. 1 is a circuit diagram of a switching control circuit for preventing voltage drop caused by overload according to an embodiment of the present invention;

FIG. 2 is a waveform diagram of a conventional control method;

FIG. 3 is a waveform diagram of an embodiment of the present invention;

fig. 4 is a schematic flowchart of a switch control method for preventing a voltage drop caused by an excessive load according to an embodiment of the present invention.

Description of reference numerals:

c1, a first capacitance; c2, a second capacitor; c3, a third capacitance;

GPIO, signal control end;

q1 and a PMOS tube; s, a source electrode; d. a drain electrode; g. a gate electrode;

q2, switching triode; b. a base electrode; c. a collector electrode; e. an emitter;

r1, a first resistor; r2, a second resistor; r3, third resistor;

vin, a power supply input end; vout, a power supply output terminal;

iout, load transient current.

Detailed Description

In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

Referring to fig. 1 to 3, a switch control circuit for preventing voltage drop caused by excessive load includes a switch circuit and a control circuit;

the switch circuit comprises a PMOS (P-channel metal oxide semiconductor) tube and a first capacitor, wherein the source electrode of the PMOS tube is electrically connected with the power supply input end, the drain electrode of the PMOS tube is simultaneously electrically connected with one end of the first capacitor and the power supply output end, and the other end of the first capacitor is grounded;

the control circuit comprises a switching triode, the base electrode of the switching triode is electrically connected with the signal control end, the collector electrode of the switching triode is electrically connected with the grid electrode of the PMOS tube, and the emitter electrode of the switching triode is grounded;

the switch control signal of the signal control end is a PWM signal, the duty ratio of the PWM signal is increased along with the increase of the load instantaneous current, and the frequency is reduced along with the increase of the load instantaneous current.

From the above description, the beneficial effects of the present invention are: the switching on and off of the switching triode are controlled through the height change of the PWM signals, so that the switching on and off of the PMOS tube are controlled, the load instantaneous current of the load equipment is restrained, the input voltage is prevented from being lowered, therefore, the frequency and the duty ratio of the PWM signals can be flexibly controlled according to the load instantaneous current of the load equipment, hardware does not need to be added, the first capacitor does not need to be replaced according to the load requirement, and the PWM signal switching circuit can be compatible with different load equipment and reduces the hardware cost.

Furthermore, the switch circuit further comprises a second capacitor, wherein one end of the second capacitor is electrically connected with the power supply input end, and the other end of the second capacitor is grounded.

Further, the capacitance value of the second capacitor is between 5 μ F and 20 μ F.

As can be seen from the above description, the input voltage is filtered by the second capacitor to obtain a smoother voltage.

Further, the switch circuit further comprises a first resistor and a second resistor;

two ends of the first resistor are respectively and electrically connected with a collector electrode of the switching triode and a grid electrode of the PMOS tube;

one end of the second resistor is electrically connected with the power supply input end, the other end of the second resistor is electrically connected with the grid electrode of the PMOS tube, and the resistance value of the first resistor is smaller than that of the second resistor.

Further, the resistance value of the first resistor is between 50k Ω and 200k Ω, and the resistance value of the second resistor is between 500k Ω and 2M Ω.

From the above description, after the voltage division by the first resistor and the second resistor, a bias voltage is provided to the PMOS transistor to ensure the conduction of the PMOS transistor.

Furthermore, the switch circuit further comprises a third capacitor, wherein one end of the third capacitor is electrically connected with the power supply input end, and the other end of the third capacitor is electrically connected with the grid electrode of the PMOS tube.

Further, the capacitance value of the third capacitor is between 50nF and 200 nF.

From the above description, it can be known that a small capacitor is connected between the power supply input terminal and the gate of the PMOS transistor, so that the PMOS transistor can be turned on more stably.

Furthermore, the control circuit further comprises a third resistor, wherein one end of the third resistor is electrically connected with the base electrode of the switching triode, and the other end of the third resistor is electrically connected with the signal control end.

Further, the third resistor has a resistance value between 10k Ω and 100k Ω.

As can be seen from the above description, the base of the switching transistor is connected with a resistor to limit the current when the base of the switching transistor is turned on, so as to ensure the stability of the circuit.

Referring to fig. 4, a switching control method for preventing voltage drop caused by overload includes the following steps:

receiving an input voltage of a power supply input end and a PWM signal of a signal control end;

when the PWM signal is at a high level, the switching triode is switched on, so that the PMOS tube is switched on, the input voltage is output to load equipment connected with a power supply output end, otherwise, when the PWM signal is at a low level, the switching triode is switched off, so that the PMOS tube is switched off, the input voltage stops being output, and the cycle is repeated until the load instantaneous current of the load equipment reaches the working current, and the signal control end keeps a high level signal.

From the above description, the beneficial effects of the present invention are: the switching on and off of the switching triode are controlled through the height change of the PWM signals, so that the switching on and off of the PMOS tube are controlled, the load instantaneous current of the load equipment is restrained, the input voltage is prevented from being lowered, therefore, the frequency and the duty ratio of the PWM signals can be flexibly controlled according to the load instantaneous current of the load equipment, hardware does not need to be added, the first capacitor does not need to be replaced according to the load requirement, and the PWM signal switching circuit can be compatible with different load equipment and reduces the hardware cost.

Referring to fig. 1 to fig. 3, a first embodiment of the present invention is:

a switch control circuit for preventing voltage drop caused by overlarge load comprises a switch circuit and a control circuit.

As shown in fig. 1, the switch circuit includes a PMOS transistor Q1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1 and a second resistor R2, a source s of the PMOS transistor Q1 is electrically connected to the power supply input terminal Vin, one end of the second capacitor C2, one end of the third capacitor C3 and one end of the second resistor R2, a drain d of the PMOS transistor Q1 is electrically connected to one end of the first capacitor C1 and the power supply output terminal Vout, a gate g of the PMOS transistor Q1 is electrically connected to one end of the first resistor R1, the other end of the second resistor R2 and the other end of the third capacitor C3, and the other end of the first capacitor C1 and the other end of the second capacitor C2 are both grounded. The resistance value of the first resistor R1 is smaller than that of the second resistor R2.

In this embodiment, the first resistor R1 has a resistance of 100k Ω, the second resistor R2 has a resistance of 1M Ω, and the bias voltage is provided to the PMOS transistor Q1 after the voltage division by the first resistor R1 and the second resistor R2. In other equivalent embodiments, the first resistor R1 has a resistance value between 50k Ω and 200k Ω, and the second resistor R2 has a resistance value between 500k Ω and 2M Ω.

In the embodiment, the first capacitor C1 is substantially a load of an equivalent device, and the larger the capacitance value of the first capacitor C1 is, the larger the load transient current Iout of the load device is, for example, the load transient current Iout of the load device is 5A, a capacitor of 100 μ F may be selected, and if 1A, a capacitor of 10 μ F may be selected.

In the present embodiment, the capacitance of the second capacitor C2 is 10 μ F to filter the input voltage; the capacitance of the third capacitor C3 is 100nF to make the PMOS transistor Q1 conduct more stably. In other equivalent embodiments, the capacitance value of the second capacitor C2 is between 5 μ F and 20 μ F, and the capacitance value of the third capacitor C3 is between 50nF and 200 nF.

As shown in fig. 1, the control circuit includes a switching transistor Q2 and a third resistor R3, a base b of the switching transistor Q2 is electrically connected to one end of the third resistor R3, a collector c of the switching transistor Q2 is electrically connected to the other end of the first resistor R1, and an emitter e of the switching transistor Q2 is grounded; the other end of the third resistor R3 is electrically connected with the signal control terminal GPIO.

In this embodiment, the third resistor R3 has a resistance of 50k Ω, which functions to limit the current of the base b of the switching transistor Q2 when conducting, and in other equivalent embodiments, the third resistor R3 has a resistance of 10k Ω to 100k Ω.

In this embodiment, the switching transistor is a common NPN transistor, and may be of any conventional type as the PMOS transistor.

Therefore, as shown in fig. 2, in the circuit of this embodiment, if a conventional switching control mode is adopted, when a switching control signal of the signal control terminal GPIO is at a high level, so that the switching transistor Q2 and the PMOS transistor Q1 are always kept in a conducting state, an instantaneous charging current to the first capacitor C1 is very large, which causes an input voltage at a preceding-stage input voltage terminal Vin of the PMOS transistor Q1 to be pulled down instantaneously, which may cause a system under-voltage and sudden power failure to form an abnormal operation, and in a severe case, may damage a power supply circuit device of the input voltage terminal Vin, which may cause a product damage. In the conventional solution, a larger capacitor is arranged at the base b of the switching triode Q2 in fig. 1, so that the use of the device is increased, the product cost is increased, the effect is not ideal, the capacitor cannot be temporarily replaced when the load instantaneous current Iout is larger, the use is not flexible, and the compatibility is poor.

In the embodiment, the switch control signal of the signal control terminal GPIO is a PWM signal, and the duty ratio of the PWM signal increases with the increase of the load instantaneous current Iout and the frequency decreases with the increase of the load instantaneous current Iout. If the load instantaneous current Iout is 2A, the duty ratio of the PWM signal is 0.5, and the frequency thereof is 50 Hz.

As shown in fig. 3, the PWM signal output from the signal control terminal GPIO changes in height to serve as a switch control signal, which can effectively suppress the load instantaneous current Iout of the load device, thereby avoiding pulling down the input voltage, so that the frequency and duty ratio of the PWM signal can be flexibly controlled by the CPU software according to the load instantaneous current Iout of the load device, without increasing hardware and without replacing the first capacitor C1 according to the load requirement, thereby being compatible with different load devices and reducing the hardware cost.

Referring to fig. 4, a second embodiment of the present invention is:

a switch control method for preventing voltage drop caused by overlarge load comprises the following steps:

receiving an input voltage of a power supply input end and a PWM signal of a signal control end;

when the PWM signal is at a high level, the switching triode is switched on, so that the PMOS tube is switched on, and the input voltage is output to the load equipment connected with the power supply output end, otherwise, when the PWM signal is at a low level, the switching triode is switched off, so that the PMOS tube is switched off, the input voltage stops being output, and the process is repeated until the load instantaneous current Iout of the load equipment reaches the working current, and the signal control end keeps the high-level signal.

In summary, according to the switch control circuit and the method for preventing voltage drop caused by excessive load provided by the invention, the switching on and off of the switching triode is controlled through the high-low change of the PWM signal, the bias voltage is provided to the PMOS transistor after the voltage division of the first resistor and the second resistor, and a small capacitor is connected between the power supply input end and the gate of the PMOS transistor, so that the PMOS transistor can be more stably switched on, the load transient current of the load equipment is suppressed, and the input voltage is prevented from being pulled down.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.