阅读说明：本技术 一种启动继电器开启控制方法及装置 (Start relay opening control method and device ) 是由 刘树猛 李家烜 刘志远 侯涛 王群伟 程浩 杨凯 余高旺 马杰华 于 2021-01-06 设计创作，主要内容包括：本发明涉及一种启动继电器开启控制方法及装置,通过控制器产生两路控制信号组串联开启启动继电器的双重设计,只有两路控制信号组同时有效时,启动继电器才会动作闭合,大大降低了启动继电器误动作的机率,提高了独立CPU运行的继电保护控制装置的出口安全性,有效避免了与独立CPU运行错误导致的装置误出口问题,提升电力系统的稳定运行性能。(The invention relates to a starting relay opening control method and a starting relay opening control device, wherein a controller is used for generating two control signal sets which are connected in series to open a double design of a starting relay, the starting relay can act and close only when the two control signal sets are effective simultaneously, the probability of misoperation of the starting relay is greatly reduced, the outlet safety of a relay protection control device operated by an independent CPU is improved, the problem of device misoutlet caused by the operation error of the independent CPU is effectively avoided, and the stable operation performance of a power system is improved.)

1. A starting relay opening control method is characterized by comprising the following steps:

outputting a first control signal group and a second control signal group, wherein the signal state of the second control signal group is related to the signal state of the first control signal group;

and when the first control signal group and the second control signal group are both effective, outputting a starting signal to the starting relay, and enabling the starting relay to act.

2. The method of claim 1, wherein an enable signal is output through an enable switch when the first control signal group and the second control signal group are both active.

3. The method of claim 2, wherein the first control signal set is asserted, and wherein the start-up power is provided to the start-up switch via the first switch and the second switch.

4. The method of claim 3, wherein the enable signal is provided to the start switch via a third switch when the second set of control signals is asserted.

5. The method of claim 4, wherein the signal states of the second control signal group are related to the signal states of the first control signal group, including asserting the second control signal group when asserting the first control signal group.

6. A starting relay opening control device is characterized by comprising a control module, a signal transmission module and a starting relay; wherein the content of the first and second substances,

the control module outputs a first control signal group and a second control signal group, and the signal state of the second control signal group is related to the signal state of the first control signal group;

and the signal transmission module outputs a starting signal to the starting relay when the first control signal group and the second control signal group are both effective, and the starting relay acts.

7. The apparatus of claim 6, wherein the signal transmission module comprises an activation switch, and the activation switch outputs an activation signal when the first control signal group and the second control signal group are both active.

8. The apparatus of claim 7, wherein the signal transmission module further comprises a first switch and a second switch, and the first control signal set is valid, and the first switch and the second switch provide the start power for the start switch.

9. The apparatus of claim 8, wherein the signal transmission module further comprises a third switch, and wherein the enable signal is provided to the enable switch via the third switch when the second control signal group is active.

10. The apparatus of claim 9, wherein the control module is configured to enable the second control signal group when the first control signal group is enabled.

Technical Field

The invention relates to the technical field of power system relay protection, in particular to a starting relay opening control method and device.

Background

The existing opening mode of the exit start relay QD of the relay protection control program independently operated by a single CPU plug-in usually only has a differential control circuit, and a control circuit diagram of the differential control circuit is shown in fig. 1. In fig. 1, START _ P and START _ N signal states output from the output pin of the CPU processor control the on and off of the startup relay QD. When the START _ P signal is at a high level and the START _ N signal is at a low level, the transistor Q18 is turned on to change the G pin signal of the switch U20 to a low level, the switch U20 is closed to output a signal +5V _ QD from the pin D terminal to the high level 5.0VCC at the pin S terminal, so that the operating voltage of the starter relay QD is satisfied and the outlet node is closed. When the START _ P signal is at a low level and the START _ N signal is at an arbitrary state, or when the START _ N signal is at a high level and the START _ P signal is at an arbitrary state, the transistor Q18 cannot be turned on, the G pin signal of the switch U20 is always at a high level, the switch U20 is in an off state, the high level at the S pin end cannot be output through the D pin end, the operating voltage of the START relay QD is not satisfied, and the outlet node is off. Table 1 shows the relationship between the START _ P signal, the START _ N signal, and the action of the starter relay QD.

TABLE 1 START _ P, START _ N, and QD action relationship for a Start Relay

When the CPU processor works normally, the high and low levels of the START _ P signal and the START _ N signal are controlled to be inverted, and the purposes of controlling the action and the return of the starting relay QD are achieved. When the CPU processor is abnormal, for example, the program is disordered, the register is failed, and the difference signal START _ P, START _ N has a 25% probability of causing a malfunction to open the START relay QD, and the reliability of the START relay control is low.

Disclosure of Invention

Based on the above situation in the prior art, the invention aims to provide a method for improving the reliability of starting a starting relay, which is realized by a dual design that a controller generates two control signal groups to be connected in series to start the starting relay, so that the reliability of controlling the starting relay to be started is greatly improved.

In order to achieve the above object, according to an aspect of the present invention, there is provided a startup relay opening control method, including the steps of:

outputting a first control signal group and a second control signal group, wherein the signal state of the second control signal group is related to the signal state of the first control signal group;

and when the first control signal group and the second control signal group are both effective, outputting a starting signal to the starting relay, and enabling the starting relay to act.

Furthermore, when the first control signal group and the second control signal group are both effective, the starting switch outputs a starting signal.

Furthermore, when the first control signal group is effective, a starting power supply is provided for the starting switch through the first switch and the second switch.

Furthermore, when the second control signal group is effective, an enabling signal is provided for the starting switch through the third switch.

Further, the signal status of the second control signal group is correlated with the signal status of the first control signal group, including enabling the second control signal group to be output when the first control signal group is output enabled.

According to another aspect of the invention, a starting relay opening control device is provided, which comprises a control module, a signal transmission module and a starting relay; wherein the content of the first and second substances,

the control module outputs a first control signal group and a second control signal group, and the signal state of the second control signal group is related to the signal state of the first control signal group;

and the signal transmission module outputs a starting signal to the starting relay when the first control signal group and the second control signal group are both effective, and the starting relay acts.

Further, the signal transmission module comprises a start switch, and when the first control signal group and the second control signal group are both valid, the start switch outputs a start signal.

Furthermore, the signal transmission module further comprises a first switch and a second switch, and when the first control signal group is effective, the first switch and the second switch provide a starting power supply for the starting switch.

Furthermore, the signal transmission module further comprises a third switch, and when the second control signal group is valid, the third switch provides an enable signal for the start switch.

Further, the control module enables the second control signal group when the first control signal group is enabled.

In summary, the invention provides a start relay opening control method and a start relay opening control device, and a double design that a controller generates two control signal sets to be connected in series to open a start relay is adopted, so that the start relay can act and be closed only when the two control signal sets are effective simultaneously, the false operation probability of the start relay is greatly reduced, the outlet safety of a relay protection control device operated by an independent CPU is improved, the problem of device false outlet caused by the operation error of the independent CPU is effectively avoided, and the stable operation performance of a power system is improved.

Drawings

FIG. 1 is a control circuit diagram of a prior art starter relay differential control circuit;

FIG. 2 is a flow chart of a start relay on control method of the present invention;

FIG. 3 is a control circuit diagram of a start relay opening control loop according to the first embodiment of the present invention;

FIG. 4 is a control circuit diagram of a start relay opening control loop according to a second embodiment of the present invention;

FIG. 5 is a control circuit diagram of a start relay opening control loop according to a third embodiment of the present invention;

fig. 6 is a block diagram showing the configuration of the starter relay on control device of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

The technical solution of the present invention will be described in detail below with reference to the accompanying drawings. According to a set of embodiments of the present invention, there is provided a method for controlling the opening of a starter relay, and fig. 2 shows a flowchart of the method, including the steps of:

outputting a first control signal group and a second control signal group, the second control signal group being related to the first control signal group.

And when the first control signal group and the second control signal group are both effective, outputting a starting signal to the starting relay, and enabling the starting relay to act.

Fig. 3 shows a control circuit diagram of a starter relay on control loop according to a first embodiment, which is described in detail below with reference to fig. 3. In fig. 3, the control signal group is output through the CPU processor and the FPGA chip, and after being transmitted through the switching circuit, the output value starts the switch U21, and the start switch U21 is configured to output a start signal +5V _ QD to the start relay QD, thereby turning on the start relay.

The output pin of the CPU processor outputs a first control signal group, which includes START _ P and START _ N, and the START power signal +5V _ QD' of the second switch U20 is controlled by the states of the START _ P and START _ N signals. When the START _ P signal is at a high level and the START _ N signal is at a low level, the transistor Q18 is turned on, the transistor Q18 may be used as a first switch to change the G pin signal of the second switch U20 to a low level, the second switch U20 is closed to output the high level 5.0VCC at the S pin end from the D pin end, and the START power supply +5V _ QD' is provided for the START switch U21.

The output pin of the FPGA chip outputs a second control signal group, which includes START _ P 'and START _ N', and the signal states of START _ P 'and START _ N' control the opening and closing of the START switch U21 to provide a START power supply signal +5V _ QD. When the START _ P ' signal is at a high level and the START _ N ' signal is at a low level, the transistor Q1 is turned on, the transistor Q1 may serve as a third switch, a G pin signal of the START switch U21 is changed to a low level to serve as an enable signal to close the START switch U21, a high level +5V _ QD ' at the pin S end is output as a START signal +5V _ QD from the pin D end, an operation voltage of the START relay QD is satisfied, and the outlet node is closed. The output START _ P 'and START _ N' signal states of the FPGA chip are controlled by the CPU, namely, the second control signal group is related to the first control signal group, the CPU outputs the START _ P signal as high level and the START _ N signal as low level, and simultaneously controls the FPGA chip to output the START _ P 'signal as high level and the START _ N' signal as low level through the coding message. Table 2 shows the action relationship between the START _ P signal, the START _ N signal, the state START _ P 'signal, the START _ N' signal, and the START relay QD.

TABLE 2 START _ P, START _ N, START _ P ', START _ N' signal vs. START Relay QD action

When the CPU processor works normally, the high-low level inversion of the START _ P signal and the START _ N signal is controlled, and meanwhile, the high-low level inversion of the START _ P 'signal and the START _ N' signal is controlled by the FPGA chip through the coded message, so that the purposes of controlling the action and the return of the starting relay QD are achieved. When the CPU processor is abnormal, such as program confusion, register fault, etc., to cause the differential signal START _ P, START _ N to be output and cause the FPGA chip to output the differential signals START _ P 'and START _ N', there is only a 6.25% probability of causing a malfunction to open the START relay QD. According to the embodiment, the dual design that the two control signal sets are connected in series to start the starting relay is generated through the controller, the outlet safety of the relay protection control device operated by the independent CPU is improved, the problem of device misoutlet caused by operation error of the independent CPU is effectively avoided, and the stable operation performance of the power system is improved.

According to the second embodiment of the invention, the two control signal groups generated by the double-differential start control circuit are used for controlling the start relay QD in series, so that the abnormal start probability is reduced. Fig. 4 shows a control circuit diagram of a starter relay on control loop according to a second embodiment, which is described in detail below with reference to fig. 4. In fig. 4, the first control signal group and the second control signal group are both output by the CPU processor, the START _ P and START _ N signals output by the output pin of the CPU processor may be used as the first control signal group, and the states of the START _ P and START _ N signals control the START power signal +5V _ QD' of the second switch U20; the START _ P 'and START _ N' signals output by the output pins of the CPU processor may be used as a second control signal group, and the state of the START _ P 'and START _ N' signals controls the opening and closing of the START switch U21, providing the START signal +5V _ QD. When the START _ P signal is at a high level and the START _ N signal is at a low level, the transistor Q18 is turned on, the transistor Q18 is used as a first switch to change the G pin signal of the second switch U20 to a low level, the second switch U20 is closed to output the high level 5.0VCC at the S end of the pin from the D end of the pin, and a starting power supply +5V _ QD' is provided for the starting switch U21; when the START _ P ' signal is at a high level and the START _ N ' signal is at a low level, the transistor Q1 is turned on, the transistor Q1 serves as a third switch, the G pin signal of the START switch U21 is changed to a low level, the START switch U21 is closed, the high level +5V _ QD ' at the pin S end is output from the pin D end, the action voltage of the START relay QD is satisfied, and the outlet node is closed. Table 3 shows the relationship between the START _ P signal, the START _ N signal, the START _ P 'signal, the START _ N' signal, and the action of the starter relay QD.

TABLE 3 START _ P, START _ N, START _ P ', START _ N' signal vs. START Relay QD action

When the CPU processor works normally, the high-low level inversion of the START _ P signal, the START _ N signal, the START _ P 'signal and the START _ N' signal is controlled at the same time, and the action and the return of the starting relay QD are controlled. When the CPU processor is abnormal, for example, program confusion, register fault, etc., the differential signals START _ P, START _ N, START _ P 'and START _ N' are output, and only 12.5% of the probability causes malfunction to open the START relay QD.

The dual control signals may also be generated by sequentially tuning a differential start-up loop in series with a software-coded start-up loop. According to the third embodiment of the present invention, the two control signal sets are generated by adjusting the serial connection sequence of the differential start circuit and the software coding start circuit to control the start relay QD in series, so as to reduce the abnormal start probability. Fig. 5 shows a control circuit diagram of a starter relay on control loop according to a third embodiment, which is described in detail below with reference to fig. 5. In fig. 5, the control signal group generated by the CPU and the control signal group generated by the FPGA chip are exchanged and adjusted for connection with the subsequent stage circuit. The output pin of the FPGA chip outputs a first control signal group, which includes START _ P ' and START _ N ' signals, and the states of the START _ P ' and START _ N ' signals control the on/off of the second switch U20, providing a START power supply signal +5V _ QD '. When the START _ P ' signal is at a high level and the START _ N ' signal is at a low level, the transistor Q1 is turned on, the transistor Q1 is used as a first switch to change the G pin signal of the second switch U20 to a low level, the second switch U20 is closed to output the high level 5.0VCC at the S end of the pin S end of the second switch from the D end of the pin of the second switch U20, and an input power supply +5V _ QD ' is provided for starting the switch U21; the output START _ P 'and START _ N' signal states of the FPGA chip are controlled by the CPU, when the CPU outputs the START _ P signal as high level and the START _ N signal as low level, the FPGA chip is controlled by the coded message to output the START _ P 'signal as high level and the START _ N' signal as low level. The output pin of the CPU processor outputs a second control signal group, which includes START _ P and START _ N signals, the state of which controls the START signal +5V _ QD of the START switch U21. When the START _ P signal is at a high level and the START _ N signal is at a low level, the transistor Q18 is turned on, the transistor Q18 serves as a third switch, the G pin signal of the START switch U21 is changed to a low level, the START switch U21 is closed, the high level at the pin S end is output from the pin D end, the actuation voltage of the START relay QD is satisfied, and the outlet node is closed. Table 4 shows the action relationship between the START _ P signal, the START _ N signal, the state START _ P 'signal, the START _ N' signal, and the START relay QD.

TABLE 4 START _ P, START _ N, START _ P ', START _ N' signal vs. START Relay QD action relationship

When the CPU processor works normally, the high-low level inversion of the START _ P signal and the START _ N signal is controlled, meanwhile, the FPGA chip is controlled through the coded message to output the high-low level inversion of the START _ P 'signal and the START _ N' signal, and the action and the return of the starting relay QD are controlled. When the CPU processor is abnormal; for example, program confusion, register fault, etc., cause a differential signal START _ P, START _ N, and the FPGA chip outputs START _ P 'and START _ N' have only 6.25% of the probability of causing a malfunction to open the START relay QD.

According to another group of embodiments of the present invention, a starting relay opening control device is provided, which is configured as shown in fig. 6, and comprises a control module, a signal transmission module and a starting relay.

And the control module outputs a first control signal group and a second control signal group, wherein the second control signal group is related to the first control signal group. The control module may be implemented together with the FPGA chip by the CPU processor according to the technical solutions provided in the first to third embodiments of the present invention, or implemented by only the CPU processor. The first control signal group and the second control signal group may each include two differential signals. The second control signal group is associated with the first control signal group and includes both the first and second control signal groups being active.

And the signal transmission module outputs a starting signal to the starting relay when the first control signal group and the second control signal group are both effective, and the starting relay acts. The signal transmission module comprises a starting switch, and when the first control signal group and the second control signal group are both effective, starting signals are output through the starting switch. The signal transmission module further comprises a first switch, a second switch and a third switch, and when the first control signal group is effective, the first switch and the second switch provide starting power for the starting switch. And when the second control signal group is effective, providing an enabling signal for the starting switch through the third switch. The first switch may be implemented by the transistor Q1 or Q18 in the first to third embodiments, the second switch may be implemented by the switch U20 in the first to third embodiments, the third switch may be implemented by the transistor Q18 or Q1 in the first to third embodiments, and the start switch may be implemented by the switch U21 in the first to third embodiments. The specific working modes of the modules can refer to the technical solutions of the first to third embodiments.

In summary, the invention relates to a start relay opening control method and a start relay opening control device, and the double design that a controller generates two control signal sets to be connected in series to open a start relay is adopted, so that the start relay can act and be closed only when the two control signal sets are effective simultaneously, the false operation probability of the start relay is greatly reduced, the outlet safety of a relay protection control device operated by an independent CPU is improved, the problem of device false outlet caused by the operation error of the independent CPU is effectively avoided, and the stable operation performance of a power system is improved.

It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.