阅读说明：本技术 一种斜坡产生电路及控制方法 (Slope generation circuit and control method ) 是由 边疆 黄鑫 张适 谢瑞 于 2021-01-12 设计创作，主要内容包括：本发明提供了一种斜坡产生电路及控制方法,SW开关结点的电压信号是输入电压经过开关以固定占空比斩波后所形成的与输入和输出电压都相关的信号,利用该电压信号,将其经过低通滤波电路后滤除高频成分,降压即得到与输出电压成正比的一个电压值,将此电压值经过运放转换为电流,以与开关信号同步的脉冲开关信号控制电容充放电,所产生的斜坡电流镜像出去即得到一个自适应的斜坡电压。本发明能很好的适应宽输入电压范围、多输出版本的情况,使DC-DC产品的使用更具有灵活性；得到的斜坡补偿电压更具有跟随特性。同时采用PMOS输入差分对,适应更宽的输入共模电平范围。(The invention provides a ramp generating circuit and a control method, wherein a voltage signal of a SW switch node is a signal which is formed by chopping an input voltage with a fixed duty ratio through a switch and is related to both input and output voltages, the voltage signal is utilized, a low-pass filter circuit is used for filtering high-frequency components, voltage reduction is carried out to obtain a voltage value which is in direct proportion to the output voltage, the voltage value is converted into current through an operational amplifier, a pulse switch signal synchronous with a switch signal is used for controlling charging and discharging of a capacitor, and the generated ramp current is mirrored to obtain a self-adaptive ramp voltage. The invention can well adapt to the conditions of wide input voltage range and multiple output versions, so that the use of the DC-DC product is more flexible; the obtained slope compensation voltage has more following characteristics. Meanwhile, a PMOS input differential pair is adopted, so that the wide input common mode level range is adapted.)

1. A ramp generation circuit comprises P-channel enhancement type MOS transistors PM1-PM8, N-channel enhancement type MOS transistors NM1-NM8, capacitors C1-C3, resistors R1-R6, a current source IDC1, a VDD input port, a SW input port and a GND port, and is characterized in that:

the VDD port is connected with an external power supply; the SW port is connected with a switch node connected with an inductor; the VPULSE port is connected with a switching MOS tube related to a clock to generate a pulse signal of a ramp voltage; the ISLOPE port is connected with a current mirror for outputting a ramp current, and a ramp voltage is generated on a resistor; the GND port is connected with the ground potential;

the source of the P-channel enhancement type MOS transistor PM1 is connected with the sources of current sources IDC1 and PM2, the grid of the P-channel enhancement type MOS transistor PM1 is connected with one end of a resistor R4 and the upper electrode plate of a capacitor C2, and the drain of the P-channel enhancement type MOS transistor PM1 is connected with the drain and the grid of NM1 and the grid of NM 4; the source of the P-channel enhancement type MOS transistor PM2 is connected with the sources of current sources IDC1 and PM1, the gate of the P-channel enhancement type MOS transistor PM2 is connected with one end of a resistor R5 and the source of NM5, and the drain of the P-channel enhancement type MOS transistor NM2 is connected with the drain of the resistor R2 and the gate of the resistor NM 3; the main functions of the PM1 and the PM2 are input differential pairs of voltage-current conversion; the source electrode of the P-channel enhancement type MOS transistor PM3 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM3 is connected with the drain electrode of the P-channel enhancement type MOS transistor PM4, and the drain electrode of the P-channel enhancement type MOS transistor PM3 is connected with the drain electrode of NM 3; the source electrode of the P-channel enhancement type MOS transistor PM4 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM4 is connected with the grid electrode of PM3, and the drain electrode of the P-channel enhancement type MOS transistor PM4 is connected with the drain electrode of NM4 and the grid electrode of NM 5; the source electrode of the P-channel enhancement type MOS transistor PM5 is connected with VDD, and the grid electrode of the P-channel enhancement type MOS transistor PM5 is connected with the drain electrode, the drain electrode of NM5 and the grid electrode of PM 6; the source electrode of the P-channel enhancement type MOS transistor PM6 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM6 is connected with the grid electrode of PM5, and the drain electrode of the P-channel enhancement type MOS transistor NM6 is connected with the drain electrode and the grid electrode of NM 8; the source electrode of the P-channel enhancement type MOS transistor PM7 is connected with VDD, and the grid electrode of the P-channel enhancement type MOS transistor PM7 is connected with the drain electrode, the drain electrode of NM8 and the grid electrode of PM 8; the source electrode of the P-channel enhancement type MOS transistor PM8 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM8 is connected with the grid electrode and the drain electrode of PM7 and the drain electrode of NM8, and the drain electrode of the P-channel enhancement type MOS transistor PM8 is connected with an ISLOPE port; the PM3-PM8 are current mirrors;

the drain electrode of the N-channel enhancement type MOS transistor NM1 is connected with the gate electrode, the drain electrode of the PM1 and the gate electrode of the NM4, and the source electrode of the NM1 is connected with GND; the drain electrode of the N-channel enhancement type MOS transistor NM2 is connected with the grid electrode, the grid electrode of NM3 and the drain electrode of PM2, and the source electrode of the N-channel enhancement type MOS transistor NM2 is connected with GND; the gate of the N-channel enhancement type MOS transistor NM3 is connected with the gate and the drain of NM2 and the drain of PM2, the drain is connected with the drain and the gate of PM3 and the gate of PM4, and the source is connected with GND; the grid electrode of the N-channel enhancement type MOS transistor NM4 is connected with the grid electrode of NM1, the drain electrode of the N-channel enhancement type MOS transistor NM4 is connected with the drain electrode of PM4 and the grid electrode of NM5, and the source electrode of the N-channel enhancement type MOS transistor NM4 is connected with GND; the drain electrode of the N-channel enhancement type MOS transistor NM5 is connected with the drain electrode and the gate electrode of the PM5 and the gate electrode of the PM6, and the source electrode of the N-channel enhancement type MOS transistor NM5 is connected with the gate electrode of the PM2 at one end of the resistor R5; the N-channel enhanced MOS tube NM1-NM4 is mainly used as a current mirror load of an amplifier, and the N-channel enhanced MOS tube NM5 is mainly used as an output buffer stage of a transconductance operational amplifier; the drain electrode of the N-channel enhancement type MOS transistor NM6 is connected with the gate electrode, the drain electrode of the PM6 and the gate electrode of the NM8, and the source electrode of the N-channel enhancement type MOS transistor NM6 is connected with the drain electrode of the NM7 and the upper electrode plate of the capacitor C3; the grid electrode of the N-channel enhancement type MOS transistor NM7 is connected with a VPULSE port, and the source electrode of the N-channel enhancement type MOS transistor NM7 is connected with a GND port; the grid electrode of the N-channel enhancement type MOS transistor NM8 is connected with the grid electrode and the drain electrode of NM6 and the drain electrode of PM6, the drain electrode is connected with the grid electrode and the drain electrode of PM7 and the grid electrode of PM8, and the source electrode is connected with one end of a resistor R6; the N-channel enhancement type MOS tube NM6-NM8 mainly functions to generate a ramp voltage through a switching signal pulse;

the upper polar plate of the capacitor C1 is connected with one end of R3 and R4, and the lower polar plate is connected with GND; the upper polar plate of the capacitor C2 is connected with one end of the R4 and the PM1 grid, and the lower polar plate is connected with GND;

one end of the resistor R1 is connected with the SW port, and the other end of the resistor R1 is respectively connected with one ends of the resistors R3 and R2; one end of the resistor R2 is connected with the other end of the resistor R1, and the other end of the resistor R2 is connected with GND; the resistors R1 and R2 mainly function to step down a relatively high output voltage into a common mode input range of the PMOS differential pair; the resistors R3 and R4 and the capacitor form a low-pass filter; one end of the resistor R5 is connected with the source of NM5 and the grid of PM2, and the other end is connected with GND, so that the voltage quantity related to the output voltage is converted into current; one end of the resistor R6 is connected with the source of NM8, and the other end is connected with GND, and the resistor R6 is mainly used for linearizing the voltage-current relationship of NM8 and obtaining a ramp current.

2. A ramp generating circuit and control method using the circuit of claim 1, comprising the steps of:

the voltage signal of the SW switch node is a signal which is formed by chopping an input voltage with a fixed duty ratio through a switch and is related to both the input voltage and the output voltage, the voltage signal is utilized, a low-pass filter circuit is utilized to filter high-frequency components, voltage reduction is carried out to obtain a voltage value which is in direct proportion to the output voltage, the voltage value is converted into current through operational amplification, a pulse switch signal synchronous with a switch signal is used for controlling charging and discharging of a capacitor, and the generated ramp current is mirrored to obtain a self-adaptive ramp voltage.

Technical Field

The invention relates to the technical field of circuits, in particular to a self-adaptive ramp generating circuit in a peak current control mode.

Background

With the development of social productivity, a large number of power management chips are needed in various electronic devices and industrial products to reduce energy dissipation, peak current mode control widely used in DC-DC products is characterized in that the control mode is a compensation ramp voltage generated by sampling an inductive current, and most of ramp compensation circuits in products in the market have the defects that the compensation ramp value is fixed and cannot flexibly change along with the output voltage and the duty ratio of a converter, so that the designed ramp circuit is overcompensated or undercompensated, the waveform of the output inductive current is unstable, the output voltage is unstable, and the good power supply requirements of application equipment cannot be met.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a ramp generating circuit and a control method, and provides a wide-input-swing self-adaptive ramp generating circuit after the general idea of designing a ramp circuit is used.

The technical scheme adopted by the invention for solving the technical problems is as follows:

a ramp generating circuit, as shown in fig. 1: the device comprises P-channel enhanced MOS transistors PM1-PM8, N-channel enhanced MOS transistors NM1-NM8, capacitors C1-C3, resistors R1-R6, a current source IDC1, a VDD input port, a SW input port and a GND port;

the VDD port is connected with an external power supply; the SW port is connected with a switch node connected with an inductor; the VPULSE port is connected with a switching MOS tube related to a clock to generate a pulse signal of a ramp voltage; the ISLOPE port is connected with a current mirror for outputting a ramp current, and a ramp voltage is generated on a resistor; the GND port is connected to ground potential.

The source of the P-channel enhancement type MOS transistor PM1 is connected with the sources of current sources IDC1 and PM2, the grid of the P-channel enhancement type MOS transistor PM1 is connected with one end of a resistor R4 and the upper electrode plate of a capacitor C2, and the drain of the P-channel enhancement type MOS transistor PM1 is connected with the drain and the grid of NM1 and the grid of NM 4; the source of the P-channel enhancement type MOS transistor PM2 is connected with the sources of current sources IDC1 and PM1, the gate of the P-channel enhancement type MOS transistor PM2 is connected with one end of a resistor R5 and the source of NM5, and the drain of the P-channel enhancement type MOS transistor NM2 is connected with the drain of the resistor R2 and the gate of the resistor NM 3; the primary role of the PM1 and PM2 is as an input differential pair for voltage-to-current conversion. The source electrode of the P-channel enhancement type MOS transistor PM3 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM3 is connected with the drain electrode of the P-channel enhancement type MOS transistor PM4, and the drain electrode of the P-channel enhancement type MOS transistor PM3 is connected with the drain electrode of NM 3; the source electrode of the P-channel enhancement type MOS transistor PM4 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM4 is connected with the grid electrode of PM3, and the drain electrode of the P-channel enhancement type MOS transistor PM4 is connected with the drain electrode of NM4 and the grid electrode of NM 5; the source electrode of the P-channel enhancement type MOS transistor PM5 is connected with VDD, and the grid electrode of the P-channel enhancement type MOS transistor PM5 is connected with the drain electrode, the drain electrode of NM5 and the grid electrode of PM 6; the source electrode of the P-channel enhancement type MOS transistor PM6 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM6 is connected with the grid electrode of PM5, and the drain electrode of the P-channel enhancement type MOS transistor NM6 is connected with the drain electrode and the grid electrode of NM 8; the source electrode of the P-channel enhancement type MOS transistor PM7 is connected with VDD, and the grid electrode of the P-channel enhancement type MOS transistor PM7 is connected with the drain electrode, the drain electrode of NM8 and the grid electrode of PM 8; the source electrode of the P-channel enhancement type MOS transistor PM8 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM8 is connected with the grid electrode and the drain electrode of PM7 and the drain electrode of NM8, and the drain electrode of the P-channel enhancement type MOS transistor PM8 is connected with an ISLOPE port. The primary role of the PM3-PM8 is as a current mirror.

The drain electrode of the N-channel enhancement type MOS transistor NM1 is connected with the gate electrode, the drain electrode of the PM1 and the gate electrode of the NM4, and the source electrode of the NM1 is connected with GND; the drain electrode of the N-channel enhancement type MOS transistor NM2 is connected with the grid electrode, the grid electrode of NM3 and the drain electrode of PM2, and the source electrode of the N-channel enhancement type MOS transistor NM2 is connected with GND; the gate of the N-channel enhancement type MOS transistor NM3 is connected with the gate and the drain of NM2 and the drain of PM2, the drain is connected with the drain and the gate of PM3 and the gate of PM4, and the source is connected with GND; the grid electrode of the N-channel enhancement type MOS transistor NM4 is connected with the grid electrode of NM1, the drain electrode of the N-channel enhancement type MOS transistor NM4 is connected with the drain electrode of PM4 and the grid electrode of NM5, and the source electrode of the N-channel enhancement type MOS transistor NM4 is connected with GND; the drain electrode of the N-channel enhancement type MOS transistor NM5 is connected with the drain electrode and the gate electrode of the PM5 and the gate electrode of the PM6, and the source electrode of the N-channel enhancement type MOS transistor NM5 is connected with the gate electrode of the PM2 at one end of the resistor R5; the N-channel enhancement type MOS tube NM1-NM4 mainly acts as a current mirror load of the amplifier, and the N-channel enhancement type MOS tube NM5 mainly acts as an output buffer stage of the transconductance operational amplifier. The drain electrode of the N-channel enhancement type MOS transistor NM6 is connected with the gate electrode, the drain electrode of the PM6 and the gate electrode of the NM8, and the source electrode of the N-channel enhancement type MOS transistor NM6 is connected with the drain electrode of the NM7 and the upper electrode plate of the capacitor C3; the grid electrode of the N-channel enhancement type MOS transistor NM7 is connected with a VPULSE port, and the source electrode of the N-channel enhancement type MOS transistor NM7 is connected with a GND port; the gate of the N-channel enhancement type MOS transistor NM8 is connected with the gate and the drain of NM6 and the drain of PM6, the drain is connected with the gate and the drain of PM7 and the gate of PM8, and the source is connected with one end of a resistor R6. The main function of the N-channel enhancement type MOS transistor NM6-NM8 is to generate a ramp voltage through a switching signal pulse.

The upper polar plate of the capacitor C1 is connected with one end of R3 and R4, and the lower polar plate is connected with GND; the upper plate of the capacitor C2 is connected with one end of the R4 and the PM1 grid, and the lower plate is connected with GND. The capacitors C1 and C2 mainly function to filter out high-frequency components.

One end of the resistor R1 is connected with the SW port, and the other end of the resistor R1 is respectively connected with one ends of the resistors R3 and R2; one end of the resistor R2 is connected with the other end of the resistor R1, and the other end is connected with GND. The main function of the resistors R1, R2 is to step down the relatively high output voltage into the common mode input range of the PMOS differential pair. The resistors R3 and R4 mainly function as low-pass filters together with capacitors. One end of the resistor R5 is connected to the source of NM5 and the gate of PM2, and the other end is connected to GND, and mainly functions to convert a voltage amount related to an output voltage into a current. One end of the resistor R6 is connected with the source of NM8, and the other end is connected with GND, and the resistor R6 is mainly used for linearizing the voltage-current relationship of NM8 and obtaining a ramp current.

The invention also provides a control method related to the ramp generating circuit, which comprises the following specific steps:

the voltage signal of the SW switch node is a signal which is formed by chopping an input voltage with a fixed duty ratio through a switch and is related to both the input voltage and the output voltage, the voltage signal is utilized, a low-pass filter circuit is utilized to filter high-frequency components, voltage reduction is carried out to obtain a voltage value which is in direct proportion to the output voltage, the voltage value is converted into current through operational amplification, a pulse switch signal synchronous with a switch signal is used for controlling charging and discharging of a capacitor, and the generated ramp current is mirrored to obtain a self-adaptive ramp voltage.

The invention has the beneficial effects that:

1. the ramp voltage generated by the ramp compensation circuit is positively correlated with the output voltage, so that the condition of wide input voltage range and multiple output versions can be well adapted, and the use of a DC-DC product is more flexible.

2. The 2-stage transconductance operational amplifier and the output stage are used for converting the voltage into the current, the 2-stage transconductance operational amplifier is used for enabling the conversion precision to be higher, and the obtained slope compensation voltage has the following characteristic. Meanwhile, a PMOS input differential pair is adopted, so that the wide input common mode level range is adapted.

Drawings

Fig. 1 is a schematic diagram of an adaptive ramp generation circuit in a peak current control mode according to the present invention.

Detailed Description

The invention is further illustrated with reference to the following figures and examples.

The present invention is described in further detail below with reference to fig. 1. As shown in FIG. 1, the adaptive ramp generation circuit in the peak current control mode comprises P-channel enhancement type MOS transistors PM1-PM8, N-channel enhancement type MOS transistors NM1-NM8, capacitors C1-C3, resistors R1-R6, a current source IDC1, a VDD input port, a SW input port and a GND port. The VDD port is connected with an external power supply; the SW port is connected with a switch node connected with an inductor; the VPULSE port is connected with a switching MOS tube related to a clock to generate a pulse signal of a ramp voltage; the ISLOPE port is connected with a current mirror for outputting a ramp current, and a ramp voltage is generated on a resistor; the GND port is connected to ground potential.

The source of the P-channel enhancement type MOS transistor PM1 is connected with the sources of current sources IDC1 and PM2, the grid of the P-channel enhancement type MOS transistor PM1 is connected with one end of a resistor R4 and the upper electrode plate of a capacitor C2, and the drain of the P-channel enhancement type MOS transistor PM1 is connected with the drain and the grid of NM1 and the grid of NM 4; the source of the P-channel enhancement type MOS transistor PM2 is connected with the sources of current sources IDC1 and PM1, the gate of the P-channel enhancement type MOS transistor PM2 is connected with one end of a resistor R5 and the source of NM5, and the drain of the P-channel enhancement type MOS transistor NM2 is connected with the drain of the resistor R2 and the gate of the resistor NM 3; the primary role of the PM1 and PM2 is as an input differential pair for voltage-to-current conversion. The source electrode of the P-channel enhancement type MOS transistor PM3 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM3 is connected with the drain electrode of the P-channel enhancement type MOS transistor PM4, and the drain electrode of the P-channel enhancement type MOS transistor PM3 is connected with the drain electrode of NM 3; the source electrode of the P-channel enhancement type MOS transistor PM4 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM4 is connected with the grid electrode of PM3, and the drain electrode of the P-channel enhancement type MOS transistor PM4 is connected with the drain electrode of NM4 and the grid electrode of NM 5; the source electrode of the P-channel enhancement type MOS transistor PM5 is connected with VDD, and the grid electrode of the P-channel enhancement type MOS transistor PM5 is connected with the drain electrode, the drain electrode of NM5 and the grid electrode of PM 6; the source electrode of the P-channel enhancement type MOS transistor PM6 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM6 is connected with the grid electrode of PM5, and the drain electrode of the P-channel enhancement type MOS transistor NM6 is connected with the drain electrode and the grid electrode of NM 8; the source electrode of the P-channel enhancement type MOS transistor PM7 is connected with VDD, and the grid electrode of the P-channel enhancement type MOS transistor PM7 is connected with the drain electrode, the drain electrode of NM8 and the grid electrode of PM 8; the source electrode of the P-channel enhancement type MOS transistor PM8 is connected with VDD, the grid electrode of the P-channel enhancement type MOS transistor PM8 is connected with the grid electrode and the drain electrode of PM7 and the drain electrode of NM8, and the drain electrode of the P-channel enhancement type MOS transistor PM8 is connected with an ISLOPE port. The primary role of the PM3-PM8 is as a current mirror.

The drain electrode of the N-channel enhancement type MOS transistor NM1 is connected with the gate electrode, the drain electrode of the PM1 and the gate electrode of the NM4, and the source electrode of the NM1 is connected with GND; the drain electrode of the N-channel enhancement type MOS transistor NM2 is connected with the grid electrode, the grid electrode of NM3 and the drain electrode of PM2, and the source electrode of the N-channel enhancement type MOS transistor NM2 is connected with GND; the gate of the N-channel enhancement type MOS transistor NM3 is connected with the gate and the drain of NM2 and the drain of PM2, the drain is connected with the drain and the gate of PM3 and the gate of PM4, and the source is connected with GND; the grid electrode of the N-channel enhancement type MOS transistor NM4 is connected with the grid electrode of NM1, the drain electrode of the N-channel enhancement type MOS transistor NM4 is connected with the drain electrode of PM4 and the grid electrode of NM5, and the source electrode of the N-channel enhancement type MOS transistor NM4 is connected with GND; the drain electrode of the N-channel enhancement type MOS transistor NM5 is connected with the drain electrode and the gate electrode of the PM5 and the gate electrode of the PM6, and the source electrode of the N-channel enhancement type MOS transistor NM5 is connected with the gate electrode of the PM2 at one end of the resistor R5; the N-channel enhancement type MOS tube NM1-NM4 mainly acts as a current mirror load of the amplifier, and the N-channel enhancement type MOS tube NM5 mainly acts as an output buffer stage of the transconductance operational amplifier. The drain electrode of the N-channel enhancement type MOS transistor NM6 is connected with the gate electrode, the drain electrode of the PM6 and the gate electrode of the NM8, and the source electrode of the N-channel enhancement type MOS transistor NM6 is connected with the drain electrode of the NM7 and the upper electrode plate of the capacitor C3; the grid electrode of the N-channel enhancement type MOS transistor NM7 is connected with a VPULSE port, and the source electrode of the N-channel enhancement type MOS transistor NM7 is connected with a GND port; the gate of the N-channel enhancement type MOS transistor NM8 is connected with the gate and the drain of NM6 and the drain of PM6, the drain is connected with the gate and the drain of PM7 and the gate of PM8, and the source is connected with one end of a resistor R6. The main function of the N-channel enhancement type MOS transistor NM6-NM8 is to generate a ramp voltage through a switching signal pulse.

The upper polar plate of the capacitor C1 is connected with one end of R3 and R4, and the lower polar plate is connected with GND; the upper plate of the capacitor C2 is connected with one end of the R4 and the PM1 grid, and the lower plate is connected with GND. The capacitors C1 and C2 mainly function to filter out high-frequency components.

One end of the resistor R1 is connected with the SW port, and the other end of the resistor R1 is connected with one ends of the resistors R3 and R2; one end of the resistor R2 is connected with the other end of the resistor R1, and the other end is connected with GND. The main function of the resistors R1, R2 is to step down the relatively high output voltage into the common mode input range of the PMOS differential pair. The resistors R3 and R4 mainly function as low-pass filters together with capacitors. One end of the resistor R5 is connected to the source of NM5 and the gate of PM2, and the other end is connected to GND, and mainly functions to convert a voltage amount related to an output voltage into a current. One end of the resistor R6 is connected with the source of NM8, and the other end is connected with GND, and the resistor R6 is mainly used for linearizing the voltage-current relationship of NM8 and obtaining a ramp current.

As shown in fig. 1, the working principle of the whole circuit is as follows: the voltage signal of the SW switch node is a signal which is formed by chopping an input voltage with a certain duty ratio through a switch and is related to both input voltage and output voltage, the signal is utilized, a high-frequency component is filtered after the signal passes through a low-pass filter circuit, a voltage value which is in direct proportion to the output voltage is obtained by reducing the voltage, the voltage value is converted into current through operational amplification, the charge and discharge of a capacitor are controlled by a pulse switch signal synchronous with a switch signal, and the generated ramp current is mirrored to obtain a self-adaptive ramp voltage.

In summary, the present invention provides an adaptive ramp generating circuit under a peak current control mode, and after a general idea of designing a ramp circuit is used, the adaptive ramp generating circuit with a wide input swing is provided.

In the light of the above description, with reference to the accompanying drawings, embodiments of the method according to the invention have been explained, but the method according to the invention is not limited to the details of the embodiments described, and within the scope of a certain technical idea, many simple variants thereof are possible, all falling within the scope of the method according to the invention.