阅读说明：本技术 多台共母线三相逆变器输出并联带异步电机变频调速装置 (Frequency conversion speed regulation device with asynchronous motor and multiple common bus three-phase inverters connected in parallel ) 是由 金浩 潘冬华 李武杰 姚川 于 2021-05-12 设计创作，主要内容包括：本发明提供了多台共母线三相逆变器输出并联带异步电机变频调速装置,包括：直流电源、多台三相逆变器、异步电机、电机负载和LC滤波电路；多台逆变器的直流输入正极接直流电源正极,直流输入负极接直流电源负极；每台三相逆变器输出都接LC滤波电路的输入端,LC滤波电路的输出A、B、C相分别接一起并分别与电机U、V、W相电性连接；异步电机通过联轴器与电机负载连接；每台三相逆变器采用独立的芯片DSP控制；三相逆变器之间还采用硬件同步电路进行输出调制波同步,采用CAN通讯和硬件同步电路共同实现EPWM载波同步；本发明在减小逆变器重量和体积的同时,减小了噪声,还增加了系统可靠性,具备冗余切换的能力,易于维护。(The invention provides a variable frequency speed regulation device with asynchronous motors connected in parallel by a plurality of common bus three-phase inverters, which comprises: the system comprises a direct-current power supply, a plurality of three-phase inverters, an asynchronous motor, a motor load and an LC filter circuit; the direct current input positive electrodes of the inverters are connected with the direct current power supply positive electrode, and the direct current input negative electrodes are connected with the direct current power supply negative electrode; the output of each three-phase inverter is connected with the input end of an LC filter circuit, and the A, B, C phases of the output of the LC filter circuit are respectively connected together and are respectively electrically connected with the motor U, V, W phase; the asynchronous motor is connected with a motor load through a coupler; each three-phase inverter is controlled by an independent chip DSP; a hardware synchronization circuit is adopted among the three-phase inverters to synchronize output modulation waves, and CAN communication and the hardware synchronization circuit are adopted to realize EPWM carrier synchronization together; the invention reduces the weight and the volume of the inverter, reduces the noise, increases the reliability of the system, has the capability of redundant switching and is easy to maintain.)

1. Many total generatrix three-phase inverters output parallelly connected and take asynchronous machine variable frequency speed adjusting device, including DC power supply, three-phase inverter, asynchronous machine and motor load, its characterized in that: further comprising: an LC filter circuit; the LC filter circuit comprises a filter inductor L and a filter capacitor C;

the direct current input positive electrodes of the inverters are connected with the direct current power supply positive electrode, and the direct current input negative electrodes of the inverters are connected with the direct current power supply negative electrode; the output of each three-phase inverter is connected with the input end of an LC filter circuit, the output A of the LC filter circuit is connected with the U phase of the motor, the output B is connected with the V phase of the motor, and the output C is connected with the W phase of the motor; the asynchronous motor is connected with a motor load through a coupler; each three-phase inverter is controlled by an independent chip DSP.

2. The multi-bus three-phase inverter output parallel connection asynchronous motor variable frequency speed regulation device of claim 1, characterized in that: and a hardware synchronization circuit is adopted between each three-phase inverter to synchronize output modulation waves, and CAN communication and the hardware synchronization circuit are adopted to realize EPWM carrier synchronization together.

3. The multi-bus three-phase inverter output parallel connection asynchronous motor variable frequency speed regulation device of claim 2, characterized in that: CAN communication is divided into two paths, namely CAN A and CAN B; the CAN A and the hardware synchronization circuit are used for realizing EPWM carrier signal synchronization between the chip DSPs; and the CAN B receives a motor speed regulation instruction sent by the upper computer or other display screens and responds to the speed regulation instruction in real time.

4. The multi-bus three-phase inverter output parallel connection asynchronous motor variable frequency speed regulation device of claim 3, characterized in that: the CAN A adopts an independent communication link; the CAN B adopts another independent communication link; the hardware synchronization circuit employs a single communication link.

5. The multi-bus three-phase inverter output parallel connection asynchronous motor variable frequency speed regulation device of claim 2, characterized in that: the hardware synchronization circuit comprises a first optical coupler chip, a second optical coupler chip and resistors R1-R7; the ANODE end of the first optical coupler chip is electrically connected with one end of the resistor R1; the other end of the resistor R1 is connected with a power supply; a CATH end of the first optical coupler chip receives a PWM signal; the VB end and the VO end of the first optical coupler chip are electrically connected and are commonly connected to one end of a resistor R2; the other end of the resistor R2 is electrically connected with one end of the resistor R3 and the base of a triode; the other end of the resistor R3 is grounded; the collector of the triode is electrically connected with one end of the resistor R4; the other end of the resistor R4 is connected with a power supply and is also electrically connected with one end of the resistor R5; the emitter of the triode is grounded; the other end of the resistor R5 is electrically connected with the ANODE end of the second optocoupler chip; the CATH end of the second optical coupling chip is used as a SYN port of a synchronous signal; the VB end and the VO end of the second optical coupler chip are electrically connected and are commonly connected to one end of a resistor R6; the other end of the resistor R6 is electrically connected with one end of the resistor R7 and the ECAP port of the chip DSP; the other end of the resistor R7 is connected to ground.

Technical Field

The invention relates to the field of motor control, in particular to a variable-frequency speed regulation device for an asynchronous motor with multiple common-bus three-phase inverters connected in parallel.

Background

The traditional three-phase inverter with a motor usually adopts a single inverter, and the whole motor system is broken down under the condition that the inverter fails and cannot be used. Under such circumstances, it is important to control the motor by using a plurality of common-bus three-phase inverters.

Then, a plurality of common-bus three-phase inverters have the problems that the amplitude, the frequency and the phase of the output voltage of each inverter are required to be equal or synchronous, high-frequency circulation is required to be restrained, and carrier waves and modulation waves are required to be synchronous.

Disclosure of Invention

In view of the above technical defects, the invention provides a variable-frequency speed regulation device for an asynchronous motor with multiple common-bus three-phase inverters connected in parallel. The device adopts a plurality of modularized three-phase inverters to input common direct current bus output three-phase to be connected in parallel to realize frequency modulation and speed regulation on an asynchronous motor, each three-phase inverter adopts an independent controller, and each three-phase inverter can be used in a single machine or in parallel.

The invention provides a variable frequency speed regulation device with asynchronous motors connected in parallel by a plurality of common bus three-phase inverters, which comprises: the system comprises a direct-current power supply, a three-phase inverter, an asynchronous motor, a motor load and an LC filter circuit; the LC filter circuit comprises a filter inductor L and a filter capacitor C;

the direct current input positive electrodes of the inverters are connected with the direct current power supply positive electrode, and the direct current input negative electrodes of the inverters are connected with the direct current power supply negative electrode; the output of each three-phase inverter is connected with the input end of an LC filter circuit, the output A of the LC filter circuit is connected with the U phase of the motor, the output B is connected with the V phase of the motor, and the output C is connected with the W phase of the motor; each three-phase inverter is connected with the motor load through a coupler and is controlled by an independent chip DSP.

Furthermore, a hardware synchronization circuit is adopted between each three-phase inverter to synchronize output modulation waves, and CAN communication and the hardware synchronization circuit are adopted to realize EPWM carrier synchronization together.

Further, CAN communication is divided into two paths, namely CAN A and CAN B; the CAN A and the hardware synchronization circuit are used for realizing EPWM carrier signal synchronization between the chip DSPs; and the CAN B receives a motor speed regulation instruction sent by the upper computer or other display screens and responds to the speed regulation instruction in real time.

Further, the CAN A adopts a single communication link; the CAN B adopts another independent communication link; the hardware synchronization circuit employs a single communication link.

The hardware synchronization circuit comprises a first optical coupler chip, a second optical coupler chip and resistors R1-R7; the ANODE end of the first optical coupler chip is electrically connected with one end of the resistor R1; the other end of the resistor R1 is connected with a power supply; a CATH end of the first optical coupler chip receives a PWM signal; the VB end and the VO end of the first optical coupler chip are electrically connected and are commonly connected to one end of a resistor R2; the other end of the resistor R2 is electrically connected with one end of the resistor R3 and the base of a triode; the other end of the resistor R3 is grounded; the collector of the triode is electrically connected with one end of the resistor R4; the other end of the resistor R4 is connected with a power supply and is also electrically connected with one end of the resistor R5; the emitter of the triode is grounded; the other end of the resistor R5 is electrically connected with the ANODE end of the second optocoupler chip; the CATH end of the second optical coupling chip is used as a SYN port of a synchronous signal; the VB end and the VO end of the second optical coupler chip are electrically connected and are commonly connected to one end of a resistor R6; the other end of the resistor R6 is electrically connected with one end of the resistor R7 and the ECAP port of the chip DSP; the other end of the resistor R7 is connected to ground.

The invention has the beneficial effects that: the inverter has the advantages of reducing noise, increasing system reliability, having redundant switching capability and being good in maintenance while reducing the weight and the volume of the inverter. The problems of large noise, large volume, heavy weight and the like when a single three-phase inverter is provided with a high-power asynchronous motor are solved.

Drawings

FIG. 1 is a block diagram of the apparatus of the present invention;

FIG. 2 is a schematic diagram of signal connections between corresponding controllers of a three-phase inverter;

FIG. 3 is a schematic diagram of a hardware synchronization circuit;

fig. 4 is a schematic diagram of a PWM wave (square wave) generated by the phase of the output modulation wave of the inverter module 1 (set as the main module) leading the output phase PWM wave (square wave) of the inverter module 2;

fig. 5 is a schematic diagram of a PWM wave (square wave) generated by lagging the output modulation wave phase of the inverter module 1 (set as the main module) by the output phase PWM wave (square wave) of the inverter module 2;

FIG. 6 is an EPWM carrier synchronization flow diagram;

FIG. 7 is a schematic view of a motor speed curve in an embodiment of the present invention;

FIG. 8 is a three-phase current graph of a motor, in which A, B, C phase current curves are sequentially arranged from top to bottom in the first quarter period;

FIG. 9 is a schematic diagram of a synchronization signal SYN square wave;

FIG. 10 is a schematic illustration of the main machine phase voltages;

FIG. 11 is a schematic representation of slave phase voltages;

FIG. 12 is a schematic diagram of the active power of the device;

fig. 13 is a schematic diagram of the reactive power of the device.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be further described with reference to the accompanying drawings.

Referring to fig. 1, the multiple common-bus three-phase inverters output the variable-frequency speed control device with the asynchronous motor in parallel, which includes the following: the system comprises a direct-current power supply, a three-phase inverter, an asynchronous motor, a motor load and an LC filter circuit; the LC filter circuit comprises a filter inductor L and a filter capacitor C;

the direct current input positive electrodes of the inverters are connected with the direct current power supply positive electrode, and the direct current input negative electrodes of the inverters are connected with the direct current power supply negative electrode; the output of each three-phase inverter is connected with the input end of an LC filter circuit, the output A of the LC filter circuit is connected with the U phase of the motor, the output B is connected with the V phase of the motor, and the output C is connected with the W phase of the motor; each three-phase inverter is connected with the motor load through a coupler and is controlled by an independent chip DSP. Each three-phase inverter can be used in a single machine or in parallel.

A plurality of three-phase inverters are connected in parallel, and the inverter modules are ensured to be connected in parallel and realize power uniform distribution.

And a hardware synchronization circuit is adopted between each three-phase inverter to synchronize output modulation waves, and CAN communication and the hardware synchronization circuit are adopted to realize EPWM carrier synchronization together.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating signal connections between controllers corresponding to three-phase inverters;

CAN communication is divided into two paths, namely CAN A and CAN B; the CAN A and the hardware synchronization circuit are used for realizing EPWM carrier signal synchronization between the chip DSPs; and the CAN B receives a motor speed regulation instruction sent by the upper computer or other display screens and responds to the speed regulation instruction in real time.

The CAN A adopts an independent communication link; the CAN B adopts another independent communication link; the hardware synchronization circuit employs a single communication link.

Referring to fig. 3, fig. 3 is a schematic diagram of a hardware synchronization circuit.

The hardware synchronization circuit comprises a first optical coupler chip, a second optical coupler chip and resistors R1-R7; the ANODE end of the first optical coupler chip is electrically connected with one end of the resistor R1; the other end of the resistor R1 is connected with a power supply; a CATH end of the first optical coupler chip receives a PWM signal; the VB end and the VO end of the first optical coupler chip are electrically connected and are commonly connected to one end of a resistor R2; the other end of the resistor R2 is electrically connected with one end of the resistor R3 and the base of a triode; the other end of the resistor R3 is grounded; the collector of the triode is electrically connected with one end of the resistor R4; the other end of the resistor R4 is connected with a power supply and is also electrically connected with one end of the resistor R5; the emitter of the triode is grounded; the other end of the resistor R5 is electrically connected with the ANODE end of the second optocoupler chip; the CATH end of the second optical coupling chip is used as a SYN port of a synchronous signal; the VB end and the VO end of the second optical coupler chip are electrically connected and are commonly connected to one end of a resistor R6; the other end of the resistor R6 is electrically connected with one end of the resistor R7 and the ECAP port of the chip DSP; the other end of the resistor R7 is connected to ground.

The principle of the hardware synchronization circuit is that the output modulation wave of each inverter module generates PWM wave, the PWM wave is isolated through an optical coupling chip, the PWM wave is output through the opening and leakage of a triode, the opening and leakage output SYN of the triode of each module is connected together to realize the function of line connection, signals of the line and the later signals are fed back to an ECAP port of a DSP through the optical coupling chip, the ECAP port can capture the frequency and the positive duty ratio of inflow signals at the moment, the phase advance or the phase lag can be known by comparing the difference value of the signal frequency and the positive duty ratio captured by the PWM output by the modulation wave and the ECAP port, and therefore the voltage phase can be adjusted by adjusting and compensating the output frequency.

The parallel connection synchronization principle of the multiple common-bus three-phase inverters is further explained for the circuit;

referring to fig. 4, fig. 4 is a schematic diagram of a PWM wave (square wave) generated by the phase of the output modulation wave of the inverter module 1 (set as the main module) leading the PWM wave (square wave) of the output phase of the inverter module 2;

when the PWM wave (square wave) generated by the output modulation wave phase of the inverter module 1 (set as the main module) leads the PWM wave (square wave) of the output phase of the inverter module 2, by capturing the synchronization signal SYN line of each inverter module and the feedback signal thereafter, an interrupt is generated at the falling edge of the synchronization signal captured by ECAP, a positive duty count length is read during the interrupt, if the positive duty length detected by the PWM wave generated by the inverter module 2 itself outputting the modulation wave during the interrupt is consistent with the positive duty count length captured by the synchronization feedback signal, it is indicated that the output voltage phase of the inverter module 2 lags behind or is equal to the output voltage phase of the inverter module 1 (main module), at this time, only the positive duty count length obtained by capturing the synchronization feedback signal needs to be subtracted from the positive duty count length of the inverter module 1 (main module), and the difference is multiplied by a scaling coefficient to forward compensate the frequency of the inverter module 2 itself, the frequency integration results in the phase of the output voltage, so that the phase lag of the inverter module 2 can be adjusted to zero by integrating the compensation frequency and superimposing the compensation frequency on the phase.

Referring to fig. 5, fig. 5 is a schematic diagram of the PWM wave (square wave) generated by the output modulation wave phase of the inverter module 1 (set as the main module) lagging behind the output phase PWM wave (square wave) of the inverter module 2;

when the PWM wave (square wave) generated by the output modulation wave phase of the inverter module 1 (set as the main module) lags behind the output phase PWM wave (square wave) of the inverter module 2, by capturing the synchronization signal SYN line of each inverter module and the feedback signal thereafter, an interrupt is generated at the falling edge of the synchronization signal captured by ECAP, a positive duty count length is read during the interrupt, if the positive duty length detected in the interrupt by the PWM wave generated by the inverter module 2 itself outputting the modulation wave is greater than the positive duty count length captured by the synchronization feedback signal, it is indicated that the output voltage phase of the inverter module 2 leads the output voltage phase of the inverter module 1 (main module), at this time, the positive duty count length obtained by capturing the synchronization feedback signal is subtracted from the positive duty count length of the inverter module 2, and the difference is multiplied by a scaling coefficient to compensate the frequency of the inverter module 2 itself in the reverse direction, the frequency integration obtains the phase of the output voltage, so that the phase advance of the inverter module 2 can be adjusted to zero through an integration link by integrating and superposing the reverse compensation frequency on the phase.

The EPWM carrier synchronization principle is explained further below;

referring to fig. 6, fig. 6 is a schematic diagram of an EPWM carrier synchronization process; after the output voltage modulation waves of each inverter module are synchronized in the above manner, the EPWM carrier waves of each inverter module need to be synchronized to reduce the high-frequency loop current between the parallel modules, in an ECAP interrupt generated by a hardware synchronization feedback signal, the inverter module 1 (main module) reads the count value of the EPWM at this time, the count value inverter module 1 (main module) is sent to a CANA network in a CANA communication manner, other slave modules receive the count value through the CANA network, and then assigns a counter of the EPWM to the slave module in the ECAP interrupt generated by the respective slave synchronization feedback signal, since the EPWM count value read by the main module is in the ECAP interrupt generated by the synchronization feedback signal, the slave module assigns the EPWM counter in the ECAP interrupt generated by the synchronization feedback signal, and each module generates the ECAP interrupt simultaneously, the ECAP interrupt generated by the CANA communication and the hardware synchronization feedback signal is interrupted, the EPWM carrier synchronization function is completed.

After the EPWM carrier synchronization and the output voltage modulation wave phase synchronization, a speed regulation instruction can be sent to each module through an upper computer or a display screen through a CANB network, the rotating speed or the voltage frequency of the motor is set, after the frequency of each inverter module is consistent, the output voltage is controlled according to a VF curve designed according to the characteristics of the asynchronous motor in advance, and the output voltage amplitude can be kept consistent due to the consistent frequency. At this point, the EPWM carrier synchronization is completed and the output voltage amplitude, frequency and phase are consistent.

In order to ensure that the power of each inverter module can be evenly divided after the inverter modules are connected in parallel, the power information of each inverter module is sent through a CANA network, the total power is calculated to calculate the average power, then the average power and the power of each inverter module are subjected to closed-loop control, the power of each inverter module is equal to the average power, and therefore the parallel power even division of the multiple inverter modules is achieved.

The present invention provides an embodiment as follows:

the parameters of the asynchronous motor are set as follows: the rated power of the motor is 4kW, the rated voltage is 380V, the rated current is 8.8A, the rated rotating speed is 1440rpm, and the stator resistance R_s1.252 Ω, rotor resistance R_r0.933 omega, stator inductance L_s0.1482H, rotor inductance L_r0.1482H, equivalent mutual inductance L_m0.1403H, moment of inertia J0.0139 kggm²And the voltage of the direct current bus is 700V.

In the above parameter setting situation, please refer to fig. 7-13, fig. 7 is a schematic diagram of a rotational speed curve of a motor according to an embodiment of the present invention; FIG. 8 is a three-phase current graph of a motor, in which A, B, C phase current curves are sequentially arranged from top to bottom in the first quarter period; FIG. 9 is a schematic diagram of a synchronization signal SYN square wave; FIG. 10 is a schematic illustration of the main machine phase voltages; FIG. 11 is a schematic representation of slave phase voltages; FIG. 12 is a schematic diagram of the active power of the device; FIG. 13 is a schematic diagram of the reactive power of the device;

the invention has the beneficial effects that: the inverter has the advantages of reducing noise, increasing system reliability, having redundant switching capability and being good in maintenance while reducing the weight and the volume of the inverter. The problems of large noise, large volume, heavy weight and the like when a single three-phase inverter is provided with a high-power asynchronous motor are solved.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.