阅读说明：本技术 一种晶圆级计量标准器及其制备方法 (Wafer-level measurement standard device and preparation method thereof ) 是由 饶张飞 秦凯亮 金红霞 于 2021-01-19 设计创作，主要内容包括：本发明公开了一种晶圆级计量标准器及其制备方法,属于微纳米二维栅格计量标准器领域。一种晶圆级计量标准器,包括晶圆,晶圆上设有多晶硅薄膜；多晶硅薄膜上设有图形区域,图形区域外围设有一级引导标记；图形区域包括二维栅格标准图形区域和位于其外围的二级引导标记；二维栅格标准图形区域内设有一个或多个标准图形。本发明的晶圆级计量标准器,在使用时具有一级和二级引导标记,能够快速寻找到相应的标准结构,使用方便快捷,能够进行集成电路产线测量设备的在线校准。(The invention discloses a wafer-level metering standard device and a preparation method thereof, and belongs to the field of micro-nano two-dimensional grid metering standard devices. A wafer-level measurement standard device comprises a wafer, wherein a polycrystalline silicon film is arranged on the wafer; a graphic area is arranged on the polycrystalline silicon film, and a first-level guide mark is arranged on the periphery of the graphic area; the graphic area comprises a two-dimensional grid standard graphic area and a secondary guide mark positioned on the periphery of the two-dimensional grid standard graphic area; one or more standard patterns are arranged in the two-dimensional grid standard pattern area. The wafer-level metering standard device provided by the invention has the primary and secondary guide marks when in use, can quickly find out a corresponding standard structure, is convenient and quick to use, and can perform online calibration on measuring equipment of an integrated circuit production line.)

1. A wafer-level measurement standard device is characterized by comprising a wafer, wherein a polycrystalline silicon film is arranged on the wafer;

a graphic area (2) is arranged on the polycrystalline silicon film, and a primary guide mark (3) is arranged on the periphery of the graphic area (2);

the pattern area (2) comprises a two-dimensional grid standard pattern area (4) and a secondary guide mark (5) positioned at the periphery of the two-dimensional grid standard pattern area;

one or more standard patterns are arranged in the two-dimensional grid standard pattern area (4).

2. The wafer-level metrology standard according to claim 1 wherein the pattern area (2) is one or more.

3. The wafer level metrology standard of claim 1 wherein the level one guide mark (3) is in the form of a line or a square block.

4. The wafer-level metrology standard of claim 1 wherein the standard patterns comprise a grid-type two-dimensional grid structure standard pattern, a horizontal-vertical two-dimensional grid structure standard pattern, and a comb-type two-dimensional grid structure standard pattern.

5. The wafer-level metrology standard of claim 4 wherein the comb-type two-dimensional grid is comprised of equal-sized lines and grids in both the lateral and longitudinal directions.

6. A method for preparing a wafer-level metrology standard, comprising:

preparing a polycrystalline silicon film on the surface of the bare silicon wafer;

etching a first-level guide mark (3) on the polycrystalline silicon thin film by using an i-line photoetching process and an etching process;

exposing the secondary guide mark (5) and the standard graph on the surface of the wafer etched with the primary guide mark (3) by using a mask through a DUV (deep ultraviolet) lithography process;

and after the photoetching is finished, etching the secondary guide mark (5) and the standard pattern by adopting a reactive ion etching method.

7. The method of claim 6, wherein the polysilicon film is formed by low pressure chemical vapor deposition.

8. The method for preparing a wafer-level metrology standard as claimed in claim 6 wherein the specific operation of etching the first level guide mark (3) is:

carrying out photoetching technology on the polycrystalline silicon film, namely sequentially carrying out gluing, exposure and development, and exposing the first-stage guide mark (3);

and etching the first-level guide mark (3) by adopting a reactive ion etching method after the photoetching is finished.

9. The method for preparing a wafer-level metrology standard as claimed in claim 8 wherein the lithography process for the first level guide mark (3) uses AZ4620 photoresist, the photoresist being 20um thick;

adjusting the position of a baffle of the photoetching machine to form a cross shape after the gluing is finished, and carrying out primary exposure;

the wafer is then rotated 45 deg. to perform a second exposure.

10. The method for preparing a wafer-level metrology standard as claimed in claim 6 wherein the photolithography process for the secondary guide marks (5) and the standard patterns uses AZ4620 positive photoresist with a thickness of 20 um.

Technical Field

The invention belongs to the field of micro-nano two-dimensional grid measuring standard devices, and particularly relates to a wafer-level measuring standard device and a preparation method thereof.

Background

Critical Dimension (CD) refers to the smallest feature size on a silicon wafer. The critical dimension is a special pattern which is designed for evaluating and controlling the processing precision of a process pattern for manufacturing an integrated circuit photomask, a photoetching process and the like and reflects the characteristic dimension of the integrated circuit, and is an important scale for measuring the manufacturing and design level of the integrated circuit, and the accuracy of a measuring result can directly influence various performance parameters of a circuit product. In the process of developing a semiconductor integrated circuit, instruments such as a scanning electron microscope and an atomic force microscope are required to measure critical dimensions, and in order to ensure the accuracy of a measurement result, a measuring instrument is generally calibrated by means of a nanometer geometric characteristic parameter measurement standard (line width, one-dimensional grid, two-dimensional grid, step, film thickness and the like).

The existing two-dimensional grid metering standard device is mainly prepared by methods of phase shift mask lithography, extreme ultraviolet lithography, electron beam lithography and the like, but the obtained standard sample wafer cannot be directly used for on-line calibration of a high-precision measuring instrument of a wafer-level semiconductor production line, so that the nanometer metering in an integrated circuit is disconnected from the industry.

Disclosure of Invention

The invention aims to overcome the defect that the conventional two-dimensional grid measuring standard cannot be directly used for on-line calibration of a high-precision measuring instrument of a wafer-level semiconductor production line, and provides a wafer-level measuring standard and a preparation method thereof.

In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:

a wafer-level measurement standard device comprises a wafer, wherein a polycrystalline silicon film is arranged on the wafer;

a graphic area is arranged on the polycrystalline silicon film, and a first-level guide mark is arranged on the periphery of the graphic area;

the graphic area comprises a two-dimensional grid standard graphic area and a secondary guide mark positioned on the periphery of the two-dimensional grid standard graphic area;

one or more standard patterns are arranged in the two-dimensional grid standard pattern area.

Further, the graphic area is one or more.

Further, the primary guiding mark is in a line shape or a square shape.

Further, the standard graph comprises a grid type two-dimensional grid structure standard graph, a horizontal and vertical two-dimensional grid structure standard graph and a comb type two-dimensional grid structure standard graph.

Furthermore, the transverse direction and the longitudinal direction of the comb-shaped two-dimensional grid are respectively composed of lines and grids with equal sizes.

A method of fabricating a wafer-level metrology etalon, comprising:

preparing a polycrystalline silicon film on the surface of the bare silicon wafer;

etching a first-level guide mark on the polycrystalline silicon thin film by using an i-line photoetching process and an etching process;

exposing the secondary guide mark and the standard graph on the surface of the wafer etched with the primary guide mark by using a mask through a DUV photoetching process;

and after the photoetching is finished, etching the secondary guide mark (5) and the standard pattern by adopting a reactive ion etching method.

Furthermore, the polycrystalline silicon film is prepared by low-pressure chemical vapor deposition.

Further, the specific operation of etching the first-level guide mark is as follows:

carrying out photoetching technology on the polycrystalline silicon film, namely sequentially carrying out gluing, exposure and development, and exposing the first-stage guide mark;

and etching the first-level guide mark by adopting a reactive ion etching method after the photoetching is finished.

Furthermore, the photoetching process of the first-level guide mark adopts AZ4620 photoresist, and the thickness of the photoresist is 20 um;

adjusting the position of a baffle of the photoetching machine to form a cross shape after the gluing is finished, and carrying out primary exposure;

the wafer is then rotated 45 deg. to perform a second exposure.

Furthermore, the photoetching process of the secondary guide mark and the standard pattern adopts AZ4620 positive photoresist, and the thickness of the photoresist is 20 um.

Compared with the prior art, the invention has the following beneficial effects:

according to the wafer-level metering standard device, the graphic area can be quickly found through the primary guide mark, after the graphic area is quickly found through the primary guide mark, the two-dimensional grid standard graphic area can be further quickly found through the secondary guide mark, and the two-dimensional grid standard graphic area is provided with the plurality of two-dimensional grid standard structures, so that the on-line calibration of the measuring equipment of the integrated circuit production line can be carried out. The wafer-level metering standard device provided by the invention has the primary and secondary guide marks when in use, can quickly find out a corresponding standard structure, and is convenient and quick to use.

The preparation method of the wafer-level measurement standard device uses a mode of combining an i-line photoetching technology and a DUV photoetching technology, uses the i-line photoetching technology as a first-level guide mark, and directly carries out shielding exposure by using a photoetching machine baffle; the secondary guide mark and the grid structure are realized by using a photoetching mask plate through a DUV photoetching technology; the accurate preparation of characteristic structures of various size measurement standard devices can be realized while the preparation cost is effectively reduced. The preparation method can ensure that each guide mark and the two-dimensional grid structure have good appearance and high precision.

Drawings

FIG. 1 is a wafer-level two-dimensional grid metrology standard with guide marks;

FIG. 2 is a detailed structure of a pattern region;

FIG. 3 is a two-dimensional grid standard pattern area;

FIGS. 4-6 are three different two-dimensional lattice structures;

in the figure, 1-wafer slide; 2, a graphic area; 3-primary guide mark; 4-a two-dimensional grid standard pattern area; 5-Secondary guide marker.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The invention is described in further detail below with reference to the accompanying drawings:

referring to fig. 1, fig. 1 is a schematic structural diagram of a wafer-level two-dimensional grid measurement standard device with guide marks, which includes a wafer carrier 1, wherein the center of the wafer carrier 1 is provided with 1 graphic area 2, and linear first-level guide marks 3 are arranged from the graphic area 2 to the edge of the wafer carrier 1; wherein, the size of the wafer carrier 1 can be 6 inches/8 inches/12 inches, etc.; the number of the graphic areas 2 can be multiple, and the positions and the sizes of the graphic areas 2 can be adjusted according to requirements; the first-level guide mark 3 can be in a shape of a line, a square block or the like, and the position, the number and the size of the guide mark 3 can be adjusted according to needs.

Referring to fig. 2, fig. 2 is a schematic diagram of a specific structure of the graphic area; the center of the graph area 2 is a two-dimensional grid standard graph area 4, a secondary guide mark 5 is arranged on the periphery of the two-dimensional grid standard graph area 4, the secondary guide mark 5 is composed of a plurality of triangular marks, and the top end of each triangular mark points to the two-dimensional grid standard graph area 4; the size of the two-dimensional grid standard pattern area 4 can be adjusted according to the requirement; the position, number and size of the secondary guide marks 5 can be adjusted as required.

Referring to fig. 3, fig. 3 is a two-dimensional grid standard pattern area, in which standard patterns of various sizes and structures are disposed, and one or more standard patterns of various sizes and structures may be disposed as required.

Referring to fig. 4-6, fig. 4 is a standard graph of a grid type two-dimensional grid structure, and the size and number of two-dimensional grids can be adjusted as required; FIG. 5 is a X, Y (horizontal and vertical) standard graph of two-dimensional grid structure, the size and number of the grids in X and Y directions can be adjusted according to the requirement; fig. 6 is a standard graph of a comb-shaped two-dimensional grid structure, the horizontal direction and the vertical direction of the comb-shaped two-dimensional grid structure are respectively composed of lines and grids with equal sizes, and the line size, the grid size and the number can be adjusted according to needs.

Examples

A preparation method of a wafer-level measurement standard device with a micro-nano two-dimensional grid structure and a guide mark comprises the following steps:

(1) wafer cleaning

Cleaning a bare silicon wafer, wherein the size of the wafer is 6 inches, and the material of the wafer is<si100>. The cleaning method adopts a B-clean cleaning mode in the RCA cleaning technology and uses SC-1 cleaning solution to clean the wafer. The SC-1 cleaning solution is prepared from NH₄OH、H₂O₂And H₂O composition, NH₄OH：H₂O₂：H₂O＝0.05:1:1。

(2) Film preparation

Preparing a layer of film on the surface of the cleaned bare silicon wafer, wherein the film is made of polysilicon, and the preparation method adopts low-pressure chemical vapor deposition (LPCVD) in Chemical Vapor Deposition (CVD). When the low pressure chemical vapor deposition LPCVD is used for preparing polysilicon, the polysilicon is prepared by thermal decomposition of silane at the temperature of 600-650 ℃, and the general chemical reaction (overall reaction) equation is as follows: SiH₄→ Si (poly crystal) +2H₂(ii) a The film thickness was 150 nm.

(3) Preparing a first-order guide mark

The first-stage guide mark 3 in fig. 1 is implemented using an i-line photolithography process and an etching process. The surface of the wafer with the film is firstly subjected to a photoetching process, namely glue coating, exposure and development in sequence, and the primary guide mark 3 is exposed. Wherein, the photoetching process adopts AZ4620 photoresist, and the thickness of the photoresist is 20 um. And adjusting the position of a baffle of the photoetching machine to form a cross shape after the glue is coated, carrying out primary exposure, and carrying out secondary exposure after rotating the bare silicon wafer by 45 degrees. And etching by adopting a Reactive Ion Etching (RIE) method in dry etching after the photoetching is finished. Reactive Ion Etching (RIE) is a physical + chemical process, i.e. combining physical and chemical methods, the resulting method is called reactive particle etching, etching by the dual action of physical bombardment and chemical reaction of reactive particles on the substrate.

(4) Preparing two-stage guide mark and standard pattern

Before preparing the secondary guide marks and the standard patterns, firstly, designing a photoetching mask plate according to the diagram shown in fig. 2, wherein the size of a pattern area is 5mm multiplied by 5mm during design, the positions of the secondary guide marks 5 are distributed around the two-dimensional grid standard pattern area and are 58 in number as shown in fig. 2, the size of the two-dimensional grid standard pattern area 4 is 0.3mm multiplied by 0.35mm, the patterns in the two-dimensional grid standard pattern area 4 are shown in fig. 3 and comprise 1 type of two-dimensional grid structures in fig. 4-6, and the sizes of the two-dimensional grids are 0.5um, 1um and 2 um. The wafer surface on which the primary guide mark is prepared is first exposed by a DUV photolithography process (i.e., sequentially applying glue, exposing and developing) using a reticle, and the secondary guide mark 5 and the standard pattern are exposed. The photoetching process can adopt AZ4620 positive photoresist, and the thickness of the photoresist is 20 um. And etching by adopting a Reactive Ion Etching (RIE) method in dry etching after the photoetching is finished. Reactive Ion Etching (RIE) is a physical + chemical process, i.e. combining physical and chemical methods, the resulting method is called reactive particle etching, etching by the dual action of physical bombardment and chemical reaction of reactive particles on the substrate.

The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.