阅读说明：本技术 双电源低侧门驱动器 (Dual-power low-side door driver ) 是由 A·E·哈希姆 于 2019-11-01 设计创作，主要内容包括：本发明揭示一种汽车系统(100),其包含经配置以基于第一输入电压电平(V1)提供第一输出电压(VO1)的第一调节器(102)。所述系统(100)还包含经配置以基于第二输入电压电平(V2)提供第二输出电压(VO2)的第二调节器(104)。所述系统(100)包含耦合到第一驱动器电路(108)及第二驱动器电路(110)的控制器(112)。所述控制器(112)经配置以基于控制信号(驱动信号)选择所述第一驱动器电路(108)及所述第二驱动器电路(110)中的一者来驱动开关(114)。所述系统(100)包含耦合到所述开关(114)的开关节点(120)。所述开关节点(120)处的开关节点电压是接通及关断所述开关(114)的函数。所述系统(100)还包含耦合到所述开关节点(120)的负载(118)。(An automotive system (100) includes a first regulator (102) configured to provide a first output voltage (VO1) based on a first input voltage level (V1). The system (100) also includes a second regulator (104) configured to provide a second output voltage (VO2) based on a second input voltage level (V2). The system (100) includes a controller (112) coupled to a first driver circuit (108) and a second driver circuit (110). The controller (112) is configured to select one of the first driver circuit (108) and the second driver circuit (110) to drive a switch (114) based on a control signal (drive signal). The system (100) includes a switch node (120) coupled to the switch (114). The switch node voltage at the switch node (120) is a function of turning the switch (114) on and off. The system (100) also includes a load (118) coupled to the switch node (120).)

1. An automotive system, comprising:

a first regulator configured to provide a first output voltage based on a first input voltage level;

a second regulator configured to provide a second output voltage based on a second input voltage level;

a first driver circuit coupled to the first regulator and a switch, wherein the first driver circuit is configured to drive the switch based on the first output voltage;

a second driver circuit coupled to the second regulator and the switch, wherein the second driver circuit is configured to drive the switch based on the second output voltage;

a driver controller coupled to the first driver circuit and the second driver circuit, wherein the driver controller is configured to select one of the first driver circuit and the second driver circuit to drive the switch based on a control signal;

a switch node coupled to the switch, wherein a switch node voltage at the switch node is a function of turning the switch on and off; and

a load coupled to the switching node.

2. The system of claim 1, further comprising a voltage monitoring circuit configured to monitor the second input voltage level and provide the control signal to the driver controller.

3. The system of claim 2, wherein the driver controller is configured to select the second driver circuit when the control signal indicates that the second input voltage level is greater than a threshold.

4. The system of claim 2, wherein the driver controller is configured to select the first driver circuit when the control signal indicates that the second input voltage level is equal to or less than a threshold.

5. The system of claim 1, wherein the switch is a low side switch.

6. The system of claim 1, further comprising a resistor coupled between an output node of the first regulator and an output node of the second regulator.

7. The system of claim 6, further comprising a sense switch coupled to the resistor and configured to receive an average of the first and second output voltages.

8. A circuit, comprising:

a first regulator configured to provide a first output voltage based on a first input voltage level;

a second regulator configured to provide a second output voltage based on a second input voltage level, wherein the second input voltage level is lower than the first input voltage level;

a first driver circuit coupled to the first regulator, wherein the first driver circuit is configured to provide a first gate drive signal based on the first output voltage;

a second driver circuit coupled to the second regulator, wherein the second driver circuit is configured to provide a second gate drive signal based on the second output voltage;

a driver controller coupled to the first driver circuit and the second driver circuit; and

a drive signal node coupled to an output node of the first driver circuit and an output node of the second driver circuit, wherein the driver controller is configured to select between the first driver circuit and the second driver circuit to provide a respective gate drive signal to the drive signal node.

9. The circuit of claim 8, further comprising a voltage monitoring circuit configured to monitor the second input voltage level and provide a control signal to the driver controller.

10. The circuit of claim 9, wherein the driver controller is configured to select the second driver circuit to provide the second gate drive signal to the drive signal node when the control signal indicates that the second input voltage level is greater than a threshold.

11. The circuit of claim 9, wherein the driver controller is configured to select the first driver circuit to provide the second gate drive signal to the drive signal node when the control signal indicates that the second input voltage level is less than a threshold.

12. The circuit of claim 8, further comprising a low side switch coupled to the drive signal node.

13. The circuit of claim 8, further comprising:

a resistor coupled between an output node of the first regulator and an output node of the second regulator; and

a sense switch coupled to the resistor and configured to receive an average of the first and second output voltages.

14. A dual power gate driver, comprising:

a first regulator circuit coupled to a first input voltage node;

a second regulator circuit coupled to a second input voltage node;

a first driver circuit coupled to an output node of the first regulator circuit;

a second driver circuit coupled to an output node of the second regulator circuit;

a driver controller coupled to the first driver circuit and the second driver circuit; and

a drive signal node coupled to an output node of the first driver circuit and an output node of the second driver circuit.

15. The dual-powered gate driver of claim 14, further comprising a voltage monitoring circuit coupled to the second input voltage node and an input node of the driver controller.

16. The dual-supply gate driver of claim 15, wherein the driver controller is configured to select a second driver circuit to provide a gate drive signal to the drive signal node when a signal from the voltage monitoring circuit indicates a second input voltage level greater than a threshold.

17. The dual-supply gate driver of claim 15, wherein the driver controller is configured to select the first driver circuit to provide a gate drive signal to the drive signal node when a signal from the voltage monitoring circuit indicates that the second input voltage level is equal to or less than a threshold value.

18. The dual-power gate driver of claim 14, wherein the first regulator circuit comprises a first transistor having a control terminal, a first current terminal, and a second current terminal, wherein the first current terminal of the first transistor is coupled to the first input voltage node, wherein the control terminal of the first transistor is coupled to a current source, and wherein the second current terminal of the first transistor is coupled to the first driver circuit and a first end of a resistor.

19. The dual-supply gate driver of claim 18, wherein the second regulator circuit comprises a second transistor having a control terminal, a first current terminal, and a second current terminal, wherein the first current terminal of the second transistor is coupled to the second input voltage node, wherein the control terminal of the second transistor is coupled to the current source, and wherein the second current terminal of the second transistor is coupled to the second driver circuit and a second end of the resistor.

20. The dual-supply gate driver of claim 14, wherein a first input voltage level at the first input voltage node is higher than a second input voltage level at the second input voltage node.

Background

Power supplies and power converters are used in various electronic systems. Power is typically transmitted over long distances as Alternating Current (AC) signals. The AC signal is distributed and metered as needed for each commercial or home location and is typically converted to Direct Current (DC) for use with individual electronic devices or components. Modern electronic systems typically employ devices or components designed to operate using different DC voltages. Thus, such systems require different DC-DC converters or DC-DC converters that support various output voltages.

Various DC-DC converter topologies exist. The available topology may vary with the components used, the amount of power processed, the input voltage, the output voltage, the efficiency, the reliability, the size, and/or other characteristics. One example DC-DC converter topology uses a secondary low voltage "bias" input driven by an output voltage or auxiliary power supply. This option increases efficiency at the expense of additional components and increased topology size. Work is constantly being done to improve the topology of DC-DC converters.

Disclosure of Invention

According to one example, an automotive system includes a first regulator configured to provide a first output voltage based on a first input voltage level. The system also includes a second regulator configured to provide a second output voltage based on a second input voltage level. The system also includes a first driver circuit coupled to the first regulator and to a switch, wherein the first driver circuit is configured to drive the switch based on the first output voltage. The system also includes a second driver circuit coupled to the second regulator and the switch, wherein the second driver circuit is configured to drive the switch based on the second output voltage. The system also includes a driver controller coupled to the first driver circuit and the second driver circuit, wherein the driver controller is configured to select one of the first driver circuit and the second driver circuit to drive the switch based on a control signal. The system also includes a switch node coupled to the switch, wherein a switch node voltage at the switch node is a function of turning the switch on and off. The system also includes a load coupled to the switch node.

According to one example, a circuit includes a first regulator configured to provide a first output voltage based on a first input voltage level. The circuit also includes a second regulator configured to provide a second output voltage based on a second input voltage level, wherein the second input voltage level is lower than the first input voltage level. The circuit also includes a first driver circuit coupled to the first regulator, wherein the first driver circuit is configured to provide a first gate drive signal based on the first output voltage. The circuit also includes a second driver circuit coupled to the second regulator, wherein the second driver circuit is configured to provide a second gate drive signal based on the second output voltage. The circuit also includes a driver controller coupled to the first driver circuit and the second driver circuit. The circuit also includes a drive signal node coupled to an output node of the first driver circuit and an output node of the second driver circuit, wherein the driver controller is configured to select between the first driver circuit and the second driver circuit to provide a respective gate drive signal to the drive signal node.

According to one example, a dual-power gate driver includes a first regulator circuit coupled to a first input voltage node. The dual power gate driver also includes a second regulator circuit coupled to a second input voltage node. The dual power gate driver also includes a first driver circuit coupled to an output node of the first regulator circuit. The dual power gate driver also includes a second driver circuit coupled to an output node of the second regulator circuit. The dual power gate driver also includes a driver controller coupled to the first driver circuit and the second driver circuit. The dual power gate driver also includes a drive signal node coupled to an output node of the first driver circuit and an output node of the second driver circuit.

Drawings

Fig. 1 is a block diagram showing a system according to some examples.

Fig. 2 is a schematic diagram showing a buck converter system, according to some examples.

Fig. 3 is a schematic diagram showing a flyback converter system according to some examples.

Fig. 4 is a schematic diagram showing a voltage regulator of a low side switching driver, according to some examples.

Fig. 5 is a schematic diagram showing a dual-powered gate driver, according to some examples.

Fig. 6 is a schematic diagram showing another dual-powered gate driver, according to some examples.

Fig. 7 is a schematic diagram showing controller logic for a dual power gate driver, according to some examples.

Fig. 8 is a timing diagram showing various waveforms related to a dual power gate driver, according to some examples.

Fig. 9 is a schematic diagram showing a driver circuit, according to some examples.

Detailed Description

Dual power gate driver topologies and related systems are described herein. In some examples, a dual-power-gate driver includes a first regulator circuit coupled to a first input voltage node and a second regulator circuit coupled to a second input voltage node. The dual power gate driver also includes a first driver circuit coupled to an output node of the first regulator circuit. The dual power gate driver also includes a second driver circuit coupled to an output node of the second regulator circuit. The dual-powered gate driver also includes a driver controller coupled to the first driver circuit and the second driver circuit. The dual power gate driver also includes a drive signal node coupled to an output node of the first driver circuit and an output node of the second driver circuit.

In some examples, dual-powered gate drivers are commercialized as stand-alone Integrated Circuits (ICs) or chips. In other examples, the dual power gate driver is combined with an IC, chip, multi-die module (MDM), or other circuitry in a Printed Circuit Board (PCB) (power and/or sense switches of the converter circuit, load). With the described dual power gate driver topology, the drive signal to switch the switches of the converter is efficiently provided without an external capacitor (for providing the drive current). In some examples, dual-power gate drivers are used to drive low-side switches of switching converters, while providing efficiency, small size, and low cost compared to other gate drivers. Various dual power gate driver options and related problems will be described below.

Fig. 1 is a block diagram showing a system 100 according to some examples. As shown, the system 100 includes a first regulator circuit 102 and a second regulator circuit 104. The first regulator circuit 102 receives a first input voltage (V1) and provides a first output voltage (VO1) based on V1. The second regulator circuit 104 receives a second input voltage (V2) and provides a second output voltage (VO2) based on V2. As shown, VO1 is provided to first driver circuit 108. When directed by driver controller 112, first driver circuit 108 is configured to provide a drive signal to switch 114 based on VO 1. Meanwhile, when directed by driver controller 112, second driver circuit 110 is configured to provide a drive signal to switch 114 based on VO 2.

In some examples, the driver controller 112 selects the first driver circuit 108 or the second driver circuit 110 to provide the drive signal to the switch 114 based on the signal 124 from the voltage monitoring circuit 106. Also, a signal (such as the on signal in fig. 5) from a PWM controller (not shown) is used to determine when the driver controller 112 asserts CS1 or CS 2. In the example of fig. 1, voltage monitoring circuit 106 is configured to monitor V2. When signal 124 indicates that V2 is greater than the threshold, driver controller 112 selects second driver circuit 110 (using control signal "CS 2") to provide the drive signal to switch 114. On the other hand, when the signal 124 indicates that V2 is less than or equal to the threshold, the driver controller 112 selects the first driver circuit 108 (using the control signal "CS 1") to provide the drive signal to the switch 114.

In the example of fig. 1, the drive signal is provided to the switch 114 via a drive signal node 122. In some examples, the drive signal node 122 corresponds to an output pin of a dual-powered gate driver IC or chip that includes the first regulator circuit 102, the second regulator circuit 104, the voltage monitoring circuit 106, the first driver 108, the second driver 110, and the driver controller 112.

The on/off operation of switch 114 changes the voltage at node 120, node 120 corresponding to the switch node. In the example of fig. 1, output component 116 is coupled to node 120. Examples of output components 116 include an output inductor and an output capacitor. Coupled to the output component 116 is a load 118 powered by an output Voltage (VOUT) based on the operation of the switch 114. In some examples, system 100 corresponds to an automotive system. In this case, the first regulator circuit 102 receives V1 (e.g., 5V to 40V) from a battery or a regulating component (e.g., a filter and/or a regulator). Meanwhile, V2 may be a bias voltage based on VOUT or a lower voltage auxiliary supply. In some examples, the dual-powered gate driver component of fig. 1 is part of a buck converter or buck converter controller for directing low-side switching operations, where VOUT is less than V1. Example VOUT levels include 5V, 3.3V, 1.8V, or 1.2V. Multiple switching converters are used in automotive systems or other electrical systems to power different loads with different input voltage requirements, as desired. Example loads for automotive systems include, but are not limited to, microprocessors, sensors, actuators, displays, infotainment interfaces, and Intelligent Power Modules (IPMs). With the dual power gate drive topology of fig. 1, drive signal efficiency is higher at small chip size and low cost than other gate drive topologies that use only V1 or use external capacitors to generate the drive signal.

Fig. 2 is a schematic diagram showing a buck converter system 200, according to some examples. As shown, the buck converter system 200 includes a buck converter circuit 202 having an input supply Voltage (VIN) node, a bias node, a Switch (SW) node, a voltage supply (VCC) node, and a Feedback (FB) node. More specifically, the SW node of the buck converter circuit 202 is coupled to a first end of an output inductor (LOUT). A second terminal of LOUT is coupled to a first (e.g., upper) plate of an output Capacitor (COUT). A second (e.g., lower) plate of the COUT is coupled to the ground node. In the example of fig. 2, VOUT of the buck converter system 200 is provided to a load (not shown) and a voltage divider formed using R1 and R2. The node 204 between R1 and R2 is coupled to the FB node of the buck converter circuit 202. The buck converter circuit 202 also receives VOUT at a bias voltage node. In contrast to the system 100 of fig. 1, the buck converter system 200 of fig. 2 includes an external capacitor (C1) coupled to the VCC node of the buck converter circuit 202, where VCC is the driver supply.

Fig. 3 is a schematic diagram showing a flyback converter system 300 according to some examples. As shown, the flyback converter system 300 includes a flyback converter circuit 302 having an input supply Voltage (VIN) node, a Switch (SW) node, a bias node, and a VCC node. More specifically, the switching node is coupled to a transformer 304. A first winding of transformer 304 is coupled between an input supply Voltage (VIN) and a SW node. A second winding of the transformer 403 is coupled between the further voltage supply node 308 and the anode of the diode (D1). The cathode of D1 is coupled to a first (e.g., upper) plate of an output Capacitor (COUT). A second (e.g., lower) plate of COUT is coupled to voltage supply node 308 and the second winding.

In the example of fig. 3, the bias node is coupled to a circuit that includes a bias coil 306 inductively coupled to a transformer 304. As shown, the third winding 306 is coupled between a ground node and the anode of another diode (D2). The cathode of D2 is coupled to the bias node of the flyback converter circuit 302. Also, a first (e.g., upper) plate of the capacitor (C3) is coupled to the cathode of D2 and the bias node. The second (e.g., lower) plate of C3 is coupled to the ground node. In contrast to the system 100 of fig. 1, the flyback converter system 300 includes an external capacitor (C2) coupled to the VCC node of the flyback converter circuit 302. More specifically, a first (e.g., upper) plate of C2 is coupled to the VCC node of flyback converter 300, and a second (e.g., lower) plate of C2 is coupled to a ground node.

Under the buck converter 200 of fig. 2, the bias voltage is driven by the output voltage. In contrast, under the flyback converter 300 of fig. 3, the bias voltage is driven by the bias winding 306. In either case, the bias voltage provided to the buck converter circuit 202 or the flyback converter circuit 302 may improve efficiency by shifting the efficiently generated chip bias current from VIN to a lower voltage supply. In some examples, the low side switch driver drains VCC, which is a regulated supply derived from VIN or bias voltage when available. Once the bias voltage exceeds the minimum required voltage, the VCC regulator will draw all driver current from the bias voltage.

Fig. 4 is a schematic diagram of a voltage regulator 400 showing a low side switching driver, according to some examples. As shown, voltage regulator 400 includes a current source 402 coupled to VIN node 408. Voltage regulator 400 also includes a transistor (M1) having a control terminal, a first current terminal, and a second current terminal. Also, the voltage regulator 400 also includes a diode (D3), with the anode of D3 coupled to the current source 402 and the cathode of D3 coupled to the control terminal of M1. Meanwhile, a first current terminal of M1 is coupled to VIN node 408. Also, a second current terminal of M1 is coupled to the input node of comparator 404. The other input node of the comparator 404 is a voltage reference (Ref), and the output of the comparator 404 is coupled to the cathode of D3 and the control terminal of M1. As shown, the second current terminal of M1 is also coupled to driver circuit 412, driver circuit 412 being powered by the charge stored by an external capacitor (Cext) coupled to VCC pin 406 (e.g., the VCC node of fig. 2 or 3). As shown, the driver circuit 412 includes a series of inverters 404, with the charge stored by Cext being provided to an inverter 414.

In the example of fig. 4, Cext is charged by the voltage at VIN node 408 through M1 or from bias node 410 through transistor (M2). As shown, M2 includes a control terminal coupled to node 416 between current source 402 and the anode of D3. Also, a first current terminal of M3 is coupled to the bias node 410 via a diode (D4), with the anode of D4 coupled to the bias node 410 and the cathode of D4 coupled to the first current terminal of M2. A second current terminal of M2 is coupled to driver circuit 412, VCC pin 406, and a first (e.g., upper) plate of Cext. The second (e.g., below) plate of Cext is coupled to the ground node.

In the example of fig. 4, voltage regulator 400 also includes a transistor (M3) coupled between driver circuit 412 and switch node (SW) pin 416. As shown, the control terminal of M3 is coupled to the output of driver circuit 412. Also, a first current terminal of M3 is coupled to SW pin 416. Also, a second current terminal of M3 is coupled to the ground node.

In some examples, driver circuit 412 is a low-side switching driver that drains VCC, which is a regulated supply derived from the VIN voltage or bias voltage (if present). Once the bias voltage exceeds the minimum required voltage, the VCC regulator will draw all driver current from the bias voltage. Cext is needed to ensure that the VCC rail remains well regulated when driver 412 switches and draws very high peak currents from the VCC rail.

Figure 5 is a schematic diagram showing a dual-power gate driver circuit 500 according to some examples. As shown, dual-powered gate driver circuit 500 includes a first driver circuit 514 and a second driver circuit 516, with output nodes of first driver circuit 514 and second driver circuit 516 coupled to drive signal node 522. In the example of fig. 5, the power transistor (M7) has its control terminal coupled to the drive signal node 522. Also, a first current terminal of M7 is coupled to switch node (SW) pin 518, and a second current terminal of M7 is coupled to a ground node.

In some examples, dual-powered gate driver circuit 500 includes a single IC having driver components (e.g., first driver circuit 514 and second driver circuit 516), driver control components (e.g., controller logic 512 and other components), and a power transistor (e.g., M7). In other examples, the components represented for dual-powered gate driver circuit 500 correspond to multiple ICs (e.g., M7 is part of a first IC, while the driver components and driver control components are part of a second IC).

In the example of fig. 5, the operation of controller logic 512 (an example of driver controller 112 in fig. 1) of dual power gate driver circuit 500 is based on a control signal ("on") and a BIAS voltage level indication signal ("BIAS _ ok"). In some examples, the BIAS _ ok signal is provided by comparator 506, where the output of comparator 506 indicates when the BIAS voltage at node 508 is greater than a threshold. When the bias voltage at node 508 is greater than the threshold, the controller logic 512 uses the control signal ("Tri-stateB") to select the second driver circuit 516, where the input signal (IN) to the second driver circuit 516 is buffered based on the bias voltage available at node 508 using the voltage supply signal (VCCB). In the example of fig. 5, VCCB is provided via a transistor (M5), M5 has its first current terminal coupled to node 508 via a diode (D5), D5 blocks the reverse path back to node 508 at start-up. If the diode drop of D5 is too large, another option is to use a switch across D5, where the switch closes when the bias voltage is sufficiently high. With the switch across D5, a lower bias voltage may be used. More specifically, the anode of D5 is coupled to node 508, and the cathode of D5 is coupled to the first current terminal of M5. Also, a second current terminal of M5 is coupled to VCCB node 510. Also, the control terminal of M5 is coupled to current source 504 powered by the VIN voltage at node 502. As shown, the control terminal of M5 is also coupled to a first end of a zener diode (Z1) and a first (e.g., upper) plate of a capacitor (C4). The second (e.g., lower) plate of C4 and the second end of Z1 are coupled to a ground node. Under the arrangement of fig. 5, the voltage level at the VCCB node 510 is based on the bias voltage at the node 508 and is provided to the second driver circuit 516. When the bias voltage is sufficiently high, the controller logic 512 uses the second driver circuit 516 to provide the drive signal of M7.

When the bias voltage at node 508 is equal to or less than the threshold, the controller logic 512 uses the control signal ("Tri-stateA") to select the first driver circuit 514, where the input signal (IN) to the first driver circuit 514 is buffered based on the VIN voltage available at node 502 using the voltage supply signal (VCCA). In the example of fig. 5, VCCA is provided via a transistor (M4), M4 having its first current terminal coupled to node 502. Also, a second current terminal of M4 is coupled to VCCA node 509. Also, the control terminal of M4 is coupled to current source 504 powered by the VIN voltage at node 502. As shown, the control terminal of M4 is also coupled to the first (e.g., upper) plate of Z1 and C4. In at least some examples, M4 provides the same amount of current, but can handle higher voltages relative to M5. The second (e.g., lower) plate of C4 and the second end of Z1 are coupled to a ground node. Under the arrangement of fig. 5, the voltage level at VCCA node 509 is based on the VIN voltage at node 502 and is provided to first driver circuit 514. When the bias voltage is not high enough, the controller logic 512 uses the first driver circuit 514 to provide the drive signal of M7. With the arrangement of fig. 5, the dual-power-gate driver circuit 500 adds complexity over a single driver arrangement that benefits from reducing power consumption for low-side switch drive operations (by using bias voltages for power driver operations when the bias voltages are sufficiently high). Also, dual-power gate driver circuit 500 eliminates external capacitors (to maintain VCC) and ICs compared to other driver solutions.

Another component represented in fig. 5 is a sense transistor (M6). As shown, the control terminal of M6 is coupled to a resistor (R3) between the VCCA node 509 and the VCCB node 510. In some examples, R3 corresponds to two resistors coupled in series with an intermediate node coupled to the one of M6. Through R3, the control terminal of M6 receives the average of the voltage levels at VCCA and VCCB. Meanwhile, a second current terminal of M6 is coupled to the ground node, and a first current terminal of M6 is coupled to the sense node 520. In different examples, the sensing node 520 provides a signal for feedback control and/or monitoring the operation of the switching converter. In one example, the signal at the sense node 520 is provided to a pulse-switch modulation (PWM) controller coupled to the driver controller 112 of fig. 1. For example, the PWM controller may use the signal at the sensing node 520 to adjust the duty cycle and/or timing of the SWITCH ON signal provided to the logic 512.

Fig. 6 is a schematic diagram showing another dual-powered gate driver 600, according to some examples. As shown, dual power gate driver circuit 600 includes a first driver circuit 614 and a second driver circuit 616, with output nodes of the first and second driver circuits 614, 616 coupled to a drive signal node 620. In the example of fig. 6, M7 has its control terminal coupled to the drive signal node 620 via the low side gate pin 618. Also, a first current terminal of M7 is coupled to switch node (SW) pin 622, and a second current terminal of M7 is coupled to a ground node.

In some examples, dual-powered gate driver circuit 600 includes a single IC having driver components (e.g., first driver circuit 614 and second driver circuit 616), driver control components (e.g., controller logic 612 and other components), and a power transistor (e.g., M7). In other examples, the components represented for dual-powered gate driver circuit 600 correspond to multiple ICs (e.g., M7 is part of a first IC, while the driver components and driver control components are part of a second IC).

In the example of fig. 6, the operation of controller logic 612 (an example of driver controller 112 in fig. 1) of dual power gate driver circuit 600 is based on a control signal ("on") and a BIAS voltage level indication signal ("BIAS _ ok"). In some examples, the BIAS _ ok signal is provided by the comparator 608, where the output of the comparator 608 indicates when the BIAS voltage at the node 610 is greater than a threshold. When the bias voltage at node 610 is greater than the threshold, the controller logic 612 uses the control signal ("Tri-stateB") to select the second driver circuit 616, where the input signal (IN) to the second driver circuit 616 is buffered based on the bias voltage available at node 610 using the voltage supply signal (VCCB). In the example of fig. 6, the VCCB is provided with a low dropout regulator (LDO) circuit 606 coupled to the node 610 under the arrangement of fig. 6, the VCCB voltage is based on the bias voltage at the node 610 and is provided to the second driver circuit 616. When the bias voltage is sufficiently high, the controller logic 612 uses the second driver circuit 616 to provide the drive signal for M7.

When the bias voltage at node 610 is equal to or less than the threshold, the controller logic 612 uses the control signal ("Tri-stateA") to select the first driver circuit 614, where the input signal (IN) to the first driver circuit 614 is buffered based on the VIN voltage available at node 602 using the voltage supply signal (VCCA). In the example of fig. 6, VCCA is provided by another LDO circuit 604 coupled to node 602. Under the arrangement of fig. 6, the VCCA voltage is based on the VIN voltage at node 602 and is provided to the first driver circuit 614. When the bias voltage is not high enough, the controller logic 612 uses the first driver circuit 614 to provide the drive signal for M7. With the arrangement of fig. 6, dual-power-gate driver circuit 600 adds complexity over a single-driver arrangement that benefits from reducing power consumption for low-side switch drive operations (by using bias voltages for power driver operations when the bias voltages are sufficiently high).

Fig. 7 is a schematic diagram showing controller logic 700 of a dual-powered gate driver, such as dual-powered gate driver circuits 500 or 600 of fig. 5 and 6, according to some examples. Controller logic 700 of fig. 7 is an example of driver controller 112 of fig. 1, controller logic 512 of fig. 5, or controller logic 612 of fig. 6. As shown, the controller logic 700 includes a D latch 702 with the D input node receiving the BIAS _ ok signal. Also, the reset node of the D latch 702 receives a turn-on signal via the inverter 704. The controller logic 700 also includes an AND gate 708 that receives the BIAS _ ok signal AND the output of the D latch 702. When the BIAS _ ok signal is high and the output of the D latch 702 is high, the Tri-stateA signal is high to disable the driver. Also, when the output of the D-latch 702 is in a low state, the Tri-stateB signal is in a high state due to the inverter 706 to disable the driver. In the example of fig. 7, the AND gate 708 AND inverter 706 have a 20ns rise delay. In other examples, the rise delay may change (the delay ensures some overlap of control signals to avoid undefined states).

Fig. 8 is a timing diagram 800 showing various waveforms related to a dual-powered gate driver, according to some examples. As shown, the timing diagram 800 includes a bias input waveform 802, a bias ok waveform 812, a Tri-state a waveform 842, a Tri-state b waveform 832, a Switch ON waveform 852, a Switch gate waveform 862 (corresponding to the gate signal of M7 at node 522 in fig. 5 or node 620 in fig. 6), a VIN average current waveform 872, and a bias average current waveform 882. Note that: the Switch _ gate signal following the Switch _ ON waveform 852 is not interrupted when switching between drivers for providing the Switch _ gate waveform 862 (e.g., switching between the first driver circuit 514 and the second driver circuit 516 in fig. 5 or switching between the first driver circuit 614 and the second driver circuit 616 in fig. 6). In practice, the Switch _ gate signal will be slightly delayed with respect to the Switch _ ON signal.

In timing diagram 800, when the bias input reaches threshold 804, the value of the bias _ ok signal goes high during interval 814, as represented by waveforms 802 and 812. Also, when the bias _ ok signal goes high, the Tri-stateA goes high during interval 834, as represented by waveforms 812 and 832. Also, the Tri-stateB remains low during interval 814, as represented by waveforms 812 and 842. During interval 834, the average VIN current drops to zero within interval 874, as represented by waveforms 832 and 872. During interval 834, the average current increases within interval 884 as represented by waveforms 832 and 882. At time 806, the bias input drops below threshold 804, causing the bias _ ok signal to go low, as represented by waveforms 802 and 812. As represented in the timing diagram 800, the Switch _ ON waveform 852 shows transitions between a high value 854 and a low value 856 where these transitions are unaffected by other values represented for the timing diagram 800. As shown, the Switch _ gate waveform 852 follows the pattern of the Switch _ ON waveform 852.

In some examples, the bias current maximum is less than the VIN current maximum (e.g., a lower number mA). In the described driver topology, selective use of dual drivers is implemented to improve the efficiency of providing drive signals (e.g., low side drive signals). The efficiency improvement is due to the bias current being lower than the VIN current, which can be used to reduce the power consumption of a dual power gate driver circuit (such as dual power gate driver circuits 500 or 600 of fig. 5 and 6) in place of a single power gate driver circuit. Also, the described driver topology avoids external capacitors for driving operations to reduce the size and cost of the dual power gate driver circuit described herein.

Fig. 9 is a schematic diagram showing a driver circuit 900 (an example of the first driver circuit 514 in fig. 5, the second driver circuit 516 in fig. 5, the first driver circuit 614 in fig. 6, or the second driver circuit 616 in fig. 6). As shown, the driver circuit 900 includes a plurality of inverter circuits 903, 905, 907, and 909 connected in series between an input node 902 and an output node 916. More specifically, the first inverter circuit 903 includes two transistors M8 and M9 coupled between the first input supply node 906 and the ground node 908. As shown, a first current terminal of M8 is coupled to first input supply node 906 (e.g., to receive an input voltage of 1x, where x is a reference voltage level), a second current terminal of M8 is coupled to a first current terminal of M9, and a second current terminal of M9 is coupled to ground node 908. Meanwhile, the control terminals of M8 and M9 are coupled to the input node 902.

As shown, the second inverter circuit 905 includes two transistors M10 and M11 coupled between the second input supply node 910 and the ground node 908. More particularly, a first current terminal of M10 is coupled to a second input supply node 910 (e.g., to receive an input voltage of nx, where n is an integer value greater than 1, and where x is a reference voltage level), a second current terminal of M10 is coupled to a first current terminal of M11, and a second current terminal of M11 is coupled to a ground node 908. Meanwhile, the control terminals of M10 and M11 are coupled to the output node 918 of the first inverter circuit 903.

As shown, the third inverter circuit 907 includes two transistors M12 and M13 coupled between the third input supply node 912 and the ground node 908. More particularly, a first current terminal of M12 is coupled to a third input supply node 912 (e.g., to receive n)²x, where n is an integer value greater than 1, and where x is a reference voltage level), a second current terminal of M12 is coupled to the first current terminal of M13, and a second current terminal of M13 is coupled to ground node 908. Meanwhile, the control terminals of M12 and M13 are coupled to the output node 920 of the second inverter circuit 905.

As shown, the fourth inverter circuit 909 includes two transistors M14 and M15 coupled between the fourth input supply node 914 and the ground node 908. More particularly, a first current terminal of M14 is coupled to fourth input supply node 914 (e.g., to receive n)³x, where n is an integer value greater than 1, and where x is a reference voltage level), a second current terminal of M14 is coupled to the first current terminal of M15, and a second current terminal of M15 is coupled to ground node 908. Meanwhile, the control terminals of M14 and M15 are coupled to the output node 922 of the second inverter circuit 905. As shown, the firstThe output node 924 of the four-inverter circuit 909 is coupled to the output node 916 of the driver circuit 916.

In the detailed description, the term "coupled (couples) means an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. The statement "based on" means "based at least in part on. Thus, if X is based on Y, X may be a function of Y and any number of other factors.

The described embodiments may be modified and other embodiments are possible within the scope of the claims.