阅读说明：本技术 驱动系统 (Drive system ) 是由 市川聪一朗 中村雅史 伊藤拓巳 于 2020-01-22 设计创作，主要内容包括：实施方式的驱动系统(1)的主装置(10)按包含多个第一周期的基准周期中的每个第一周期发送第一周期的识别信息和第一发送同步信号,或者按基准周期中的每个第一周期发送第一周期的识别信息、第一发送同步信号以及第二发送同步信号。第一驱动装置(31)使用识别信息来调整所述第一控制周期的相位,以使第一控制周期同步于与多个第一同步信号中的特定第一同步信号相关的定时,所述多个第一同步信号是通过多次的所述第一发送同步信号的接收而得到的,所述第一驱动装置控制第一电力转换器。第二驱动装置(32)使用识别信息来调整所述第二控制周期的相位,以使第二控制周期同步于与多个第二同步信号中的特定第二同步信号相关的定时,所述多个第二同步信号是通过多次的所述第一发送同步信号的接收、以及多次的所述第二发送同步信号的接收中的任一方的接收而得到的,所述第二驱动装置控制第二电力转换器。(A host device (10) of a drive system (1) according to an embodiment transmits, for each first cycle of a reference cycle including a plurality of first cycles, identification information of the first cycle and a first transmission synchronization signal, or transmits, for each first cycle of the reference cycle, identification information of the first cycle, the first transmission synchronization signal, and a second transmission synchronization signal. A first drive device (31) uses the identification information to adjust the phase of the first control period so as to synchronize the first control period with the timing associated with a specific first synchronization signal of a plurality of first synchronization signals obtained by a plurality of receptions of the first transmission synchronization signal, the first drive device controlling a first power converter. A second drive device (32) uses the identification information to adjust the phase of the second control cycle so that the second control cycle is synchronized with the timing of a specific second synchronization signal of a plurality of second synchronization signals obtained by receiving either the first transmission synchronization signal or the second transmission synchronization signal a plurality of times, and controls a second power converter.)

1. A drive system is provided with:

a first drive device including a first power converter that supplies first electric power to a winding of a first motor, and a first control unit that controls the first power converter;

a second driving device including a second power converter that supplies second electric power to a winding of a second motor, and a second control unit that controls the second power converter; and

a master device that controls the first control unit and the second control unit using a first cycle and a reference cycle including a plurality of the first cycles,

the master device transmits the identification information of the first period and a first transmission synchronization signal in each of the first periods in the reference period, or transmits the identification information of the first period, a first transmission synchronization signal and a second transmission synchronization signal in each of the first periods in the reference period,

the first control unit adjusts a phase of a first control cycle using the identification information so that the first control cycle is synchronized with a timing related to a specific first synchronization signal among a plurality of first synchronization signals obtained by a plurality of times of reception of the first transmission synchronization signal, the first control unit controlling the first power converter using the first control cycle,

the second control unit adjusts a phase of a second control cycle so that the second control cycle is synchronized with a timing of a specific second synchronization signal among a plurality of second synchronization signals obtained by receiving the first transmission synchronization signal a plurality of times and receiving the second transmission synchronization signal a plurality of times, using the identification information, and controls the second power converter using the second control cycle.

2. The drive system of claim 1,

the first control unit performs control as follows: removing a first synchronization signal, which does not correspond to the specific first synchronization signal, from the plurality of first synchronization signals, from a target signal when the first control period is synchronized,

the second control unit performs control as follows: and removing a second synchronization signal, which does not correspond to the specific second synchronization signal, from the plurality of second synchronization signals, from the target signal when the second control period is synchronized.

3. The drive system of claim 1,

the length of the reference of the first period and the length of the reference of the first control period are different from each other.

4. The drive system of claim 1,

the main device transmits the first transmission synchronization signal and identification information for identifying the first one of the reference periods to the first driving device in each of the first periods in the reference periods, transmits the second transmission synchronization signal and the identification information to the second driving device in each of the first periods in the reference periods,

the first control unit determines a first reference timing in the reference cycle, which is associated with a time when a specific first transmission synchronization signal is generated, from among a plurality of first synchronization signals obtained by a plurality of times of reception of the first transmission synchronization signal using the identification information, and adjusts a phase of the first control cycle so that the first control cycle is synchronized with the specific first synchronization signal corresponding to the first reference timing,

the second control unit determines, from among a plurality of second synchronization signals obtained by a plurality of times of reception of the second transmission synchronization signal, a second reference timing related to a time when a specific second transmission synchronization signal is generated in the reference period, using the identification information, and the first control unit adjusts a phase of the second control period so that the second control period is synchronized with the specific second synchronization signal corresponding to the second reference timing.

5. The drive system of claim 4,

the host device transmits the first transmission synchronization signal to which the identification information is added to the first drive device and transmits the second transmission synchronization signal to which the identification information is added to the second drive device,

the first control unit adjusts a phase of the first control cycle so that the first control cycle is synchronized with the specific first synchronization signal corresponding to the specific first transmission synchronization signal transmitted at the first reference timing when a value of the identification information added to the first transmission synchronization signal is a constant value having a predetermined value,

the second control unit adjusts the phase of the second control cycle so that the second control cycle is synchronized with the specific second synchronization signal corresponding to the specific second transmission synchronization signal transmitted at the second reference timing, when the value of the identification information added to the second transmission synchronization signal is a constant value having a predetermined value.

6. The drive system of claim 4,

the first control unit adjusts the phase of the first control cycle so that the first control cycle is synchronized with the specific first synchronization signal at a first adjustment timing delayed by a first time from the first reference timing,

the second control unit adjusts the phase of the second control cycle so that the second control cycle is synchronized with the specific second synchronization signal at a second adjustment timing delayed by a second time from the second reference timing.

7. The drive system of claim 6,

the first control unit determines the first adjustment timing based on a first reference time reported from the host device, the first reference time indicating when the specific first transmission synchronization signal is transmitted,

the second control unit determines the second adjustment timing based on a second reference time notified from the host device, the second reference time indicating when the specific second transmission synchronization signal is transmitted.

8. The drive system of claim 1, wherein,

the master device transmits the first transmission synchronization signal and the second transmission synchronization signal at timings different from each other.

9. The drive system of claim 1, wherein,

the master device transmits the first synchronization signal and the second synchronization signal in the first period.

10. The drive system of claim 1,

the first period of the master device is one-M times the reference period,

the first control period of the first control section is one-nth of the reference period,

the second control period of the second control section is one-nth v of the reference period

The value of M and the value of N are integers different from each other in value.

11. The drive system of claim 4,

the first driving device includes a first communication processing unit that outputs the identification information attached to the first transmission synchronization signal and the specific first synchronization signal corresponding to the first transmission synchronization signal,

the first control unit includes:

a first counter that generates a first clock signal by dividing a first reference clock, generates a count value of a first count of a result of counting a wave number of the first clock signal from a start point of the first control period, corrects the count value of the first count according to a condition of a time point of the first reference timing, and generates a second clock of the first control period using either the count value of the first count or the count value of the corrected first count;

a first phase comparator that compares a phase difference between a reference of the phase of the first control period and a reference of the phase of the specific first synchronization signal using the count value of the first count, and generates a correction value for correcting the count value of the first count at a time point of the first reference timing;

a first interrupt signal generation unit that generates a first interrupt signal of a first control period based on the second clock; and

a first control unit main body that starts a first process for controlling the first power converter using the first clock signal based on the first interrupt signal.

12. The drive system of claim 11,

the first phase comparator generates a correction value for correcting the count value of the first count so that a deviation between the reference of the phase of the first control period and the reference of the phase of the specific first synchronization signal becomes small based on the result of the comparison.

13. The drive system of claim 11,

the second driving device includes a second communication processing unit that outputs the identification information appended to the second transmission synchronization signal and the specific second synchronization signal corresponding to the second transmission synchronization signal,

the second control section includes:

a second counter that generates a third clock signal by dividing a second reference clock, generates a count value of a third count of a result of counting a wave number of the third clock signal from a start point of the second control period, corrects the count value of the third count according to a condition of a time point of the second reference timing, and generates a fourth clock of the second control period using either the count value of the third count or the count value of the corrected third count;

a second phase comparator that compares a phase difference between a reference of the phase of the second control period and a reference of the phase of the specific second synchronization signal using the count value of the third count, and generates a correction value for correcting the count value of the third count at the time point of the second reference timing;

a second interrupt signal generation unit that generates a second interrupt signal for a second control period based on the fourth clock; and

and a second control unit main body that starts a second process for controlling the second power converter using the third clock signal, based on the second interrupt signal.

14. The drive system of claim 13,

the second phase comparator generates a correction value for correcting the count value of the third count so that a deviation between the reference of the phase of the second control period and the reference of the phase of the specific second synchronization signal becomes small based on a result of the comparison.

15. The drive system of claim 1,

the first control section controls the first power converter by executing a first interrupt process using a first interrupt signal of the first control cycle,

the second control unit controls the second power converter by executing a second interrupt process using a second interrupt signal of the second control cycle.

16. A drive system is provided with:

a first driving device that drives a first motor based on control and uses power of the first motor for conveyance of an object;

a second driving device that drives a second motor based on control and uses power of the second motor for conveyance of the object; and

a master device that controls the first drive device and the second drive device using a first period and a reference period including a plurality of the first periods,

the master device outputs a first transmission synchronization signal capable of identifying the first cycle in the reference cycle for each of the first cycles,

the first driving device receives the first transmission synchronization signal a plurality of times, selects a specific first synchronization signal corresponding to a first reference timing in the reference cycle from a plurality of first synchronization signals obtained by the plurality of times of reception of the first transmission synchronization signal, and adjusts a first control timing at which a process related to control of the first motor is started using the specific first synchronization signal,

the second driving device receives the first transmission synchronization signal a plurality of times, selects a specific second synchronization signal corresponding to the first reference timing from a plurality of second synchronization signals obtained by the plurality of times of reception of the first transmission synchronization signal, and adjusts a second control timing at which a process related to control of the second motor is started using the specific second synchronization signal.

Technical Field

Embodiments of the present invention relate to a drive system.

Background

The drive system drives motors provided in the plurality of drive devices, respectively. In applications where objects are conveyed at a desired speed by the power of each motor, it is necessary that the motors have good uniform speed (japanese: speed performance). In contrast, there is a drive system in which it is difficult to further improve the constant speed performance of a plurality of motors.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2007-213474

Disclosure of Invention

Problems to be solved by the invention

The present invention aims to provide a drive system capable of further improving the same speed performance of a plurality of motors.

Means for solving the problems

The drive system of the embodiment includes a first drive device, a second drive device, and a host device. The first driving device includes a first power converter that supplies first electric power to a winding of a first motor, and a first control unit that controls the first power converter. The second driving device includes a second power converter that supplies second electric power to a winding of a second motor, and a second control unit that controls the second power converter. The host device controls the first control unit and the second control unit using a first cycle and a reference cycle including a plurality of the first cycles. The master device transmits the identification information of the first cycle and a first transmission synchronization signal for each of the first cycles in the reference cycle, or transmits the identification information of the first cycle, a first transmission synchronization signal and a second transmission synchronization signal for each of the first cycles in the reference cycle. The first control unit adjusts a phase of the first control cycle using the identification information so that the first control cycle is synchronized with a timing associated with a specific first synchronization signal among a plurality of first synchronization signals obtained by a plurality of times of reception of the first transmission synchronization signal, and controls the first power converter using the first control cycle. The second control unit adjusts a phase of the second control cycle using the identification information so that the second control cycle is synchronized with a timing of a specific second synchronization signal among a plurality of second synchronization signals obtained by one of reception of the first transmission synchronization signal and reception of the second transmission synchronization signal a plurality of times, and controls the second power converter using the second control cycle.

Drawings

Fig. 1 is a configuration diagram of a drive system of a first embodiment.

Fig. 2 is a configuration diagram of a host apparatus according to the first embodiment.

Fig. 3A is a configuration diagram of a first driving device of the first embodiment.

Fig. 3B is a configuration diagram of a second driving device of the first embodiment.

Fig. 4 is a flowchart of the speed adjustment process performed by the drive device of the first embodiment.

Fig. 5 is a diagram for explaining a phase relationship between control cycles of the host device and the drive device in the first comparative example.

Fig. 6 is a diagram for explaining an operation when the length of the control period of the host device and the length of the synchronization period of the drive device are different from each other in the second comparative example.

Fig. 7 is a diagram for explaining an operation when the main device, the first drive device, and the second drive device of the first embodiment are combined.

Fig. 8 is a configuration diagram of the first driving device of the first embodiment.

Fig. 9 is a configuration diagram of a host apparatus according to the second embodiment.

Fig. 10A is a configuration diagram of a first driving device of the second embodiment.

Fig. 10B is a configuration diagram of a second driving device of the second embodiment.

Fig. 11 is a diagram for explaining a transmission time data table according to the second embodiment.

Fig. 12 is a diagram for explaining a correction calculation data table according to the second embodiment.

Fig. 13 is a diagram for explaining the adjustment of the phase of the control cycle by the driving device of the second embodiment.

Fig. 14A is a configuration diagram of a drive system of the first modification.

Fig. 14B is a configuration diagram of a drive system of a second modification.

Fig. 14C is a configuration diagram of a drive system of a third modification.

Detailed Description

Hereinafter, a drive system according to an embodiment will be described with reference to the drawings.

In the following description, a drive system that performs the same-speed control will be referred to simply as a drive system. In addition, the same reference numerals are given to components having the same or similar functions. Moreover, a repetitive description of these configurations may be omitted. In addition, the electrical connection may be simply referred to as "connection".

(first embodiment)

Fig. 1 is a configuration diagram of a drive system 1 of the first embodiment.

The drive system 1 includes, for example, a host device 10, and first to fourth drive devices 31 to 34. The first motor 21 to the fourth motor 24 are examples of motors to be controlled by the drive system 1.

Fig. 1 also shows an example of a manufacturing facility related to the drive system 1.

The manufacturing facility shown in fig. 1 includes, for example, first to fourth rolling stands ST1 to ST4 for conveying an object. The first rolling stand ST1 is provided with a first motor 21, the second rolling stand ST2 is provided with a second motor 22, the third rolling stand ST3 is provided with a third motor 23, and the fourth rolling stand ST4 is provided with a fourth motor 24. The first to fourth rolling stands ST1 to ST4 are driven by the power of the first to fourth motors 21 to 24.

The first motor 21 is driven by a first drive device 31. The second motor 22 is driven by a second drive device 32. The third motor 23 is driven by a third drive device 33. The fourth motor 24 is driven by a fourth drive 34. In the case where the first to fourth motors 21 to 24 are not distinguished, only the motor 20 is referred to. In the case where the first to fourth driving devices 31 to 34 are not distinguished, only the driving device 30 is referred to. The respective driving devices 30 simultaneously operate the respective motors 20, and drive the first rolling stand ST1 to the fourth rolling stand ST4 by the power output from the respective motors 20. Thereby, at least the object relatively long in the first direction is conveyed in the extending direction (first direction) of the object. The drive devices 30 operate the motors 20 simultaneously includes a case where the drive devices 30 are controlled in parallel to operate the motors 20, or a case where the drive devices 30 cooperate to operate the motors 20. This manufacturing facility can be applied to, for example, a rolling process of steel (object). Alternatively, the drive system 1 is not limited thereto, and may be applied to a manufacturing process of paper or the like.

The main apparatus 10 (higher-level controller) transmits a command value to each of the drive devices 30 via the network NW, and adjusts the conveyance amount and conveyance speed of the object by each of the motors 20 by controlling each of the drive devices 30 using the command value. The main apparatus 10 keeps the object in a good conveyance state by adjusting the rotation speed of the motor 20 by each of the driving devices 30 (at the same speed). The Network NW is, for example, a wired LAN (Local Area Network). The network NW according to the embodiment is configured to connect the host device 10 and each of the drive devices 30 by a bus. The type of the network NW is not limited to this, and other types of networks having different connection methods may be appropriately selected. The host device 10 and each drive device 30 communicate various information as packets via the network NW.

A more specific example of the host device 10 will be described with reference to fig. 2. Fig. 2 is a configuration diagram of the host device 10 according to the first embodiment.

The host device 10 includes, for example, an interface unit 11 (shown as IF in fig. 2), a counter 13, an interrupt signal generation unit 14 (shown as INTR-PROC in fig. 2), a storage unit 15 (shown as STRAGE in fig. 2), and a control unit main body 16 (shown as M _ CONT in fig. 2).

The interface unit 11 communicates with each of the drive devices 30 via the network NW, receives various information provided by the host device 10 from the control unit main body 16, and transmits the information to each of the drive devices 30.

The counter 13 counts the wave number of a signal of a fixed period supplied from an oscillator not shown in fig. 2, and supplies a clock for discrete time control of the control unit main body 16 to the control unit main body 16. The counter 13 divides the clock by a predetermined number to generate an M clock signal of a first period, and supplies the generated M clock signal of the first period to the interrupt signal generating unit 14. Thereby, the interrupt cycle of the interrupt signal generation unit 14 is executed.

The interrupt signal generation unit 14 generates an interrupt signal related to the M clock signal supplied from the counter 13, and supplies the interrupt signal to the control unit main body 16.

The standard length is a design specification and the actual first period is allowed to vary within a design tolerance. The first period including the fluctuation amount is referred to as a fixed period.

The storage unit 15 is implemented by a ROM (Read Only Memory), a RAM (Random Access Memory), an HDD (Hard Disk Drive), a flash Memory, or the like. The storage unit 15 is allocated with a storage area for storing various setting information for causing the control unit main body 16 to function, basic programs such as an OS, and application programs.

The control unit main body 16 is connected to a bus not shown in fig. 2 together with the interface unit 11 and the storage unit 15.

The control unit main body 16 includes a first processor that executes a software program. The first processor is sometimes referred to as a CPU (Central Processing Unit), FPGA (field-programmable Gate array). The software program executed by the first processor of the control unit main body 16 may be stored in the storage unit 15 in advance, or may be downloaded from an external device, a portable storage medium, or the like, which are not shown in fig. 2, or may be downloaded via the network NW. The control unit main body 16 executes a software program to form all functions of the control unit main body 16 and a part of the functions of the interrupt signal generation means 14, which will be described below.

The control unit main body 16 generates a command value COM _ i for controlling each drive device 30, and then supplies the command value COM _ i to each drive device 30. "i" is an integer corresponding to the identification information i associated with the first cycle. For example, when the control unit main body 16 detects the interrupt signal supplied from the interrupt signal generating means 14, the command value COM _ i of each drive device 30 is generated for each first cycle, and the command values COM _ i of each drive device 30 are supplied to each drive device 30 in a predetermined order. For example, the control unit main body 16 supplies the command value COM _ i for all the drive devices 30 in each first cycle.

The control unit main body 16 uses a reference cycle having a period of a multiple of the first cycle as a cycle in order to synchronize the control cycles of the respective driving devices 30. The control unit main body 16 associates identification information i for uniquely identifying each first period within the reference period with each first period. For example, the control unit main body 16 sets the identification information i on the starting point side of the reference period to 0, and monotonically increases the value of the identification information i associated with each first period in succession thereafter. The control unit main body 16 adds the identification information i to information (packet) transmitted to each drive device 30 and transmits the information.

The host device 10 generates a synchronization signal (for example, referred to as a first transmission synchronization signal) for synchronizing the speeds of the drive devices 30 at every first cycle. Then, the host device 10 supplies the first transmission synchronization signal packetized for each first cycle to the first to fourth drive devices 31 to 34.

The control unit main body 16 gives the value of the identification information i associated with each first cycle to the first transmission synchronization signal and transmits it. The control unit main body 16 transmits a common first transmission synchronization signal to each of the driving devices 30. The control unit main body 16 may transmit the command value COM _ i for each drive device 30 separately from the first transmission synchronization signal, or may transmit the command value COM _ i together with the first transmission synchronization signal.

A more specific example of each driving device 30 will be described with reference to fig. 3A and 3B. Fig. 3A is a configuration diagram of the first driving device 31 of the first embodiment.

The first driving device 31 includes, for example, a first power converter 311, a first control unit 312, and a first communication processing unit 313. The first power converter 311 supplies first electric power for conveying an object to a winding (not shown) of the first motor 21.

In order to control the motor 20 of the ac motor using the dc power POW, the first power converter 311 functions as a so-called inverter and converts the dc power POW into ac power. The above is an example, and is not limited thereto. For example, in order to control the motor 20 of the dc motor using the ac power POW, the first power converter 311 converts the ac power POW into dc power as a so-called inverter. The specifications of the first power converter 311 and the second power converter 321 are determined by the specification of the electric motor 20 and the specification of the power source, and therefore, may be other types than those described above. In the following description, a case where the motor 20 is an ac motor will be described.

The first power converter 311 (denoted as PC in fig. 3A) includes, for example, a plurality of semiconductor switches not shown in fig. 3A and a driving circuit thereof, and the plurality of semiconductor switches are formed in a full bridge type or a half bridge type, for example. The circuit form of the first power converter 311 is not limited to this, and may be changed as appropriate. The type of the plurality of semiconductor switches may be any of, for example, an IGBT (Insulated Gate Bipolar Transistor) and an FET (Field-Effect Transistor), and is not limited to this type, and other types of semiconductor switches may be applied, and diodes may be appropriately combined.

The first control section 312 controls the first power converter 311.

The first control UNIT 312 includes, for example, a first control UNIT main body 3121 (described as S _ CONT in fig. 3A), a first interrupt signal generation UNIT 3122 (described as INTR in fig. 3A), a phase adjustment UNIT 3123 (described as PA _ UNIT in fig. 3A), and a comparator 3124.

The first control portion main body 3121 generates a first gate signal GP for driving the first electric motor 21 in accordance with the command value COM _ i supplied from the host device 10, and then supplies the first gate signal GP to the first power converter 311. For example, the first control portion main body 3121 may generate the first gate signal GP by using the information of the position of the shaft of the first electric motor 21 and the information of the output state of the first power converter 311 for discrete time control of the feedback amount of the feedback control. When the first control portion main body 3121 detects an interrupt signal supplied from a first interrupt signal generation unit 3122 described later, processing for control related to driving of the first motor 21 is started, and then the started processing is executed in one or more control cycles of discrete time control. For example, the first control portion main body 3121 may perform a process (first process) for controlling the first power converter 311 by discrete time control in synchronization with a cycle of a first clock signal, using the first clock signal described later.

The first interrupt signal generation unit 3122 generates an interrupt signal at an interval adjusted to a standard length, and supplies the interrupt signal to the first control portion main body 3121. The period adjusted to the standard length is referred to as a first control period. The standard length is a design specification, and the actual first control period is allowed to vary within a design allowance.

The comparator 3124 outputs a result of identifying the first cycle of the master device 10 with a logical value using the identification information i. The comparator 3124 outputs a logic 1 when it is determined from the value of the identification information i that the first cycle of the host device 10 is a desired cycle determined by the user, in other words, when the identification information i is a desired value, and outputs a logic 0 when the first cycle of the host device 10 is not a desired cycle.

The phase adjustment unit 3123 supplies the first clock used by the first control portion main body 3121 for discrete time control to the first control portion main body 3121, and supplies the second clock that is the source of the first control cycle to the first interrupt signal generation unit 3122. The phase adjustment unit 3123 adjusts the second clock so that the second clock has a standard length, for example, based on the timing information on the first transmission synchronization signal supplied from the host device 10 and the comparison result of the comparator 3124. The details of the phase adjustment unit 3123 including the contents related to the generation of the first clock and the second clock will be described later.

The first communication processing unit 313 communicates with the host apparatus 10 via the network NW, and supplies various information acquired from the host apparatus 10 to the first control unit 312.

For example, the first communication processing unit 313 includes an interface unit 3131 (described as IF in fig. 3A) and an extraction processing unit 3133 (described as EXTR in fig. 3A).

The interface unit 3131 is connected to a network NW, and communicates with the host device 10 via the network NW to acquire various information transmitted by the host device 10. The various information transmitted by the host device 10 includes information relating to a command value COM _ i that the host device 10 commands the first drive device 31, and identification information i relating to a control cycle of the host device 10.

Extraction processing section 3133 acquires various information transmitted from host device 10 from interface section 3131, extracts the acquired information, and supplies the extracted information to each supply destination.

Extraction processing section 3133 supplies identification information i (identification information i indicating the control cycle in which the packet was transmitted) given to the packet of the first transmission synchronization signal transmitted by host device 10, and a first synchronization signal (described as SYNC _ S1 in fig. 3A) indicating the timing at which the packet was received, to phase adjustment section 3123.

For example, an arbitrary integer, for example, 0, is set in the first input a of the comparator 3124, and identification information i for identifying the control cycle of the host device 10 is supplied from the first communication processing unit 313 to the second input b. In this case, when the identification information i is 0, the comparator 3124 detects that the control cycle of the host device 10 is 0, and outputs a logic 1.

As described above, the first control unit 312 can obtain both the first synchronization signal and the identification information i output from the extraction processing unit 3133.

The second driving device 32 shown in fig. 3B will be explained.

Fig. 3B is a configuration diagram of the second driving device 32 of the first embodiment. The second driving device 32 shown in fig. 3B includes, for example, a second power converter 321, a second control unit 322, and a second communication processing unit 323.

The second power converter 321 supplies second electric power for conveying the object to a winding (not shown) of the second motor 22. The second control unit 322 controls the second power converter 321. The second communication processing unit 323 communicates with the host apparatus 10. The second power converter 321, the second control unit 322, and the second communication processing unit 323 correspond to the first power converter 311, the first control unit 312, and the first communication processing unit 313 described above. The second power converter 321, the second control unit 322, and the second communication processing unit 323 may have the same configurations as those of the first power converter 311, the first control unit 312, and the first communication processing unit 313 described above. The same reference numerals are given to the second driving device 32 in place of the 100-bit values of the reference numerals of the first driving device 31, and detailed description thereof is omitted.

The speed adjustment process performed by the first drive device 31 will be described with reference to fig. 4.

Fig. 4 is a flowchart of the speed adjustment process performed by the first driving device 31 of the first embodiment. For example, the first control unit 312 of the first drive device 31 performs the following processing as the speed adjustment.

The first control unit 312 receives the first transmission synchronization signal transmitted from the host device 10 and the identification information i for identifying each first period in the reference period (step S12).

The first control unit 312 determines whether or not the value of the identification information i is equal to the constant C (step S16). The value of the constant C is predetermined, and may be 0, for example.

When the value of the identification information i is not equal to the constant C, the first control unit 312 ends the series of processes. When the value of the identification information i is equal to the constant C, the first control unit 312 calculates the deviation X (step S18). For example, the deviation X is a phase difference between the phase of the reference cycle of the host device 10 and the phase of the first control unit 312.

The first control unit 312 determines whether the absolute value of the deviation X is smaller than a predetermined threshold TH (step S20). When the absolute value of the deviation X is smaller than the threshold TH, the first control unit 312 ends the series of processing.

When the absolute value of the deviation X exceeds the threshold TH, the first control unit 312 calculates the integrated value Y of the interrupt counter based on the deviation X (step S22). For example, the threshold TH is a positive real number near 0.

Next, the first control unit 312 writes and updates the accumulated value Y in the variable area in order to change the current value of the interrupt counter of the variable area stored in the storage area of the storage unit 314 (fig. 8) to the calculated accumulated value Y of the interrupt counter (step S24). Further, the first counter 31232 sequentially updates the value of the variable region independently of the processing of step S24.

The first control unit 312 performs the above processing to synchronize the first drive device 31 with the host device 10.

The second control unit 322 of the second drive device 32 performs the same processing as the first control unit 312 shown in fig. 4, thereby enabling the second drive device 32 to be synchronized with the host device 10.

Hereinafter, control for synchronizing the control cycle of each drive device 30 with the timing of supply by the host device 10 will be described.

Referring to fig. 5 and 6, a comparative example will be described for comparison with the embodiment. Fig. 5 is a diagram for explaining the phase relationship between the control cycles of the host device # M and the drive devices #11 and #12 of the first comparative example. The control periods of the master device # M and the drive devices #11 and #12 of the first comparative example are equal to each other in length.

The first level in fig. 5 shows a triangular wave (Ma) and a rectangular wave (Mb) related to the control period of the host apparatus # M, the second level in fig. 5 shows a triangular wave (11a) and a rectangular wave (11b) related to the control period of the drive apparatus #11, and the third level in fig. 5 shows a triangular wave (12a) and a rectangular wave (12b) related to the control period of the drive apparatus # 12.

For example, the triangular wave (Ma) of the first layer in fig. 5 represents the count value of the clock (or step size) used for control by the master device # M. For example, a counter (not shown) of the master device # M counts the number of detected clocks, and the count value is represented by values from 0 to MAX # M. When the count value of the counter sequentially increases to MAX # M, the counter sets the count value to 0 when the next clock is detected. For example, when the count value is set to 0, the master apparatus # M executes an interrupt process of a fixed cycle. The timing of the interrupt processing is represented by a square wave (Mb).

The master device # M uses the rectangular wave (Mb) of the first layer in fig. 5 as a trigger for interrupt processing of the pulses MP1 to MP4, and performs processing related thereto in each control cycle.

The descriptions of the triangular wave and the rectangular wave of the second layer and the third layer in fig. 5 are the same as the descriptions of the triangular wave and the rectangular wave of the first layer in fig. 5, and reference can be made to the descriptions. Note that the point at which the count value of the clock of the driver #11 changes from 0 to MAX #11, the point at which the count value of the clock of the driver #12 changes from 0 to MAX #12, and the points at which the drivers #11 and #12 respectively serve as triggers for performing interrupt processing on the pulses SP1 to SP4 are different.

Here, when the rectangular wave (Mb) of the first layer in fig. 5 is compared with the rectangular wave (11b) of the second layer in fig. 5, the positions in the time axis direction of the first to fourth control periods corresponding to the pulses MP1 to MP4 of the first layer coincide with the positions in the time axis direction of the first to fourth control periods corresponding to the pulses SP1 to SP4 of the second layer. This state indicates a state in which the phase of the control cycle of the host apparatus # M and the phase of the control cycle of the drive apparatus #11 are not out of phase with each other.

In contrast, when the rectangular wave (Mb) of the first layer in fig. 5 is compared with the rectangular wave (12b) of the third layer in fig. 5, the positions in the time axis direction of the first to fourth control periods corresponding to the pulses MP1 to MP4 of the first layer and the positions in the time axis direction of the first to fourth control periods corresponding to the pulses SP1 to SP4 of the third layer are shifted from each other. This state indicates a state in which the phase of the control cycle of the host apparatus # M and the phase of the control cycle of the drive apparatus #12 are out of phase with each other.

In this state, for example, even if the host apparatus # M transmits a speed change command to the drive apparatus #11 and the drive apparatus #12 at time ta1 and the drive apparatus #11 and the drive apparatus #12 can simultaneously receive the speed change command, a deviation occurs at the time of starting the processing of the control cycle for processing the speed change command. This is because, as shown in fig. 5, a phase difference occurs in the control period of the drive device #11 and the control period of the drive device # 12. For example, the hatching given to the rectangular waves (Mb), (11b), and (12b) of each layer in fig. 5 indicates the control cycle in which each drive device 30 processes the speed change command transmitted at time ta 1. In this way, if a phase difference occurs in the control cycles, the timing at which the electric power supplied to each motor is switched also varies. The maximum value of the deviation in the time axis direction is the length of the control period common to the drive device #11 and the drive device # 12. Therefore, if the drive device #11 and the drive device #12 of the first comparative example do not synchronize with each other, the influence of the phase difference of the respective control periods may not be completely reduced, and it is difficult to ensure the same speed.

With reference to fig. 6, an operation in the second comparative example in which the lengths of the control cycles of the host device and the drive device are different from each other will be described. Fig. 6 is a diagram for explaining an operation when the length of the control cycle of the host device and the length of the control cycle of the drive device in the second comparative example are different from each other. The length of the control period of the main device and the length of the control period of the drive device shown in fig. 6 are different from each other. Therefore, the control cycle of the host device and the control cycle of the drive device do not coincide with each other in the second comparative example, and therefore, the influence of the phase difference of the control cycles cannot be reduced, and the synchronism cannot be improved.

A combination of the host device 10, the first drive device 31, and the second drive device 32 will be described with reference to fig. 7. Fig. 7 is a diagram for explaining an operation when the main device 10, the first drive device 31, and the second drive device 32 according to the first embodiment are combined. As shown in the embodiment, the length of the control period (first period) of the host device 10 and the length of the first control period of the first drive device 31 are different from each other, and the length of the second control period of the second drive device 32 is different from each other.

The first level in fig. 7 shows triangular waves (10a), (10c) and a rectangular wave (10b) associated with the control period of the host device 10, the second level in fig. 7 shows triangular waves (31a), (31c) and a rectangular wave (31b) associated with the control period of the first drive device 31, and the third level in fig. 7 shows two triangular waves (32a), (32c) and a rectangular wave (32b) associated with the control period of the second drive device 32.

The two triangular waves (for example, the triangular wave (10a) and the triangular wave (10c)) described in each layer in fig. 7 have different lengths of one period in the time axis direction. One cycle of the triangular wave (10a) is shorter than one cycle of the triangular wave (10c) in the time axis direction. The relationship between the triangular wave (10a) and the rectangular wave (10b) corresponds to the relationship between the triangular wave (Ma) and the rectangular wave (Mb) in each layer in fig. 5. The second and third layers in fig. 7 are also in the same orientation.

In addition, the first period of the host device 10 is M times the reference period. The first cycle of the host device 10 corresponds to the cycle of the triangular wave (10a), and the reference cycle of the host device 10 corresponds to the cycle of the triangular wave (10 c). The first control period of the first control section 312 is one N times the reference period. The first control cycle of the first control unit 312 corresponds to the cycle of the triangular wave (31a), and the reference cycle of the first control unit 312 corresponds to the cycle of the triangular wave (31 c). The second control period of the second control unit 322 is one-N of the reference period described above. The second control cycle of the second control unit 322 corresponds to the cycle of the triangular wave (32a), and the reference cycle of the second control unit 322 corresponds to the cycle of the triangular wave (32 c). The value of M and the value of N are integers different from each other.

The values of the triangular waves (10a), (31a), and (32a) having one period shorter in the time axis direction are count values of clocks used by the host device 10 and the drive device 30 for the respective processes. For example, the value of the triangular wave (a) of the host device 10 is the count value of the counter 13. The value of the triangular wave (31a) of the first driving device 31 is the count value of the first counter 31232 within the phase adjustment unit 3123. The value of the triangular wave (32a) of the second driving device 32 is the count value of the second counter 32232 in the phase adjusting unit 3223.

For example, the first control unit 312 of the first drive device 31 acquires the state of the first electric motor 21 and the state of the first power converter 311 before the count value of the first counter 31232 changes from 0 to k1 (process a), generates a command value for the first power converter 311 before the count value changes from k1 to k2 (process B), and generates the first gate pulse GP for driving the first electric motor 21 before the count value changes from k2 to kMAX31 (process C). The first control unit 312 performs the above-described processes a to C in one first control cycle in which the count value of the first counter 31232 changes from 0 to kmax, and repeats the processes a to C for each first control cycle.

Then, the second controller 322 of the second driving device 32 acquires the state of the second electric motor 22 and the state of the second power converter 321 before the count value of the second counter 32232 changes from 0 to k1, generates a command value for the second power converter 321 before the count value thereof changes from k1 to k2, and generates the second gate pulse GP for driving the second electric motor 22 before the count value thereof changes from k2 to kMAX 32. The second control unit 322 performs the above-described processes a to C in one second control cycle in which the count value of the second counter 32232 changes from 0 to kmax, and repeats the processes a to C for each second control cycle. The processing a to the processing C are one example of the first processing.

The triangular wave (10c) having one cycle longer in the time axis direction is shown for the sake of explanation, and the drive system 1 may not count the value thereof.

For example, the period (referred to as a reference period) of the triangular wave (10c) shown in the first layer of fig. 7 is N times the control period of the host device 10. The waveform shown in fig. 7 is a waveform obtained when the value of N is 1000, and a part of the waveform is omitted. The number of the rectangular wave (10b) shown along the first layer of fig. 7 is the value of the identification information i of the control period that increases in order from 0 to 999. The amplitude of the triangular wave (10c) schematically represents the value of the identification information i. The actual identification information i does not change continuously but changes stepwise in synchronization with the timing of switching of the control cycle.

The state of the first drive device 31 shown in the second layer of fig. 7 is a state in which the deviation X is 0 because the phase is well adjusted by using a certain first control period for phase adjustment with the reference period of the host device 10. M times the first control period coincides with the reference period of the host device 10. The waveform shown in the second layer of fig. 7 is a waveform in which the value of M is 1024. The number along the rectangular wave (31b) is the value of the identification information j of the control period that sequentially increases from 0 to 1023. The amplitude of the triangular wave (31c) schematically represents the value of the identification information j. The actual identification information j does not change continuously but changes stepwise in synchronization with the switching timing of the first control cycle.

In the state of the second driving device 32 shown in the third layer of fig. 7, the phase of the control cycle is not adjusted well, and therefore, the deviation X is generated. The description of each waveform is the same as that of the first driving device 31 of the second layer in fig. 7. The second driving device 32 shown in the third layer of fig. 7 is different from the first driving device 31 shown in the second layer of fig. 7 in that the state of the first driving device 31 shown in the second layer of fig. 7 coincides with the timing of the reference cycle of the host device 10, whereas the state of the second driving device 32 shown in the third layer of fig. 7 is different from the state of the reference cycle.

The processing of the first driving device 31 will be described with reference to the first layer and the second layer of fig. 7.

The first driving device 31 determines a specific first synchronization signal among the plurality of first synchronization signals obtained by receiving the first transmission synchronization signal a plurality of times using the identification information i, and adjusts the phase of the specific first synchronization signal. The plurality of first synchronization signals in fig. 7 correspond to the rectangular wave (31b) of the second layer in fig. 7. The specific first synchronization signal in this case is one rectangular wave (pulse) corresponding to the timing at which the identification information i changes from 999 to 0 among the rectangular waves (pulses) corresponding to the values (0 to 1023) of the identification information j. Therefore, the first control unit 312 of the first driving device 31 can adjust the phase of the period (first control period) of the rectangular wave (31b) of the first driving device 31 so as to synchronize the period (first control period) of the rectangular wave (31b) of the first driving device 31 with the timing at which the identification information i changes from 999 to 0.

In the above case, the control period of the host device 10 (the period of the pulse of the rectangular wave (10b) of the first layer in fig. 7) and the control period of the first driving device 31 (the period of the pulse of the rectangular wave (31b) of the second layer in fig. 7) are strictly different. In the phase relationship as shown in fig. 7, the first control cycle in which the identification information j of the first drive device 31 is identified as 0 and the control cycle in which the identification information i of the host device 10 is identified as 0 are close in phase to each other. Therefore, the first driving device 31 adjusts the phase of the rectangular wave (31b) of the first driving device 31 shown in the second layer of fig. 7 at a control cycle in which the identification information i added to the rectangular wave (10b) of the host device 10 shown in the first layer of fig. 7 is 0.

Even in the case of such adjustment to a good phase relationship, the phase of the reference of the rectangular wave of the host device 10 whose identification information i of the first layer of fig. 7 is 1 to 999 does not coincide with the phase of the reference of the rectangular wave of the first drive device 31 whose identification information j of the second layer of fig. 7 is 1 to 1023. Therefore, the first drive device 31 can stably adjust the phase with respect to the reference cycle of the host device 10 by performing control so that the phase is adjusted when the identification information i is 0 and is not adjusted when the identification information i is other than 0.

In contrast, the second drive device 32 shown in the third layer of fig. 7 has a phase relationship in which the identification information j added to the rectangular wave (32b) of the second drive device 32 shown in the third layer of fig. 7 is not 0 even when the identification information i added to the rectangular wave (10b) of the main device 10 shown in the first layer of fig. 7 is 0. Therefore, the phase of each waveform shown in the third layer of fig. 7 is different from the phase of each waveform shown in the second layer of fig. 7 showing a state where the deviation X does not occur due to matching with the phase of the reference period of the host device 10, and the deviation X occurs with respect to the phase of the reference period of the host device 10.

When the phase relationship is as shown in the third layer of fig. 7, the second control unit 322 of the second drive device 32 adjusts the phase of the second control cycle in the same manner as the first control unit 312 of the first drive device 31. More specifically, the second driving device 32 determines a specific second synchronization signal among the plurality of second synchronization signals obtained by receiving the first transmission synchronization signal a plurality of times, using the identification information i, and adjusts the phase of the specific second synchronization signal, as in the first driving device 31. The second synchronization signal and the specific second synchronization signal processed by the second driving device 32 are signals inside the second driving device 32, and correspond to the first synchronization signal and the specific first synchronization signal of the first driving device 31 of different devices, respectively. Thus, the second control unit 322 of the second drive device 32 can match the phase of the second control period with the phase of the reference period of the host device 10 shown in the first layer, and as a result, can obtain waveforms having the phase relationship shown in the second layer of fig. 7.

Further, the same processing is performed by each of the driving devices 30 other than the first driving device 31 and the second driving device 32, so that the reference phase of the rectangular wave of the host device 10 matches the reference phase of the rectangular wave of each of the driving devices 30.

Fig. 8 is a configuration diagram of the first driving device 31 of the embodiment.

The first drive device 31 includes, for example, a storage unit 314 (illustrated as STRAGE in fig. 8), an input/output unit 315, and an arithmetic processing unit 316. The first driving device 31 is an example of a computer.

The storage unit 314 is implemented by ROM, RAM, HDD, flash memory, or the like. The storage unit 314 is allocated with a storage area for storing various setting information for causing the first control unit 312 to function, basic programs such as an OS, application programs, and the like.

The input/output unit 315 acquires, for example, information on the position of the shaft of the first electric motor 21 and information on the output state of the first power converter 311 as input information, and outputs the gate signal GP. The input/output unit 315 may include a display unit such as a liquid crystal display for displaying various information and an operation detection unit. The display unit and the operation detection unit may be configured as a touch panel in which these units are combined.

The arithmetic processing unit 316 includes a second processor that executes a software program. The second processor is sometimes referred to as a CPU, FPGA. The arithmetic processing unit 316 is connected to the BUS together with the first communication processing unit 313, the storage unit 314, and the input/output unit 315. The arithmetic processing unit 316 executes software programs to form a part or all of the functions of the first control portion main body 3121, the first interrupt signal generation unit 3122, the phase adjustment unit 3123, and the comparator 3124.

The software program executed by the second processor of the arithmetic processing unit 316 may be stored in the storage unit 314 in advance, downloaded from an external device, a portable storage medium, or the like, not shown, or downloaded via a communication line.

A part or all of the range of the first communication processing unit 313 other than the hardware for connecting to the network NW may be formed by executing a software program of the arithmetic processing unit 316, or may be formed by an arithmetic processing unit different from the arithmetic processing unit 316.

According to the above embodiment, the drive system 1 includes the first drive device 31, the second drive device 32, and the host device 10. The master device 10 transmits the identification information of the first cycle and the first transmission synchronization signal every first cycle in the reference cycle. The first control unit 312 of the first drive device 31 adjusts the phase of the first control cycle using the identification information so that the first control cycle is synchronized with the timing (referred to as a first reference timing) associated with a specific first synchronization signal among the plurality of first synchronization signals obtained by receiving the first transmission synchronization signal a plurality of times. Further, first control unit 312 controls first power converter 311 using the first control cycle. The second control unit 322 of the second drive device 32 adjusts the phase of the second control period using the identification information so that the second control period is synchronized with a timing (referred to as a second reference timing) related to a specific second synchronization signal among the plurality of second synchronization signals obtained by receiving the first transmission synchronization signal a plurality of times. Further, the second control unit 322 controls the second power converter 321 using the second control cycle. This enables the drive system 1 to further improve the synchronization between the plurality of motors 20.

The specific first synchronization signal may be a first synchronization signal corresponding to the time when the first drive device 31 detects the identification information i of the specific value. Similarly, the specific second synchronization signal may be a second synchronization signal corresponding to when the second driving device 32 detects the identification information i of the specific value. In addition, the first driving device 31 may determine the specific first synchronization signal using the value of the common identification information i. The second drive means 32 may determine the specific second synchronization signal using the value of the common identification information i.

In addition, the first control portion 312 may control as follows: a first synchronization signal that does not correspond to a specific first synchronization signal is removed from a target signal when synchronizing the first control period, from among the plurality of first synchronization signals. The second control section 322 can also perform control as follows: the second synchronization signal that does not correspond to the specific second synchronization signal is removed from the target signal when the second control period is synchronized, from among the plurality of second synchronization signals.

For example, the first driving device 31 may receive the first transmission synchronization signal a plurality of times, select a specific first synchronization signal corresponding to the first reference timing in the reference cycle from a plurality of first synchronization signals obtained by the plurality of times of reception of the first transmission synchronization signal, and adjust the first control timing at which the process related to the control of the first motor 21 is started using the specific first synchronization signal. The second driving device 32 may receive the first transmission synchronization signal a plurality of times, select a specific second synchronization signal corresponding to the first reference timing from a plurality of second synchronization signals obtained by receiving the first transmission synchronization signal a plurality of times, and adjust the second control timing at which the process related to the control of the second motor 22 is started using the specific second synchronization signal.

In this way, the first control unit 312 and the second control unit 322 select the target signal, respectively, and the drive system 1 can further improve the synchronization of the plurality of motors 20.

When the target signal for adjusting the phase is limited as described above, the reference length of the first period for control by the host device 10 and the reference length of the first control period of the first drive device 31 and the second control period of the second drive device 32 may be different from each other. Further, by performing control so as to remove a part of the plurality of first synchronization signals and a part of the plurality of second synchronization signals from the target signal for phase adjustment, the drive system 1 can control the first motor 21 and the second motor 22 separately while ensuring the same speed of the first motor 21 and the second motor 22.

By making the main device 10 cooperate with the first driving device 31 and making the main device 10 cooperate with the second driving device 32, the main device 10 can control the first driving device 31 and the second driving device 32.

(second embodiment)

A drive system 1A of a second embodiment will be explained.

The drive system 1A is configured in the same manner as the drive system 1 of fig. 1, for example. The host device 10 in the drive system 1A according to the first embodiment transmits a common first transmission synchronization signal to each drive device 30. In the second embodiment, the host device 10A transmits a transmission synchronization signal to each of the drive devices 30A individually.

Fig. 9 is a configuration diagram of a host apparatus 10A according to the embodiment.

The master device 10A further includes a TIMER 12 (indicated as TIMER in fig. 2) for the above-described master device 10.

The timepiece 12 includes, for example, a timepiece not shown in fig. 9, and a timepiece adjustment unit that performs time alignment processing of the timepiece. The timer 12 communicates with each drive device 30A via the interface unit 11 and the network NW. The timer 12 communicates with each of the driving devices 30A, and adjusts the time thereof on the side of each of the driving devices 30A so that the time information on the side of each of the driving devices 30A matches the time information on the side of the host device 10. The master device 10A may use a known protocol in the processing related to the adjustment at that time. For example, a protocol for adjusting the time may be PTP (Precision time protocol: IEEE (institute of Electrical and Electronics Engineers) 1588). In the above case, when transmitting a signal (packet) to the network NW, the interface unit 11 adds the time information of the timer 12 to the packet and transmits the packet.

The host device 10A generates a synchronization signal (referred to as a transmission synchronization signal) for synchronizing the respective drive devices 30. For example, the host device 10A generates transmission synchronization signals for individually transmitting to the drive devices 30.

More specifically, the master device 10A generates a first transmission synchronization signal and a second transmission synchronization signal every first cycle. The first transmission synchronization signal and the second transmission synchronization signal are examples of the transmission synchronization signal described above. After that, the host device 10A supplies the first transmission synchronization signal to the first drive device 31 every first cycle, and supplies the second transmission synchronization signal to the second drive device 32 every first cycle. The same applies to the third drive device 33 and the fourth drive device 34.

The first driving device 31A and the second driving device 32A will be described with reference to fig. 10A and 10B. Fig. 10A is a configuration diagram of a first driving device 31A of the embodiment.

The first drive device 31A includes a first control unit 312A and a first communication processing unit 313A instead of the first control unit 312 and the first communication processing unit 313 of the first drive device 31.

The first communication processing unit 313A communicates with the host apparatus 10A via the network NW, and supplies various information acquired from the host apparatus 10A to the first control unit 312A.

The first communication processing unit 313A includes an interface unit 3131A and an extraction processing unit 3133A (described as EXTR in fig. 10A) instead of the interface unit 3131 and the extraction processing unit 3133 of the first communication processing unit 313, and further includes a delay time storage unit 3134, an adder 3135, and a comparator 3136.

The interface unit 3131A is connected to the network NW, and acquires various information transmitted by the host device 10A by communicating with the host device 10A via the network NW. The various types of information transmitted by the host device 10A include time information of the host device 10A, information relating to a command value COM _ i that the host device 10A commands the first drive device 31, identification information i relating to a control cycle of the host device 10A, and the like.

The timepiece 3132 includes, for example, a first timepiece not shown in fig. 10A, and a timepiece adjustment unit that performs time alignment processing of the first timepiece. The timer 3132 communicates with the host device 10A via the interface unit 3131A and the network NW, and synchronizes with the time information of the timer 12 of the host device 10A. Timer 3132 thereby adjusts the time of the first timepiece. The timer 3132 uses a protocol common to the master device 10A in the process related to the adjustment of this time. The timer 3132 supplies the adjusted time information to the first input a of the comparator 3136.

In addition, the timer 3132 limits the accuracy of the time using a protocol used in the processing. In the case where stability higher than stability of timing based on a protocol used in processing is required, a stabilizing circuit such as a PLL (phase locked loop) may be provided at a subsequent stage to reduce timing fluctuation due to the protocol.

Extraction processing unit 3133A acquires various information transmitted by host device 10A from interface unit 3131A, extracts the acquired information, and provides the extracted information to each supply destination.

For example, in order to calculate the timing at which synchronization is actually achieved, extraction processing section 3133A supplies a value of the delay time (TD 1 in fig. 10A) specified by host device 10A to delay time storage section 3134 described later, and supplies time information (tTX 1 in fig. 10A) relating to the time at which host device 10A transmits a packet of the first transmission synchronization signal to the first input of adder 3135. The time information related to the time at which the master device 10A has transmitted is an example of the time information of the master device 10A.

The extraction processing unit 3133A supplies identification information i (identification information i indicating a control cycle in which a packet is transmitted) given to a packet of the first transmission synchronization signal transmitted by the host device 10A to the phase adjustment unit 3123A.

The delay time storage unit 3134 stores a value of the delay time specified by the host device 10A in a storage area capable of storing an integer value, for example. The delay time storage unit 3134 supplies the held value of the delay time to a second input of the adder 3135. The delay time storage section 3134 may use a correction operation data table described later as a storage area capable of storing an integer value.

The adder 3135 adds the value tTX1 of the time information related to the time at which the host device 10A transmits the packet of the first transmission synchronization signal to the value TD1 of the delay time held in the delay time storage unit 3134, and supplies the operation result tST1 to the comparator 3136. The calculation result tST1 is a value that specifies the time at which the phase comparison for detecting the coincidence is performed.

The comparator 3136 detects that the time specified by the time information transmitted from the host device 10A has reached, outputs a positive logic pulse when the specified time has reached, and outputs a logic 0 when the specified time is other than the specified time.

For example, information on the current time outputted by the timer 3132 (described as tCT1 in fig. 10A) is supplied to the first input a of the comparator 3136, and time information tST1 specifying the time at which the phase comparison for detecting the synchronism is performed is supplied to the second input b. The comparator 3136 detects that the time designated by the host device 10A has reached, based on the comparison result between tCT1 and tST1, and outputs a positive logic pulse at this time. The positive logic pulse becomes the first synchronization signal whose timing is adjusted based on the timing at which the master device 10A transmits the packet of the first transmission synchronization signal (described as SYNC _ S1 in fig. 10A). The timing shown by this pulse is an example of the first adjustment timing.

The first control unit 312A includes a phase adjustment unit 3123A instead of the phase adjustment unit 3123 of the first control unit 312 described above.

The phase adjustment unit 3123A supplies the first control portion main body 3121 with a first clock for discrete time control of the first control portion main body 3121, and supplies the first interrupt signal generation unit 3122 with a second clock that is a source of the first control cycle. The phase adjustment unit 3123A adjusts the length of the second clock, for example, based on the first synchronization signal SYNC _ S1 generated by the comparator 3136 and the comparison result of the comparator 3124.

The phase adjustment unit 3123A includes, for example, a clock generation unit 31231, a first counter 31232, and a first phase comparator 31233.

The clock generation unit 31231 includes an oscillator not shown in fig. 3A, generates a first reference clock signal of a fixed period, and supplies to the first counter 31232.

The first counter 31232 divides the first reference clock signal supplied from the clock generation unit 31231 by a predetermined number by counting the wave number of the first reference clock signal, thereby generating a first clock signal having a period shorter than the length of the first control period.

The first counter 31232 generates a count value of a first count representing a value corresponding to the phase of the first control period as a result of counting the wave number of the first clock signal from the start of the first control period. The first counter 31232 supplies the generated second clock signal to the second input of the first phase comparator 31233 for phase correction, and corrects the count value of the first count according to the condition. The first counter 31232 generates a second clock of the first control period using, for example, either the count value of the first count or the count value of the corrected first count, and supplies the generated second clock signal to the first interrupt signal generation unit 3122.

Here, a condition for correcting the count value of the first count will be described. As the above condition, the result of the comparator 3124 at the time point of the first reference timing can be utilized. For example, when the logical value of the result of the comparator 3124 is "1", it is specified that the above condition is satisfied.

The first synchronization signal SYNC _ S1 is supplied from the extraction processing unit 3133 to a first input of the first phase comparator 31233. The first phase comparator 31233 compares the phase difference between the reference of the phase of the first synchronization signal SYNC _ S1 supplied from the extraction processing unit 3133 and the reference of the phase of the first control period generated by the first counter 31232 using the count value of the first count, and outputs the result of the comparison. The result of the comparison shows the relationship between the timing of the first synchronization signal SYNC _ S1 and the phase of the first control period based on the timing at which the master device 10A transmits the packet of the first transmission synchronization signal. For example, the first phase comparator 31233 calculates a correction value of the count value of the first counter 31232 based on the result of the comparison.

As described above, the first control unit 312A corrects the count value of the first count using the identification information i relating to the control cycle of the host device 10A based on the information output by the extraction processing unit 3133A with reference to the timing specified by the first synchronization signal SYNC _ S1.

Here, the respective parts of the first control unit 312A are arranged.

The first counter 31232 generates a first clock signal by dividing the first reference clock. The first counter 31232 generates a count value of a first count of a result of counting the wave number of the first clock signal from the start of the first control period. The first counter 31232 corrects the count value of the first count according to a condition of a time point of the first reference timing, and generates the second clock of the first control period using either the count value of the first count or the corrected count value of the first count. The count value of the first count corresponds to the phase of the first control period.

The first phase comparator 31233 compares the phase difference between the reference of the phase of the first control period and the reference of the phase of the specific first synchronization signal included in the first synchronization signal SYNC _ S1, using the count value of the first count obtained by the first counter 31232. The first phase comparator 31233 generates a correction value for correcting the count value of the first count at the time point of the first reference timing with respect to the reference of the phase of the specific first synchronization signal, based on the result of the comparison, so that the first deviation X between the reference of the phase of the first control period and the reference of the phase of the specific first synchronization signal becomes small.

The first interrupt signal generation unit 3122 generates a first interrupt signal of a first control period based on the second clock.

The first control portion main body 3121 starts a first process for controlling the first power converter 311 using the first clock signal based on the first interrupt signal. Thereby, first control unit 312A controls first power converter 311.

The second driving device 32 shown in fig. 10B will be explained.

Fig. 10B is a configuration diagram of the second driving device 32A of the embodiment.

The second driving device 32A shown in fig. 10B includes, for example, a second power converter 321, a second control unit 322A, and a second communication processing unit 323A.

The second power converter 321 supplies second electric power for conveying the object to a winding (not shown) of the second motor 22. Second control unit 322A controls second power converter 321. The second communication processing unit 323A communicates with the host device 10.

The second control unit 322A and the second communication processing unit 323A correspond to the first control unit 312A and the first communication processing unit 313A described above. The second control unit 322A and the second communication processing unit 323A may have the same configurations as the first control unit 312A and the first communication processing unit 313 described above. The second drive device 32A is denoted by the same reference numeral as the first drive device 31A.

Here, the respective parts of the second control unit 322A are arranged.

The second counter 32232 generates a third clock signal by dividing the second reference clock. The second counter 32232 generates a count value of a third count of the result of counting the wave number of the third clock signal from the start of the second control period. The second counter 32232 corrects the count value of the third count according to the condition of the time point of the second reference timing, and generates the fourth clock of the second control period using either the count value of the third count or the corrected count value of the third count. The count value of the third count is a value corresponding to the phase of the second control period.

The second phase comparator 32233 compares the phase difference between the reference of the phase of the second control period and the reference of the phase of the specific second synchronization signal included in the second synchronization signal SYNC _ S2, using the count value of the third count obtained by the second counter 32232. The second phase comparator 32233 generates a correction value for correcting the count value of the fourth count at the time point of the second reference timing with respect to the reference of the phase of the specific second synchronization signal, based on the result of the comparison, so that the second deviation X between the reference of the phase of the second control period and the reference of the phase of the specific second synchronization signal becomes smaller.

The second interrupt signal generation unit 3222 generates a second interrupt signal of a second control period based on the fourth clock.

The second control section main body 3221 starts a second process for controlling the second power converter 321 using the fourth clock signal based on the second interrupt signal. Thus, second control unit 322A controls second power converter 321.

For more details than the description of the second driving device 32A, reference is made to the description of the first driving device 31A. The third driving device 33A and the fourth driving device 34A are also the same as the first driving device 31A and the second driving device 32A.

The following describes the adjustment of the phase of the control cycle by the driving device 30 according to the embodiment.

Fig. 11 is a diagram for explaining a transmission time data table according to the second embodiment. The transmission time data table shown in fig. 11 includes items of identification numbers and time difference data. Data for identifying the drive device is stored in the item of the identification number. In the item of the time difference data, data defining a delay time from the start of the first control to the transmission of the transmission synchronization signal is stored. For example, the transmission time data table is allocated to the storage unit 15 of the host device 10A.

Fig. 12 is a diagram for explaining a correction calculation data table according to the second embodiment. The correction calculation data table shown in fig. 12 includes items of identification information, delay time, transmission time, and designated time. The delay time item stores data of the delay time specified by the master device 10A. Data relating to the time at which the master device 10A performed transmission is stored at the transmission time. The data at the specified time is stored in the item at the specified time.

Fig. 13 is a diagram for explaining the adjustment of the phase of the control cycle by the driving device 30 of the second embodiment. The waveform shown in fig. 13 is an enlarged waveform of a portion corresponding to the range a of fig. 7 described above.

The timing chart shown in fig. 13 shows the triangular waves and the rectangular waves of fig. 7, and the transmission timing (10d) of the packet and the reception timings (31e) and (32e) of the packet are added. The waveform of (10c) in fig. 13 shows a value (identification information i) corresponding to the triangular wave (10c) in fig. 7, using a waveform that changes stepwise. The time axis in the time chart shown in fig. 13 is a time axis in which a part of the time axis in the time chart shown in fig. 7 is enlarged. The time t0 to the time t10 are the first cycle of the master device 10A.

In the host device 10A, at time t0, the counter 13 starts counting from 0, and the count value thereof is sequentially incremented. The amplitude of the triangular wave (10a) represents the count value thereof. Further, a pulse of a rectangular wave (10b) is generated at time t 0.

Similarly, in the first drive device 31A, at time t0, the first counter 31232 starts counting from 0, and its count value is sequentially incremented. The amplitude of the triangular wave (31a) represents the count value thereof. Similarly, a pulse of a rectangular wave (31b) is generated at time t 0. By generating the pulse of the rectangular wave (31b), the first control portion 312 of the first drive device 31A generates an interrupt signal by the first interrupt signal generation unit 3122, thereby starting the first control process based on the interrupt process.

The control unit main body 16 of the host device 10A adds the value of the time difference data in the transmission time data table (fig. 11) to the time t0 to determine the timing at which each packet is individually transmitted to each drive device 30A. For example, the host device 10A adds Δ t1 to the time t0 to obtain a time t1 for the first drive device 31A, and adds Δ t2 to the time t0 to obtain a time t2 for the second drive device 32A.

When the result of the counting by the timer 12 reaches time t1, the host device 10A transmits a first packet of the first transmission synchronization signal to the first drive device 31A. At this time, the first communication processing unit 313A of the master device 10A transmits the first packet by adding the time information tTX1 regarding the time t1 at which the first transmission synchronization signal is transmitted to the first packet.

Thereafter, at time t1d, the first drive device 31A receives the first transmission synchronization signal.

Thereafter, when the result of the counting by the timer 12 reaches time t2, the master device 10A transmits a second packet of the second transmission synchronization signal to the second drive device 32A. At this time, the second communication processor 323A of the master device 10A transmits the second packet by adding the time information tTX2 regarding the time t2 at which the second transmission synchronization signal is transmitted.

Thereafter, at time t2d, the second drive device 32A receives the second transmission synchronization signal.

When the first communication processing unit 313A of the first drive device 31A receives the first transmission synchronization signal, the first communication processing unit 313A extracts the time information tTX1 about the time t1 at which the master device 10A has transmitted from the received first transmission synchronization signal, and adds the tTX1 described above to the value TD1 of the delay time. The first communication processing section 313A uses, for example, the value TD1 of the delay time held in the delay time storage section 3134 as a correction calculation data table. The first communication processing section 313A adds the calculation result tST1 as data of an entry at a specified time in the correction calculation data table. The first control unit 312A uses the calculation result tST1 as a specified value of the time when the phase comparison is performed.

When the second communication processing unit 323A of the second driving device 32A receives the second transmission synchronization signal, the second communication processing unit 323A extracts the time information tTX2 about the time t2 at which the master device 10A has performed transmission from the received second transmission synchronization signal, and adds the above-described tTX2 to the value TD2 of the delay time. The second communication processing section 323A uses, for example, the value TD2 of the delay time held in the delay time storage section 3234 as a correction calculation data table. The second communication processing section 323A adds the calculation result tST2 as data of an item at a specified time in the correction calculation data table. The second control unit 322A uses the calculation result tST2 as a specified value of the time at which the phase comparison is performed.

As described above, the first drive device 31A uses the time information tTX1 regarding the time t1 at which the master device 10A has transmitted, instead of using the time at which the first communication processing unit 313A has received the first transmission synchronization signal. It is assumed that even if a delay time occurs from the transmission of the first transmission synchronization signal by the host device 10A to the reception by the first drive device 31A or even if the delay time fluctuates, the time designated by the host device 10A can be reproduced without being affected by the delay time (tST 1). The same applies to the second drive 32A.

Thus, the first drive device 31A determines the timing of the comparison phase at the time (tST1) designated by the host device 10A, and the second drive device 32A determines the timing of the comparison phase at the time (tST2) designated by the host device 10A. Each of the driving devices 30A can compare the current phase with respect to the reference phase at the timing of the designated time. Since the respective drive devices 30A specify respective times at substantially common timings, the respective phases can be compared at the common timings.

According to the above embodiment, the drive system 1A includes the first drive device 31A, the second drive device 32A, and the host device 10A. The master device 10A transmits the identification information of the first cycle, the first transmission synchronization signal, and the second transmission synchronization signal every first cycle in the reference cycle. The first control section 312A of the first drive device 31A adjusts the phase of the first control period using the identification information so that the first control period is synchronized with the timing with respect to a specific first synchronization signal among the plurality of first synchronization signals obtained by the reception of the first transmission synchronization signal a plurality of times. Further, first control unit 312A controls first power converter 311 using the first control cycle. The second control unit 322A of the second drive device 32A adjusts the phase of the second control period using the identification information so that the second control period is synchronized with the timing of a specific second synchronization signal among the plurality of second synchronization signals obtained by receiving the second transmission synchronization signal a plurality of times. Further, second control unit 322A controls second power converter 321 using the second control cycle. This enables the drive system 1A to further improve the uniformity of the speeds of the plurality of motors 20.

In addition, when transmitting the identification information of the first cycle, the first transmission synchronization signal, and the second transmission synchronization signal, the host device 10A may generate the first transmission synchronization signal and the second transmission synchronization signal for each first cycle in the reference cycle, supply the first transmission synchronization signal and the identification information i for identifying the first cycle in the reference cycle to the first driving device 31A for each first cycle in the reference cycle, and supply the second transmission synchronization signal and the identification information i to the second driving device 32A in the same manner.

The first control unit 312A of the first drive device 31A may determine, from a plurality of first synchronization signals obtained by receiving a plurality of times of the first transmission synchronization signal, a first reference timing in the reference cycle, which is associated with the generation of the specific first transmission synchronization signal, using the identification information i, adjust the phase of the first control cycle so that the first control cycle is synchronized with the specific first synchronization signal corresponding to the first reference timing, and control the first power converter using the first control cycle.

Similarly, the second control unit 322A of the second drive device 32A may determine, from the plurality of second synchronization signals obtained by the plurality of times of reception of the second transmission synchronization signal, a second reference timing in the reference cycle, which is associated with the generation of the specific second transmission synchronization signal, using the identification information i, adjust the phase of the second control cycle so that the second control cycle is synchronized with the timing of the specific second synchronization signal corresponding to the second reference timing, and control the second power converter using the second control cycle. This makes it possible to further improve the synchronism of at least the first electric motor 21 and the second electric motor 22 in the drive system 1A.

The host device 10A supplies the first transmission synchronization signal to which the identification information i is added to the first drive device 31, and similarly supplies the second transmission synchronization signal to which the identification information i is added to the second drive device 32. The first control section 312A may adjust the phase of the first control cycle so that the first control cycle is synchronized with the specific first synchronization signal corresponding to the specific first transmission synchronization signal supplied at the first reference timing, when the value of the identification information i added to the supplied first transmission synchronization signal is a value of a constant C (constant value). Meanwhile, the second control unit 322A may also adjust the phase of the second control period so that the second control period is synchronized with the specific second synchronization signal corresponding to the specific second transmission synchronization signal supplied at the second reference timing, when the value of the identification information i added to the supplied second transmission synchronization signal is a value of the constant C.

In addition, depending on the specification of the network NW used, the specification of the protocol used for communication, or the specification of the relay device, the host device 10 may transmit the first transmission synchronization signal and the second transmission synchronization signal at different timings from each other. The drive system 1 also allows a configuration in which the first transmission synchronization signal and the second transmission synchronization signal need to be transmitted at different timings from each other, as described above.

The first control unit 312A may adjust the phase of the first control cycle in synchronization with the specific first synchronization signal at a first adjustment timing delayed by a first time from the first reference timing. The second control unit 322A may adjust the phase of the second control period at a second adjustment timing delayed by a second time from the second reference timing in synchronization with the specific second synchronization signal. Thus, after the host device 10A transmits the first transmission synchronization signal at the first reference timing, the first control unit 312A can reproduce the first adjustment timing delayed by the first time from the first reference timing. Further, after the master device 10A transmits the second transmission synchronization signal at the second reference timing, the second control unit 322A can reproduce the second adjustment timing delayed by the second time from the second reference timing.

The master device 10A may transmit the first transmission synchronization signal and the second transmission synchronization signal at timings different from each other. In this case, if the difference between the first reference timing and the second reference timing is determined in advance, the first adjustment timing and the second adjustment timing can be matched by applying the difference to the first time lag and the second time in order to cancel the difference between the first reference timing and the second reference timing.

For example, when a specific first transmission synchronization signal is generated, the first control unit 312A may determine the first adjustment timing based on the first reference time notified from the host device 10A. When the specific second transmission synchronization signal is generated, the second control unit 322A may determine the second adjustment timing based on the second reference time notified from the host device 10A. For example, if the first reference time and the second reference time notified from the host device 10A are information corresponding to the transmission time of the packet, the influence of the variation due to the transmission standby time before the host device 10 transmits the packet can be reduced.

(modification example)

Next, a drive system according to a modification common to the first and second embodiments will be described with reference to fig. 14A to 14C. The network configuration of the modification shown here is different from the network configurations of the first and second embodiments described above.

Fig. 14A is a configuration diagram of a drive system 1B of a first modification.

The drive system 1B shown in fig. 14A uses a cascade connection type network NWB. For example, the drive system 1B includes a host device 10B, and first to fourth drive devices 31B to 34B cascade-connected with the host device 10 as a starting point. The host device 10B and the first to fourth driving devices 31B to 34B correspond to the host device 10 and the first to fourth driving devices 31 to 34 described above.

For example, when the host device 10B transmits a packet to the network NWB for communication with any one of the first drive device 31B to the fourth drive device 34B, the first drive device 31B receives the packet and relays the packet to the second drive device 32B at the subsequent stage. When detecting that the packet is addressed to the first drive device 31B, the first drive device performs processing related to the packet. The second drive device 32B and the third drive device 33B relay packets in the same manner as the second drive device 32B, but the fourth drive device 34B may be the destination of the network NWB and may not relay packets. When detecting that the packet is addressed to the second drive device 32B to the fourth drive device 34B, the second drive device performs processing related to the packet.

For example, when the first to fourth driving devices 31B to 34B transmit information to the host device 10, respectively, it may transmit when there is a request from the host device 10. The transmission methods for transmitting information to the host device 10 by the first to fourth drive devices 31B to 34B may be applied to a network configuration described later.

Fig. 14B is a configuration diagram of a drive system 1C of a second modification.

The drive system 1C shown in fig. 14B uses a network NWC of a ring connection type. For example, the drive system 1C includes a host device 10C having a first communication port and a second communication port, and further includes first to fourth drive devices 31C to 34C. The first to fourth drive devices 31C to 34C are sequentially arranged in a ring of the network NWC starting from the first communication port of the host device 10C and ending at the second communication port.

Fig. 14C is a configuration diagram of a drive system 1D of a third modification.

The drive system 1D shown in fig. 14C uses a network NWD of a single star connection type. The network NWD includes a HUB (HUB)40 provided at a position of a node of a single star connection type. The host device 10D and the first to fourth driving devices 31D to 34D correspond to the host device 10 and the first to fourth driving devices 31 to 34 described above. For example, the master device 10 of the drive system 1D and the first to fourth drive devices 31D to 34D are connected to the hub 50, respectively. The master device 10 communicates with the first to fourth drive devices 31D to 34D through the hub 50, respectively. The hub 50 may be a switch or a repeater that electrically relays packets, or may be an optical coupler for optical communication.

In the case of the drive system 1A and the drive system 1B described above, when each drive device relays a packet, a delay time due to relay processing may occur. The drive system 1A and the drive system 1B described above can ensure the same speed without being affected by the variation of the delay time due to the relay processing by using the communication method described in the embodiment. In the case of the drive system 1D, although a delay time may occur when the hub 50 relays a packet, it is also possible to ensure the constant speed without being affected by the variation in the delay time.

According to at least one embodiment described above, the drive system of the embodiment includes the first drive device, the second drive device, and the host device. The first driving device includes a first power converter 311 that supplies first electric power to the winding of the first motor 21, and a first control unit that controls the first power converter 311. The second driving device includes a second power converter 321 that supplies second electric power to the winding of the second motor 22, and a second control unit that controls the second power converter 321. The master device controls the first control unit and the second control unit using a first cycle and a reference cycle including a plurality of the first cycles. The master device transmits the identification information of the first cycle and the first transmission synchronization signal for each first cycle in the reference cycle, or transmits the identification information of the first cycle, the first transmission synchronization signal and the second transmission synchronization signal for each first cycle in the reference cycle. The first control section adjusts the phase of the first control period using the identification information so that the first control period is synchronized with the timing related to a specific first synchronization signal among a plurality of first synchronization signals obtained by receiving the first transmission synchronization signal a plurality of times, and controls the first power converter 311 using the first control period. The second control unit adjusts the phase of the second control period using the identification information so that the second control period is synchronized with the timing of a specific second synchronization signal among a plurality of second synchronization signals obtained by either one of the reception of the first transmission synchronization signal and the reception of the second transmission synchronization signal, and controls the second power converter 321 using the second control period. This enables the drive system to further improve the synchronization between the plurality of motors.

While several embodiments have been described above, the configurations of the embodiments are not limited to the above examples. For example, the configurations of the respective embodiments may be combined with each other.

Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in other various manners, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Description of the reference numerals

1 drive system, 20 electric motor, 21 first electric motor, 22 second electric motor, 30 drive device, 31A, 31B, 31C, 31D first drive device, 32A, 32B, 32C, 32D second drive device, 10A, 10B, 10C, 10D host device, 311 first power converter, 321 second power converter, 312 first control part, 322 second control part, 313 first communication processing unit, 323 second communication processing unit, 3121 first control part main body, 3122 first interrupt signal generation unit, 31232 first counter, 31233 first phase comparator, 3221 second control part main body, 3222 second interrupt signal generation unit, 32232 second counter, 32233 second phase comparator