阅读说明：本技术 用于rf等离子体反应器的等离子体鞘控制 (Plasma sheath control for RF plasma reactor ) 是由 艾丽亚·斯劳伯道夫 迪麦西·津巴 肯尼斯·米勒 詹姆斯·普拉格 于 2019-08-09 设计创作，主要内容包括：一些实施例包括一种等离子体鞘控制系统,其包括：RF电源,其产生具有大于20kHz的频率和大于1kV的峰值电压的正弦波形；和等离子体腔室,其与所述RF电源电耦合,所述等离子体腔室具有通过大于大约1kV的能量受加速到所部署的表面中的多个离子,并且所述等离子体腔室从所述正弦波形在所述等离子体腔室内产生等离子体鞘。所述等离子体鞘控制系统包括：阻流二极管,其电连接在所述RF电源与所述等离子体腔室之间；和电容放电电路,其与所述RF电源、所述等离子体腔室和所述阻流二极管电耦合；所述电容放电电路通过大于1kV的峰值电压并且通过小于250纳秒的放电时间使所述等离子体腔室内的电容电荷放电。(Some embodiments include a plasma sheath control system comprising: an RF power supply that generates a sinusoidal waveform having a frequency greater than 20kHz and a peak voltage greater than 1 kV; and a plasma chamber electrically coupled to the RF power supply, the plasma chamber having a plurality of ions accelerated into a deployed surface by an energy greater than about 1kV, and the plasma chamber generating a plasma sheath within the plasma chamber from the sinusoidal waveform. The plasma sheath control system includes: a current blocking diode electrically connected between the RF power supply and the plasma chamber; and a capacitive discharge circuit electrically coupled with the RF power supply, the plasma chamber, and the current blocking diode; the capacitive discharge circuit discharges capacitive charges within the plasma chamber through a peak voltage greater than 1kV and through a discharge time less than 250 nanoseconds.)

1. A plasma sheath control system, comprising:

an RF power supply that generates a sinusoidal waveform having a frequency greater than 20kHz and a peak voltage greater than 1 kV;

a plasma chamber electrically coupled to the RF power source, the plasma chamber having a plurality of ions accelerated into a surface disposed within the plasma chamber by an energy greater than about 1kV, and the plasma chamber generating a plasma sheath within the plasma chamber from the sinusoidal waveform;

a choke diode electrically connected between the RF power source and the plasma chamber, the choke diode rectifying the sinusoidal waveform; and

a capacitive discharge circuit electrically coupled with the RF power supply, the plasma chamber, and the current blocking diode; the capacitive discharge circuit discharges capacitive charges within the plasma chamber through a peak voltage greater than 1kV and through a discharge time less than 250 nanoseconds.

2. The plasma sheath control system of claim 1, wherein the capacitive discharge circuit includes a resistive output stage comprising a resistor and an inductor arranged in series, the resistive output stage disposed between a point on the plasma sheath control system between the choke diode and the plasma chamber and ground.

3. The plasma sheath control system of claim 1, wherein the capacitive discharge circuit comprises an energy recovery circuit comprising a diode and an inductor arranged in series, the energy recovery circuit disposed between the choke diode and the plasma chamber and the RF power supply.

4. The plasma sheath control system of claim 1, further comprising a bias capacitor disposed in series between the current blocking diode and the plasma chamber.

5. The plasma sheath control system of claim 1, further comprising a bias compensation circuit comprising a DC power supply, a resistor, a diode, and a high voltage switch, the bias compensation circuit disposed between the current blocking diode and a point on the plasma sheath control system between the RF power supply.

6. The plasma sheath control system of claim 1, further comprising a matching network electrically coupled to the plasma chamber, the matching network matching a reactive impedance of a plasma load within the plasma chamber to an output impedance of the RF power supply.

7. The plasma sheath control system of claim 1, wherein the choke diode rectifies the sinusoidal waveform creating a sinusoidal waveform with a substantially flat portion for at least 25% of each cycle.

8. A plasma sheath control system, comprising:

a high voltage DC power supply that generates a DC voltage greater than 200V;

a resonant circuit driver comprising a plurality of high voltage switches that are alternately turned on and off to produce a sinusoidal waveform having a frequency greater than 20kHz and a peak voltage greater than 1 kV;

a plasma chamber electrically coupled with the resonant circuit driver, the plasma chamber having a plurality of ions accelerated into a surface disposed within the plasma chamber by an energy greater than about 1kV, and the plasma chamber generating a plasma sheath within the plasma chamber from the sinusoidal waveform;

a current blocking diode electrically connected between the resonant circuit driver and the plasma chamber, the current blocking diode rectifying the sinusoidal waveform.

9. The plasma sheath control system of claim 8, wherein the choke diode rectifies the sinusoidal waveform creating a substantially flat portion for at least 25% of each cycle.

10. The plasma sheath control system of claim 8, further comprising a resistive output stage comprising a resistor and an inductor arranged in series, the resistive output stage disposed between a point on the plasma sheath control system between the choke diode and the plasma chamber and ground.

11. The plasma sheath control system of claim 8, further comprising an energy recovery circuit comprising a diode and an inductor arranged in series, the energy recovery circuit disposed between the choke diode and the plasma chamber and the DC power supply.

12. The plasma sheath control system of claim 8,

wherein the plurality of switches comprises a first switch, a second switch, a third switch, and a fourth switch;

wherein the first switch and the fourth switch are closed during a first period of time to allow current to flow in a first direction; and

wherein the second switch and the third switch are closed during a second time period to allow current to flow in a second direction opposite the first direction.

13. The plasma sheath control system of claim 8,

wherein the plurality of switches comprises a first switch and a second switch;

wherein the first switch is closed during a first time period to allow current to flow in a first direction; and

wherein the second switch is closed during a second time period to allow current to flow in a second direction opposite the first direction.

14. The plasma sheath control system of claim 8, wherein the plurality of switches are switched at a frequency according to the following equation:wherein f is greater than 10kHz, wherein L represents the inductance of a load within the plasma chamber and C represents the capacitance of a capacitor within the resonant circuit driver.

15. The plasma sheath control system of claim 8, wherein the plurality of switches are switched at a frequency according to the following equation:wherein f is greater than 10kHz, wherein L represents the inductance of an inductor within the resonant circuit driver and C represents the capacitance of the load within the plasma chamber.

16. The plasma sheath control system of claim 8, wherein the plurality of switches are switched at a frequency according to the following equation:wherein f is greater than 10kHz, wherein L represents the inductance of an inductor within the resonant circuit driver and C representsA capacitance of a capacitor within the resonant circuit driver.

17. The plasma sheath control system of claim 8, wherein the plasma sheath control system generates a voltage across the plasma sheath of greater than about 1kV while the resonant circuit driver is generating the sinusoidal waveform.

18. The plasma sheath control system of claim 8, further comprising a controller that adjusts one or both of the frequency or power of the sinusoidal waveform generated by the resonant circuit on a time scale of less than about 1 ms.

19. The plasma sheath control system of claim 8, further comprising a controller that measures a frequency of a sinusoidal waveform at a point before the plasma chamber and adjusts the frequency of the sinusoidal waveform generated by the resonant circuit driver if the frequency of the sinusoidal waveform at the point before the plasma chamber does not match a resonant frequency.

20. The plasma sheath control system of claim 8, further comprising a controller that measures the power of the sinusoidal waveform at a point before the plasma chamber and adjusts the power of the sinusoidal waveform generated by the resonant circuit driver if the power of the sinusoidal waveform at the point before the plasma chamber does not match a desired power.

21. A plasma sheath control system, comprising:

an RF power supply that generates a sinusoidal waveform having a frequency greater than 20kHz and a peak voltage greater than 1 kV;

a plasma chamber electrically coupled to the RF power source, the plasma chamber having a plurality of ions accelerated into a surface disposed within the plasma chamber by an energy greater than about 1kV, and the plasma chamber generating a plasma sheath within the plasma chamber from the sinusoidal waveform;

a choke diode electrically connected between the RF power source and the plasma chamber, the choke diode rectifying the sinusoidal waveform; and

a resistive output stage comprising a resistor and an inductor arranged in series, the resistive output stage disposed between a point on the plasma sheath control system between the choke diode and the plasma chamber and ground.

Background

The use of RF excited gas discharges in thin film manufacturing technology has become standard. The simplest geometry most commonly used is that of two planar electrodes between which a voltage is applied. A schematic representation of such a planar RF plasma reactor is shown in fig. 1. The plasma sheath separates the plasma from each electrode.

Positive ions generated in the plasma volume are accelerated across the plasma sheath and to the electrode by an Ion Energy Distribution Function (IEDF) determined by the magnitude and waveform of the time-dependent potential difference across the sheath, the gas pressure, the physical geometry of the reactor, and/or other factors. The ion bombardment energy distribution can determine the degree of anisotropy in the film etching amount of ions caused by damage to the surface.

Disclosure of Invention

Some embodiments include a plasma sheath control system comprising: an RF power supply that generates an RF sinusoidal waveform having a frequency greater than 20kHz and a peak voltage greater than 1 kV; and a plasma chamber electrically coupled to the RF power supply, the plasma chamber having a plurality of ions accelerated into a deployed surface by an energy greater than about 1kV, and the plasma chamber generating a plasma sheath within the plasma chamber from the RF sinusoidal waveform. The plasma sheath control system includes: a current blocking diode electrically connected between the RF power supply and the plasma chamber; and a capacitive discharge circuit electrically coupled with the RF power supply, the plasma chamber, and the current blocking diode; the capacitive discharge circuit discharges capacitive charges within the plasma chamber through a peak voltage greater than 1kV and through a discharge time less than 250 nanoseconds.

In some embodiments, the capacitive discharge circuit includes a resistive output stage comprising a resistor and an inductor arranged in series, the resistive output stage disposed between a point on the plasma sheath control system between the choke diode and the plasma chamber and ground. In some embodiments, the capacitive discharge circuit includes an energy recovery circuit comprising a diode and an inductor arranged in series, the energy recovery circuit disposed between the choke diode and the plasma chamber and the DC power supply.

In some embodiments, the plasma sheath control system may include a bias capacitor disposed in series between the current blocking diode and the plasma chamber. In some embodiments, the plasma sheath control system may include a bias compensation circuit comprising a DC power supply, a resistor, a diode, and a high voltage switch, the bias compensation circuit disposed between the current blocking diode and a point on the plasma sheath control system between the RF power supply.

In some embodiments, the plasma sheath control system may include a matching network electrically coupled with the plasma chamber, the matching network matching a reactive impedance of a plasma load within the plasma chamber to an output impedance of the RF power supply.

In some embodiments, the choke diode rectifies the sinusoidal waveform, creating a sinusoidal waveform with a substantially flat portion for at least 25% of each cycle.

Some embodiments include a plasma sheath control system. The plasma sheath control system may include a high voltage DC power supply that generates a DC voltage greater than 200V. The plasma sheath control system may include a resonant circuit driver including a plurality of high voltage switches coupled with a resonant load, the high voltage switches being alternately turned on and off to produce a sinusoidal waveform having a frequency greater than 20kHz and a peak voltage greater than 1 kV; the plasma sheath control system may include a plasma chamber electrically coupled with the resonant circuit driver, the plasma chamber having a plurality of ions accelerated into a surface disposed within the plasma chamber by an energy greater than about 1kV, and the plasma chamber generating a plasma sheath within the plasma chamber from the sinusoidal waveform. The plasma sheath control system may include a current blocking diode electrically connected between the resonant circuit driver and the plasma chamber, the current blocking diode rectifying the sinusoidal waveform.

In some embodiments, the choke diode rectifies the sinusoidal waveform, creating a waveform with a substantially flat portion for at least 25% of each cycle.

In some embodiments, the plasma sheath control system may include a resistive output stage comprising a resistor and an inductor arranged in series, the resistive output stage disposed between a point on the plasma sheath control system between the choke diode and the plasma chamber and ground.

In some embodiments, the plasma sheath control system may include an energy recovery circuit comprising a diode and an inductor arranged in series, the energy recovery circuit disposed between the choke diode and the plasma chamber and the DC power supply.

In some embodiments, the plurality of switches includes a first switch, a second switch, a third switch, and a fourth switch. In some embodiments, the first switch and the fourth switch are closed during a first time period to allow current to flow in a first direction; and the second switch and the third switch are closed during a second time period to allow current to flow in a second direction opposite the first direction.

In some embodiments, the plurality of switches includes a first switch and a second switch. In some embodiments, the first switch is closed during a first time period to allow current to flow in a first direction; and the second switch is closed during a second time period to allow current to flow in a second direction opposite the first direction.

In some embodiments, the plurality of switches are switched at a frequency according to the following equation:wherein f is greater than 10kHz, wherein L represents the inductance of a load within the plasma chamber and C represents the capacitance of a capacitor within the resonant circuit driver.

In some embodimentsWherein the plurality of switches are switched at a frequency according to the following equation:wherein f is greater than 10kHz, wherein L represents the inductance of an inductor within the resonant circuit driver and C represents the capacitance of the load within the plasma chamber.

In some embodiments, the plurality of switches are switched at a frequency according to the following equation:wherein f is greater than 10kHz, wherein L represents the inductance of an inductor within the resonant circuit driver and C represents the capacitance of the capacitor within the resonant circuit driver.

In some embodiments, the plasma sheath control system generates a voltage across the plasma sheath of greater than about 1kV while the resonant circuit driver is generating the sinusoidal waveform.

In some embodiments, the plasma sheath control system may include a controller that adjusts one or both of the frequency or power of the sinusoidal waveform generated by the resonant circuit on a time scale of less than about 1 ms.

In some embodiments, the plasma sheath control system may include a controller that measures a frequency of a sinusoidal waveform at a point before the plasma chamber and adjusts the frequency of the sinusoidal waveform generated by the resonant circuit driver if the frequency of the sinusoidal waveform at the point before the plasma chamber does not match a resonant frequency.

In some embodiments, the plasma sheath control system may include a controller that measures the power of the sinusoidal waveform at a point before the plasma chamber and adjusts the power of the sinusoidal waveform generated by the resonant circuit driver if the power of the sinusoidal waveform at the point before the plasma chamber does not match a desired power.

Some embodiments of the invention include a plasma sheath control system comprising: an RF power supply that generates a high voltage and high frequency sinusoidal waveform; a resistive output stage comprising a resistor and an inductor; and a current blocking diode disposed between the RF power supply and the resistive output stage. In some embodiments, a plasma reactor may be included, which may include, for example, a gas feed system, a control system, a plasma generation system, a vacuum pump, a wafer transfer system, and the like. In some embodiments, the resistive output stage has a capacitance of less than about 200 pF. In some embodiments, the plasma sheath control system further comprises an output configured to couple with a wafer deposition apparatus. In some embodiments, the plasma sheath control system further comprises an output configured to output a high voltage sinusoidal waveform having an amplitude greater than 2kV and a frequency greater than 1 kHz.

Some embodiments of the invention include a plasma sheath control system comprising: an RF power source; a bias capacitor; and a high voltage switch coupled across the blocking diode, wherein the high voltage switch is configured to turn off when the high voltage switching power supply is on and to turn on when the high voltage switching power supply is not pulsing. In some embodiments, the plasma sheath control system further comprises an output configured to couple with a wafer deposition apparatus. In some embodiments, the plasma sheath control system further comprises an output configured to output a high voltage sinusoidal waveform having an amplitude greater than 2kV and a frequency greater than 1 kHz.

Some embodiments of the invention include a plasma sheath control system that generates an output that creates a plasma within a wafer deposition chamber such that a voltage potential between a wafer and a chuck is about 2kV during periods when the plasma sheath control system is on and the plasma sheath control system is off.

In some embodiments, the resistive output stage may include a series or parallel network of passive components. For example, the resistive output stage may include a resistor, a capacitor, and an inductor in series. As another example, a resistive output stage may include a capacitor in parallel with an inductor and a capacitor-inductor combination in series with a resistor. Regardless of the arrangement, the component values may be selected to match the RF frequency of the RF source.

These illustrative embodiments are mentioned not to limit or define the disclosure, but to provide examples to assist understanding thereof. Additional embodiments are discussed in the detailed description, and further description is provided herein. Advantages offered by one or more of the various embodiments may be further understood by examining this specification or by practicing one or more embodiments as presented.

Drawings

These and other features, aspects, and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings.

Fig. 1 is a schematic representation of an RF plasma reactor according to some embodiments.

Fig. 2 is a schematic diagram of an RF driver for an RF plasma chamber according to some embodiments.

FIG. 3 shows the voltage V across the plasma chamber_rAnd a plasma potential V for equal area target and substrate electrodes_PThe waveform of (2).

FIG. 4 shows the potential V across the plasma sheath adjacent to the target electrode within the plasma chamber_STAnd a potential V across the substrate electrode_ssThe waveform of (2).

Fig. 5 is a schematic diagram of a plasma sheath control system for an RF chamber according to some embodiments.

Fig. 6 shows a waveform across a sheath (e.g., C3) and at a clip (e.g., C2).

Fig. 7 is another schematic diagram of a plasma sheath control system for an RF chamber having a resistive output stage according to some embodiments.

Figure 8 shows a waveform across the sheath (e.g., C3) and at the clip (e.g., C2) from the circuit shown in figure 7.

Fig. 9 is an enlarged view of three cycles of the waveform shown in fig. 8.

Figure 10 shows a waveform across the sheath (e.g., C3) and at the clip (e.g., C2) from the circuit shown in figure 7.

Figure 11 shows a waveform across the sheath (e.g., C3) and at the clip (e.g., C2) from the circuit shown in figure 7.

Fig. 12 is another schematic diagram of a plasma sheath control system for an RF chamber having a resistive output stage and a high voltage switching bias compensation stage, according to some embodiments.

Figure 13 shows a waveform across the sheath (e.g., C3) and at the clip (e.g., C2) from the circuit shown in figure 12.

Fig. 14 is an enlarged view of three cycles of the waveform shown in fig. 12.

Figure 15 shows the end of a burst waveform where the voltage on the cardholder returns to zero.

Fig. 16 is a schematic diagram of a plasma sheath control system for an RF chamber with a resonant full bridge driver, according to some embodiments.

Fig. 17 is a circuit diagram of a plasma sheath control system with an energy recovery circuit according to some embodiments.

Fig. 18 is a block diagram of a high voltage switch with an isolated power supply according to some embodiments.

Fig. 19 is a circuit diagram of a plasma sheath control system with a half-bridge resonant circuit according to some embodiments.

Detailed Description

A plasma sheath control system is disclosed that includes one or both of a diode and a capacitive discharge circuit (e.g., a resistive output stage or an energy recovery circuit) and/or a high voltage switch with a current blocking diode. In some embodiments, the plasma sheath control circuit may include an RF bias power supply with a plasma chamber to manufacture semiconductors or similar devices. In some embodiments, the plasma sheath control circuitry may generate an output that creates a plasma within the semiconductor manufacturing apparatus. For example, so that a more controllable and constant plasma sheath potential can be generated between the plasma and the target electrode or wafer. Enhanced control may allow for peaked and/or adjustable ion energy distribution of bombarding ions from the plasma, which may, for example, result in higher application performance (e.g., such as in etching, thin film deposition, ion deposition, solar panel and/or display panel manufacturing, etc.). Additionally or alternatively, the substantially constant potential between the wafer and the chuck may be maintained at approximately 2kV during periods when the plasma sheath control circuit is on and the plasma sheath control is off. In some embodiments, the RF power supply system may generate a sinusoidal waveform having a peak amplitude greater than approximately 1kV-10 kV.

Fig. 2 is a schematic diagram of an RF plasma power supply and RF driver for a reactor. Here, V_RFIs a voltage of an applied sinusoidal waveform from a matched RF power supply. V_TAnd V_PThe potentials of the target electrode and the plasma, respectively. In addition, V_SS＝V_PAnd V_ST＝V_T-V_PRespectively, are the voltage across the substrate or chamber wall plasma sheath and the target plasma sheath. The choke capacitor being denoted C_B；C_STAnd I_TRespectively, the capacitance and conduction current through the sheath adjacent the target electrode, and C_ssAnd I_SThe corresponding values for the sheath adjacent to the substrate electrode are indicated.

The resistance of the plasma is small relative to the sheath resistance for the plasma electron density and voltage frequency ranges considered in this discussion. However, including the plasma resistance does not introduce any complexity with respect to the circuit model.

FIG. 3 shows the voltage V across the plasma chamber_rAnd a plasma potential V for equal area target and substrate electrodes_PThe waveform of (2).

FIG. 4 shows for A_T/A_S0.2, potential V across the plasma sheath adjacent to the target electrode_STAnd a potential V across the substrate electrode sheath_ssThe waveform of (2). Figure 4 shows a half sine wave of the sheath potential going from 0 to-450V.

Fig. 5 is a schematic diagram of a plasma sheath control system 500 for an RF chamber according to some embodiments. The plasma sheath control system 500 includes an electrical representation of a wafer plasma sheath 505 deployed on a waferThe circuit and the circuit representing the wall plasma sheath 510 on the wall of the plasma chamber. Capacitor C3 represents the sheath capacitance between the plasma and the wafer, which may be a function of both the physical geometry across the sheath and the plasma parameters. Capacitor C3 represents the sheath capacitance between the plasma and the wafer, which may be a function of both the physical geometry across the sheath and the plasma parameters. RF power supply V₅Is an RF voltage supply that provides a high voltage sinusoidal waveform. Switch S2 may be used to turn RF power supply V5 on and off, which may be an element used to model the turning off and on of RF power supply V5. Various other components represent stray capacitance, inductance, and/or resistance.

In some embodiments, the lead stage 103 may represent one or both of leads or traces between the RF generator 515 and the DC bias circuit 104. One or both of inductor L2 or inductor L6 may represent inductance for one or both of a lead or trace.

In this example, the DC bias circuit 104 does not include any bias compensation. The DC bias circuit 104 includes an offset supply voltage V1 that may bias the output voltage, for example, positively or negatively. In some embodiments, the offset supply voltage V1 may be adjusted to change the offset between the wafer voltage and the chuck voltage. In some embodiments, the offset supply voltage V1 may have a voltage of approximately 5kV, + -4 kV, + -3 kV, + -2kV, + -1 kV, and so on.

In some embodiments, the bias capacitor C12 may isolate (or separate) one or both of the DC bias voltage and the resistive output stage or other circuit elements. For example, the biasing capacitor C12 may allow for a potential transfer from one part of the circuit to another. In some embodiments, this potential transfer may ensure that the electrostatic force holding the wafer in place on the chuck stays below a voltage threshold. Resistor R2 may isolate the DC bias supply from the high voltage sinusoidal waveform output from RF generator 515.

For example, the bias capacitor C12 is 100pF, 10pF, 1pF, 100 μ F, 10 μ F, 1 μ F, or the like. For example, resistor R2 may have a high resistance (e.g., a resistance such as approximately 1kOhm, 10kOhm, 100kOhm, 1MOhm, 10MOhm, 100MOhm, etc.).

The second lead stage 105 represents circuit elements between the RF power circuit and the load stage 106. For example, resistor R13 may represent a stray resistance of a lead or transmission line connected to an electrode (e.g., load stage 106) from an output of the high voltage power system. For example, capacitor C1 may represent stray capacitance in a lead or transmission line.

In some embodiments, the load stage 106 may represent an idealized or effective circuit for a semiconductor processing chamber (e.g., a plasma deposition system, a semiconductor manufacturing system, a plasma sputtering system, etc.). For example, the capacitance C2 may represent the capacitance of a chuck in which the wafer may be seated. For example, the clip may include a dielectric material. For example, the capacitor C1 may have a small capacitance (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

For example, capacitor C3 may represent the sheath capacitance between the plasma and the wafer. For example, resistor R6 may represent the sheath resistance between the plasma and the wafer. For example, inductor L2 may represent the sheath inductance between the plasma and the wafer. For example, current source I2 may represent the ion current through the sheath. For example, the capacitor C1 or the capacitor C3 may have a small capacitance (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

The capacitor C9 may represent, for example, the capacitance within the plasma between the chamber wall and the plasma. For example, the resistor R7 may represent the resistance within the plasma between the chamber wall and the top surface of the wafer. For example, current source I1 may represent the ion current in the plasma. For example, the capacitor C1 or the capacitor C9 may have a small capacitance (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

As used in this document, the plasma voltage is the voltage measured from ground to circuit point 123; the wafer voltage is the voltage measured from ground to circuit point 122 and may represent the voltage at the surface of the wafer; the clip voltage is the voltage measured from ground to circuit point 121 to point 122; the electrode voltage is the voltage measured from earth to circuit point 121 and earth; and the input voltage is the voltage measured from ground to circuit point 125.

Fig. 6 shows the waveform across the sheath between circuit point 122 and circuit point 123 (e.g., across capacitor C3) and at the clip as circuit point 121 (e.g., across capacitor C2). Waveform 605 shows the voltage across a plasma sheath (e.g., wafer plasma sheath 505 and/or wall plasma sheath 510). Waveform 605 is a full sine wave slightly clamped at zero because of diode (D3), which is part of the plasma effect. Waveform 610 shows the voltage at the electrode (or across the clip). In some embodiments, the difference between the chuck voltage and the wafer voltage (e.g., the difference between the waveforms) may be kept around 2kV or slightly less. On shut down, the difference returns to-2 kV. A difference of about 2kV may be sufficient to electrostatically couple the wafer to the chuck, while a difference of greater than 2kV may do so while becoming damaging to the wafer.

Fig. 7 is another schematic diagram of a plasma sheath control system 700 for an RF plasma reactor having a resistive output stage 705, according to some embodiments. In this example, plasma sheath control system 700 includes a current blocking diode D7. The choke diode D7 may rectify the sinusoidal waveforms, which may, for example, produce a flat top on each sinusoidal waveform, as shown in fig. 9. For example, the choke diode D7 may rectify the sinusoidal waveform, creating a sinusoidal waveform with a substantially flat portion for at least 10%, 15%, 20%, 25%, 30%, etc. of each cycle.

The resistive output stage 705 may include one or more inductors L1 and one or more resistors R1. The RESISTIVE OUTPUT STAGE 705 may include any type of RESISTIVE OUTPUT STAGE (e.g., such as the RESISTIVE OUTPUT STAGE described in U.S. patent application No.15/941,731 entitled "HIGH VOLTAGE responsive OUTPUT STAGE CIRCUIT," which is incorporated by reference herein in its entirety for all purposes).

In some embodiments, the resistor R1 may have a resistance of less than approximately 500 ohms, 200 ohms, 100 ohms, or the like.

In some embodiments, the resistive output stage 705 may be electrically coupled in parallel with the load stage 106 (e.g., plasma chamber) and the high voltage switching power supply. In some embodiments, the resistive output stage may include at least one resistor (e.g., R1) that discharges the load (e.g., from the wafer plasma sheath or the wall plasma sheath 510). In some embodiments, the resistive output stage may be configured to discharge an average power in excess of about 1 kilowatt during each sinusoidal waveform period, and/or to discharge an energy of one joule or less during each sinusoidal waveform period. In some embodiments, the resistance of the resistor R1 in the resistive output stage may be less than 200 ohms. In some embodiments, the resistor R1 may include multiple resistances arranged in series or parallel with a combined capacitance of less than about 200pF (e.g., C11).

In some embodiments, the resistive output stage 705 may include a set of circuit elements that may be used to control the shape of a voltage waveform across a load. In some embodiments, the resistive output stage 705 may include only passive elements (e.g., resistors, capacitors, inductors, etc.). In some embodiments, the resistive output stage 705 may include active circuit elements (e.g., switches) as well as passive circuit elements. In some embodiments, for example, the resistive output stage 705 may be used to control the voltage rise time of a waveform and/or the voltage fall time of a waveform.

In some embodiments, the resistive output stage 705 may discharge a capacitive load (e.g., capacitive charge from the wafer plasma sheath 505 and/or the wall plasma sheath 510). For example, these capacitive loads may have small capacitances (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

In some embodiments, the resistive output stage may be used in circuits having sinusoidal waveforms with high peak voltages (e.g., voltages greater than 1kV, 10kV, 20kV, 50kV, 100kV, etc.) and/or high frequencies (e.g., frequencies greater than 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.).

In some embodiments, the resistive output stage 705 may be selected to handle high average power, high peak power, fast rise time, and/or fast/fall time. For example, the average power rating may be greater than about 0.5kW, 1.0kW, 10kW, 25kW, etc., and/or the peak power rating may be greater than about 1kW, 10kW, 100kW, 1MW, etc.

In some embodiments, the resistive output stage 705 may include a series or parallel network of passive components. For example, the resistive output stage 705 may include a resistor R5, a capacitor C11, and an inductor L7 in series. As another example, a resistive output stage may include a capacitor in parallel with an inductor and a capacitor-inductor combination in series with a resistor. Regardless of the arrangement, the component values may be selected to match the RF frequency of the RF source. The choke diode D7 may rectify the output of the RF generator 515. For example, the choke diode D7 may rectify the sinusoidal waveform, creating a sinusoidal waveform with a substantially flat portion for at least 10%, 15%, 20%, 25%, 30%, etc. of each cycle.

In some embodiments, the resistive output stage 705 may rapidly discharge the capacitive load (e.g., capacitive charge from the wafer plasma sheath 505 and/or the wall plasma sheath 510) of high voltage at the load stage 106 through a fast discharge time. The high voltage load may be a load having a voltage greater than about 1kV, 10kV, 20kV, 50kV, 100kV, etc. The fast discharge time may be a time less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, and so forth.

Plasma sheath control system 700 may include RF generator 515, resistive output stage 705, lead stage 103, DC bias circuit 104, and second lead stage 105. The plasma sheath control system may include a plasma sheath control circuit and load stage 106, which may include a plasma chamber.

Fig. 8 shows the waveform across the sheath between circuit point 122 and circuit point 123 (e.g., across capacitor C3) and at the clip as circuit point 121 (e.g., across capacitor C2). Fig. 9 is an enlarged view of three cycles of the waveform shown in fig. 8. Waveform 805 shows the voltage across the sheath (e.g., the capacitive charge from wafer plasma sheath 505 and/or wall plasma sheath 510). Waveform 805 is a full sine wave slightly clamped at zero because of diode (D3), which is part of the plasma effect. Waveform 810 shows the voltage at the pole (or across the clip).

When RF source V5 is continuously on, the flatness may be a result of the value of current blocking diode D7 and/or all relevant capacitances in the circuit, including the plasma sheath capacitance. The resistive output stage 705 may reset the sheath capacitor during one half cycle of the RF sinusoid. The waveform 805 is much flatter around-2.5 kV. For example, the flatness of waveform 805 can be better used to keep ions at a constant potential during etching. For example, resistive output stage 705 and/or current blocking diode D7 may produce a bias that causes this flatness. The component values may be adjusted to change the rise time, fall time, and/or degree of flatness of the portion of the output waveform.

In some embodiments, the blocking diode D7 may be replaced by a switch (e.g., such as a high voltage switch). The high voltage switch may comprise the high voltage switch 1800 shown in fig. 18. For example, the high voltage switch may be closed during forward conduction (e.g., when the output of the RF generator 515 is above a voltage threshold) and open during reverse bias (e.g., when the output of the RF generator 515 is below a voltage threshold).

The cardholder voltage may be around 500V during a burst and about 2kV when closed, which may be acceptable. The RF output voltage is increased to around 4kV and the difference may be about 2kV during both the on and off periods, as shown in fig. 10. Increasing the RF output voltage to around 6kV, the difference during the on time may be about 3kV or more (which may not be acceptable), and during the off time may be about 2kV, as shown in fig. 11. In the case of a 3kV difference, wafer damage may occur.

Fig. 12 is another schematic diagram of a plasma sheath control system 1200 for an RF plasma reactor having a resistive output stage 705 and a DC bias circuit 1204, according to some embodiments.

The DC bias circuit 1204 may include the components shown in the DC bias circuit 104. The DC bias circuit 1204 may further include a high voltage switch S1 and/or a current blocking diode D2. In some embodiments, the high voltage switch S1 may include multiple switches arranged in series to collectively open and close the high voltage. The high voltage switch S1 may include a high voltage switch (e.g., such as the high voltage switch 1800 shown in fig. 18).

In some embodiments, the high voltage switch S1 may be open while the RF power source V5 voltage waveform is positive and closed when negative. When closed, for example, the high voltage switch S1 may short the current across the current blocking diode D2. Shorting the current may allow the bias between the wafer and the chuck to be maintained at approximately 2kV, which may be within acceptable tolerances and/or may be adjusted by varying the DC bias supply voltage V1.

Figure 13 shows a waveform across the sheath (e.g., C3) and at the clip (e.g., C2) from the circuit shown in figure 12. As shown, the difference between the wafer and chuck voltage remains very close to-2 kV regardless of whether the RF power supply is on or off.

Fig. 14 is an enlarged view of three cycles of the waveform shown in fig. 12.

Figure 15 shows the end of a burst waveform where the voltage on the cardholder returns to zero.

Fig. 16 is a circuit diagram of a plasma sheath control system 1600 according to some embodiments. In this example, the plasma sheath control system 1600 may include a full bridge driver 1605. The full bridge driver 1605 may include an input voltage source V1, which may be a DC voltage source (e.g., a capacitive source, an AC-DC converter, etc.). In some embodiments, the full bridge driver 1605 may include four switches. In some embodiments, the driver may include a plurality of switches in series or in parallel. For example, the switches may include any type of solid state switch (e.g., such as IGBTs, MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, opto-electronic switches, etc.). These switches may be switched at high frequencies and/or may generate high voltage sinusoidal waveforms. For example, the frequencies may include frequencies of approximately 400kHz, 0.5MHz, 2.0MHz, 4.0MHz, 13.56MHz, 27.12MHz, 40.68MHz, 50MHz, and so forth.

In some embodiments, a full bridge driver is coupled with the resonant circuit 1610. The resonant circuit 1610 may include a resonant inductor L5 and/or a resonant capacitor C2 coupled with a transformer T1. In some embodiments, transformer T1 may be removed. The resonant circuit may further include a stray resistance R5, which may include, for example, the resistance of the full bridge driver and the resonant circuit 1610 and/or any leads between any components within the resonant circuit 1610 (e.g., transformer T1, capacitor C2, inductor L5, and resistor R5).

Although the inductance and/or capacitance of other circuit elements may affect the drive frequency, the drive frequency may be set greatly by choosing the resonant inductor L5 and/or the resonant capacitor C2. Further refinement and/or tuning may be required to create the appropriate drive frequency. Furthermore, by changing the inductance of inductor L5 and/or the capacitance of capacitor C2, the rise time across transformer T1 can be adjusted, given:

for example, the capacitor C2, resistor R5, or inductor L5 may be tunable such that the values for the device may be tuned or modified to ensure that the frequency is constant as other components change over time.

In some embodiments, a large inductance value for inductor L5 may result in a slower or shorter rise time. These values may also affect the burst envelope. Each burst may include transient and steady state sinusoidal waveforms. The instantaneous sine waveform within each burst is set by L5 and/or the Q of the system until the full voltage is reached during the steady state sine waveform.

If the switches in the driver circuit are at the resonant frequency f_resonantSwitching is performed and the output voltage at the transformer will be amplified. In some embodiments, the resonant frequency may be approximately 20Hz, 50Hz, 100Hz, 250Hz, 400kHz, 0.5MHz, 2.0MHz, 4.0MHz, 13.56MHz, 27.12MHz, 40.68MHz, 50MHz, 100MHz, and the like.

In some embodiments, resonant capacitor C2 may include stray capacitance of transformer T1 and/or a physical capacitor. In some embodiments, the resonant capacitor C2 may have a capacitance of approximately 10 μ F, 1 μ F, 100nF, 10nF, etc. In some embodiments, resonant inductor L5 may include stray inductance of transformer T1 and/or a physical inductor. In some embodiments, the resonant inductor L5 may have an inductance of approximately 50nH, 100nH, 150nH, 500nH, 1,000nH, and so on. In some embodiments, the resonant resistor R5 may have a resistance of approximately 10 ohms, 25 ohms, 50 ohms, 100 ohms, 150 ohms, 500 ohms, or the like.

In some embodiments, the plasma load within the plasma chamber may be a time-varying load. This time-variation may affect one or both of the inductance or capacitance of the resonant circuit, which may cause the resonant frequency f_resonantOf (3) is detected. In some embodiments, the plasma sheath control system may include a controller (e.g., a microcontroller, FPGA, or any control device). In some embodiments, the controller may measure the output voltage and/or current of the plasma sheath control system, for example, at point 121. In some embodiments, the voltage or current measurement may be used to determine whether the plasma sheath control system is operating at a resonant frequency. In some embodiments, if the system is not operating at a resonant frequency, the controller may change the operating frequency of the plasma sheath control system to match the resonant frequency, such as by adjusting an inductance or capacitance value in the resonant circuit 1610, for example.

In some embodiments, for example, the amplitude of the current or voltage waveform generated by the plasma sheath control system at points 121, 122, 124, 125 or at any point in the circuit may be measured by the controller. In some embodiments, the measured or current and/or voltage may be used to determine the output power of the plasma sheath control system. In some embodiments, the controller may alter the operating frequency, voltage, or duty cycle in response to the measurement to achieve a desired output voltage, current, or power level.

In some embodiments, one or both of the operating frequency and the output power of the plasma sheath control system may be controlled by a controller. In some embodiments, the controller may detect changes in the input waveform and adjust the operating frequency and/or power level on a fast time scale (e.g., less than about 100ms, less than about 1ms, less than about 10 μ s, less than about 500ns, etc.).

In some embodiments, resistor R5 may represent a stray resistance of a wire, trace, and/or transformer winding within a physical circuit. In some embodiments, resistor R5 may have a resistance of approximately 10mohm, 50mohm, 100mohm, 200mohm, 500mohm, or the like.

In some embodiments, Transformer T2 may comprise the Transformer disclosed in U.S. patent application No.15/365,094 entitled "High Voltage Transformer," which is incorporated into this document for all purposes.

In some embodiments, the output voltage of the resonant circuit 1610 may be varied by varying the duty cycle of the switches S1, S2, S3, and/or S4 (e.g., the switch "on" time or the time the switch is conducting). For example, the longer the duty cycle, the higher the output voltage; and the shorter the duty cycle, the shorter the output voltage. In some embodiments, the output voltage of the resonant circuit 1610 may be varied or tuned by adjusting the duty cycle of the switches in the full bridge driver. For example, the output voltage of the driver may be adjusted by adjusting the duty cycle of the signals (e.g., Sig1 and Sig2) that open and close switches S1, S2, S3, and S4.

In some embodiments, each switch (e.g., S1, S2, S3, and/or S4) in the resonant circuit may be switched independently or in combination with one or more of the other switches.

In some embodiments, the resonant circuit 1610 may be coupled with a half-wave rectifier 1615 and/or a current blocking diode D7. In some embodiments, the blocking diode D7 may be replaced by a switch (e.g., such as a high voltage switch). The high voltage switch may comprise the high voltage switch 1800 shown in fig. 18. For example, the high voltage switch may be closed during forward conduction (e.g., when the output of the RF generator 515 is above a voltage threshold) and open during reverse bias (e.g., when the output of the RF generator 515 is below a voltage threshold).

In some embodiments, the current blocking diode D7 may rectify the sinusoidal waveform from the full bridge driver 1605. For example, the choke diode D7 may rectify the sinusoidal waveform, creating a rectified sinusoidal waveform with a substantially flat portion for at least 10%, 15%, 20%, 25%, 30%, etc. of each cycle.

In some embodiments, a half-wave rectifier 1615 or a current blocking diode D7 may be coupled with the resistive output stage 1620. The resistive output stage 1620 may comprise any resistive output stage known in the art. For example, the RESISTIVE OUTPUT STAGE 1620 may comprise any of the RESISTIVE OUTPUT STAGEs described in U.S. patent application No.16/178,538 entitled "HIGH VOLTAGE responsive OUTPUT STAGE CIRCUIT," which is incorporated in its entirety into this disclosure for all purposes. For example, the resistive output stage 1620 may include elements in the resistive output stage 705.

In some embodiments, the resistive output stage may include at least one resistor (e.g., R1) that discharges a load (e.g., plasma sheath capacitance). In some embodiments, the resistive output stage may be configured to discharge an average power in excess of about 1 kilowatt during each sinusoidal waveform period, and/or to discharge an energy of one joule or less during each sinusoidal waveform period. In some embodiments, the resistance of the resistor R1 in the resistive output stage may be less than 200 ohms. In some embodiments, the resistor R1 may include multiple resistances arranged in series or parallel with a combined capacitance of less than about 200pF (e.g., C11).

In some embodiments, the resistive output stage 1620 may include a set of circuit elements that may be used to control the shape of a voltage waveform across a load. In some embodiments, the resistive output stage 1620 may include only passive elements (e.g., resistors, capacitors, inductors, etc.). In some embodiments, the resistive output stage 1620 may include active circuit elements (e.g., switches) as well as passive circuit elements. In some embodiments, for example, the resistive output stage 1620 may be used to control a voltage rise time of a waveform and/or a voltage fall time of a waveform.

In some embodiments, the resistive output stage 705 may discharge a capacitive load (e.g., capacitive charge from the wafer plasma sheath 505 and/or the wall plasma sheath 510). For example, these capacitive loads may have small capacitances (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

In some embodiments, resistive output stage 1620 may be used in a circuit having a sinusoidal waveform with high peak voltages (e.g., voltages greater than 1kV, 10kV, 20kV, 50kV, 100kV, etc.) and/or high frequencies (e.g., frequencies greater than 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.) and/or frequencies of about 400kHz, 0.5MHz, 2.0MHz, 4.0MHz, 13.56MHz, 27.12MHz, 40.68MHz, 50MHz, etc.

In some embodiments, the resistive output stage 1620 may be selected to handle high average power, high peak power, fast rise time, and/or fast/fall time. For example, the average power rating may be greater than about 0.5kW, 1.0kW, 10kW, 25kW, etc., and/or the peak power rating may be greater than about 1kW, 10kW, 100kW, 1MW, etc.

In some embodiments, the resistive output stage 1620 may comprise a series or parallel network of passive components. For example, the resistive output stage may include a resistor, a capacitor, and an inductor in series. As another example, a resistive output stage may include a capacitor in parallel with an inductor and a capacitor-inductor combination in series with a resistor. For example, L11 may be chosen to be large enough so that there is no significant energy injected into the resistive output stage when there is a voltage outside the rectifier. The values of R3 and R1 may be chosen so that the L/R time can deplete the appropriate capacitors in the load faster than the RF frequency.

In some embodiments, the resistive output stage 1620 may be coupled with a bias compensation circuit 1625.

Bias compensation circuit 1625 may include any bias and/or bias compensation circuit known in the art. For example, the BIAS COMPENSATION circuit 1625 may include any of the BIAS and/or BIAS COMPENSATION circuits described in U.S. patent application No.162/711,406 entitled "nanoelectronic pulse BIAS COMPENSATION," which is incorporated in its entirety into this disclosure for all purposes.

In some embodiments, the bias compensation circuit 1625 may include a bias capacitor C7, a current blocking capacitor C12, a current blocking diode D8, a switch S8 (e.g., a high voltage switch), an offset supply voltage V1, a resistor R2, and/or a resistor R4. In some embodiments, switch S8 includes a high voltage switch (e.g., such as high voltage switch 1800 shown in fig. 18).

In some embodiments, the offset supply voltage V5 may include a DC voltage source that may bias the output voltage positively or negatively. In some embodiments, the capacitor C12 may isolate/split the offset supply voltage V5 from the resistive output stage 1620 and/or other circuit elements. In some embodiments, bias compensation circuit 1625 may allow for the transfer of power from one portion of the circuit to another. In some embodiments, the bias compensation circuit 1625 may be used to hold the wafer in place because the high voltage sinusoidal waveform is active within the chamber. Resistor R2 may protect/isolate the DC bias supply from the bridge driver.

In some embodiments, switch S8 may be open at the same time full bridge driver 1605 is pulsing, and closed when full bridge driver 1605 is not pulsing. While closed, switch S8 may short circuit the current, e.g., across current blocking diode D8. Shorting the current may allow for a bias between the wafer and the chuck of less than 2kV, which may be within acceptable tolerances.

In some embodiments, the plasma sheath control system 1600 may or may not include a conventional matching network (e.g., such as a 50ohm matching network or an external matching network or a stand-alone matching network). Embodiments described within this document may or may not require a 50ohm matching network to tune the switching power applied to the wafer chamber. Typically, tuning of the matching network may take at least 100-200 mus. In some embodiments, the power change may occur within one or two RF cycles (e.g., 2.5 μ s-5.0 μ s) at 400 kHz.

Fig. 17 is a circuit diagram of a plasma sheath control system 1700 according to some embodiments. The plasma sheath control system 1700 includes a waveform generator 1745 that generates a high voltage and high frequency sinusoidal waveform, such as, for example, to drive a plasma chamber. In some embodiments, waveform generator 1745 may comprise any device that produces a sinusoidal waveform having a peak voltage greater than 1kV, 10kV, 20kV, 50kV, 100kV, etc., and a high frequency greater than 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.

In some embodiments, the waveform generator 1745 may include an RF generator 515, a full-bridge driver 1605, or a half-bridge driver 1905. In some embodiments, waveform generator 1745 may or may not include a transformer.

In some embodiments, waveform generator 1745 may be coupled to energy recovery circuitry 1705. If waveform generator 1745 includes a transformer, energy recovery circuit 1705 may be located on or electrically coupled to the secondary side of transformer T1.

For example, energy recovery circuit 1705 may include a diode 1730 (e.g., crowbar diode) across the secondary side of transformer T1. For example, the energy recovery circuit 1705 may include a diode 1710 and an inductor 1715 (arranged in series), which may allow a discharge flow of current from the load stage 106 (e.g., a capacitive load) to charge the power supply C7. Diode 1710 and inductor 1715 may be electrically connected to load stage 106 and power supply C7.

In some embodiments, energy recovery circuit 1705 may include a current blocking diode 1735. The current blocking diode 1735 may be similar to the current blocking diode D7, or may operate in a similar manner as the current blocking diode D7. For example, the choke diodes 1735 may rectify the sinusoidal waveforms, which may, for example, produce a flat top on each sinusoidal waveform (e.g., as shown in fig. 9). For example, the choke diodes 1735 may rectify the sinusoidal waveform, creating a sinusoidal waveform with substantially flat portions for at least 10%, 15%, 20%, 25%, 30%, etc. of each cycle.

In some embodiments, the current blocking diode 1735 may be replaced with a switch (e.g., such as a high voltage switch). The high voltage switch may comprise the high voltage switch 1800 shown in fig. 18. For example, the high voltage switch may be closed during forward conduction (e.g., when the output of the RF generator 515 is above a voltage threshold) and open during reverse bias (e.g., when the output of the RF generator 515 is below a voltage threshold).

In some embodiments, the energy recovery circuit 1705 may include an inductor 1740 that may be electrically coupled with the load stage 106. Inductor 1740 may represent a stray inductance of a transformer within waveform generator 1745 and/or may include a stray inductance between waveform generator 1745 and energy recovery circuitry 1705 (e.g., inductive transformer T1).

When the waveform generator 1745 is turned on, current may charge the load stage 106 (e.g., charge capacitor C3, capacitor C2, or capacitor C9). For example, when the voltage on the secondary side of transformer T1 rises above the charging voltage on power supply C7, some current may flow through inductor 1715. When the waveform generator 1745 is off, current may flow from the capacitor within the load stage 106 through the inductor 1715 to charge the supply C7 until the voltage across the inductor 1715 is zero. The diode 1730 may prevent looping of capacitors within the load stage 106 and inductors in the load stage 106 or the DC bias circuit 104.

For example, diode 1710 may prevent charge from flowing from power supply C7 to a capacitor within load stage 106.

The value of inductor 1715 may be selected to control the current fall time. In some embodiments, inductor 1715 may have an inductance value between 1 μ H-500 μ H.

In some embodiments, the energy recovery circuit 1705 may include a switch that may be used to control the flow of current through the inductor 1715. For example, a switch may be placed in series with inductor 1715. In an embodiment, when the switch S1 is open and/or no longer pulsed, the switch may be closed to allow current to flow from the load stage 106 back to the high voltage load C7. For example, the switch may comprise a high voltage switch (e.g., such as high voltage switch 1800).

An energy recovery circuit 1705 may be added to the plasma sheath control system 500, the plasma sheath control system 700, the plasma sheath control system 1200, the plasma sheath control system 1600, or the plasma sheath control system 1900. In some embodiments, energy recovery circuit 1705 may replace a resistive output stage (e.g., such as resistive output stage 705 or resistive output stage 1620).

The DC bias circuit 1704 may include a DC bias circuit 1704, a bias compensation circuit 1625, a DC bias circuit 1204, or a DC bias circuit 104.

The second lead stage 105 may represent a circuit element between the waveform generator 1745 and the load stage 106.

In this example, the plasma sheath control system 1700 can be coupled with the load stage 106 (which can, for example, include any element in the load stage 106) and provide a sinusoidal waveform thereto.

Fig. 18 is a block diagram of a high voltage switch 1800 with an isolated power supply according to some embodiments. The high voltage switch 1800 may include a plurality of switching modules 1805 (collectively or individually 1805, and individually 1805A, 1805B, 1805C, and 1805D) that may switch the voltage from the high voltage source 1860 through a fast rise time and/or high frequency and/or through a variable pulse width. Each switch module 1805 may include a switch 1810 (e.g., such as a solid state switch).

In some embodiments, the switch 1810 may be electrically coupled with a gate driver circuit 1830, which may include a power source 1840 (e.g., 1840A, 1840B, 1840C, or 1840D) and/or an isolated fiber trigger 1845 (e.g., 1845A, 1845B, 1845C, or 1845D) (also referred to as a gate trigger or switch trigger). For example, the switch 1810 may include a collector, an emitter, and a gate (or a drain, a source, and a gate), and the power supply 1840 may drive the gate of the switch 1810 via the gate driver circuit 1830. For example, the gate driver circuit 1830 may be isolated from other components of the high voltage switch 1800.

In some embodiments, for example, the power supply 1840 may be isolated using an isolation transformer. The isolation transformer may comprise a low capacitance transformer. For example, the low capacitance of the isolation transformer may allow the power supply 1840 to charge on a fast time scale without requiring significant current. For example, the isolation transformer may have a capacitance of less than about 100 pF. As another example, the isolation transformer may have a capacitance of less than about 30-100 pF. In some embodiments, the isolation transformer may provide voltage isolation of up to 1kV, 5kV, 10kV, 25kV, 50kV, and the like.

In some embodiments, the isolation transformer may have a low stray capacitance. For example, the isolation transformer may have a stray capacitance of less than about 1,000pF, 100pF, 10pF, etc. In some embodiments, the low capacitance may minimize electrical coupling to low voltage components (e.g., a source of an input control power supply) and/or may reduce EMI generation (e.g., electrical noise generation). In some embodiments, the transformer stray capacitance of the isolation transformer may comprise a measured capacitance between the primary winding and the secondary winding.

In some embodiments, the isolation transformer may be a DC to DC converter or an AC to DC transformer. In some embodiments, for example, the transformer may comprise a 110V AC transformer. Regardless, the isolation transformer may provide a power source that is isolated from other components in the high voltage switch 1800. In some embodiments, the isolation may be galvanic (galvanic) such that the conductor on the primary side of the isolation transformer does not pass through or make contact with the secondary side of the isolation transformer.

In some embodiments, the transformer may include a primary winding that may be tightly wound or wrapped around the transformer core. In some embodiments, the primary winding may include a conductive sheet wrapped around the core of the transformer. In some embodiments, the primary winding may include one or more windings.

In some embodiments, the secondary winding may be wound around the core as far away from the core as possible. For example, a winding bundle including a secondary winding may be wound through the center of an aperture in a transformer core. In some embodiments, the secondary winding may include one or more windings. In some embodiments, the wire bundle including the secondary winding may include a circular or square cross-section, for example, to minimize stray capacitance. In some embodiments, an insulator (e.g., oil or air) may be disposed between the primary winding, the secondary winding, or the transformer core.

In some embodiments, keeping the secondary winding away from the transformer core may have some benefits. For example, it may reduce stray capacitance between the primary side of the isolation transformer and the secondary side of the isolation transformer. As another example, it may allow for high voltage isolation between the primary side of the isolation transformer and the secondary side of the isolation transformer such that no corona and/or breakdown is formed during operation.

In some embodiments, the separation between the primary side of the isolation transformer (e.g., the primary winding) and the secondary side of the isolation transformer (e.g., the secondary winding) may be about 0.1 inches, 0.5 inches, 1 inch, 5 inches, or 10 inches. In some embodiments, a typical spacing between the core of the isolation transformer and the secondary side (e.g., secondary winding) of the isolation transformer may be about 0.1 inches, 0.5 inches, 1 inch, 5 inches, or 10 inches. In some embodiments, the gaps between the windings may be filled with the lowest possible dielectric material (e.g., such as vacuum, air, any insulating gas or liquid, or a solid material with a relative dielectric constant less than 3).

In some embodiments, power supply 1840 may include any type of power supply that may provide high voltage isolation or have low capacitance (e.g., less than about 1,000pF, 100pF, 10pF, etc.). In some embodiments, the control voltage power supply may provide 1820V AC or 240V AC at 60 Hz.

In some embodiments, each power supply 1840 may be inductively electrically coupled to a single control voltage supply. For example, the power supply 1840A may be electrically coupled to a power supply via a first transformer; the power supply 1840B may be electrically coupled to a power supply via a second transformer; the power supply 1840C may be electrically coupled to a power supply via a third transformer; and power supply 1840D may be electrically coupled to a power supply via a fourth transformer. For example, any type of transformer that can provide voltage isolation between the various power sources may be used.

In some embodiments, the first, second, third and fourth transformers may comprise different secondary windings around the core of a single transformer. For example, a first transformer may include a first secondary winding, a second transformer may include a second secondary winding, a third transformer may include a third secondary winding, and a fourth transformer may include a fourth secondary winding. Each of these secondary windings may be wound around the core of a single transformer. In some embodiments, the first secondary winding, the second secondary winding, the third secondary winding, the fourth secondary winding, or the primary winding may comprise a single winding or a plurality of windings wound around the transformer core.

In some embodiments, power supply 1840A, power supply 1840B, power supply 1840C, and/or power supply 1840D may not share a return reference ground or a local ground.

For example, the isolating fiber trigger 1845 may also be isolated from other components of the high voltage switch 1800. The isolation fiber triggers 1845 may include fiber optic receivers that allow each switch module 1805 to float relative to other switch modules 1805 and/or other components of the high voltage switch 1800 and/or, for example, while allowing active control of the gate of each switch module 1805.

In some embodiments, the return reference ground or local ground or common ground for each switch module 1805 may be isolated from each other, for example, using an isolation transformer.

For example, the electrical isolation of each switch module 1805 from the common ground may allow multiple switches to be arranged in a series configuration for accumulating high voltage switches. In some embodiments, some hysteresis in the timing of the switch modules may be allowed or designed. For example, each switch module 1805 may be configured or rated for 1kV of switches, each switch module may be electrically isolated from each other, and/or the timing of closing each switch module 1805 may not need to be perfectly aligned for a period of time defined by the capacitance of the snubber capacitor and/or the voltage rating of the switches.

In some embodiments, electrical isolation may provide a number of advantages. For example, one possible advantage may include: minimize switch-to-switch jitter, and/or allow arbitrary switch timing. For example, each switch 1810 may have a switch transition jitter of less than approximately 500ns, 50ns, 20ns, 5ns, etc.

In some embodiments, electrical isolation between two components (or circuits) may imply an extremely high resistance between the two components, and/or may imply a small capacitance between the two components.

Each switch 1810 may include any type of solid state switching device (e.g., such as an IGBT, MOSFET, SiC junction transistor, FET, SiC switch, GaN switch, opto-electronic switch, etc.). For example, switch 1810 may be capable of switching high voltages (e.g., voltages greater than about 1 kV) at high speeds (e.g., repetition rates greater than about 500 kHz) with high frequencies (e.g., greater than 1kHz) and/or with fast rise times (e.g., rise times less than about 25 ns). In some embodiments, each switch may be individually rated for switching 1,200V-1,700V, while in combination more than 4,800V-6,800V (for four switches) may be switched. Switches having various other voltage ratings may be used.

There may be some advantages to using a large number of lower voltage switches instead of a few higher voltage switches. For example, low voltage switches typically have better performance: low voltage switches may switch faster, may have faster transition times and/or may switch more efficiently than high voltage switches. However, the larger the number of switches, the greater the timing issues that may be required.

The high voltage switch 1800 shown in fig. 18 includes four switch modules 1805. Although four are shown in this figure, any number of switch modules 1805 may be used (e.g., two, eight, twelve, sixteen, twenty-four, etc.). For example, if each switch in each switch module 1805 is rated at 1200V and sixteen switches are used, high voltage switching may be performed up to 19.2 kV. As another example, if each switch in each switch module 1805 is rated at 1700V and sixteen switches are used, high voltage switching may be performed up to 27.2 kV.

In some embodiments, the high voltage switch 1800 may include a flying capacitor 1855. For example, the flying capacitor 1855 may include one or more capacitors arranged in series and/or parallel. For example, the capacitors may include one or more polypropylene capacitors. The flying capacitor 1855 may store energy from the high voltage source 1860.

In some embodiments, the flying capacitor 1855 may have a low capacitance. In some embodiments, the flying capacitor 1855 may have a capacitance value of about 1 μ F, about 5 μ F, between about 1 μ F and about 5 μ F, between about 100nF and about 1,000nF, and the like.

In some embodiments, high voltage switch 1800 may or may not include crowbar diode 1850. The crowbar diode 1850 may include a plurality of diodes arranged in series or parallel, which may be beneficial for driving inductive loads, for example. In some embodiments, the crowbar diode 1850 may include one or more schottky diodes (e.g., such as silicon carbide schottky diodes). For example, crowbar diode 1850 may sense whether the voltage from a switch of the high voltage switches is above a particular threshold. If so, crowbar diode 1850 may short the power from the switch module to ground. For example, crowbar diodes may allow the alternating current path to dissipate the energy stored in the inductive load after switching. This may prevent large inductive voltage spikes, for example. In some embodiments, the crowbar diode 1850 may have a low inductance (e.g., such as 1nH, 10nH, 100nH, etc.). In some embodiments, the crowbar diode 1850 may have a low capacitance (e.g., such as 100pF, 1nF, 10nF, 100nF, etc.).

In some embodiments, such as when the load 1865 is primarily resistive, for example, the crowbar diode 1850 may not be used.

In some embodiments, each gate driver circuit 1830 may generate a jitter of less than approximately 1000ns, 100ns, 10.0ns, 5.0ns, 3.0ns, 1.0ns, and so on. In some embodiments, each switch 1810 can have a minimum on-time (e.g., less than about 10 μ β, 1 μ β, 500ns, 100ns, 50ns, 10ns, 5ns, etc.) and a maximum on-time (e.g., greater than 25s, 10s, 5s, 1s, 500ms, etc.).

In some embodiments, during operation, each of the high voltage switches may turn on and/or off within 1ns of each other.

In some embodiments, each of the switching modules 1805 may have the same or substantially the same (± 5%) stray inductance. The stray inductance may include any inductance within the switch module 1805 not associated with an inductor (e.g., such as inductance in leads, diodes, resistors, switches 1810, and/or circuit board traces, etc.). The stray inductance within each switching module 1805 may include a low inductance (e.g., an inductance such as less than about 300nH, 100nH, 10nH, 1nH, etc.). The stray inductance between each of the switching modules 1805 can include a low inductance (e.g., an inductance such as less than about 300nH, 100nH, 10nH, 1nH, etc.).

In some embodiments, each of the switch modules 1805 may have the same or substantially the same (± 5%) stray capacitance. Stray capacitances may include any capacitance within switch module 1805 not associated with a capacitor (e.g., such as capacitances in leads, diodes, resistors, switch 1810, and/or circuit board traces, etc.). The stray capacitances within each switch module 1805 may include low capacitances (e.g., such as less than about 1,000pF, 100pF, 10pF, etc.). The stray capacitance between each switch module 1805 may include a low capacitance (e.g., such as less than about 1,000pF, 100pF, 10pF, etc.).

For example, defects in voltage distribution may be addressed by passive snubber circuits (e.g., snubber diode 1815, snubber capacitor 1820, and/or freewheeling diode 1825). For example, small differences in timing or differences in inductance or capacitance between the opening or closing of each of the switches 1810 may cause voltage spikes. These spikes may be mitigated by various snubber circuits (e.g., snubber diode 1815, snubber capacitor 1820, and/or freewheeling diode 1825).

For example, the snubber circuit may include a snubber diode 1815, a snubber capacitor 1820, a snubber resistor 1816, and/or a freewheeling diode 1825. In some embodiments, a snubber circuit may be arranged in parallel with the switch 1810. In some embodiments, the buffer capacitor 1820 may have a low capacitance (e.g., such as a capacitance of less than about 100 pF).

In some embodiments, high voltage switch 1800 may be electrically coupled with or include a load 1865 (e.g., a resistive or capacitive or inductive load). For example, the load 1865 may have a resistance from 50 ohms to 500 ohms. Alternatively or additionally, the load 1865 may be an inductive load or a capacitive load.

Fig. 19 is a circuit diagram of a plasma sheath control system 1900 according to some embodiments. In this example, the plasma sheath control system 1900 may include a half-bridge driver 1905 instead of the full-bridge driver 1605 shown in fig. 16. Switches S1 and S2 may be alternately opened to allow current to flow through the load in one direction during a first time period and to allow current to flow through the load in the opposite direction during a second time period.

In some embodiments, a matching network may be included to match the impedance of the plasma chamber to the impedance of the RF generator, for example, to deliver maximum power to the plasma. This may be beneficial, for example, when using a 50ohm system. For example, plasma sheath control system 500, plasma sheath control system 700, or plasma sheath control system 1200 can include a matching network near resistor R13. As another example, plasma sheath control system 1600, plasma sheath control system 1700, or plasma sheath control system 1900 can include a matching network before inductor L2.

Unless otherwise specified, the term "substantially" means within 5% or 10% of the value referred to or within manufacturing tolerances. Unless otherwise specified, the term "about" means within 5% or 10% of the value referred to or within manufacturing tolerances.

As used in this document, the conjunction "or" is inclusive.

Numerous specific details are set forth herein to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, methods, devices, or systems that are well known to those of ordinary skill in the art have not been described in detail so as not to obscure claimed subject matter.

The use of "adapted to" or "configured to" herein is meant to not exclude both open and inclusive languages of devices adapted to or configured to perform additional tasks or steps. Further, the use of "based on" means open and inclusive in that: a process, step, calculation, or other action that is "based on" one or more stated conditions or values may actually be based on additional conditions or values beyond those stated. Headings, lists, and numbers are included herein for ease of explanation only and are not meant to be limiting.

While the present subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing may readily produce alterations to, variations of, and equivalents to these embodiments. Accordingly, it should be understood that the present disclosure has been presented for purposes of illustration and not limitation, and does not preclude inclusion of such modifications, variations and/or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art.