阅读说明：本技术 纳秒脉冲发生器偏置补偿 (Nanosecond pulser bias compensation ) 是由 肯尼斯·米勒 迪麦西·津巴 约翰·卡斯凯德 摩根·昆利 艾丽亚·斯劳伯道夫 于 2019-07-29 设计创作，主要内容包括：公开一种高电压功率系统。在一些实施例中,所述高电压功率系统包括：高电压脉冲发生电源；变压器,其与所述高电压脉冲发生电源电耦合；输出,其与所述变压器电耦合,并且配置为输出具有大于1kV的幅度和大于1kHz的频率的高电压脉冲；和偏置补偿电路,其布置为与所述输出并联。在一些实施例中,所述偏置补偿电路可以包括：阻流二极管；和DC电源,其布置为与所述阻流二极管串联。(A high voltage power system is disclosed. In some embodiments, the high voltage power system comprises: a high voltage pulse generating power supply; a transformer electrically coupled to the high voltage pulse generating power supply; an output electrically coupled to the transformer and configured to output high voltage pulses having an amplitude greater than 1kV and a frequency greater than 1 kHz; and a bias compensation circuit arranged in parallel with the output. In some embodiments, the bias compensation circuit may include: a current blocking diode; and a DC power supply arranged in series with the blocking diode.)

1. A high voltage power system comprising:

a high voltage pulse generating power supply;

a transformer electrically coupled to the high voltage pulse generating power supply;

an output electrically coupled to the transformer and configured to output high voltage pulses having an amplitude greater than 1kV and a frequency greater than 1 kHz; and

a bias compensation circuit arranged in parallel with the output, the bias compensation circuit comprising:

a bias compensation diode; and

a DC power supply disposed in series with the bias compensation diode.

2. The high voltage power system of claim 1, further comprising a bias compensation capacitor disposed at least across the DC power supply, the bias compensation capacitor having a capacitance of less than about 10 μ Ρ.

3. The high voltage power system of claim 1 wherein the high voltage pulse generating power source comprises a nanosecond pulser and transformer.

4. The high voltage power system of claim 1, wherein the high voltage power supply comprises: a plurality of switches arranged in series; and a transformer.

5. The high voltage power system of claim 1, wherein the bias compensation circuit comprises a high voltage switch disposed across the bias compensation diode, wherein the high voltage switch is configured to open when the high voltage pulse generating power supply is pulsing, and wherein the high voltage switch is configured to close when the high voltage pulse generating power supply is not pulsing.

6. The high voltage power system of claim 5 wherein the high voltage switch comprises a plurality of switches arranged in series.

7. The high voltage power system of claim 5, further comprising an inductor disposed in series with the high voltage switch, the inductor having an inductance of less than about 1 mH.

8. The high voltage power system of claim 1, wherein the output is coupled to an electrode that is capacitively coupled to the plasma.

9. A high voltage power system comprising:

a high voltage pulse generating power supply;

an output electrically coupled to the high voltage pulse generating power supply and configured to output high voltage pulses having an amplitude greater than 1kV and a pulse repetition frequency greater than 2 kHz; and

a bias compensation diode;

a DC power supply arranged in series with a bias compensation diode, the bias compensation diode and the DC power supply arranged in parallel with the output; and

a high voltage switch coupled across the bias compensation diode, wherein the high voltage switch is configured to turn off when the high voltage switching power supply is pulsing and to turn on when the high voltage switching power supply is not pulsing.

10. The high voltage power system of claim 9, further comprising a bias compensation capacitor disposed at least across the DC power supply.

11. The high voltage power system of claim 9, wherein the bias compensation diode, the DC power source, and the high voltage switch comprise a bias compensation circuit disposed across the output in the high voltage power system.

12. The high voltage power system of claim 9, wherein the output is coupled to an electrode that is capacitively coupled to the plasma.

13. The high voltage power system of claim 9, wherein the high voltage switch is configured to open when the high voltage pulse generating power supply is pulsing, and wherein the high voltage switch is configured to close when the high voltage pulse generating power supply is not pulsing.

14. The high voltage power system of claim 9, wherein the DC power source provides-5 kV to +5 kV.

15. The high voltage power system of claim 9, wherein the high voltage switch comprises a snubber circuit.

16. The high voltage power system of claim 9 wherein the high voltage switch comprises a plurality of switches arranged in series and having a plurality of voltage distribution resistors such that each of the plurality of voltage distribution resistors is arranged across a corresponding switch of the plurality of switches.

17. The high voltage power system of claim 9, wherein the bias compensation diode is configured to conduct current between 10A and 1kA at a frequency between 10Hz and 10 kHz.

18. The high voltage power system of claim 9, further comprising: a bias capacitor electrically coupled with the high voltage pulse generating power supply and the bias compensation diode, the bias capacitor having a value of less than about 10 μ F.

19. The high voltage power system of claim 9, further comprising an inductor disposed in series with the high voltage switch, the inductor having an inductance of less than about 1 mH.

20. The high voltage power system of claim 9, further comprising a resistor disposed in series with the high voltage switch, the resistor having a resistance of less than about 1000 mohms.

21. A method, comprising:

opening a bias compensation switch arranged in series with a DC power source, the bias compensation switch and the DC power source arranged across a load;

pulsing a high voltage power supply into the load at a voltage greater than 1kV and a pulse repetition frequency greater than 20 kHZ;

closing the bias compensation switch; and

the high voltage power supply is not pulsed.

22. The method of claim 21, wherein the load comprises an electrode that is capacitively coupled to the plasma.

Background

In plasma deposition systems, the wafer is typically electrostatically held in a chamber by a chuck (chuck). A plasma is created within the chamber and a high voltage pulse is introduced to accelerate ions within the plasma onto the wafer. If the potential between the chuck and the wafer exceeds a certain voltage threshold (e.g., about 2kV), the force on the wafer may be large enough to damage or destroy the wafer.

Disclosure of Invention

Embodiments of the invention include a method and circuit for bias compensation in a high voltage plasma chamber (e.g., such as a plasma deposition system, a semiconductor manufacturing system, a plasma sputtering system, etc.).

A high voltage power system is disclosed. In some embodiments, the high voltage power system comprises: a high voltage pulse generating power supply (e.g., nanosecond pulser); a transformer electrically coupled to the high voltage pulse generating power supply; an output electrically coupled with the transformer. The output of the high voltage power system may be configured to output high voltage pulses having an amplitude of greater than 1kV, 2kV, 5kV, 10kV, 25kV, etc., and a frequency of greater than 1 kHz; a bias compensation circuit arranged in parallel with the output. In some embodiments, the bias compensation circuit may include: a current blocking diode; and a DC power supply arranged in series with the blocking diode. In some embodiments, the high voltage power system may include a bias capacitor arranged at least across the DC power supply. In some embodiments, the high voltage power system may include a bias capacitor arranged at least across the DC power supply.

In some embodiments, the high voltage pulse generating power supply includes a nanosecond pulser and a transformer. In some embodiments, the high voltage power supply comprises: a plurality of switches arranged in series; and a transformer. In some embodiments, the high voltage power supply comprises a radio frequency power supply (such as an RF generator, for example).

In some embodiments, the bias compensation circuit includes a high voltage switch disposed across the bias compensation diode, wherein the high voltage switch is configured to open when the high voltage pulse generating power supply is pulsing, and wherein the high voltage switch is configured to close when the high voltage pulse generating power supply is not pulsing.

In some embodiments, the high voltage power supply comprises a plurality of switches arranged in series. In some embodiments, the bias compensation inductor has an inductance of less than about 100 μ H. In some embodiments, the output is coupled to the plasma, such as via an electrode capacitively coupled to the plasma, for example.

In some embodiments, a high voltage power system may include: a high voltage pulse generating power supply; an output electrically coupled to the transformer and configured to output high voltage pulses having an amplitude greater than 2kV and a frequency greater than 2 kHz; a current blocking diode; a DC power supply arranged in series with a current blocking diode, the current blocking diode and the DC power supply arranged in parallel with an output; and a high voltage switch coupled across the blocking diode, wherein the high voltage switch is configured to turn off when the high voltage switching power supply is pulsing (e.g., during a burst) and to turn on when the high voltage switching power supply is not pulsing (e.g., between bursts).

In some embodiments, the high voltage power system may further include a bias compensation capacitor disposed at least across the DC power supply, the bias compensation capacitor having a capacitance of less than approximately 500 μ F, 250 μ F, 100 μ F, 50 μ F, 25 μ F, 10 μ F, and so forth.

In some embodiments, the current blocking diode, the DC power source, and the high voltage switch include a bias compensation circuit disposed across the output in the high voltage power system.

In some embodiments, the output may comprise a plasma load. In some embodiments, the DC power supply provides approximately ± 5kV, ± 4kV, ± 3kV, ± 2kV, ± 1kV, and the like.

In some embodiments, the high voltage switch is configured to open when the high voltage pulse generating power supply is pulsing and wherein the high voltage switch is configured to close when the high voltage pulse generating power supply is not pulsing.

In some embodiments, the high voltage switch includes a snubber circuit.

Some embodiments may include a method comprising: opening a bias compensation switch arranged in series with a DC power source, the bias compensation switch and the DC power source arranged across a load; pulsing a high voltage power supply into the load at a high voltage and a high frequency; closing the bias compensation switch; and not pulsing the high voltage power supply.

Some embodiments include a high voltage power system comprising: a plurality of switches; a transformer; an output configured to output high voltage pulses having an amplitude greater than 2kV and a frequency greater than 1 kHz; a current blocking diode; and a bias capacitor.

Some embodiments include a high voltage power system comprising: a high voltage switching power supply; an output configured to output high voltage pulses having an amplitude greater than 2kV and a frequency greater than 1 kHz; a current blocking diode; a bias capacitor; and a high voltage switch coupled across the bias compensation diode, wherein the high voltage switch is configured to turn off when the high voltage switching power supply is pulsing and to turn on when the high voltage switching power supply is not pulsing.

Some embodiments include a high voltage power system that produces an output that creates a plasma within a wafer deposition chamber such that a voltage potential between the wafer and chuck is about 2kV during periods when the high voltage power system is pulsing and not pulsing.

These illustrative embodiments are mentioned not to limit or define the disclosure, but to provide examples to assist understanding thereof. Additional embodiments are discussed in the detailed description, and further description is provided herein. Advantages offered by one or more of the various embodiments may be further understood by examining this specification or by practicing one or more embodiments as presented.

Drawings

These and other features, aspects, and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings.

Fig. 1 is a circuit diagram of a high voltage power system with a plasma load according to some embodiments.

Fig. 2 illustrates example waveforms generated by a high voltage power system, according to some embodiments.

Fig. 3 is a circuit diagram of a high voltage power system with a plasma load according to some embodiments.

Fig. 4 illustrates example waveforms generated by a high voltage power system, according to some embodiments.

Fig. 5 is a circuit diagram of a high voltage power system with a plasma load according to some embodiments.

Fig. 6 illustrates example waveforms generated by a high voltage power system, according to some embodiments.

Fig. 7 is a circuit diagram of a high voltage power system with a plasma load according to some embodiments.

Fig. 8 illustrates example waveforms generated by a high voltage power system, according to some embodiments.

Fig. 9 is a circuit diagram of a high voltage power system with a plasma load according to some embodiments.

Fig. 10 illustrates example waveforms from a high voltage power system, according to some embodiments.

Fig. 11A illustrates example waveforms from a high voltage power system, according to some embodiments.

Fig. 11B illustrates example waveforms from a high voltage power system, according to some embodiments.

Fig. 12 is a circuit diagram of a high voltage power system with a plasma load according to some embodiments.

Fig. 13 is a circuit diagram of a high voltage power system with a plasma load according to some embodiments. Buffer and voltage divider resistor

Fig. 14 is a circuit diagram of a high voltage power system according to some embodiments.

Fig. 15 is a block diagram of a high voltage switch with an isolated power supply according to some embodiments.

Fig. 16 illustrates example waveforms from a high voltage power system, according to some embodiments.

Fig. 17 illustrates example waveforms from a high voltage power system, according to some embodiments.

Fig. 18 illustrates example waveforms from a high voltage power system, according to some embodiments.

Fig. 19 is a circuit diagram of a high voltage power system with a plasma load according to some embodiments.

Detailed Description

In plasma deposition systems, the wafer is typically electrostatically held in a chamber by a chuck (chuck). A plasma is created within the chamber and a high voltage pulse is introduced to accelerate ions within the plasma onto the wafer. If the potential between the chuck and the wafer exceeds a certain voltage threshold (e.g., about 2kV), the force on the wafer may be large enough to damage or destroy the wafer. In addition, it may be beneficial to introduce higher voltage pulses into the chamber to increase the trench depth, improve quality, or speed up the etch process. The introduction of high and relatively high voltage pulses into the plasma within the deposition chamber may affect the electrical potential between the chuck and the wafer and damage or destroy the wafer.

Systems and methods are disclosed for ensuring that the voltage between the wafer and the chuck is near or below a threshold value (e.g., about 2kV) during periods when high voltage pulses are occurring as well as during periods when no high voltage pulses are occurring. For example, these systems may also limit the self-bias of the wafer when using a high voltage rf power supply. For example, the systems and methods may compensate for voltage changes to ensure that the voltage between the chuck and the wafer does not exceed a voltage threshold.

In some embodiments, the high voltage power system may generate pulsed voltages introduced into the plasma having an amplitude of about 1kV, 2kV, 5kV, 10kV, 15kV, 20kV, 30kV, 40kV, and the like. In some embodiments, the high voltage power system may be switched at frequencies up to about 500 kHz. In some embodiments, the high voltage power system may provide a single pulse of varying pulse width from about 50 nanoseconds to about 1 nanosecond. In some embodiments, the high voltage power system may switch at a frequency greater than about 10 kHz. In some embodiments, the high voltage power system may operate with a rise time of less than about 20 ns.

As used throughout this document, the term "high voltage" may include voltages greater than about 1kV, 10kV, 20kV, 50kV, 100kV, 1,000kV, etc.; the term "high frequency" can be a frequency greater than about 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.; the term "high repetition rate" may be a rate greater than about 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc., and the term "fast rise time" may include rise times less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc.; the term "fast fall time" can include fall times of less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, and the like; the term "low capacitance" may include capacitances of less than about 1.0pF, 10pF, 100pF, 1,000pF, etc.; the term "low inductance" can include inductances of less than about 10nH, 100nH, 1,000nH, 10,000nH, and the like; and the term "short pulse width" may include pulse widths of less than about 10,000ns, 1,000ns, 500ns, 250ns, 100ns, 20ns, etc.

Fig. 1 is a circuit diagram of a high voltage power system 100 with a plasma load according to some embodiments. The high voltage power system 100 with plasma load may be generalized to six stages (which may be broken down into other stages or generalized to fewer stages, or may not include the components shown in the figures). A high voltage power system 100 with a plasma load includes a pulse generator stage 101, a resistive output stage 102, a lead stage 103, a DC bias circuit 104, a second lead stage 105, and a load stage 106. The pulse generator stage 101, the resistive output stage 102, or the DC bias circuit 104 may comprise a high voltage power system. Lead stage 103 or second lead stage 105 may also be included in a high voltage power system. And load stage 106 may include a plasma load.

In some embodiments, a high voltage power system 100 having a plasma load (or pulser stage 101) can introduce pulses into the load stage, wherein the voltages are greater than 1kV, 10kV, 20kV, 50kV, 100kV, 1,000kV, etc., wherein the rise times are less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc., wherein the fall times are less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc., and wherein the frequencies are greater than about 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.

In some embodiments, for example, the pulse generator stage 101 may comprise any device capable of generating pulses of greater than 500V, peak currents of greater than 10 amps, or pulse widths of less than about 10,000ns, 1,000ns, 100ns, 10ns, etc. As another example, the pulse generator stage 101 may generate pulses having an amplitude greater than 1kV, 5kV, 10kV, 50kV, 200kV, etc. As another example, the pulse generator stage 101 may generate pulses having rise or fall times of less than about 5ns, 50ns, 300ns, or the like.

In some embodiments, pulse generator stage 101 may generate multiple high voltage bursts. For example, each burst may include a plurality of high voltage pulses having a fast rise time and a fast fall time. For example, the plurality of high voltage bursts may have a burst repetition frequency of about 10Hz to 10 kHz. More specifically, for example, the plurality of high voltage bursts may have a burst repetition frequency of approximately 10Hz, 100Hz, 250Hz, 500Hz, 1kHz, 2.5kHz, 5.0kHz, 10kHz, and so forth.

Within each of the plurality of high voltage bursts, the high voltage pulses may have a pulse repetition frequency of about 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.

In some embodiments, the frequency time is repeated from one burst until the burst of the next burst. The frequency of the bias compensation switch is operated.

In some embodiments, the pulse generator stage 101 may include one or more solid state switches S1 (e.g., solid state switches (e.g., such as IGBTs, MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, etc.) coupled with a voltage source V2). In some embodiments, the pulse generator stage 101 may include one or more source snubber resistors R3, one or more source snubber diodes D4, one or more source snubber capacitors C5, or one or more source freewheeling diodes D2. One or more switches and/or circuits may be arranged in parallel or in series.

In some embodiments, the pulse generator stage 101 may generate a plurality of high voltage pulses having a high frequency, a fast rise time, a fast fall time, at a high frequency, and the like. The pulse generator stage 101 may include one or more nanosecond pulse generators.

In some embodiments, the pulse generator stage 101 may include a high voltage pulse generating power supply.

For example, the pulse generator stage 101 may comprise any of the pulse generators described in U.S. patent application serial No. 14/542,487 entitled "High Voltage Nanosecond Pulser," which is fully incorporated into this disclosure for all purposes. For example, the pulse generator stage 101 may comprise any of the pulse generators described in U.S. patent No.9,601,283 entitled "Efficient IGBT Switching," which is fully incorporated into the present disclosure for all purposes. For example, the pulse generator stage 101 may include any of the pulse generators described in U.S. patent application serial No.15/365,094 entitled "High Voltage Transformer," which is incorporated fully into this disclosure for all purposes.

For example, the pulse generator stage 101 may include a high voltage switch (see, e.g., fig. 3). For example, the pulse generator stage 101 may include the high voltage switch 1500 depicted in fig. 15. As another example, the pulse generator stage 101 may include any of the switches described in U.S. patent application serial No. 16/178,565 filed on 11/1/2018 entitled "High Voltage Switch with Isolated Power," which is incorporated in its entirety into this disclosure for all purposes, for example.

In some embodiments, the pulse generator stage 101 may include a transformer T2. The transformer T2 may include a transformer core (e.g., a toroidal or non-toroidal core); at least one primary winding wound once or less than once around the transformer core; and a secondary winding wound around the transformer core a plurality of times.

In some embodiments, the transformer T2 may include a single turn primary winding and a multi-turn secondary winding around the transformer core. For example, a single turn primary winding may include one or more wires wound around the transformer core one or less times. For example, a single-turn primary winding may include more than 2, 10, 20, 50, 100, 250, 1200, etc. individual single-turn primary windings. In some embodiments, the primary winding may comprise a conductive strip.

For example, a multi-turn secondary winding may include a single wire wound around a transformer core multiple times. For example, the multi-turn secondary winding may be wound more than 2 times, 10 times, 25 times, 50 times, 100 times, 250 times, 500 times, etc. around the transformer core. In some embodiments, a plurality of multi-turn secondary windings may be wound around the transformer core. In some embodiments, the secondary winding may comprise a conductive strip.

In some embodiments, the high voltage transformer may be used to output voltages greater than 1,000 volts with a fast rise time of greater than 150 nanoseconds, or less than 50 nanoseconds, or less than 5 ns.

In some embodiments, the high voltage transformer may have a low impedance and/or low capacitance. For example, the high voltage transformer has a stray inductance of less than 100nH, 50nH, 30nH, 20nH, 10nH, 2nH, 100pH measured on the primary side, and/or the transformer has a stray capacitance of less than 100pF, 30pF, 10pF, 1pF measured on the secondary side.

The Transformer T2 may comprise a Transformer as disclosed in U.S. patent application No.15/365,094 entitled "High Voltage Transformer," which is incorporated into this document for all purposes.

In some embodiments, multiple pulse generators may be combined in one or both of parallel or series. In some embodiments, the pulse generator stage 101 may be coupled with the resistive output stage 102 across the inductor L1 and/or the resistor R1. In some embodiments, inductor L1 may include an inductance of about 5 μ H to about 25 μ H. In some embodiments, the resistor R1 may include a resistance of about 50 ohms to about 250 ohms. Each of the plurality of pulse generator stages 101 may further include one or both of a current blocking diode D4 or a diode D6. In some embodiments, capacitor C4 may represent the stray capacitance of diode D6.

In some embodiments, the resistive output stage 102 may discharge a capacitive load (e.g., wafer and/or plasma).

In some embodiments, resistive output stage 102 may include one or more inductive elements represented by inductor L1 and/or inductor L5. For example, inductor L5 may represent the stray inductance of the leads in resistive output stage 102 and may have an inductance of less than approximately 500nH, 250nH, 100nH, 50nH, 25nH, 10nH, and so on. For example, inductor L1 may be set to minimize the power flowing from pulse generator stage 101 into resistor R1.

In some embodiments, the resistive output stage 102 may include at least one resistor R1, which may, for example, include a plurality of resistors in series or parallel, which may discharge a load (e.g., plasma sheath capacitance).

In some embodiments, the resistor R1 may dissipate charge from the load stage 106, for example, on a fast time scale (e.g., 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc. time scale). The resistance of resistor R1 may be low to ensure that the pulse across load stage 106 has a fast fall time t_f。

In some embodiments, the resistive output stage 102 may be configured to discharge an average power in excess of about 1 kilowatt during each pulse period, and/or to discharge an energy of one joule or less in each pulse period. In some embodiments, the resistance of the resistor R1 in the resistive output stage may be less than 200 ohms.

The capacitor C11 may represent a stray capacitance of the resistor R1 (or a plurality of resistors in a series or parallel arrangement represented by resistor R1), which includes the capacitance of the arrangement of series and/or parallel resistors. For example, the capacitance of stray capacitance C11 may be less than 500pF, 250pF, 100pF, 50pF, 10pF, 1pF, and so on. For example, the capacitance of the stray capacitance C11 may be less than the load capacitance (e.g., less than the total capacitance of C2, C3, and/or C9 or the individual capacitances of C2, C3, or C9).

In some embodiments, the resistive output stage 102 may include a set of circuit elements that may be used to control the shape of a voltage waveform across a load. In some embodiments, the resistive output stage 102 may include only passive elements (e.g., resistors, capacitors, inductors, etc.). In some embodiments, the resistive output stage 102 may include active circuit elements (e.g., switches) as well as passive circuit elements. In some embodiments, for example, the resistive output stage 102 may be used to control a voltage rise time of a waveform and/or a voltage fall time of a waveform.

In some embodiments, the resistive output stage 102 may be used in circuits with pulses of one or both of high pulsed voltage (e.g., voltages greater than 1kV, 10kV, 20kV, 50kV, 100kV, etc.) or high frequency (e.g., frequencies greater than 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.).

In some embodiments, the resistive output stage 102 may be selected to handle high average power, high peak power, fast rise time, fast fall time. For example, the average power rating may be greater than about 0.5kW, 1.0kW, 10kW, 25kW, etc., or the peak power rating may be greater than about 1kW, 10kW, 100kW, 1MW, etc.

In some embodiments, the resistive output stage 102 may include a series or parallel network of passive components. For example, the resistive output stage 102 may include a resistor, a capacitor, and an inductor in series. As another example, the resistive output stage 102 may include a capacitor in parallel with an inductor and a capacitor-inductor combination in series with a resistor.

In some embodiments, for example, current blocking diode D1 may ensure that current flows through resistor R1. For example, capacitor C8 may represent the stray capacitance of current blocking diode D1.

In some embodiments, the resistive output stage 102 may be replaced by an energy recovery circuit or any other sink (sink) stage or any other circuit that can quickly sink charge from the plasma on a fast time scale.

In some embodiments, the lead stage 103 may represent one or both of a lead or trace between the resistive output stage 102 and the DC bias circuit 104. One or both of inductor L2 or inductor L6 may represent inductance for one or both of a lead or trace.

In this example, the DC bias circuit 104 does not include any bias compensation. The DC bias circuit 104 includes an offset supply voltage V1 that may bias the output voltage, for example, positively or negatively. In some embodiments, the offset supply voltage V1 may be adjusted to change the offset between the wafer voltage and the chuck voltage. In some embodiments, the offset supply voltage V1 may have a voltage of approximately 5kV, + -4kV, + -3 kV, + -2kV, + -1 kV, and so on.

In some embodiments, the bias capacitor C12 may isolate (or separate) one or both of the DC bias voltage and the resistive output stage or other circuit elements. For example, the biasing capacitor C12 may allow for a potential transfer from one part of the circuit to another. In some embodiments, this potential transfer may ensure that the electrostatic force holding the wafer in place on the chuck stays below a voltage threshold. Resistor R2 may isolate the DC bias supply from the high voltage pulsed output from pulse generator stage 101.

For example, the bias capacitor C12 is 100pF, 10pF, 1pF, 100 μ F, 10 μ F, 1 μ F, or the like. For example, resistor R2 may have a high resistance (e.g., a resistance such as approximately 1kOhm, 10kOhm, 100kOhm, 1MOhm, 10MOhm, 100MOhm, etc.).

The second lead stage 105 represents circuit elements between the high voltage power system and the load stage 106. For example, resistor R13 may represent the resistance of a lead or transmission line connected from the output of the high voltage power system to an electrode (e.g., load stage 106). For example, capacitor C1 may represent stray capacitance in a lead or transmission line.

In some embodiments, the load stage 106 may represent an idealized or effective circuit for a semiconductor processing chamber (e.g., a plasma deposition system, a semiconductor manufacturing system, a plasma sputtering system, etc.). For example, the capacitance C2 may represent the capacitance of a chuck in which the wafer may be seated. For example, the clip may include a dielectric material. For example, the capacitor C1 may have a small capacitance (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

For example, capacitor C3 may represent the sheath capacitance between the plasma and the wafer. For example, resistor R6 may represent the sheath resistance between the plasma and the wafer. For example, inductor L2 may represent the sheath inductance between the plasma and the wafer. For example, current source I2 may represent the ion current through the sheath. For example, the capacitor C1 or the capacitor C3 may have a small capacitance (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

For example, the capacitor C9 may represent the capacitance within the plasma between the chamber wall and the top surface of the wafer. For example, the resistor R7 may represent the resistance within the plasma between the chamber wall and the top surface of the wafer. For example, current source I1 may represent the ion current in the plasma. For example, the capacitor C1 or the capacitor C9 may have a small capacitance (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

As used in this document, the plasma voltage is the voltage measured from ground to circuit point 123; the wafer voltage is the voltage measured from ground to circuit point 122 and may represent the voltage at the surface of the wafer; the clip voltage is the voltage measured from ground to circuit point 121; the electrode voltage is the voltage measured from ground to circuit point 124; and the input voltage is the voltage measured from ground to circuit point 125.

Fig. 2 shows an example waveform generated by a high voltage power system 100 with a plasma load. In these example waveforms, pulse waveform 205 may represent the voltage provided to load stage 106. As shown, the pulse waveform 205, which is the voltage at circuit point 124, produces a pulse with the following qualities: a high voltage (e.g., greater than about 4kV as shown in the waveform), a fast rise time (e.g., less than about 200ns as shown in the waveform), a fast fall time (e.g., less than about 200ns as shown in the waveform), and a short pulse width (e.g., less than about 300ns as shown in the waveform). Waveform 210 may represent the voltage at circuit point 122 (e.g., at the surface of the wafer). Waveform 215 represents the current flowing through the plasma (e.g., the current flowing through inductor L2).

During the transition state (e.g., during an initial number of pulses not shown in the figure), the high voltage pulses from pulse generator stage 101 charge capacitor C2. Because the capacitance of the capacitor C2 is large compared to one or both of the capacitor C3 or the capacitor C1, or because of the short pulse width of the pulses, the capacitor C2 can take multiple pulses from the high voltage pulse generator to fully charge. Once capacitor C2 is fully charged, the circuit reaches a steady state, as shown by the waveforms in fig. 2.

In steady state, and when switch S1 is open, capacitor C2 is charged and slowly dissipates through resistive output stage 110, as shown by the slightly rising slope of waveform 210. Once the capacitor C2 is charged, and while the switch S1 is open, the voltage at the surface of the wafer (the point between the capacitor C2 and the capacitor C3) is negative. The negative voltage may be the negative of the voltage of the pulse provided by the pulse generator stage 101. For the example waveform shown in fig. 2, the voltage of each pulse is about 4 kV; and the steady state voltage at the wafer is about-4 kV. This results in a negative potential across the plasma (e.g., across capacitor C3), which accelerates positive ions from the plasma to the surface of the wafer. While switch S1 is open, the charge on capacitor C2 slowly dissipates through the resistive output stage.

When the switch S1 changes from open to closed, the voltage across the capacitor C2 may flip as the capacitor C2 is charged (the pulse from the pulse generator is high, as shown by waveform 205). Further, as capacitor C2 charges, the voltage at circuit point 123 (e.g., at the surface of the wafer) changes to about zero, as shown by waveform 210. Thus, pulses from the high voltage pulse generator may generate a plasma potential (e.g., a potential in the plasma) that rises from a negative high voltage to zero and returns to a negative high voltage at a high frequency, with any or all of a fast rise time, a fast fall time, or a short pulse width.

In some embodiments, the action of the resistive output stage 102, the elements represented by the resistive output stage 102, may rapidly discharge the stray capacitance C1, and may allow the voltage at the point between the capacitor C2 and the capacitor C3 to rapidly return to its stable negative value of about-4 kV, as illustrated by waveform 210. The resistive output stage may allow the voltage at the point between capacitor C2 and capacitor C3 to exist for approximately% of the time, and thus maximize the time for ions to accelerate into the wafer. In some embodiments, the components contained within the resistive output stage may be specifically selected to optimize the time for which ions are accelerated into the wafer, and to keep the voltage during that time approximately constant. Thus, for example, short pulses with fast rise times and fast fall times may be useful, so there may be long periods of reasonably uniform negative potential.

In some embodiments, a bias compensation subsystem may be used to adjust chuck voltage in a semiconductor manufacturing wafer chamber. For example, a cardholder voltage may be applied to the cardholder to follow the track of a burst on/off pattern to ensure a constant voltage over the cardholder.

In some embodiments, any of the various High Voltage power systems may include the Resistive Output stages disclosed in this document, may include any or all of the components, arrangements, functions, etc. shown or described in U.S. patent application serial No. 15/941,731 entitled "High Voltage reactive Output Stage Circuit," filed 3, 30, 2018, which is incorporated herein in its entirety for all purposes.

Fig. 3 is a circuit diagram of a high voltage power system 300 with a plasma load according to some embodiments. The high voltage power system 300 with plasma load is similar to the high voltage power system 100 with plasma load. In this example, the pulse generator stage 110 includes a high voltage switch S1. In some embodiments, the high voltage switch S1 may include multiple switches arranged in series to collectively open and close the high voltage. For example, high voltage switch S1 may include high voltage switch 1500 described in fig. 15. As another example, the High Voltage Switch S1 may include any of the switches described in U.S. patent application serial No. 16/178,565, filed on 1/11/2018 entitled "High Voltage Switch with Isolated Power," which is incorporated in its entirety into this disclosure for all purposes, for example.

In any embodiment, pulse generator stage 101 or pulse generator stage 110 may be used to generate high voltage pulses. Furthermore, the pulse generator stage 101 and the pulse generator stage 110 may be interchangeable.

In this example, the DC bias circuit 104 does not include any bias compensation.

In some embodiments, the pulse generator stage 101 may generate pulses having the following properties: voltages greater than 1kV, 10kV, 20kV, 50kV, 100kV, 1,000kV, etc., rise times less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc., fall times less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc., and frequencies greater than about 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.

In some embodiments, the pulse generator stage 101 includes a radio frequency power supply (e.g., such as an RF generator).

Fig. 4 illustrates example waveforms generated by a high voltage power system (e.g., high voltage power system 100 with a plasma load or high voltage power system 300 with a plasma load). The wafer waveform 405 represents the voltage on the wafer and the chuck waveform 410 is the voltage on the chuck. The wafer waveform 405 is measured at the location labeled 122 on the circuit diagram in fig. 3. The cardholder waveform 410 is measured at the location marked 121 on the circuit diagram in figure 3. As shown, the difference between the chuck waveform 410 and the wafer waveform 405 is about 4kV during the pulse generation. In the case of peak voltages above 2kV, this may result in damage to the wafer on the chuck within the chamber.

The waveforms in fig. 4 show six bursts of about 10 seconds with multiple pulses within each burst.

Fig. 5 is a circuit diagram of a high voltage power system 500 with a plasma load according to some embodiments. The high voltage power system 500 with plasma load is similar to the high voltage power system 300 with plasma load.

In this example, the bias compensation circuit 114 is a passive bias compensation circuit and may include a bias compensation diode 505 and a bias compensation capacitor 510. The bias compensation diode 505 may be arranged in series with the offset supply voltage V1. The bias compensation capacitor 510 may be arranged across one or both of the offset supply voltage V1 and the resistor R2. The bias compensation capacitor 510 may have a capacitance of less than 100nF to 100 μ F (e.g., such as about 100 μ F, 50 μ F, 25 μ F, 10 μ F, 2 μ F, 500nF, 200nF, etc.).

In some embodiments, bias compensation diode 505 may conduct a current between 10A and 1kA at a frequency between 10Hz and 10 kHz.

In some embodiments, the bias capacitor C12 may allow for a voltage offset between the output of the pulse generator stage 101 (e.g., at the location labeled 125) and the voltage on the electrode (e.g., at the location labeled 124). In operation, for example, the electrodes may be at a DC voltage of-2 kV during the burst, while the output of the nanosecond pulse generator alternates between +6kV during the pulse and 0kV between the pulses.

For example, the bias capacitors C12 are 100nF, 10nF, 1nF, 100 μ F, 10 μ F, 1 μ F, and so forth. For example, resistor R2 may have a high resistance (e.g., a resistance such as approximately 1kOhm, 10kOhm, 100kOhm, 1MOhm, 10MOhm, 100MOhm, etc.).

In some embodiments, the bias compensation capacitor 510 and bias compensation diode 505 may allow a voltage offset between the output of the pulse generator stage 101 (e.g., at the location marked by 125) and the voltage on the electrode (e.g., at the location marked by 124) to be established at the beginning of each burst to achieve a desired state of equilibrium. For example, over the course of a number of pulses (e.g., about 5-100), at the beginning of each burst, charge is transferred from capacitor C12 into capacitor 510, establishing the correct voltage in the circuit.

Fig. 6 shows an example waveform generated by a high voltage power system 500 having a plasma load. As shown, the voltage bias between the wafer waveform 605 and the chuck waveform 610 remains fixed during the pulse burst, but remains charged after the burst. In this example, the difference between the wafer waveform 605 and the chuck waveform 610 during the pulsing is less than about 2kV, which may be within acceptable tolerances. However, in this example, the difference between the wafer waveform 605 and the chuck waveform 610 between pulses is greater than about 7kV, which may not be within acceptable tolerances.

The waveforms in fig. 6 show six bursts of about 10 seconds with multiple pulses within each burst.

Fig. 7 is a circuit diagram of a high voltage power system 700 with a plasma load according to some embodiments. The high voltage power system with plasma load 700 is similar to the high voltage power system with plasma load 500 and includes a second pulse generator circuit 705.

The second pulse generator circuit 705 may include the bias compensation circuit 114 or a similar component to the bias compensation circuit 114.

The second pulse generator circuit 705 may include a second pulse generator 701. For example, the second pulse generator 701 may include one or more or all of the components of the pulse generator stage 110 shown in fig. 1 or 3. For example, the pulser stage 110 can include a nanosecond pulser or a high voltage switch as disclosed in this document (e.g., fig. 15 and related paragraphs). In some embodiments, the second pulse generator 701 may be configured to turn off when the pulse generator stage 101 is generating pulses (e.g., during a burst), and the second pulse generator 701 may be configured to turn on when the pulse generator stage 101 is not generating pulses (e.g., in between bursts).

The second pulse generator circuit 705 may further include an inductor L9 on the secondary side of the transformer T2, and the switch 710 may be coupled with a voltage source V6. The inductor L9 may represent the stray inductance of the second pulse generator circuit 705 and may have a low inductance (e.g., such as an inductance of less than about 500nH, 250nH, 100nH, 50nH, 25nH, etc.). In some embodiments, voltage source V6 may represent a trigger for switch 710.

In some embodiments, the second pulse generator circuit 705 may include a current blocking diode D7. For example, current blocking diode D7 may ensure that current flows from switch 710 to load stage 106. For example, capacitor C14 may represent the stray capacitance of current blocking diode D7. For example, the capacitance of the capacitor C14 may have a low capacitance (e.g., such as less than about 1nF, 500pF, 200pF, 100pF, 50pF, 25pF, etc.).

In some embodiments, switch 710 may be opened while pulse generator stage 110 is generating a pulse and closed when pulse generator stage 110 is not generating a pulse to offset (or bias) the voltage provided by the pulse generator stage.

In some embodiments, switch S1 may include multiple switches arranged in series to collectively open and close a high voltage. In some embodiments, switch 710 may comprise high voltage switch 1500 described in fig. 15. As another example, the High Voltage Switch 905 may comprise any of the switches described in U.S. patent application serial No. 16/178,565 filed on 11/1/2018 entitled "High Voltage Switch with Isolated Power," which is incorporated in its entirety into this disclosure for all purposes, for example.

Fig. 8 illustrates example waveforms generated by a high voltage power system 700 having a plasma load. Wafer waveform 805 represents the voltage on the wafer and chuck waveform 810 is the voltage on the chuck. The wafer waveform 805 is measured at the wafer indicated by the location marked 122 on the circuit diagram in fig. 2. The entrapment waveform 810 is measured at the entrapment indicated by position 121 on the circuit diagram in figure 7. The bias waveform 815 is measured at the location marked by 124 on the circuit diagram in fig. 7. In this example, the bias capacitor 510 is discharging and the second pulse generator circuit 705 may be required to include a higher power supply than V2, for example, to repeatedly charge the bias capacitor, which may require several kilowatts of power.

The waveforms in fig. 8 show six bursts of about 10 seconds with multiple pulses within each burst.

Fig. 9 is a circuit diagram of a high voltage power system 900 with a plasma load according to some embodiments. The high voltage power system 500 with plasma load is similar to the high voltage power system 900 with plasma load.

In this embodiment, the bias compensation circuit 914 may include a high voltage switch 905 coupled across the bias compensation diode 505 and coupled with the supply V1. In some embodiments, the high voltage switch 905 may include a plurality of switches 905 arranged in series to collectively open and close the high voltage. For example, high voltage switch 905 may include high voltage switch 1500 described in fig. 15. In some embodiments, high voltage switch 905 may be coupled with switch flip-flop V4.

The high voltage switch 905 may be coupled in series with one or both of inductor L9 and resistor R11. Inductor L9 may limit the peak current through high voltage switch 905. For example, inductor L9 may have an inductance of less than about 100 μ H (e.g., such as about 250 μ H, 100 μ H, 50 μ H, 25 μ H, 10 μ H, 5 μ H, 1 μ H, etc.). For example, resistor R11 may divert power dissipation to resistive output stage 102. For example, the resistance of the resistor R11 may have a resistance of less than approximately 1000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, 10 ohms, and so forth.

In some embodiments, the high voltage switch 905 may include a snubber circuit. The snubber circuit may include a resistor R9, a snubber diode D8, a snubber capacitor C15, and a snubber resistor R10.

In some embodiments, resistor R8 may represent a stray resistance of offset supply voltage V1. For example, resistor R8 may have a high resistance (e.g., a resistance such as approximately 10kOhm, 100kOhm, 1MOhm, 10MOhm, 100MOhm, 1GOhm, etc.).

In some embodiments, the high voltage switch 905 may include a plurality of switches arranged in series to collectively open and close the high voltage. For example, high voltage switch 905 may include high voltage switch 1500 described in fig. 15. As another example, the High Voltage Switch 905 may comprise any of the switches described in U.S. patent application serial No. 16/178,565 filed on 11/1/2018 entitled "High Voltage Switch with Isolated Power," which is incorporated in its entirety into this disclosure for all purposes, for example.

In some embodiments, the high voltage switch 905 may be open at the same time that the pulse generator stage 110 is pulsing and closed when the pulse generator stage 110 is not pulsing. For example, when the high voltage switch 905 is closed, current may be shorted across the bias compensation diode 505. Shorting the current may allow for a bias between the wafer and the chuck of less than 2kV, which may be within acceptable tolerances.

In some embodiments, the high voltage switch 905 may allow the electrode voltage (124 marked position) and the wafer voltage (122 marked position) to quickly recover (e.g., less than about 100ns, 200ns, 500ns, 1 μ s) to the chucking potential (121 marked position). This is shown, for example, in fig. 10, 11A, and 11B.

Fig. 10 illustrates example waveforms generated by a high voltage power system 900 having a plasma load. The wafer waveform 1005 represents the voltage on the wafer, the chuck waveform 1010 represents the voltage on the chuck, and the bias waveform 1015 represents the voltage from the bias compensation circuit 114. The wafer waveform 1005 is measured at the location marked by 122 on the circuit diagram in fig. 9. The entrapment waveform 1010 is measured at the location marked 121 on the circuit diagram in figure 9. The bias waveform 1015 is measured at the location marked by 124 on the circuit diagram in fig. 9.

The waveforms in fig. 10 show six bursts of about 10 seconds with multiple pulses within each burst.

Fig. 11A and 11B illustrate example waveforms from a high voltage power system 900 with a plasma load, according to some embodiments. Fig. 11A shows a single burst having 340 pulses, and fig. 11B shows some of the pulses within the burst. Waveform 1105 shows the voltage at the electrode (position marked at 124 in fig. 9) and waveform 1110 shows the voltage at the wafer (position marked at 122 in fig. 9). Note that the voltage on the electrode and wafer tends to track with a constant offset of about 2 kV. The waveform also shows how the voltage returns to a DC value while the pulse generator is off until the next burst begins at some later time.

Fig. 12 is a circuit diagram of a high voltage power system 1200 with a plasma load according to some embodiments. The high voltage power system 1200 with plasma load is similar to the high voltage power system 900 with plasma load.

In some embodiments, the bias compensation circuit 1214 may include four high voltage switching stages (including switches 1220, 1225, 1230, and 1235) arranged across or in parallel with the bias compensation diode 505. Each switching stage includes a switch (e.g., switches 1220, 1225, 1230, and 1235) and a voltage distribution resistor (e.g., resistors R15, R16, R17, and R18). One or both of the resistor R11 and the inductor L7 are arranged in series with the switching stage. For example, inductor L9 may have an inductance of less than about 100 μ H (e.g., such as about 1mH, 500 μ H, 250 μ H, 100 μ H, 50 μ H, 25 μ H, 10 μ H, 5 μ H, 1 μ H, etc.). In some embodiments, switches 1220, 1225, 1230, and 1235 may be opened while pulse generator stage 110 is generating a pulse and closed when pulse generator stage 110 is not generating a pulse. For example, when switches 1220, 1225, 1230, and 1235 are closed, current may be shorted across bias compensation diode 505. Shorting the current may allow for a bias between the wafer and the chuck of less than 2kV, which may be within acceptable tolerances.

Each of the switches 1220, 1225, 1230, and 1235 may include a plurality of switches arranged in series to collectively open and close a high voltage. For example, each of the switches 1220, 1225, 1230, and 1235 may collectively or individually comprise, for example, the high voltage switch 1500 depicted in fig. 15. As another example, each of the switches 1220, 1225, 1230, and 1235 may collectively or individually comprise, for example, any of the switches described in U.S. patent application serial No. 16/178,565 entitled "High Voltage Switch with Isolated Power," filed on 11/1/2018, which is incorporated in its entirety into this disclosure for all purposes.

In some embodiments, the voltage distribution resistors (e.g., resistors R15, R16, R17, and R18) may have a high resistance (e.g., a resistance such as about 1kOhm, 10kOhm, 100kOhm, 1MOhm, 10MOhm, 100MOhm, etc.).

In this example, four high voltage switching stages are shown, any number of high voltage switching stages may be used.

Fig. 13 is a circuit diagram of a high voltage power system 1300 with a plasma load according to some embodiments. The high voltage power system 1300 with plasma load is similar to the high voltage power system 1200 with plasma load.

In this example, the bias compensation circuit 1314 is similar to the bias compensation circuit 1214. In this example, each switch module (1220, 1225, 1230, and 1235) with bias compensation circuit 1314 may include a corresponding buffer circuit. Each buffer circuit may include a buffer diode and a buffer capacitor. In some embodiments, the snubber diode may include a snubber resistor arranged across the snubber diode. Each switch module may include a resistor, which may ensure that the voltage is evenly distributed between each of the switches arranged in series.

Fig. 14 is a circuit diagram of a high voltage power system 1400 with a plasma load according to some embodiments. The high voltage power system 1400 with plasma load is similar to the high voltage power system 900 with plasma load. In this example, the bias compensation circuit 1414 does not include a buffer circuit. In this example, the bias compensation circuit 1414 includes a bias compensation inductor 1420 arranged in series with a switch S4. The inductor 1420 may have an inductance of less than approximately 300nH, 100nH, 10nH, 1nH, etc.

In some embodiments, switch S4 may include high voltage switch 1500 described in fig. 15. As another example, the Switch S4 may include any of the switches described in U.S. patent application serial No. 16/178,565, filed on 11/1/2018 entitled "High Voltage Switch with Isolated Power," which is incorporated in its entirety into this disclosure for all purposes, for example.

Fig. 15 is a block diagram of a high voltage switch 1500 with an isolated power supply according to some embodiments. High voltage switch 1500 may include multiple switch modules 1505 (collectively or individually 1505, and individually 1505A, 1505B, 1505C, and 1505D) that may switch the voltage from high voltage source 1560 through fast rise times and/or high frequencies and/or through variable pulse widths. Each switch module 1505 may include a switch 1510 (e.g., such as a solid state switch).

In some embodiments, switch 1510 may be electrically coupled with a gate driver circuit 1530, and gate driver circuit 1530 may include a power supply 1540 and/or an isolated fiber trigger 1545 (also referred to as a gate trigger or switch trigger). For example, switch 1510 may include a collector, an emitter, and a gate (or a drain, a source, and a gate), and power supply 1540 may drive the gate of switch 1510 via gate driver circuit 1530. For example, the gate driver circuit 1530 may be isolated from other components of the high voltage switch 1500.

In some embodiments, for example, power supply 1540 may be isolated using an isolation transformer. The isolation transformer may comprise a low capacitance transformer. For example, the low capacitance of the isolation transformer may allow the power supply 1540 to charge on a fast time scale without requiring significant current. For example, the isolation transformer may have a capacitance of less than about 100 pF. As another example, the isolation transformer may have a capacitance of less than about 30-100 pF. In some embodiments, the isolation transformer may provide voltage isolation of up to 1kV, 5kV, 10kV, 25kV, 50kV, and the like.

In some embodiments, the isolation transformer may have a low stray capacitance. For example, the isolation transformer may have a stray capacitance of less than about 1,000pF, 100pF, 10pF, etc. In some embodiments, the low capacitance may minimize electrical coupling to low voltage components (e.g., a source of an input control power supply) and/or may reduce EMI generation (e.g., electrical noise generation). In some embodiments, the transformer stray capacitance of the isolation transformer may comprise a measured capacitance between the primary winding and the secondary winding.

In some embodiments, the isolation transformer may be a DC to DC converter or an AC to DC transformer. In some embodiments, for example, the transformer may comprise a 110V AC transformer. Regardless, the isolation transformer may provide a power source that is isolated from other components in the high voltage switch 1500. In some embodiments, the isolation may be galvanic (galvanic) such that the conductor on the primary side of the isolation transformer does not pass through or make contact with the secondary side of the isolation transformer.

In some embodiments, the transformer may include a primary winding that may be tightly wound or wrapped around the transformer core. In some embodiments, the primary winding may include a conductive sheet wrapped around the core of the transformer. In some embodiments, the primary winding may include one or more windings.

In some embodiments, the secondary winding may be wound around the core as far away from the core as possible. For example, a winding bundle including a secondary winding may be wound through the center of an aperture in a transformer core. In some embodiments, the secondary winding may include one or more windings. In some embodiments, the wire bundle including the secondary winding may include a circular or square cross-section, for example, to minimize stray capacitance. In some embodiments, an insulator (e.g., oil or air) may be disposed between the primary winding, the secondary winding, or the transformer core.

In some embodiments, keeping the secondary winding away from the transformer core may have some benefits. For example, it may reduce stray capacitance between the primary side of the isolation transformer and the secondary side of the isolation transformer. As another example, it may allow for high voltage isolation between the primary side of the isolation transformer and the secondary side of the isolation transformer such that no corona and/or breakdown is formed during operation.

In some embodiments, the separation between the primary side of the isolation transformer (e.g., the primary winding) and the secondary side of the isolation transformer (e.g., the secondary winding) may be about 0.1 inches, 0.5 inches, 1 inch, 5 inches, or 10 inches. In some embodiments, a typical spacing between the core of the isolation transformer and the secondary side (e.g., secondary winding) of the isolation transformer may be about 0.1 inches, 0.5 inches, 1 inch, 5 inches, or 10 inches. In some embodiments, the gaps between the windings may be filled with the lowest possible dielectric material (e.g., such as vacuum, air, any insulating gas or liquid, or a solid material with a relative dielectric constant less than 3).

In some embodiments, power supply 1540 may include any type of power supply that can provide high voltage isolation or have low capacitance (e.g., less than approximately 1,000pF, 100pF, 10pF, etc.). In some embodiments, the control voltage supply may provide 1520V AC or 240V AC at 60 Hz.

In some embodiments, each power supply 1540 may be inductively electrically coupled with a single control voltage supply. For example, power supply 1540A may be electrically coupled to the power supply via a first transformer; power supply 1540B can be electrically coupled to the power supply via a second transformer; power supply 1540C may be electrically coupled to the power supply via a third transformer; and power supply 1540D may be electrically coupled to the power supply via a fourth transformer. For example, any type of transformer that can provide voltage isolation between the various power sources may be used.

In some embodiments, the first, second, third and fourth transformers may comprise different secondary windings around the core of a single transformer. For example, a first transformer may include a first secondary winding, a second transformer may include a second secondary winding, a third transformer may include a third secondary winding, and a fourth transformer may include a fourth secondary winding. Each of these secondary windings may be wound around the core of a single transformer. In some embodiments, the first secondary winding, the second secondary winding, the third secondary winding, the fourth secondary winding, or the primary winding may comprise a single winding or a plurality of windings wound around the transformer core.

In some embodiments, power supply 1540A, power supply 1540B, power supply 1540C, and/or power supply 1540D may not share a return reference ground or a local ground.

For example, the isolation fiber optic trigger 1545 may also be isolated from other components of the high voltage switch 1500. The isolated fiber trigger 1545 may include a fiber receiver that allows each switch module 1505 to float relative to other switch modules 1505 and/or other components of the high voltage switch 1500 and/or, for example, while allowing active control of the gate of each switch module 1505.

In some embodiments, the return reference ground or local ground or common ground for each switch module 1505 may be isolated from each other, for example, using an isolation transformer.

For example, the galvanic isolation of each switch module 1505 from the common ground may allow multiple switches to be arranged in a series configuration for building up high voltage switches. In some embodiments, some hysteresis in the timing of the switch modules may be allowed or designed. For example, each switch module 1505 may be configured or rated for 1kV of switches, each switch module may be electrically isolated from each other, and/or the timing of closing each switch module 1505 may not need to be perfectly aligned for a period of time defined by the capacitance of the snubber capacitor and/or the voltage rating of the switches.

In some embodiments, electrical isolation may provide a number of advantages. For example, one possible advantage may include: minimize switch-to-switch jitter, and/or allow arbitrary switch timing. For example, each switch 1510 may have a switch transition jitter of less than about 500ns, 50ns, 20ns, 5ns, and so on.

In some embodiments, electrical isolation between two components (or circuits) may imply an extremely high resistance between the two components, and/or may imply a small capacitance between the two components.

Each switch 1510 can include any type of solid state switching device (e.g., such as an IGBT, MOSFET, SiC junction transistor, FET, SiC switch, GaN switch, opto-electronic switch, etc.). For example, switch 1510 may be capable of switching high voltages (e.g., voltages greater than about 1 kV) at high speeds (e.g., repetition rates greater than about 500 kHz) through high frequencies (e.g., greater than about 1kHz) and/or through fast rise times (e.g., rise times less than about 25 ns) and/or through long pulse lengths (e.g., greater than about 10 ms). In some embodiments, each switch may be individually rated for switching 1,200V-1,700V, while in combination more than 4,800V-6,800V (for four switches) may be switched. Switches having various other voltage ratings may be used.

There may be some advantages to using a large number of lower voltage switches instead of a few higher voltage switches. For example, low voltage switches typically have better performance: low voltage switches may switch faster, may have faster transition times and/or may switch more efficiently than high voltage switches. However, the greater the number of switches, the greater the timing issues that may be required.

The high voltage switch 1500 shown in fig. 15 includes four switch modules 1505. Although four are shown in this figure, any number of switch modules 1505 may be used (e.g., two, eight, twelve, sixteen, twenty-four, etc.). For example, if each switch in each switch module 1505 is rated at 1200V and sixteen switches are used, high voltage switching may be performed up to 19.2 kV. As another example, if each switch in each switch module 1505 is rated at 1700V and sixteen switches are used, the high voltage switches may be switched up to 27.2 kV.

In some embodiments, the high voltage switch 1500 may include a flying capacitor 1555. For example, the flying capacitor 1555 may include one or more capacitors arranged in series and/or parallel. For example, the capacitors may include one or more polypropylene capacitors. Flying capacitor 1555 may store energy from high voltage source 1560.

In some embodiments, the flying capacitor 1555 may have a low capacitance. In some embodiments, the flying capacitor 1555 may have a capacitance value of about 1 μ F, about 5 μ F, between about 1 μ F and about 5 μ F, between about 100nF and about 1,000nF, and the like.

In some embodiments, high voltage switch 1500 may or may not include crowbar diode 1550. Crowbar diode 1550 may include a plurality of diodes arranged in series or parallel, which may be beneficial for driving an inductive load, for example. In some embodiments, the crowbar diode 1550 may include one or more schottky diodes (e.g., such as silicon carbide schottky diodes). For example, crowbar diode 1550 may sense whether the voltage from a switch in the high voltage switches is above a certain threshold. If so, crowbar diode 1550 may short circuit power from the switch module to ground. For example, crowbar diodes may allow the alternating current path to dissipate the energy stored in the inductive load after switching. This may prevent large inductive voltage spikes, for example. In some embodiments, crowbar diode 1550 may have a low inductance (e.g., such as 1nH, 10nH, 100nH, etc.). In some embodiments, the crowbar diode 1550 may have a low capacitance (e.g., such as 100pF, 1nF, 10nF, 100nF, etc.).

In some embodiments, crowbar diode 1550 may not be used, for example, when load 1565 is primarily resistive.

In some embodiments, each gate driver circuit 1530 may generate a jitter of less than approximately 1000ns, 100ns, 10.0ns, 5.0ns, 3.0ns, 1.0ns, and so forth. In some embodiments, each switch 1510 can have a minimum on-time (e.g., less than about 10 μ s, 1 μ s, 500ns, 100ns, 50ns, 10ns, 5ns, etc.) and a maximum on-time (e.g., greater than 25s, 10s, 5s, 1s, 500ms, etc.).

In some embodiments, during operation, each of the high voltage switches may turn on and/or off within 1ns of each other.

In some embodiments, each switch module 1505 may have the same or substantially the same (± 5%) stray inductance. The stray inductance may include any inductance within switch module 1505 not associated with an inductor (e.g., such as inductance in leads, diodes, resistors, switch 1510, and/or circuit board traces, etc.). The stray inductance within each switching module 1505 may include low inductance (e.g., inductance such as less than about 300nH, 100nH, 10nH, 1nH, etc.). The stray inductance between each switching module 1505 may include low inductance (e.g., inductance such as less than about 300nH, 100nH, 10nH, 1nH, etc.).

In some embodiments, each switch module 1505 may have the same or substantially the same (± 5%) stray capacitance. Stray capacitances may include any capacitance within switch module 1505 not associated with a capacitor (e.g., such as capacitances in leads, diodes, resistors, switch 1510, and/or circuit board traces, etc.). The stray capacitance within each switch module 1505 may include low capacitance (e.g., such as less than about 1,000pF, 100pF, 10pF, etc.). The stray capacitance between each switch module 1505 may include low capacitance (e.g., such as less than about 1,000pF, 100pF, 10pF, etc.).

For example, defects in voltage distribution may be addressed by passive snubber circuits (e.g., snubber diode 1515, snubber capacitor 1520, and/or freewheeling diode 1525). For example, small differences in timing between the turning on or off of each of the switches 1510 or differences in inductance or capacitance may cause voltage spikes. These spikes may be mitigated by various snubber circuits (e.g., snubber diode 1515, snubber capacitor 1520, and/or freewheeling diode 1525).

For example, the snubber circuit may include a snubber diode 1515, a snubber capacitor 1520, a snubber resistor 116, and/or a freewheeling diode 1525. In some embodiments, a snubber circuit may be arranged in parallel with switch 1510. In some embodiments, the buffer capacitor 1520 may have a low capacitance (e.g., such as a capacitance of less than about 100 pF).

In some embodiments, the high voltage switch 1500 may be electrically coupled with a load 1565 (e.g., a resistive or capacitive or inductive load) or include the load 1565. For example, the load 1565 may have a resistance from 50Ohm to 500 Ohm. Alternatively or additionally, the load 1565 may be an inductive load or a capacitive load.

Fig. 16 illustrates an example waveform 1600 from a high voltage power system, according to some embodiments. Waveform 1600 is generated from a high voltage power system generating a positive 2kV bias (e.g., offset supply voltage V1 generates 2kV) and outputs a signal having a peak voltage of 7 kV. In this example, a high voltage switch (e.g., high voltage switch 905) is included for the high voltage power system and is closed while the pulse generator stage is pulsing and is open while the pulse generator stage is not pulsing.

Waveform 1605 represents the voltage from the pulse generator stage 101. Waveform 1610 represents the electrode voltage measured from ground to circuit point 124. Waveform 1615 represents the wafer voltage measured from ground to circuit point 122. Waveform 1620 represents the current through bias compensation circuit 114.

Waveform 1600 shows the last pulse of a burst and the circuit returns to steady state after the burst. Waveform 1600 shows a continuous 2kV shift between the electrode voltage and the wafer voltage. The offset voltage is the chucking voltage and maintaining a continuous 2kV chucking voltage as shown may be within the threshold required to avoid damage to the wafer.

Fig. 17 illustrates an example waveform 1700 from a high voltage power system, according to some embodiments. Waveform 1700 is generated from a high voltage power system generating a positive 2kV bias (e.g., offset supply voltage V1 generates 2kV), and outputs a signal having a peak voltage of 6 kV. In this example, a high voltage switch (e.g., high voltage switch 905) is included for the high voltage power system and is closed while the pulse generator stage is pulsing and is open while the pulse generator stage is not pulsing.

Waveform 1705 represents the voltage from pulse generator stage 101. Waveform 1710 represents the electrode voltage measured from ground to circuit point 124. Waveform 1715 represents the wafer voltage measured from ground to circuit point 122. Waveform 1720 represents the current through bias compensation circuit 114.

Waveform 1700 shows all pulses within a burst.

Fig. 18 illustrates an example waveform 1800 from a high voltage power system, according to some embodiments. Waveform 1700 is generated from a high voltage power system generating a positive 2kV bias (e.g., offset supply voltage V1 generates 2kV), and outputs a signal having a peak voltage of 6 kV. In this example, no high voltage switch (e.g., high voltage switch 905) is used. Without high voltage switch enable bias compensation, waveform 1800 indicates that a constant 2kV clip voltage is not maintained at the end of the burst.

Waveform 1805 represents the voltage from the pulse generator stage 101. Waveform 1810 represents the electrode voltage measured from ground to circuit point 124. Waveform 1815 represents the wafer voltage measured from ground to circuit point 122. Waveform 1820 represents the current through the bias compensation circuit 114.

Waveform 1800 shows all pulses within a burst.

Fig. 19 is a circuit diagram of a high voltage power system 1900 with a plasma load according to some embodiments. The high voltage power system with plasma load 1900 is similar to the high voltage power system with plasma load 500 shown in fig. 5. In this example, the resistive output stage 102 is removed and an energy recovery circuit 1905 has been added.

In this example, energy recovery circuit 1905 may be positioned on or electrically coupled with the secondary side of transformer T1. For example, energy recovery circuit 1905 may include a diode 1930 (e.g., crowbar diode) across the secondary side of transformer T1. For example, the energy recovery circuit 1905 may include a diode 1910 and an inductor 1915 (arranged in series), which may allow current to flow from the secondary side of the transformer T1 to charge the power supply C7. The diode 1910 and the inductor 1915 may be electrically connected with the secondary side of the transformer T1 and the power supply C7. In some embodiments, energy recovery circuit 1905 may include a diode 1935 and/or an inductor 1940 electrically coupled to the secondary of transformer T1. Inductor 1940 may represent stray inductance, and/or may include stray inductance of transformer T1.

When the nanosecond pulser is turned on, the current may charge the load stage 106 (e.g., charge capacitor C3, capacitor C2, or capacitor C9). For example, when the voltage on the secondary side of transformer T1 rises above the charging voltage on power supply C7, some current may flow through inductor 1915. When the nanosecond pulser is off, current may flow from the capacitor within load stage 106 through inductor 1915 to charge power supply C7 until the voltage across inductor 1915 is zero. The diode 1930 may prevent capacitors within the load stage 106 from looping with inductances in the load stage 106 or the bias compensation circuit 104.

For example, the diode 1910 may prevent charge from flowing from the power supply C7 to a capacitor within the load stage 106.

The value of inductor 1915 may be selected to control the current fall time. In some embodiments, inductor 1915 may have an inductance value between 1 μ H-500 μ H.

In some embodiments, energy recovery circuit 165 may include a switch, which may be used to control the flow of current through inductor 1915. For example, a switch may be placed in series with inductor 1915. In an embodiment, when the switch S1 is open and/or no longer pulsed, the switch may be closed to allow current to flow from the load stage 106 back to the high voltage load C7. For example, the switch may include a high voltage switch (e.g., such as high voltage switch 1500).

Energy recovery circuit 1905 may be added to high voltage power system 700 with a plasma load, high voltage power system 900 with a plasma load, high voltage power system 1200 with a plasma load, high voltage power system load 1300 with a plasma or high voltage power system 1400 with a plasma load; and/or the resistive output stage 102 may be removed from any of these circuits.

In some embodiments, the pulse generator stage 101 may include a high voltage switch 1500 that replaces or supplements various components shown in the pulse generator stage 101. In some embodiments, the use of high voltage switch 1500 may allow for the removal of at least transformer T1 and switch S1.

Unless otherwise specified, the term "substantially" means within 5% or 10% of the value referred to or within manufacturing tolerances. Unless otherwise specified, the term "about" means within 5% or 10% of the value referred to or within manufacturing tolerances.

Numerous specific details are set forth herein to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, methods, devices, or systems that are well known to those of ordinary skill in the art have not been described in detail so as not to obscure claimed subject matter.

The use of "adapted to" or "configured to" herein is meant to not exclude both open and inclusive languages of devices adapted to or configured to perform additional tasks or steps. Further, the use of "based on" means open and inclusive in that: a process, step, calculation, or other action that is "based on" one or more stated conditions or values may actually be based on additional conditions or values beyond those stated. Headings, lists, and numbers are included herein for ease of explanation only and are not meant to be limiting.

While the present subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing may readily produce alterations to, variations of, and equivalents to these embodiments. Accordingly, it should be understood that the present disclosure has been presented for purposes of illustration and not limitation, and does not preclude inclusion of such modifications, variations and/or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art.