阅读说明：本技术 使用金属基前驱物的原子层沉积(ald)工艺的n型金属氧化物半导体(nmos)金属栅极材料的方法与设备 (Method and apparatus for N-type metal oxide semiconductor (NMOS) metal gate material for Atomic Layer Deposition (ALD) processes using metal-based precursors ) 是由 林永景 陈世忠 吉田尚美 董琳 吴立其 汪荣军 史蒂文·洪 卡拉·贝纳尔·拉莫斯 杨 于 2019-10-07 设计创作，主要内容包括：兹描述用于形成诸如NMOS栅电极之类的半导体结构的方法及设备。所述方法可包括以下步骤：于高k介电层的第一表面上方沉积第一覆盖层,该第一覆盖层具有第一表面；及于第一覆盖层的第一表面上方沉积至少一个金属层,该至少一个金属层具有第一表面,其中该至少一个金属层包括钛铝硅化物材料。一些方法包括以下步骤：通过使第一覆盖层接触金属氯化物,从第一覆盖层的第一表面去除氧化物层,所述金属氯化物的量足以去除氧化物层。一些用于沉积钛铝硅化物材料的方法由350至400摄氏度的温度下进行的原子层沉积工艺进行。(Methods and apparatus for forming semiconductor structures, such as NMOS gate electrodes, are described. The method may comprise the steps of: depositing a first capping layer over the first surface of the high-k dielectric layer, the first capping layer having a first surface; and depositing at least one metal layer over the first surface of the first capping layer, the at least one metal layer having a first surface, wherein the at least one metal layer comprises a titanium aluminide material. Some methods include the steps of: the oxide layer is removed from the first surface of the first overlayer by contacting the first overlayer with a metal chloride in an amount sufficient to remove the oxide layer. Some methods for depositing titanium aluminide materials are performed by atomic layer deposition processes performed at temperatures of 350 to 400 degrees celsius.)

1. A method for forming a semiconductor structure, comprising:

depositing a first capping layer over a first surface of a high-k dielectric layer, the first capping layer having a first surface; and

depositing a metal layer over the first surface of the first capping layer, the metal layer having a first surface, wherein the metal layer comprises a titanium aluminide material.

2. The method of claim 1, comprising the steps of: removing an oxide layer from the first surface of the first capping layer prior to depositing the metal layer.

3. The method of claim 2, wherein removing the oxide layer comprises: contacting the first capping layer with a metal chloride in an amount sufficient to remove the oxide layer.

4. The method of claim 1 or 2, wherein depositing the metal layer is performed at a temperature of 350 to 470 degrees celsius.

5. The method of any of claims 1 to 4, wherein depositing the metal layer is performed by atomic layer deposition.

6. The method of any one of claims 1 to 5, further comprising the steps of: depositing a second capping layer over the first surface of the metal layer, wherein the second capping layer is an n-type metal material.

7. The method of any of claims 1 to 6, wherein the first cap layer comprises titanium nitride (TiN) or tantalum nitride (TaN).

8. The method of any of claims 1 to 7, wherein depositing at least one of the metal layers comprises: a first titanium monolayer, a first aluminum monolayer, and a silicon monolayer are cyclically deposited to form a titanium aluminum silicide (TiAlSi) material.

9. The method of any of claims 1 to 8, wherein the metal layer comprises titanium in an amount of 40 to 50 atomic percent.

10. The method of any of claims 1 to 9, wherein the metal layer comprises 1 to 10 atomic percent aluminum.

11. The method of any of claims 1 to 10, wherein the metal layer comprises 30 to 40 atomic percent silicon.

12. The method of any of claims 1 to 11, wherein titanium nitride is included in the first capping layer having a thickness of about 5 to 15 angstroms and the metal layer is TiAlSi having a thickness of about 10 to 50 angstroms.

13. A method of processing a high-k dielectric material, comprising:

depositing a first capping layer over the high-k dielectric layer, the first capping layer having a first surface;

depositing one or more metal work function layers over the first surface of the first capping layer, wherein the one or more metal work function layers comprise titanium aluminum silicide (TiAlSi);

depositing a second capping layer over the one or more metal work function layers; and

optionally, a second metal layer is deposited over the second capping layer.

14. The method of claim 13, wherein the one or more metal work function layers are deposited by reacting at least one titanium halide precursor, at least one aluminum precursor, and at least one silane precursor.

15. A non-transitory computer readable medium having instructions stored thereon that when executed cause a method of forming a semiconductor structure, the method comprising: depositing a first capping layer over a first surface of a high-k dielectric layer, the first capping layer having a first surface; and depositing a metal layer over the first surface of the first capping layer, the metal layer having a first surface, wherein the metal layer comprises a titanium aluminide material.

Technical Field

Embodiments of the present disclosure generally relate to electronic device processing and, more particularly, to compositions for vapor deposition processes of metal-containing materials, and metal-containing materials deposited by bulk deposition of titanium aluminum silicide (titanium aluminum silicide) films.

Background

In the 10nm and future technology nodes, metal gate/high-k stacks are increasingly being used in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), however the inventors have found that there are still many challenges in this field of technology. In particular, the rapid development of mobile devices, the internet and machine learning requires higher transistor technology performance for more advanced nodes (n <10nm) with low power consumption. This requires that moore's law be extended to shrink the size of one or more transistors while increasing the transistor density on a chip. Currently, titanium aluminum (TiAl) is widely used in industry as a low work function metal gate material for n-type metal oxide semiconductor field effect transistors (NMOS transistors). However, the inventors have found that the threshold voltage of n-type field effect transistor (NFET) devices with thin titanium aluminum (TiAl) is problematically high, and thus the transistors cannot be further scaled down.

There is therefore a need for a material suitable for n-type transistors that is suitable for nodes below 10nm and has low power consumption.

Disclosure of Invention

Semiconductor structures, such as NMOS gate electrodes, are also provided herein as are methods and apparatus for forming such semiconductor structures. In some embodiments, a method for forming a semiconductor structure includes: depositing a first capping layer over the first surface of the high-k dielectric layer, the first capping layer having a first surface; and depositing a metal layer over the first surface of the first capping layer, the metal layer having a first surface, wherein the at least one metal layer comprises a titanium aluminide material.

In some embodiments, a method of processing a high-k dielectric material comprises the steps of: depositing a first capping layer over the high-k dielectric layer, the first capping layer having a first surface; depositing one or more metal work function layers over the first surface of the first capping layer, wherein the one or more metal work function layers comprise titanium aluminum silicide (TiAlSi); depositing a second capping layer over the one or more metal work function layers; and optionally depositing a second metal layer over the second capping layer.

In some embodiments, the NMOS gate electrode comprises: a first capping layer over the first surface of the high-k dielectric layer, the first capping layer having a first surface; and a metal work function layer over the first surface of the first capping layer, wherein the metal work function layer comprises titanium, aluminum, and silicon materials.

In some embodiments, the present disclosure relates to a non-transitory computer readable medium having instructions stored thereon that when executed cause a method of forming a semiconductor structure, the method comprising: depositing a first capping layer over the first surface of the high-k dielectric layer, the first capping layer having a first surface; and depositing a metal layer over the first surface of the first capping layer, the metal layer having a first surface, wherein the metal layer comprises a titanium aluminum silicide material.

Other and further embodiments of the present disclosure are described below.

Drawings

The embodiments of the present disclosure, briefly summarized above and discussed in detail below, may be understood by reference to the illustrative embodiments thereof that are depicted in the drawings. The appended drawings, however, depict only typical embodiments of the disclosure and are not therefore to be considered to be limiting of its scope, for the disclosure may admit to other equally effective embodiments.

Fig. 1 is a flow chart of a method of forming a semiconductor device according to some embodiments of the present disclosure.

Fig. 2A-2E are illustrative cross-sectional views of a substrate during different stages of the processing sequence of fig. 1, according to some embodiments of the present disclosure.

Fig. 3 is an apparatus suitable for performing the methods and forming devices according to the present disclosure.

Fig. 4 is an NMOS gate electrode of the present disclosure.

Fig. 5 is a flow chart of a method of processing a high-k dielectric material according to some embodiments of the present disclosure.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Detailed Description

Embodiments of the present disclosure provide semiconductor structures and methods of forming semiconductor structures. In an embodiment, a method of depositing a titanium aluminide material on a semiconductor substrate using a vapor deposition technique is disclosed. For example, in some embodiments, a method of forming a semiconductor structure comprises: depositing a first capping layer having a first surface over the first surface of the high-k dielectric layer; and depositing a metal layer with a first surface on the first surface of the first covering layer, wherein the metal layer comprises titanium aluminum silicide material. Embodiments of the present disclosure provide methods of forming one or more n-metal work function materials or layers over a substrate that advantageously include a titanium aluminum silicide material having a low resistivity suitable for forming NMOS gate electrodes having low power consumption. The aluminum content of the titanium aluminide material may be varied to adjust the work function of the titanium aluminide material. The adjusted work function according to the present disclosure may be adapted to achieve a desired threshold voltage (Vt) in a semiconductor device. Embodiments of the present disclosure may be advantageously formed using an Atomic Layer Deposition (ALD) process and used within devices that may be subject to further processing. In some embodiments, the methods of the present disclosure advantageously provide an n-metal work function titanium aluminum silicide material, such as a film having a desired or predetermined n-work function, suitable for use in 10nm technology nodes and beyond in fin field effect transistors (finfets). In an embodiment, the desired work function of the n-metal film of the present disclosure is predetermined. For example, the desired workfunction target for an n-metal film of the present disclosure is at 15 angstromsThe thickness is lower than 4.25 eV.

Fig. 1 is a flow diagram of a method 100 for forming a metal layer, wherein the metal layer comprises a titanium aluminum silicide material, according to an embodiment of the present disclosure. The method 100 is described below with reference to the stages of depositing a metal layer comprising a titanium aluminide material depicted in figures 2A-2E, and the method 100 may be performed, for example, in a suitable processing chamber, such as the processing chamber 16 of figure 3. Example processing systems that may be used to perform the methods disclosed herein may include, but are not limited to: available from applied materials, Inc. of Santa Clara, CalifOrAny of the brand processing systems. Non-limiting examples of suitable cluster tools and processing chambers are disclosed in commonly owned U.S. patent No. 7,405,158 to Lai et al, 7/29 2008. Other process chambers, including manufacturing chambers available from different manufacturers, may also be used as appropriate in conjunction with the teachings provided herein.

The method 100 is generally performed on a substrate 200 provided to a process volume of a process chamber, such as a process chamber adapted for performing cyclical deposition, such as atomic layer deposition. Although not shown in fig. 1, in an embodiment, a substrate 200 to be processed is first loaded into and disposed in a process chamber 16 capable of cyclic deposition, and process conditions are adjusted. In some embodiments, as shown in fig. 2A, the substrate 200 includes a first surface 205 and a high-k dielectric layer 210, the high-k dielectric layer 210 being located above the first surface 205 of the substrate 200. The high-k dielectric layer 210 has a first surface 212. Although described below with respect to the substantially planar substrate 200 shown in fig. 2A-2E, in some embodiments, the substrate 200 may include one or more features (not shown in fig. 2A-2E), such as a plurality of trenches, vias, or the like.

The substrate 200 may be any suitable substrate. For example, the substrate 200 may include one or more of the following: silicon (Si), silicon oxide (SiO)₂) Or class(iii) an analog. In an embodiment, the substrate 200 is an oxide substrate. In an embodiment, the substrate 200 may include a dielectric layer or a dielectric substrate. For example, low-k materials (e.g., materials having a dielectric constant less than silicon oxide, or materials having a dielectric constant less than about 3.9) or the like may be suitable for use herein. Further, the substrate 200 may include additional layers of materials or may have one or more completed or partially completed structures or devices (not shown) formed in the substrate 200 or on the substrate 200. In an embodiment, the substrate 200 may be, for example, a doped or undoped silicon substrate, a group III-V compound substrate, a silicon germanium (SiGe) substrate, an epitaxial substrate, a silicon-on-insulator (SOI) substrate, a display substrate, a Light Emitting Diode (LED) substrate, a solar cell array, a solar panel, or the like, such as a Liquid Crystal Display (LCD), a plasma display, an Electroluminescent (EL) lamp display. In some embodiments, the substrate 200 may be a semiconductor wafer. In an embodiment, the substrate 200 is an oxide substrate, a dielectric substrate, or a combination thereof. The substrate 200 is not limited to any particular size or shape. The substrate 200 may be a circular wafer having a diameter of 200mm, 300mm, or other diameter such as 450mm, etc. The substrate 200 may also be any polygonal, square, rectangular, curved, or non-circular workpiece, such as a polygonal glass substrate used in the manufacture of flat panel displays.

In an embodiment, a high-k dielectric layer 210 may be deposited over the first surface 205 of the substrate 200. In an embodiment, high-k dielectric layer 210 is suitable for an n-type device. The high-k dielectric layer 210 may be deposited to a predetermined thickness by any deposition means known in the art to form a film. In an embodiment, the high-k dielectric layer 210 is made of a material having a high dielectric constant (high-k material has a dielectric constant greater than 4.0), such as hafnium (IV) oxide (HfO)₂) Zirconium dioxide (ZrO)₂) Alumina (Al)₂O₃) Barium Strontium Titanate (BST), lead zirconate titanate (PZT), zirconium silicate (ZrSiO)₂) Hafnium silicon dioxide (HfSiO)₂) Tantalum dioxide (TaO)₂) And the like. In an embodiment, a suitable high-k dielectric layer comprises high-k oxidationThe high k oxide is grown by atomic layer deposition to form a thin film having a thickness in an amount of 1 to 3 nanometers, such as a thin film having a thickness of about 2.5 nanometers.

Referring to fig. 1, at block 120, and fig. 2B, the method 100 includes: a first capping layer 220 having a first surface 225 is deposited over the first surface 212 of the high-k dielectric layer 210. In an embodiment, the first capping layer is a material suitable for use in an n-type device deposited by any suitable deposition technique, such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). In an embodiment, the first capping layer 220 is formed of titanium nitride (TiN) or tantalum nitride (TaN). In an embodiment, first capping layer 220 is deposited to a thickness of 5 to 20 angstroms, such as about 10 angstroms. In an embodiment, the first capping layer may affect the performance of the transistor device. For example, if the first cladding layer contains too much oxygen (O) or an oxide layer or native oxide layer (not shown) over the first surface 225 of the first cladding layer 220, the threshold voltage of a transistor device including a gate electrode may be adversely affected. By treating the first capping layer 220, such as by contacting the first capping layer 220 with a metal chloride in an amount sufficient to remove any oxide layer located on the first surface 225 of the first capping layer 220, as shown at 125, the inventors have discovered that the threshold voltage of the transistor device is positively affected. For example, prior to depositing the first metal layer, embodiments include removing an oxide layer from the first surface 225 of the first capping layer 220. Non-limiting examples of metal chlorides suitable for use according to the present disclosure include: tantalum chloride, nickel chloride, tungsten oxytetrachloride (tunggsten oxytetrachloride), hafnium chloride, aluminum chloride, and combinations of the foregoing. In an embodiment, the metal chloride is contacted to the first surface 225 of the first overlayer 220 under conditions sufficient to remove an oxide layer, such as a native oxide layer, located on the first surface 225 of the first overlayer 220. In an embodiment, the metal chloride is contacted to the first surface 225 of the first overlayer 220 for a duration of 1 second to 600 seconds at a temperature ranging from 300 degrees celsius to 450 degrees celsius at a pressure of 1 to 20 torr. In an embodiment, the first capping layer is deposited to a thickness of about 5 to 15 angstroms.

Referring to fig. 1, at block 130, and fig. 2C, the method 100 includes: a metal layer 230 having a first surface 235 is deposited over the first surface 225 of the first capping layer 220, wherein the metal layer comprises titanium, aluminum, and silicon, such as a TiAlSi alloy. The metal-containing layer may be, for example, a metal or a metal titanium aluminum silicide material. In an embodiment, the metal layer includes titanium in an amount of 30 to 50 atomic percent or 40 to 50 atomic percent, aluminum in an amount of 1 to 15 atomic percent, and silicon in an amount of 20 to 40 atomic percent. In an embodiment, the titanium aluminide material comprises 1 to 10% carbon. In an embodiment, the metal layer is a TiAlSi alloy having a thickness of about 10 to 50 angstroms. In an embodiment, the metal layer comprises or consists of a compound comprising titanium, aluminum and silicon as solid compounds. In an embodiment, the solid compound is characterized by an intermetallic material, such as a metal alloy, that forms a solid compound including silicon therein, and that has an ordered crystalline structure such that the position of two or more atoms can be determined and is non-random.

During the process 130, the substrate 200 of fig. 2C is heated to an initial deposition temperature within the processing chamber 16 of fig. 3. The substrate 200 may be heated to a temperature in a range from about 350 degrees celsius to about 470 degrees celsius, from about 400 degrees celsius to about 450 degrees celsius. The substrate 200 including the high-k dielectric layer 210 and the first capping layer 220 is then contacted with a precursor sufficient to form a titanium, aluminum, and silicon (TiAlSi) layer on the substrate 200. In embodiments, the precursor is characterized by having a favorable vapor pressure. The deposition precursor may have a gaseous, liquid, or solid state at ambient temperature and pressure. However, the precursor may be volatilized as a gas within the processing chamber 16. The process chamber 16 has a controlled environment that is pressurized in a range from about 1 mtorr to about 100 torr, from about 1 torr to about 10 torr, or from about 2 torr to about 5 torr. The precursors are typically heated prior to delivery into the processing chamber, for example at a temperature from about room temperature to about 200 degrees celsius.

In an embodiment, the substrate 200 is subsequently exposed to a titanium-containing precursor gas in an ALD sequenceAn aluminum-containing precursor gas and a silicon-containing gas to form a monolayer of titanium, aluminum and silicon or a TiAlSi alloy on the first capping layer 220, as described herein. A purge gas may also be used to clean the processing chamber 16 between or during deposition cycles. The carrier gas and purge gas may be one or more of the following: argon, nitrogen, hydrogen, helium, forming gas (N)₂/H₂) Or a combination of the foregoing. In one ALD embodiment, a purge gas is continuously circulated through the process chamber while precursor gases are sequentially pulsed through the process chamber. In an embodiment, the pulsed precursor gases are separated in time.

In an embodiment, a method according to the present disclosure may form a metal layer 230 using layer deposition (ALD), such as film compositions of titanium, aluminum, and silicon, so that the work function value may be controlled or predetermined, at 130. For example, in an embodiment, a reactive gas comprising a precursor of titanium may be contacted with a workpiece comprising the substrate 200, the high-k dielectric layer 210, and the first capping layer 220. In an embodiment, depositing metal layer 230 is performed by atomic layer deposition. Non-limiting examples of suitable precursors of titanium (Ti) may include one or more of the following: TiCl (titanium dioxide)₄TiF4, TiBr4, TiI4, TDEAT (tetramethylethylenediamine), TDMAT (tetramethylethylenediamine), and combinations thereof. A precursor of titanium may be contacted with the first capping layer 220 under conditions suitable to form a monolayer of aluminum on the first capping layer 220. For example, one or more precursors of titanium may be supplied in a process gas comprising a reactive gas, wherein the temperature of the substrate 200 is about 350 degrees celsius to about 475 degrees celsius at a pressure ranging from about 0.05 torr to about 20 torr. In one embodiment, depositing the at least one metal layer is performed at a temperature of 350 degrees celsius to 475 degrees celsius. In embodiments, the composition of titanium (Ti) may be controlled by the number of cycles, pulse duration, and/or concentration of titanium in the precursor gas. In an embodiment, titanium is provided in the precursor gas in an amount sufficient to form a metal layer 230 of TiAlSi, wherein the metal layer comprises titanium in an amount of 30 to 50 atomic percent.

In embodiments, the reactive gas in ALD deposition may include aluminumA precursor. In an embodiment, an aluminum precursor may be contacted with a workpiece comprising the substrate 200, the high-k dielectric layer 210, and the first capping layer 220. Non-limiting examples of suitable precursors of aluminum may include one or more of the following: AlCl₃And TMA [ Al (CH)₃)₃]Triethylaluminum (Al)₂Et₆、(AlEt₃)₂Or TEA), dimethylaluminum hydride (dimethyl amide hydride; DMAH), tributylaluminum (tributyl aluminum; TTBA), aluminum hydride (AlH)₃) And combinations of the foregoing. In some embodiments, a hydrogen-based plasma or a plasma formed from hydrogen gas may be used to include aluminum in the deposited material. In an embodiment, an aluminum precursor may be contacted with the first capping layer 220 under conditions suitable to form a monolayer of aluminum on the first capping layer 220. For example, one or more precursors of aluminum may be supplied in a process gas comprising a reactive gas, wherein the temperature of the substrate is about 350 degrees celsius to about 475 degrees celsius at a pressure ranging from about 0.05 to about 20 torr. In some embodiments, the composition of aluminum (Al) may be controlled by the number of cycles, pulse duration, and/or concentration of aluminum in the precursor gas. In an embodiment, aluminum is provided in the precursor gas in an amount sufficient to form a metal layer 230 of TiAlSi, wherein the metal layer comprises aluminum in an amount of 1 to 15 atomic percent, or in an embodiment, in an amount of 1 to 10 atomic percent.

In an embodiment, the reactive gas in ALD deposition may include a precursor of silicon. In embodiments, the silicon precursor comprises a silicon-containing reactive gas that may be used for silicon-containing material deposition, such as silicide. Silicon-containing precursors include silanes and organosilanes. Silanes include Silane (SiH)₄) And empirical formula is Si_xH(_2x+2) Higher silanes, such as disilane (Si)₂H₆) Trisilane (Si)₃H₈) And tetrasilane (Si)₄H₁₀) There are others. The organosilanes include those having the empirical formula R_ySi_xH_(2x+2-y)Wherein R is independently methyl, ethyl, propyl or butyl, such as methylsilane ((CH)₃)SiH₃) Two, twoMethylsilane ((CH)₃)2SiH₂) Ethyl silane ((CH)₃CH₂)SiH₃) (CH) methyldisilane₃)Si₂H₅) Dimethyldisilane ((CH)₃)₂Si₂H₄) Hexamethyldisilane ((CH)₃)₆Si₂) Tris (dimethylamino) silane (TDMAS), and combinations of the foregoing. In an embodiment, a precursor of silicon may be contacted with the first capping layer 220 under conditions suitable to form a monolayer of silicon on the first capping layer 220. For example, one or more precursors of silicon may be supplied in a process gas comprising a reactive gas, wherein the temperature of the substrate is about 350 degrees celsius to about 475 degrees celsius at a pressure ranging from about 0.05 to about 20 torr. The composition of the silicon (Si) may be controlled by the number of cycles, the pulse duration, and/or the concentration of silicon in the precursor gas. In an embodiment, an amount of silicon sufficient to form a metal layer 230 of TiAlSi is provided in the precursor gas, wherein the metal layer comprises silicon in an amount of 30 to 40 atomic percent.

In some embodiments, one or more metal work function layers may be deposited by reacting at least one titanium halide precursor, at least one aluminum precursor, and at least one silane precursor.

The purge gases described above may be used during the time intervals between cycles of depositing titanium, aluminum, and silicon films using the precursors. Further, the content of the deposited film may be controlled, for example, by extending or shortening the pulse time of one or more of the titanium precursor, the aluminum precursor, or the silicon precursor, or a combination thereof. In an embodiment, depositing the metal layer at 130 includes depositing at least one metal layer, including cyclically depositing a first titanium monolayer, a first aluminum monolayer, and a first silicon monolayer to form a titanium aluminum silicide (TiAlSi) material. In an embodiment, the ALD cycle may be repeated, for example, 100 to 1000 times or more, to form a TiAlSi layer of a predetermined thickness. In an embodiment, the TiAlSi material comprises titanium in an amount of 30 to 50 atomic percent or 40 to 50 atomic percent, aluminum in an amount of 1 to 10 atomic percent, and silicon in an amount of 20 to 40 atomic percent. In an embodiment, the TiAlSi material comprises 20 to 40 atomic percent silicon. In embodiments, carbon may be present in the metal layer in an amount of 5 to 10 atomic percent. In embodiments, the TiAlSi may be substantially pure with less than 0.001 percent impurities.

In one embodiment, depositing the metal layer at block 103 includes depositing one or more metal work function layers, including one or more of the following sequential cycles: a) introducing a metal halide precursor, such as titanium halide, into the processing chamber to form a first monolayer on the first capping layer; b) purging the metal halide precursor with a purge gas; c) introducing at least one aluminum precursor to form a second monolayer on the first capping layer; d) purging the aluminum precursor with a purge gas; e) introducing at least one silane precursor to form a third monolayer on the first capping surface, wherein a) through e) form a titanium aluminum silicide layer over the first capping layer. In an embodiment, a purge gas may be applied after f); and the cycle of a-f may be repeated 1 to 100 times or more to obtain a TiAlSi layer of a predetermined thickness.

Referring to fig. 1, at block 140, and fig. 2D, the method 100 includes: optionally, a second capping layer 240 having a first surface 245 is deposited over the first surface 235 of the metal layer 230. In an embodiment, the second capping layer is an n-type metal material among the second capping layers deposited over the first surface of the metal layer. In an embodiment, the second capping layer is a material suitable for use in an n-type device deposited by any suitable deposition technique, such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). In an embodiment, the second capping layer is formed of titanium nitride (TiN) or tantalum nitride (TaN). In an embodiment, second capping layer 240 is deposited to a thickness of 5 to 20 angstroms, such as about 10 angstroms.

Referring to fig. 1, at block 150, and fig. 2E, the method 100 includes: optionally, a gate fill material is deposited on the first surface 245 of the second capping layer 240. In an embodiment, the gate fill material is a material suitable for an n-type device deposited by any suitable deposition technique, such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). In an embodiment, the gate fill material is formed of tungsten, titanium, or other metal suitable for n-type transistors. In embodiments, the gate fill material is deposited to a thickness of 20 angstroms to 2 or 3 nanometers. In embodiments, the metal layer 230 and the metal gate fill material 250 may be the same or different materials depending on the respective conductivities required of the devices, such as gate electrodes. For example, if a metal gate fill material 250 different from the work function material is used, the metal gate fill material 250 may comprise a conductive material, such as a metal or metal alloy. Non-limiting examples of metals or metal alloys for use as the metal gate fill material 250 include materials from the group consisting of: tungsten, aluminum, copper, cobalt, and combinations thereof, and alloys of tungsten, aluminum, copper, cobalt, and combinations thereof.

In some embodiments, the metal gate fill material 250 used is the same or substantially the same as the work function material, and the metal gate fill material 250 may comprise a titanium, aluminum, silicon material described herein, such as TiAlSi, and may be deposited by the processes described herein. Alternatively, in some embodiments, the metal layer 230 (such as a workfunction material layer) and the metal gate fill material 250 may be different materials, both selected from the materials described herein. In one embodiment, the high dielectric constant material comprises or consists of hafnium oxide, the metal layer 230 suitable as a work function material may comprise or consist of TiAlSi, and the gate fill material may be tungsten. In an embodiment, the resistivity of the gate fill material should be equal to or less than the resistivity of the workfunction material layer or metal layer 230.

Referring to fig. 3, fig. 3 illustrates a process chamber 16 suitable for forming layers of the present disclosure, including metal layer 230, in a single process chamber. In an embodiment, the process chamber 16 may be configured to operate in both a CVD mode and a cyclical deposition mode (ALD). An example of such a chamber is described in U.S. Pat. No. 6,878,206 entitled "Lid Assembly for a Processing System to facility Sequential Deposition Techniques", filed 12.12.2001 and assigned to applied materials, Inc. Referring to fig. 3, disposed within the processing chamber 16 is a heater/lift assembly 46, the heater/lift assembly 46 including a support pedestal 48 adapted to support a wafer, the support pedestal 48 being coupled to a support shaft 48 a. When the cover assembly 20 is in the closed position, the support base 48 is positioned between the support shaft 48a and the cover assembly 20. The support shaft 48a extends from the support base 48 away from the cover assembly 20 through a channel formed in the housing 14. The bellows 50 is attached to a portion of the housing 14 disposed opposite the cover assembly 20 to prevent leakage from between the support shaft 48a and the housing 14 into the processing chamber 16. The heater/lift assembly 46 is vertically movable within the processing chamber 16 such that the distance between the support pedestal 48 and the lid assembly 20 may be controlled. Sensors (not shown) may provide information related to the position of the support pedestal 48 within the process chamber 16.

The support pedestal 48 includes an embedded thermocouple 50a, which embedded thermocouple 50a may be used to monitor the temperature of the support pedestal 48. For example, the signal from the thermocouple 50a may be used in a feedback loop to control the power applied by the power source 52 to the heater element 52 a. The heater element 52a may be a resistive heater element or other heat transfer device disposed in the support base 48 or in contact with the support base 48 to control the temperature of the support base 48. Optionally, a heat transfer fluid (not shown) may be used to heat the support pedestal 48.

The support pedestal 48 may be formed from any process compatible material including aluminum nitride and aluminum oxide (Al)₂O₃Or alumina) and may be configured to utilize vacuum to hold the substrate 200 (not shown) on the support pedestal 48, i.e., the support pedestal 48 may be a vacuum chuck. In this regard, the support base 48 may include a plurality of vacuum holes (not shown) that are in fluid communication with a vacuum source, such as a pumping system, via a vacuum tube that is routed through the support shaft 48 a.

The liner assembly is disposed in the processing chamber 16 and includes a cylindrical portion 54 and a planar portion. The cylindrical portion 54 and the planar portion may be made of any suitable material such as aluminum, ceramic, and the like. The cylindrical portion 54 surrounds the support base 48. The cylindrical portion 54 additionally includes an aperture 60, the aperture 60 being aligned with the slit valve opening 44 disposed in the sidewall 14b of the housing 14 to allow passage of a substrate into and out of the processing chamber 16.

The planar portion extends transversely to the cylindrical portion 54 and is disposed against the chamber bottom 14a of the process chamber 16, the chamber bottom 14a being disposed opposite the lid assembly 20. The liner assembly defines a passage 58 between the housing 14 and both the cylindrical portion 54 and the planar portion. Specifically, a first portion of the channel 58 is defined between the chamber bottom 14a and the planar portion. A second portion of the channel 58 is defined between the sidewall 14b of the housing 14 and the cylindrical portion 54. Purge gas is introduced into the channel 58.

Disposed along the sidewall 14b of the processing chamber 16 and adjacent the lid assembly 20 is a pumping channel 62. The pumping channel 62 includes a plurality of holes, one of which is illustrated as a first hole 62 a. Pumping channel 62 includes a second bore 62b coupled to pumping system 18 by a conduit 66. Throttle valve 18A is coupled between pumping passage 62 and pumping system 18. Pumping channel 62, throttle valve 18A, and pumping system 18 control the flow from process chamber 16. The size and number and location of the apertures, such as the first apertures 62a in communication with the process chamber 16, are configured to allow gas exiting the lid assembly 20 to flow uniformly through the support base 48 and the substrate 200 (when the substrate 200 is positioned on the support base 48). Multiple supplies 68a, 68b and 68c of process and/or other fluids are in fluid communication with the valves 32a, 32b or 32c via a series of conduits (not shown) formed through the housing 14, the lid assembly 20 and the gas manifold 34.

The controller 70 regulates operation of the various components of the system 10. Controller 70 includes a processor 72, and processor 72 is in data communication with a memory, such as a random access memory 74, and a hard drive 76, and is in communication with at least pumping system 18, power source 52, and valves 32a, 32b, and 32 c. The random access memory 74 includes instructions stored thereon that, when read by the processor 72, control the operation of the system 10 to perform the methods disclosed herein on structures within the processing chamber described herein. In some embodiments, the controller includes a computing device that includes one or more computer-readable media. Computer-readable media generally includes any device, local or remote, that can store information which can be retrieved by a computing device. Examples of computer readable media that can be used in embodiments of the present disclosure include solid state memory, floppy disks, internal or external hard drives, and optical storage (CDs, DVDs, etc.). In one embodiment, RAM 274 may be a computer-readable medium. The software routines may be stored on a computer readable medium for execution by a computing device. When executed, the software routines transform the general purpose computer into a process specific computer that controls operation of the chamber to perform the chamber process.

Although any type of processing fluid may be utilized, one example of a processing fluid is the precursor described above, and optionally a purge fluid such as argon (Ar) gas as described above. Nitrogen (N) may also be substituted₂) Used as a purge gas. The chamber pressure may be in the pressure range as described above, or may be in the range of 1 to 150 torr or 1 to 50 torr, and the support pedestal 48 may be heated in the range of 300 degrees celsius to 500 degrees celsius so that the substrate may be maintained at a set temperature, such as 350 degrees celsius to about 470 degrees celsius, or 400 degrees celsius to about 450 degrees celsius. In an embodiment, a processing fluid, such as a precursor, may be flowed into the processing chamber 16 along with a carrier fluid, such as argon (Ar). However, the purging fluid may be different from the carrier fluid or precursor, the oxygen-containing gas, or the reactive gas.

In vapor deposition embodiments according to the present disclosure, the method includes performing an Atomic Layer Deposition (ALD) process to deposit the TiAlSi layer(s) as described above on the first capping layer. One cycle of ALD may include flowing one or more titanium precursors into a processing chamber 16 that includes a substrate; cleaning the process chamber 16, such as pumping to remove all process fluid; and, after pumping, supplying a reactive gas, such as an aluminum-containing precursor gas. Subsequent cleans may be performed to remove unreacted reactive gases, precursors, or their byproducts. After pumping, a reactive gas, such as a silicon-containing precursor gas, is supplied. Subsequent cleans may be performed to remove unreacted reactive gases, precursors, or their byproducts. In an embodiment, the cycles of the ALD sequence may be repeated until the layer being formed has desired characteristics, such as thickness, conductivity, and the like. In an embodiment, the cycles of the ALD sequence may be repeated until the layer being formed has a desired characteristic, such as an amount of aluminum, an amount of titanium, or a predetermined amount of silicon. In some embodiments, purge gas may be strategically delivered through the lower portion of the channel 73, purging the cleaning agent from the gas manifold 34 and the baffle.

Fig. 4 illustrates a cross-sectional view of an example metal oxide gate assembly 400, the metal oxide gate device 400 utilizing a metal layer deposited by ALD in accordance with an embodiment of the present disclosure. A device such as the exemplary metal oxide gate device 400 generally includes an exposed metal gate 410 surrounded by spacers 416, and silicon source/drain regions 420 formed within the substrate 412 or at a surface of the substrate 412. Spacers 416 typically comprise an oxide such as silicon dioxide or a nitride such as silicon nitride.

The exposed metal gate 410 includes a high-k dielectric layer 411, a first capping layer 414, a metal layer 415, a second capping layer 417, and a gap fill layer 422, such as a tungsten layer. The high-k dielectric layer 411 separates the substrate 412 from the first capping layer 414. A first capping layer 414 separates the high-k dielectric layer 411 from the metal layer 415. In an embodiment, the metal layer 415 is deposited by a technique according to the present disclosure. In an embodiment, all layers may be deposited by a cyclical deposition technique such as ALD.

Fig. 5 is a flow chart of a method 500 for processing a high-k dielectric material, the method 500 comprising: at 510, a first capping layer having a first surface is deposited over the high-k dielectric layer. In an embodiment, the first capping layer and the high-k dielectric layer are the same material deposited under the same conditions as described above. In an embodiment, the first capping layer and the high-k dielectric layer may be deposited by a cyclical deposition technique such as ALD. After the deposition at 510, at 520, the method of the present disclosure includes: one or more metal work function layers are deposited over the first surface of the first capping layer, wherein the one or more metal work function layers comprise titanium aluminum silicide (TiAlSi). In an embodiment, as described above, one or more metal work function layers are the same as metal layer 230 shown in fig. 2C. In an embodiment, one or more metal work function layers are deposited by cyclically depositing a first titanium monolayer, a first aluminum monolayer, and a first silicon monolayer to form a titanium aluminum silicide (TiAlSi) material. In an embodiment, for example, the ALD cycle may be repeated 1 to 100 times or more to form one or more metal work function layers of TiAlSi of a predetermined thickness. In an embodiment, the TiAlSi metal work function layer includes titanium in an amount of 30 to 50 atomic percent, aluminum in an amount of 1 to 15 atomic percent, and silicon in an amount of 20 to 40 atomic percent. In an embodiment, the one or more metal work function layers may comprise carbon.

In an embodiment, depositing one or more metal work function layers comprises one or more of the following sequential cycles: a) introducing a metal halide precursor, such as titanium halide, into the processing chamber to form a first monolayer on the first capping layer; b) purging the metal halide precursor with a purge gas; c) introducing at least one aluminum precursor to form a second monolayer on the first capping layer; d) purging the aluminum precursor with a purge gas; e) introducing at least one silane precursor to form a third monolayer on the first capping surface, wherein a) through e) form a titanium aluminum silicide layer over the first capping layer. In embodiments, a purge gas may be applied after f); and the cycle (a-f) may be repeated 1 to 100 times or more to obtain a TiAlSi layer of a predetermined thickness.

Still referring to fig. 5, according to some embodiments of the present disclosure, a second capping layer is deposited over the one or more metal work function layers at 530; and optionally, at 540, depositing a second metal layer over the second capping layer. The method 500 is suitable for depositing a metal layer as depicted in fig. 2A-2E, and the method 500 may be performed in a processing chamber, such as a suitable cluster tool and processing chamber 16 in fig. 3. In some embodiments, a cluster tool or a process chamber such as process chamber 16 in fig. 3 is configured to deposit a first capping layer having a first surface over a first surface of a high-k dielectric layer; and depositing a metal layer having a first surface over the first surface of the first capping layer, wherein the metal layer comprises a titanium aluminum silicide material.

In some embodiments, the present disclosure relates to a non-transitory computer readable medium having instructions stored thereon that when executed cause a method of forming a semiconductor structure, the method comprising: depositing a first capping layer over the first surface of the high-k dielectric layer; and depositing a metal layer having a first surface over the first surface of the first capping layer, wherein the metal layer comprises a titanium aluminum silicide material.

In some embodiments, the present disclosure relates to a non-transitory computer readable medium having instructions stored thereon that when executed cause a method of processing a high-k dielectric material, the method comprising: depositing a first capping layer over the high-k dielectric layer, the first capping layer having a first surface; depositing one or more metal work function layers over the first surface of the first capping layer, wherein the one or more metal work function layers comprise titanium aluminum silicide (TiAlSi); depositing a second capping layer over the one or more metal work function layers; and optionally depositing a second metal layer over the second capping layer.

In some embodiments, a cluster tool or a process chamber such as process chamber 16 in fig. 3 is configured to form an NMOS gate electrode comprising: a first capping layer over the first surface of the high-k dielectric layer, the first capping layer having a first surface; and a metal work function layer over the first surface of the first capping layer, wherein the metal work function layer comprises titanium, aluminum, and silicon materials.

In some embodiments, the present disclosure relates to a method for forming a semiconductor structure, the method comprising: depositing a first capping layer over the first surface of the high-k dielectric layer, the first capping layer having a first surface; and depositing a metal layer over the first surface of the first capping layer, the metal layer having a first surface, wherein the metal layer comprises a titanium aluminum silicide material. In some embodiments, the oxide layer is removed from the first surface of the first capping layer prior to depositing the metal layer. In some embodiments, removing the oxide layer comprises: the first capping layer is contacted with a metal chloride in an amount sufficient to remove the oxide layer. In some embodiments, depositing the metal layer is performed at a temperature of 350 to 470 degrees celsius. In some embodiments, depositing the metal layer is performed by atomic layer deposition. In some embodiments, the method further comprises: and depositing a second covering layer on the first surface of the metal layer, wherein the second covering layer is made of an n-type metal material. In some embodiments, the first cap layer comprises titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, depositing the at least one metal layer includes cyclically depositing a first titanium monolayer, a first aluminum monolayer, and a silicon monolayer to form a titanium aluminum silicide (TiAlSi) material. In some embodiments, the metal layer is deposited to a thickness of about 10 to 50 angstroms. In some embodiments, the first capping layer is deposited to a thickness of about 5 to 15 angstroms. In some embodiments, the metal layer comprises titanium in an amount of 40 to 50 atomic percent. In some embodiments, the metal layer comprises 1 to 10 atomic percent aluminum. In some embodiments, the metal layer comprises 30 to 40 atomic percent silicon. In some embodiments, the first capping layer comprises titanium nitride having a thickness of about 5 to 15 angstroms, and the metal layer is TiAlSi having a thickness of about 10 to 50 angstroms.

In some embodiments, the present disclosure relates to a method of processing a high-k dielectric material, the method comprising the steps of: depositing a first capping layer over the high-k dielectric layer, the first capping layer having a first surface; depositing one or more metal work function layers over the first surface of the first capping layer, wherein the one or more metal work function layers comprise titanium aluminum silicide (TiAlSi); depositing a second capping layer over the one or more metal work function layers; and optionally depositing a second metal layer over the second capping layer. In some embodiments, one or more metal work function layers are deposited by reacting at least one titanium halide precursor, at least one aluminum precursor, and at least one silane precursor. In some embodiments, depositing one or more metal work function layers comprises one or more of the following sequential cycles: a) introducing a metal halide precursor into the processing chamber to form a first monolayer on the first capping layer; b) purging the metal halide precursor with a purge gas; c) introducing at least one aluminum precursor to form a second monolayer on the first capping layer; d) purging the aluminum precursor with a purge gas; and e) introducing at least one silane precursor to form a third monolayer on the first capping layer, wherein a) through e) form a titanium aluminum silicide layer over the first capping layer. In some embodiments, the method comprises: repeating a) to e) to form a titanium aluminum silicide layer having a predetermined thickness. In some embodiments, the method comprises: the deposition of one or more metal work function layers is performed at a temperature of 350 to 470 degrees celsius.

In some embodiments, the present disclosure relates to methods of processing high-k dielectric materials, comprising or consisting of: depositing a first capping layer over the high-k dielectric layer, the first capping layer having a first surface; depositing one or more metal work function layers over the first surface of the first capping layer, wherein the one or more metal work function layers comprise or consist of titanium aluminide (TiAlSi); depositing a second capping layer over the one or more metal work function layers; and depositing a second metal layer over the second capping layer.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.