阅读说明：本技术 功率放大电路 (Power amplifying circuit ) 是由 森泽文雅 石本一彦 播磨史生 于 2019-10-15 设计创作，主要内容包括：提供一种功率放大电路,使过电流或过电压保护功能的动作速度提高。功率放大电路具备：放大器,其将无线电频率信号放大后输出；偏置电流供给电路,其向放大器供给偏置电流；检测电路,其检测放大器的电流或电压是否为规定阈值以上；以及抽取电路,在检测电路检测到电流或电压为规定阈值以上的情况下,该抽取电路抽取向放大器供给的偏置电流的至少一部分。(Provided is a power amplifier circuit, which can improve the operation speed of an overcurrent or overvoltage protection function. The power amplifier circuit includes: an amplifier for amplifying the radio frequency signal and outputting the amplified radio frequency signal; a bias current supply circuit that supplies a bias current to the amplifier; a detection circuit that detects whether or not a current or a voltage of the amplifier is equal to or higher than a predetermined threshold; and an extraction circuit that extracts at least a part of the bias current supplied to the amplifier when the detection circuit detects that the current or the voltage is equal to or greater than a predetermined threshold value.)

1. A power amplification circuit is provided with:

an amplifier for amplifying the radio frequency signal and outputting the amplified radio frequency signal;

a bias current supply circuit including a first transistor that supplies a bias current to the amplifier;

a detection circuit that detects whether or not a current or a voltage of the amplifier is equal to or higher than a predetermined threshold; and

a second transistor connected between the first transistor and ground,

the collector or the drain of the second transistor is connected to the emitter or the source of the first transistor, and the emitter or the source of the second transistor is connected to ground.

2. The power amplification circuit of claim 1,

the power amplifier circuit further includes a collector current supply circuit for supplying a current to the collector of the first transistor,

the collector current supply circuit cuts off the current supplied to the collector of the first transistor when the detection circuit detects that the current or the voltage of the amplifier is equal to or greater than the predetermined threshold.

3. The power amplification circuit of claim 1,

the power amplifier circuit further includes a collector current supply circuit for supplying a current to the collector of the first transistor,

the collector current supply circuit includes:

a current mirror circuit including a third transistor and a fourth transistor;

a fifth transistor connected between a power supply voltage and the third transistor and the fourth transistor; and

a sixth transistor connected between the third transistor or the fourth transistor and ground.

4. The power amplification circuit of claim 3,

the power amplifier circuit further includes an inverter connected to the collector current supply circuit,

a base or gate of the fifth transistor is connected to an output terminal of the inverter,

a base or a gate of the sixth transistor is connected to an input terminal of the inverter.

5. The power amplification circuit of any one of claims 1 to 4,

the power amplifier circuit further includes a second bias current supply circuit that supplies a second bias current to the base of the first transistor,

the second bias current supply circuit cuts off the second bias current when the detection circuit detects that the current or the voltage of the amplifier is equal to or greater than the predetermined threshold value.

6. The power amplification circuit of any one of claims 1 to 4,

the power amplifier circuit further includes a second bias current supply circuit that supplies a second bias current to the base of the first transistor,

the second bias current supply circuit includes:

a current mirror circuit including a seventh transistor and an eighth transistor;

a ninth transistor connected between a power supply voltage and the seventh and eighth transistors; and

a tenth transistor connected between the seventh transistor or the eighth transistor and ground.

7. The power amplification circuit of claim 6,

the power amplifier circuit further includes an inverter connected to the second bias current supply circuit,

a base or a gate of the ninth transistor is connected to an output terminal of the inverter,

a base or a gate of the tenth transistor is connected to an input terminal of the inverter.

8. The power amplification circuit of any one of claims 1 to 7,

the detection circuit includes:

a detection element that detects the current or the voltage of the amplifier; and

and a comparison circuit that compares the current or the voltage detected by the detection element with the predetermined threshold value and outputs a comparison result.

9. The power amplification circuit of any one of claims 1 to 7,

the detection circuit includes:

a replica transistor into whose collector a current corresponding to the magnitude of the current of the amplifier flows;

a replica current detection element that detects a current flowing into a collector of the replica transistor; and

and a second comparator circuit that compares the current flowing into the collector of the replica transistor detected by the replica current detection element with a predetermined second threshold value and outputs a comparison result.

10. The power amplification circuit of any one of claims 1 to 9,

the amplifier includes a heterojunction bipolar transistor.

11. The power amplification circuit of any one of claims 1 to 5,

the power amplification circuit further includes:

a second amplifier for amplifying the radio frequency signal and outputting the amplified radio frequency signal;

a third bias current supply circuit that supplies a third bias current to the second amplifier;

a second detection circuit that detects whether or not a current or a voltage of the second amplifier is equal to or higher than a predetermined second threshold value; and

and a second extraction circuit that extracts at least a part of the third bias current supplied to the second amplifier when the second detection circuit detects that the current or the voltage of the second amplifier is equal to or higher than the predetermined second threshold.

12. A power amplification circuit is provided with:

an amplifier for amplifying the radio frequency signal and outputting the amplified radio frequency signal;

a bias current supply circuit that supplies a bias current to the amplifier;

a detection circuit that detects whether or not a current or a voltage of the amplifier is equal to or higher than a predetermined threshold; and

and an extraction circuit that extracts at least a part of the bias current supplied to the amplifier when the detection circuit detects that the current or the voltage is equal to or higher than the predetermined threshold.

13. The power amplification circuit of claim 12,

the bias current supply circuit includes a first transistor, and the bias current is supplied to the amplifier from an emitter or a source of the first transistor.

14. The power amplification circuit of claim 13,

the decimation circuit comprises a second transistor having a collector or drain connected to an emitter or source of the first transistor.

Technical Field

The present invention relates to a power amplifier circuit.

Background

In a mobile communication device such as a mobile phone, a power amplifier circuit is used to amplify power of a Radio Frequency (RF) signal transmitted to a base station.

For example, patent document 1 describes an amplifier protection circuit including a drain current detection unit that detects a drain current of a power amplifier, a comparator that outputs a comparison result obtained by comparing a detection signal with a reference voltage, and a switching circuit provided between a power supply and the power amplifier. The comparator supplies an output signal representing the comparison result to the switch circuit via the latch circuit. When the drain current detection unit detects an overcurrent, the output signal level of the comparator becomes "H", and this signal is supplied to the switching circuit, which shuts off the power amplifier from the power supply. This protects the amplifier from excessive drain currents.

Prior art documents

Patent document

Patent document 1: japanese laid-open patent publication No. 9-199950

Disclosure of Invention

Problems to be solved by the invention

However, in the protection circuit described in patent document 1, the switching circuit is provided on the drain side with respect to the amplifier, and therefore a time delay occurs. Further, when a switching circuit is present on the drain side of the amplifier, loss (decrease in output) may occur due to a resistance component, and RF characteristics may be degraded.

In view of the above, an object of the present invention is to provide a power amplifier circuit that improves the operation speed of an overcurrent or overvoltage protection function.

Means for solving the problems

A power amplifier circuit according to an aspect of the present invention includes: an amplifier for amplifying the radio frequency signal and outputting the amplified radio frequency signal; a bias current supply circuit that supplies a bias current to the amplifier; a detection circuit that detects whether or not a current or a voltage supplied to the amplifier is equal to or greater than a predetermined threshold; and an extraction circuit that extracts at least a part of the bias current supplied to the amplifier when the detection circuit detects that the current or the voltage is equal to or greater than a predetermined threshold value.

According to this aspect, when an overcurrent or an overvoltage is detected, the extraction circuit directly extracts the bias current supplied from the bias current supply circuit to the amplifier, and thereby the operation of the amplifier is stopped, and the operation speed of the overcurrent or overvoltage protection function is increased.

Effects of the invention

According to the present invention, it is possible to provide a power amplifier circuit that improves the operation speed of an overcurrent or overvoltage protection function.

Drawings

Fig. 1 is an example of a schematic circuit configuration of a power amplifier circuit 1A according to a first embodiment.

Fig. 2 is a diagram showing an example of the configuration of each circuit provided in the control unit 3.

Fig. 3 is an example of a timing chart showing the operation of the power amplifier circuit 1A according to the first embodiment.

Fig. 4 is an example of a schematic circuit configuration of a power amplifier circuit 1B according to a second embodiment.

Fig. 5 is an example of a schematic circuit configuration of a power amplifier circuit 1C according to a third embodiment.

Fig. 6 is an example of a schematic circuit configuration of a power amplifier circuit 1D according to a fourth embodiment.

Fig. 7 shows an example of a schematic circuit configuration of a power amplifier circuit 1E according to a fifth embodiment.

Fig. 8 is a diagram illustrating an example of the circuit configuration of the overcurrent detection circuit 30 provided in the control unit 3.

Fig. 9 is an example of a timing chart showing the operation of the overcurrent detection circuit 30 provided in the control unit 3.

Detailed Description

Preferred embodiments of the present invention will be described with reference to the accompanying drawings. (Note that, in the drawings, the same reference numerals denote the same or similar structures.)

[ first embodiment ]

(1) Structure of the product

(1-1) Power amplifying Circuit 1A

Fig. 1 is an example of a schematic circuit configuration of a power amplifier circuit 1A according to a first embodiment. As shown in fig. 1, the power amplifier circuit 1A includes, for example, an amplifier unit 2, a control unit 3, a current detection element R1, and an inductor L1.

(1-2) amplification section 2

The amplifier 2 includes, for example, a power amplifier Amp1 and a bias current supply circuit 20.

(1-2-1) Power Amplifier Amp1

The power amplifier Amp1 (amplifier) includes, for example, a transistor. The power amplifier Amp1 is supplied with the power supply voltage Vcc via the current detection element R1 and the inductor L1. A current Icc flows from the power supply voltage Vcc to the power amplifier Amp 1. The power amplifier Amp1 receives a supply of an input signal Pin as a radio frequency signal (RF signal), amplifies the signal, and outputs an output signal Pout.

(1-2-2) bias current supply circuit 20

The bias current supply circuit 20 is a circuit for supplying the bias current Ib2 to the power amplifier Amp1, and includes, for example, transistors Q1, Q2, QD1, QD2, and resistance elements R2, R3, and R4.

The transistor Q2 (first transistor) has a collector connected to a Iec current circuit 32 described later, an emitter connected to the power amplifier Amp1 via a resistor element R2, and a base connected to the Ibias current circuit 33 via a resistor element R3. Transistor Q2 receives a collector current Iec from Iec current circuit 32 and a base current Ibias from Ibias current circuit 33. The transistor Q2 supplies a bias current Ib2 from the emitter to the power amplifier Amp1 via the resistor element R2. The transistor Q2 may be an FET. In this case, the collector may be replaced with a drain, the emitter with a source, and the base with a gate.

The transistor Q1 (second transistor) has a collector connected between the transistor Q2 and the resistor R2, an emitter grounded to GND, and a base connected to the current draw circuit 34 via the resistor R4. Under a predetermined condition, the current Ishut is supplied from the current draw circuit 34 to the base of the transistor Q1. When the current Ishut is supplied, the transistor Q1 is turned on, and the current Ib1 (collector current of the transistor Q1) is extracted from the bias current Ib2 supplied to the power amplifier Amp 1. The transistor Q1 may be an FET. In this case, the collector may be replaced with a drain, the emitter with a source, and the base with a gate. In addition, a voltage is supplied from the current draw circuit 34 to turn on the FET.

(1-3) control section 3

Fig. 2 is a diagram showing an example of the configuration of each circuit provided in the control unit 3. As shown in fig. 2, the control unit 3 includes, for example, an overcurrent detection circuit 30, a current interruption circuit 31, an Iec current circuit 32, an Ibias current circuit 33, and a current extraction circuit 34.

(1-3-1) overcurrent detection circuit 30

The overcurrent detection circuit 30 detects a current flowing through the power amplifier Amp1 by the current detection element R1, and outputs a signal indicating the detection result to the current interruption circuit 31. The overcurrent detection circuit 30 includes, for example, a current detection element R1 and a comparator 301. The current detection element R1 is a resistance element, and as shown in fig. 1, has one end supplied with the power supply voltage Vcc and the other end connected to one end of the inductor L1. The comparator 301 has a non-inverting input terminal connected between the current detection element R1 and the inductor L1, supplies a reference voltage Vref to an inverting input terminal, and outputs a voltage Vdet at an H (high) level or an L (low) level according to a comparison result. The reference voltage Vref can be set so that the output voltage Vdet of the comparator 301 is inverted when the current Icc flowing through the power amplifier Amp1 becomes equal to or greater than a predetermined threshold value (overcurrent). That is, the overcurrent detection circuit 30 detects a current flowing in the power amplifier Amp1, and supplies the output signal of the comparator 301 to the current interruption circuit 31 as a detection result. Therefore, the overcurrent detection circuit 30 compares the voltage generated when the voltage of the current detection element R1 drops with the reference voltage Vref, and outputs the Vdet signal as the H level or the L level. Therefore, the current detection element R1 is desired to have a small variation in resistance value and a small resistance value (about 10m Ω to 30m Ω).

(1-3-2) Current interruption Circuit 31

The current interruption circuit 31 supplies control signals to the Iec current circuit 32, the Ibias current circuit 33, and the current draw circuit 34, which will be described later, based on the detection result supplied from the overcurrent detection circuit 30. The current interruption circuit 31 includes inverters 311, 312, and 313, for example. Inverters 311, 312, and 313 are logic gates, and output voltages by inverting input voltage levels. Specifically, inverters 311, 312, and 313 output an L-level voltage when an H-level voltage is input, and output an H-level voltage when an L-level voltage is input. The inverter 311 supplies Iec the current circuit 32 with control signals from the input terminal and the output terminal, respectively. The inverter 312 supplies control signals to the Ibias current circuit 33 from the input terminal and the output terminal, respectively. The inverter 313 supplies control signals to the current draw circuit 34 from the input terminal and the output terminal, respectively.

(1-3-3) Iec Current Circuit 32

Iec the current circuit 32 includes, for example, a constant current source IS1, P-channel MOSFETs 321, 322, 323, and an N-channel MOSFET 324. P-channel MOSFETs 321 and 323 exemplify "third transistor" and "fourth transistor", P-channel MOSFET322 exemplifies "fifth transistor", and N-channel MOSFET324 exemplifies "sixth transistor". The source of the P-channel MOSFET321 IS supplied with the power supply voltage Vbat, the drain and gate of the P-channel MOSFET321 are diode-connected, and the gate of the P-channel MOSFET323 IS connected to the drain of the P-channel MOSFET322 and the constant current source IS 1. The power supply voltage Vbat is supplied to the source of the P-channel MOSFET323, and the drain of the P-channel MOSFET323 is connected to the drain of the N-channel MOSFET324 and the collector of the transistor Q2 of the bias current supply circuit 20 in the amplifying section 2. The constant current source IS1 IS connected between the drain of the P-channel MOSFET321 and GND. Therefore, the P-channel MOSFETs 321 and 323 constitute a current mirror circuit. The source of the P-channel MOSFET322 is supplied with the power supply voltage Vbat, and the gate of the P-channel MOSFET322 is connected to the output terminal of the inverter 311. The drain of N-channel MOSFET324 is connected to the drain of P-channel MOSFET323, the source is grounded to GND, and the gate is connected to the input terminal of inverter 311. In addition, the P-channel MOSFET322 and the N-channel MOSFET324 control Iec supply of the output current Iec of the current circuit 32 by the input terminal voltage level or the output terminal voltage level of the inverter 311 of the current cutoff circuit 31.

During a normal operation (when no overcurrent is detected), since the output voltage Vdet of the overcurrent detection circuit 30 (the comparator 301) is at the L level, the input terminal of the inverter 311 is at the L level and the output terminal thereof is at the H level. At this time, since an H-level signal is supplied from the output terminal of the inverter 311 to the gate of the P-channel MOSFET322, the P-channel MOSFET322 is turned off, and since an L-level signal is supplied from the input terminal of the inverter 311 to the gate of the N-channel MOSFET324, the N-channel MOSFET324 is turned off. Therefore, in the normal operation, a current generated by the constant current source IS1 flows through the P-channel MOSFET321, and a mirror current of the same amount as the current flows through the P-channel MOSFET 323. The mirror current is supplied from the drain of P-channel MOSFET323 to the collector of transistor Q2 as current Iec.

When an overcurrent is detected, the output voltage Vdet of the overcurrent detection circuit 30 (comparator 301) is at the H level, and therefore the input terminal of the inverter 311 is at the H level and the output terminal thereof is at the L level. At this time, since an L-level signal is supplied from the output terminal of the inverter 311 to the gate of the P-channel MOSFET322, the P-channel MOSFET322 is turned on, and since an H-level signal is supplied from the input terminal of the inverter 311 to the gate of the N-channel MOSFET324, the N-channel MOSFET324 is turned on. Therefore, P-channel MOSFET322 is turned on, the gate voltages of MOSFETs 321 and 323 become Vbat, the voltage difference between the gate and the source disappears, and MOSFET323 is turned off. On the other hand, N-channel MOSFET324 is turned on, and the drain of MOSFET323 is connected to GND. Therefore, no Iec current is supplied to the transistor Q2. When an overcurrent is detected, the Iec current supplied from the drain of the P-channel MOSFET323 to the transistor Q2 is 0 (a).

(1-3-4) Ibias current circuit 33

The Ibias current circuit 33 includes, for example, a constant current source IS2, P-channel MOSFETs 331, 332, 333, and an N-channel MOSFET 334. P-channel MOSFETs 331 and 333 exemplify a "seventh transistor" and an "eighth transistor", P-channel MOSFET332 exemplifies a "ninth transistor", and N-channel MOSFET334 exemplifies a "tenth transistor". The source of the P-channel MOSFET331 IS supplied with the power supply voltage Vbat, the drain and gate of the P-channel MOSFET331 are diode-connected, and the gate of the P-channel MOSFET333 IS connected to the drain of the P-channel MOSFET332 and the constant current source IS 2. The power supply voltage Vbat is supplied to the source of the P-channel MOSFET333, and the drain of the P-channel MOSFET333 is connected to the base of the transistor Q2 and the collector and gate of the transistor QD1 via the drain of the N-channel MOSFET334 and the resistance element R3 of the bias current supply circuit 20 in the amplifying section 2. The constant current source IS2 IS connected between the drain of the P-channel MOSFET331 and GND. Therefore, the P-channel MOSFETs 331 and 333 constitute a current mirror circuit. The source of the P-channel MOSFET332 is supplied with the power supply voltage Vbat, and the gate of the P-channel MOSFET332 is connected to the output terminal of the inverter 312. The N-channel MOSFET334 has a drain connected to the drain of the P-channel MOSFET333, a source grounded to GND, and a gate connected to the input terminal of the inverter 312. In addition, the P-channel MOSFET332 and the N-channel MOSFET334 control the supply of the output current Ibias of the Ibias current circuit 33 by the input terminal voltage level or the output terminal voltage level of the inverter 312 of the current cutoff circuit 31.

During a normal operation (when no overcurrent is detected), since the output voltage Vdet of the overcurrent detection circuit 30 (the comparator 301) is at the L level, the input terminal of the inverter 312 is at the L level and the output terminal thereof is at the H level. At this time, an H-level signal is supplied from the output terminal of the inverter 312 to the gate of the P-channel MOSFET332, and therefore, the P-channel MOSFET332 is turned off, and an L-level signal is supplied from the input terminal of the inverter 312 to the gate of the N-channel MOSFET334, and therefore, the N-channel MOSFET334 is turned off. Therefore, in the normal operation, a current generated by the constant current source IS2 flows through the P-channel MOSFET331, and a mirror current of the same amount as the current flows through the P-channel MOSFET 333. The mirror current is supplied as a current Ibias from the drain of the P-channel MOSFET333 to the bases of the transistors QD1, QD2, and transistor Q2 via the resistance element R3.

When an overcurrent is detected, the output voltage Vdet of the overcurrent detection circuit 30 (comparator 301) is at the H level, and therefore the input terminal of the inverter 311 is at the H level and the output terminal thereof is at the L level. At this time, an L-level signal is supplied from the output terminal of the inverter 312 to the gate of the P-channel MOSFET332, so that the P-channel MOSFET332 is turned on, and an H-level signal is supplied from the input terminal of the inverter 311 to the gate of the N-channel MOSFET334, so that the N-channel MOSFET334 is turned on. Therefore, the P-channel MOSFET332 is turned on, the gate voltages of the MOSFETs 331 and 333 are Vbat voltages, the voltage difference between the gate and the source disappears, and the MOSFET333 is turned off. On the other hand, N-channel MOSFET334 is on, and the drain of MOSFET333 is connected to GND. Therefore, no Ibias current is supplied. When an overcurrent is detected, the Ibias current supplied from the drain of the P-channel MOSFET333 to the bias current supply circuit 20 is 0 (a).

When the bias current supply circuit 20 is of the voltage control type, the power amplifier circuit 1A may include a voltage control circuit that controls a bias voltage for applying a voltage to the base of the transistor Q2, instead of the Ibias current circuit 33.

(1-3-5) Current-drawing Circuit 34

The current extraction circuit 34 includes, for example, a constant current source IS3, P-channel MOSFETs 341, 342, 343, and an N-channel MOSFET 344. The power supply voltage Vbat IS supplied to the source of the P-channel MOSFET341, the drain and gate of the P-channel MOSFET341 are diode-connected, and the gate of the P-channel MOSFET343 IS connected to the drain of the P-channel MOSFET342 and the constant current source IS 3. The power supply voltage Vbat is supplied to the source of the P-channel MOSFET343, and the drain of the P-channel MOSFET343 is connected to the base of the transistor Q1 via the drain of the N-channel MOSFET344 and the resistance element R4 of the bias current supply circuit 20 in the amplifying section 2. The constant current source IS3 IS connected between the drain of the P-channel MOSFET341 and ground. Thus, the P-channel MOSFETs 341, 343 constitute a current mirror circuit. The source of the P-channel MOSFET342 is supplied with a power supply voltage Vbat, and the gate of the P-channel MOSFET342 is connected to an input terminal of the inverter 313. The N-channel MOSFET344 has a drain connected to the drain of the P-channel MOSFET343, a source grounded to GND, and a gate connected to the output terminal of the inverter 313. In addition, the P-channel MOSFET342 and the N-channel MOSFET344 control the supply of the output current Ishut of the current draw circuit 34 by the input terminal voltage level or the output terminal voltage level of the inverter 313 of the current cutoff circuit 31.

During a normal operation (when no overcurrent is detected), since the output voltage Vdet of the overcurrent detection circuit 30 (the comparator 301) is at the L level, the input terminal of the inverter 311 is at the L level and the output terminal thereof is at the H level. At this time, an L-level signal is supplied from the input terminal of the inverter 313 to the gate of the P-channel MOSFET342, so that the P-channel MOSFET342 is turned on, and an H-level signal is supplied from the output terminal of the inverter 313 to the gate of the N-channel MOSFET344, so that the N-channel MOSFET344 is turned on. Therefore, the P-channel MOSFET342 is turned on, the gate voltages of the MOSFETs 341 and 343 become Vbat voltages, the voltage difference between the gate and the source disappears, and the MOSFET343 is turned off. On the other hand, the N-channel MOSFET344 is turned on, and the drain of the MOSFET343 is connected to GND. Therefore, Ishut current is not supplied. In the normal operation, the Ishut current supplied from the drain of the P-channel MOSFET343 to the transistor Q1 is 0 (a).

When an overcurrent is detected, the output voltage Vdet of the overcurrent detection circuit 30 (comparator 301) is at the H level, and therefore the input terminal of the inverter 311 is at the H level and the output terminal thereof is at the L level. At this time, since an H-level signal is supplied from the input terminal of the inverter 313 to the gate of the P-channel MOSFET342, the P-channel MOSFET342 is turned off, and since an L-level signal is supplied from the output terminal of the inverter 313 to the gate of the N-channel MOSFET344, the N-channel MOSFET344 is turned off. Therefore, when an overcurrent IS detected, a current generated by the constant current source IS3 flows to the P-channel MOSFET341, and a mirror current of the same amount as the current flows to the P-channel MOSFET 343. The mirror current is supplied as a current Ishut from the drain of the P-channel MOSFET343 to the transistor Q1 via the resistance element R4. Thereby, the transistor Q1 is turned on, and a current Ib1 (collector current of the transistor Q1) is extracted from the bias current Ib 2.

(2) Movement of

Fig. 3 is an example of a timing chart showing the operation of the power amplifier circuit 1A according to the first embodiment. (a) The time change of the current Icc flowing in the current detection element R1 is shown. (b) The temporal change of the output voltage Vdet of the overcurrent detection circuit 30 is shown. (c) The time variations of the current Iec supplied by the current circuit 32, the current Ibias supplied by the Ibias current circuit 33, and the current Ishut supplied by the current drawing circuit 34 are shown Iec. (d) The time variation of the collector current Ib1 of the transistor Q1 is shown. (e) The time change of the bias current Ib2 of the power amplifier Amp1 supplied from the transistor Q2 is shown.

(2-1) before time T1

Before time T1 of the normal operation, current Icc flowing from power supply voltage Vcc to power amplifier Amp1 does not exceed predetermined threshold value it (a) for detecting overcurrent, and takes a predetermined value ((a) of fig. 3). At this time, the output voltage Vdet of the overcurrent detection circuit 30 is 0(V) corresponding to the L level ((b) of fig. 3). As described above, the predetermined current Iec is supplied from the Iec current circuit 32 to the bias current supply circuit 20, and the predetermined current Ibias is supplied from the Ibias current circuit 33 to the bias current supply circuit 20 ((c) of fig. 3). The current Ishut supplied from the current extraction circuit 34 is 0(a) (fig. 3 (c)). Since the current Ishut is 0(a), the collector current Ib1 of the transistor Q1 is 0(a), and the current drawn from the bias current Ib2 of the power amplifier Amp1 to the transistor Q1 side is 0(a) (fig. 3 (d)). As described above, since the current Iec and the current Ibias are supplied to the bias current supply circuit 20, the predetermined bias current Ib2 is supplied from the collector of the transistor Q2 to the power amplifier Amp1 ((e) of fig. 3).

(2-2) time T1-T2

At times T1 to T2 when an overcurrent flows, the current Icc flowing from the power supply voltage Vcc to the power amplifier Amp1 increases with the passage of time in a region smaller than the predetermined threshold value it (a) for detecting an overcurrent ((a) of fig. 3). At this time, since the current Icc does not exceed the predetermined threshold value it (a), the output voltage Vdet of the overcurrent detection circuit 30 remains at the L level ((b) of fig. 3). As the current Icc increases, the bias current Ib2 flowing from the transistor Q2 to the power amplifier Amp1 increases (fig. 3 (e)), and the collector current of the transistor Q2, i.e., the current Iec also increases (fig. 3 (c)). On the other hand, a predetermined current Ibias is supplied from the Ibias current circuit 33 to the bias current supply circuit 20 ((c) of fig. 3). In addition, the current Ishut supplied from the current extraction circuit 34 is kept at 0(a) (fig. 3 (c)). Since the current Ishut is 0(a), the collector current Ib1 of the transistor Q1 is 0(a), and the current Ib1 drawn from the bias current Ib2 of the power amplifier Amp1 toward the transistor Q1 is also 0(a) (fig. 3 (d)).

(2-3) time T2-T3

At time T2 when the overcurrent is detected, current Icc reaches predetermined threshold value it (a). At this time, the output voltage Vdet of the overcurrent detection circuit 30 is inverted from the L level to the H level ((b) of fig. 3). Immediately after the output voltage Vdet of the overcurrent detection circuit 30 is inverted from the L level to the H level, the current circuit 32 from Iec still supplies the predetermined current Iec to the bias current supply circuit 20, and the current circuit 33 from Ibias still supplies the predetermined current Ibias to the bias current supply circuit 20 ((c) of fig. 3). On the other hand, as described above, since the output voltage Vdet of the overcurrent detection circuit 30 is inverted from the L level to the H level, the predetermined current Ishut is supplied from the current extraction circuit 34 to the base of the transistor Q1 ((c) of fig. 3). Thereby, the current Ib1 starts to flow into the collector of the transistor Q1, and the current Ib1 increases with the elapse of time ((d) of fig. 3). Since the current Ib1 is gradually extracted from the transistor Q2 toward the transistor Q1, the bias current Ib2 supplied from the transistor Q2 to the power amplifier Amp1 decreases with the elapse of time ((e) of fig. 3). Accordingly, the current Icc flowing from the power supply voltage Vcc to the power amplifier Amp1 also gradually decreases ((a) of fig. 3).

(2-4) after time T3

At time T3, current Icc flowing from power supply voltage Vcc to power amplifier Amp1 becomes 0(a) (fig. 3 (a)). Thus, the current Iec supplied from the current circuit Iec to the bias current supply circuit 20 and the current Ibias supplied from the Ibias current circuit 33 to the bias current supply circuit 20 are 0(a), respectively ((c) of fig. 3). Further, the bias current Ib2 supplied from the transistor Q2 to the power amplifier Amp1 also becomes 0(a) (fig. 3 (e)), the current Ib1 drawn from the bias current Ib2 of the power amplifier Amp1 to the transistor Q1 also becomes 0(a) (fig. 3 (d)), and the power amplifier Amp1 stops operating.

As described above, in the power amplifier circuit 1A according to the first embodiment, when an overcurrent is detected, the transistor Q1 directly extracts the bias current Ib2 of the power amplifier Amp1, and therefore, the operation speed of the overcurrent protection function is increased.

[ second embodiment ]

In the second embodiment, descriptions of common matters with the first embodiment are omitted, and only different points will be described. Fig. 4 is an example of a schematic circuit configuration of a power amplifier circuit 1B according to a second embodiment. The power amplifier circuit 1B according to the second embodiment has a configuration applicable to a dual-band system using two frequency bands.

As shown in fig. 4, the amplifier 2 included in the power amplifier circuit 1B further includes a power amplifier Amp2 and a bias current supply circuit 21. The power amplifiers Amp1 and Amp2 correspond to different frequency bands, respectively.

The power amplifier Amp2 (second amplifier) includes, for example, a transistor. The power amplifier Amp2 is supplied with the power supply voltage Vcc via the current detection element R5 and the inductor L2. A current IccB flows from the power supply voltage Vcc to the power amplifier Amp 2. The power amplifier Amp2 receives a supply of an input signal Pin as a radio frequency signal (RF signal), amplifies the input signal Pin, and outputs an output signal Pout.

The bias current supply circuit 21 (third bias current supply circuit) is a circuit for supplying the bias current Ib2B (third bias current) to the power amplifier Amp2, and includes, for example, transistors Q3, Q4, QD3, QD4, and resistance elements R6, R7, and R8.

The transistor Q4 (third transistor) has a collector connected to the Iec current circuit 32, an emitter connected to the power amplifier Amp2 via the resistor element R6, and a base connected to the Ibias current circuit 33 via the resistor element R7. Transistor Q4 receives a collector current IecB from Iec current circuit 32 and a base current IbiasB from Ibias current circuit 33. The transistor Q4 supplies a bias current Ib2B from the emitter to the power amplifier Amp2 via the resistor element R6.

The transistor Q3 (fourth transistor) has a collector connected between the transistor Q4 and the resistor R6, an emitter grounded to GND, and a base connected to the current draw circuit 34 via the resistor R8. Under a predetermined condition, the current IshutB is supplied from the current draw circuit 34 to the base of the transistor Q3. When the current IshutB is supplied, the transistor Q3 is turned on, and the current Ib1B (collector current of the transistor Q3) is drawn from the bias current Ib2B supplied to the power amplifier Amp 2.

As shown in fig. 4, the control unit 3 included in the power amplifier circuit 1B further includes an overcurrent detection circuit 30B (second current detection circuit) and a logic circuit 35. The overcurrent detection circuit 30B has the same configuration as the overcurrent detection circuit 30. The overcurrent detection circuits 30 and 30B detect overcurrent with respect to the collector currents Icc and IccB of the power amplifiers Amp1 and Amp2, respectively, and output signals indicating the detection results to the logic circuit 35. The logic circuit 35 receives the supply of the control signal, and supplies the output signal of the overcurrent detection circuit 30 or 30B to the current interruption circuit 31.

As described above, the power amplifier circuit 1B according to the second embodiment has a configuration for detecting an overcurrent for each of a plurality of frequency bands, and thus can perform overcurrent protection for each frequency band.

[ third embodiment ]

In the third embodiment, descriptions of common matters with the first embodiment are omitted, and only different points will be described. Fig. 5 is an example of a schematic circuit configuration of a power amplifier circuit 1C according to a third embodiment. A power amplifier circuit 1C according to a third embodiment is a different embodiment from the bias current supply circuit 20 of the power amplifier circuit 1A according to the first embodiment. The bias current supply circuit 20 of the power amplifier circuit 1A according to the first embodiment is a system in which two stages of diodes are connected, whereas the bias current supply circuit 20 of the power amplifier circuit 1C according to the third embodiment is a current mirror system.

The bias current supply circuit 20 of the power amplifier circuit 1C according to the third embodiment is a current mirror type bias current supply circuit system including a transistor Q5 and a resistance element R9 instead of the transistors QD1 and QD 2.

A collector of the transistor Q5 (fifth transistor) is connected to the other end of the resistor R3 and a base of the transistor Q2, a base is connected to one end of the resistor R9, and an emitter is grounded to GND. One end of the resistor R9 is connected to the base of the transistor Q5, and the other end is connected to the emitter of the transistor Q2 and the collector of the transistor Q1. Thus, the transistor Q5 and the power amplifier Amp1 form a current mirror connection.

[ fourth embodiment ]

In the fourth embodiment, descriptions of common matters with the first embodiment are omitted, and only different points will be described. Fig. 6 is an example of a schematic circuit configuration of a power amplifier circuit 1D according to a fourth embodiment. A method of detecting a current in the power amplifier circuit 1D according to the fourth embodiment is different from the method of detecting a current in the power amplifier circuit 1A according to the first embodiment, and a method of detecting an overcurrent using the replica transistor Rep1 is employed instead of the current detection element R1.

As shown in fig. 6, the amplifying section 2 of the power amplifying circuit 1D of the fourth embodiment includes a replica transistor Rep 1. The replica transistor Rep1 is a transistor having a size smaller than (1/N as described later) that of the power amplifier AMP1, and is a current amplifying element (amplifying transistor) that amplifies and outputs a current input to the base similarly to the transistor included in the power amplifier AMP 1. The replica transistor Rep1 detects a current Irp that follows the collector current Icc of the power amplifier AMP1, and thus functions as a current detection element. The collector of the replica transistor Rep1 is connected to the other end of an inductor L3 included in the low-pass filter 40 described later. A collector current Irp flows into the collector of the replica transistor Rep 1. The input signal Pin is supplied to the base of the replica transistor Rep 1. In addition, a part of the bias current Ib2 is supplied from the transistor Q2 to the base of the replica transistor Rep1 via the resistor element R2.

As shown in fig. 6, the power amplifier circuit 1D according to the fourth embodiment includes a low-pass filter 40. The low pass filter 40 includes a capacitor C1 and an inductor L3. One end of the capacitor C1 is connected to a drain of a P-channel MOSFET362 of the overcurrent detection circuit 36 described later and one end of an inductor L3, and the other end is grounded to GND. One end of the inductor L3 is connected to one end of the capacitor C1, and the other end is connected to the collector of the replica transistor Rep 1.

As shown in fig. 6, the control unit 3 of the power amplifier circuit 1D according to the fourth embodiment includes an overcurrent detection circuit 36. The overcurrent detection circuit 36 includes P-channel MOSFETs 361 and 362, a resistance element R10, a comparator 363, and a reference voltage source Vs. The P-channel MOSFET362 is diode-connected, and supplies a power supply voltage Vcc to the source of the P-channel MOSFET362, and the drain of the P-channel MOSFET362 is connected to the collector of the replica transistor Rep1 via the low-pass filter 40. A power supply voltage Vcc is supplied to the source of the P-channel MOSFET361, the gate of the P-channel MOSFET361 is connected to the gate of the P-channel MOSFET362, and the drain of the P-channel MOSFET361 is connected to the non-inverting input terminal of the comparator 363 and one end of the resistor element R10. One end of the resistor R10 is connected to the non-inverting input terminal of the comparator 363 and the drain of the P-channel MOSFET361, and the other end is grounded to GND. The inverting input terminal of the comparator 363 is supplied with a reference voltage Vref2 from a reference voltage source Vs.

P-channel MOSFETs 361 and 362 form a current mirror connection. Therefore, a collector current Irp flowing from the P-channel MOSFET362 to the collector of the replica transistor Rep1 via the low-pass filter 40 flows in the P-channel MOSFET 361. The collector current Irp is converted into a voltage Vsense by the resistor element R10, and the voltage Vsense is supplied to the non-inverting input terminal of the comparator 363. The output terminal of the comparator 363 is connected to the current interruption circuit 31, and outputs the voltage Vdet at H (high) level or L (low) level based on the comparison result between the voltage Vsense and the reference voltage Vref 2.

Here, the size and function of the replica transistor Rep1 are explained. The size ratio of the transistor included in the power amplifier Amp1 to the replica transistor Rep1 is set to N: 1. Here, N is a real number much larger than 1, so that the collector current Icc of the transistor included in the power amplifier Amp1 becomes a value much larger than the collector current Irp of the replica transistor Rep 1. Specifically, for example, when the transistor included in the power amplifier Amp1 and the replica transistor Rep1 have a multi-emitter structure, the ratio of the number of unit transistors included in the transistor included in the power amplifier Amp1 to the number of unit transistors included in the replica transistor Rep1 may be set to N: 1. Alternatively, for example, when the transistor included in the power amplifier Amp1 and the replica transistor Rep1 have a single emitter structure, the ratio of the size (emitter size) of the transistor included in the power amplifier Amp1 to the size (emitter size) of the replica transistor Rep1 may be set to N: 1.

At this time, the ratio of the collector current Icc of the transistor included in the power amplifier Amp1 to the collector current Irp of the replica transistor Rep1 is substantially equal to the size ratio (N: 1) of the two transistors. In other words, the current densities of the two transistors are substantially equal. Thus, by detecting the collector current Irp of the replica transistor Rep1, the collector current Icc of the transistor included in the power amplifier Amp1 can be detected.

As described above, in the power amplifier circuit 1D according to the fourth embodiment, the overcurrent detection circuit 36 detects the collector current Irp of the replica transistor Rep1 to detect an overcurrent, and based on the detection result, the power amplifier circuit performs an overcurrent protection function.

[ fifth embodiment ]

In the fifth embodiment, descriptions of common matters with the first embodiment are omitted, and only different points will be described. Fig. 7 shows an example of a schematic circuit configuration of a power amplifier circuit 1E according to a fifth embodiment.

As shown in fig. 7, the control unit 3 of the power amplifier circuit 1E according to the fifth embodiment includes an attenuator circuit 37 and an overvoltage detection circuit 38. The power amplifier circuit 1E of the fifth embodiment detects an overvoltage with respect to the collector voltage of the power amplifier, and protects the power amplifier from the overvoltage.

The attenuator circuit 37 includes a P-channel MOSFET371 and resistance elements R11, R12. A collector voltage of the power amplifier Amp1 is supplied to the source of the P-channel MOSFET371, a control signal Logic is supplied to the gate of the P-channel MOSFET371, and the drain of the P-channel MOSFET371 is connected to one end of the resistor element R11. The other end of the resistor element R11 is connected to one end of the resistor element R12. The other end of the resistance element R12 is grounded to GND. The voltage between the resistance elements R11 and R12 is supplied to the overvoltage detection circuit 38. That is, the collector voltage of the power amplifier Amp1 is divided by the resistance elements R11 and R12 via the P-channel MOSFET371, and the divided voltage is supplied to the overvoltage detection circuit 38.

The overvoltage detection circuit 38 receives the supply of the divided voltage of the collector voltage of the power amplifier Amp1 from the attenuator circuit 37, compares the divided voltage with a predetermined reference voltage, and supplies a signal indicating the comparison result to the current interruption circuit 31.

As described above, in the power amplifier circuit 1E according to the fifth embodiment, when the overvoltage is detected, the transistor Q1 directly extracts the bias current Ib2 of the power amplifier Amp1, and therefore the operation speed of the overvoltage protection function is increased.

When the power amplifier circuit 1E does not perform an amplification operation, the P-channel MOSFET371 is turned off under the control of the control signal Logic. Therefore, when the power amplifier circuit 1E does not perform an amplifying operation, it is possible to cut off the current flowing from the power supply voltage Vcc to the resistance elements R11 and R12.

[ Circuit Structure of overcurrent detection Circuit 30 ]

Fig. 8 is an example of a schematic circuit configuration of the overcurrent detection circuit 30 included in the power amplification circuit 1A according to the first embodiment of fig. 1. The overcurrent detection circuit 30 detects a current flowing in the power amplifier Amp1 by the current detection element R1, and includes a comparator 301 that compares a detection voltage V1 converted into a voltage with a reference voltage Vref, a resistance element R1a that generates the reference voltage Vref, and a constant current source IS 4. As shown in fig. 8, the inverting input terminal of the comparator 301 IS connected between the resistance element R1a that generates the reference voltage and the constant current source IS4, and the other end of the constant current source IS4 IS grounded to GND. The other end of the resistance element R1a that generates the reference voltage is connected to the power supply voltage Vcc. The non-inverting input terminal of the comparator 301 is connected between the current detection element R1 and the inductor L1.

[ operation of overcurrent detection circuit 30 ]

Fig. 9 is a diagram showing voltages of the input terminals Vref and V1 and the output terminal Vdet of the overcurrent detection circuit 30 when an overcurrent occurs and when a normal operation is performed. The reference voltage Vref IS denoted by Vref-Vcc- (R1a × IS4), and the detection voltage V1 IS denoted by V1-Vcc- (R1 × Icc). When overcurrent occurs, the operation of the overcurrent detection circuit 30 becomes V1 > Vref, and the comparator 301 outputs Vdet output H (high) level. In the normal operation, V1 < Vref is set, and the comparator 301 outputs Vdet and outputs L (low) level.

The above-described embodiments are intended to facilitate understanding of the present invention, and are not intended to limit the present invention. The elements, the arrangement, the materials, the conditions, the shapes, the dimensions, and the like of the embodiments are not limited to those exemplified, and can be appropriately modified. In addition, the structures shown in different embodiments can be partially replaced or combined with each other.

Various embodiments of the present invention have been described above. A power amplifier circuit according to an embodiment of the present invention includes: an amplifier for amplifying the radio frequency signal and outputting the amplified radio frequency signal; a bias current supply circuit that supplies a bias current to the amplifier; a detection circuit that detects whether or not a voltage supplied to the amplifier is equal to or greater than a predetermined threshold; and an extraction circuit that extracts at least a part of the bias current supplied to the amplifier when the detection circuit detects that the current or the voltage is equal to or greater than the predetermined threshold.

Thus, when an overcurrent or an overvoltage is detected, the extraction circuit directly extracts the bias current supplied from the bias current supply circuit to the amplifier, and therefore, the operation of the amplifier is stopped, and the operation speed of the overcurrent or overvoltage protection function is increased.

In the power amplifier circuit, the bias current supply circuit may include a first transistor, and the bias current may be supplied to the amplifier from an emitter or a source of the first transistor.

Thus, when an overcurrent or an overvoltage is detected, the extraction circuit directly extracts the bias current supplied from the first transistor to the amplifier, and therefore, the operation speed of the overcurrent or overvoltage protection function is increased.

In the power amplifier circuit, the extraction circuit may include a second transistor, and a collector or a drain of the second transistor may be connected to an emitter or a source of the first transistor.

Thus, the second transistor extracts the bias current supplied from the first transistor to the amplifier, and therefore, the operation speed of the overcurrent or overvoltage protection function is improved.

The power amplifier circuit may further include a collector current supply circuit for supplying a current to the collector of the first transistor, and the collector current supply circuit may cut off the current supplied to the collector of the first transistor when the detection circuit detects that the current or the voltage of the amplifier is equal to or higher than a predetermined threshold value.

Thus, by controlling the collector current of the first transistor of the bias current supply circuit, the bias current supplied from the first transistor to the amplifier can be controlled.

The power amplifier circuit may further include a second bias current supply circuit configured to supply a second bias current to the base of the first transistor, and the second bias current supply circuit may block the second bias current when the detection circuit detects that the current or the voltage of the amplifier is equal to or greater than a predetermined threshold value.

Thus, by controlling the bias current or voltage applied from the bias current supply circuit to the base of the first transistor, the bias current supplied from the first transistor to the amplifier can be controlled.

In addition, in the power amplifier circuit, the detection circuit may include: a detection element that detects a current or a voltage of the amplifier; and a comparison circuit that compares the current or voltage detected by the detection element with a predetermined threshold value and outputs a comparison result.

This can improve the operation speed of the overcurrent or overvoltage protection function with a simple configuration.

In addition, in the power amplifier circuit, the detection circuit may include: a replica transistor into which a current corresponding to the magnitude of the current of the amplifier flows; a replica current detection element that detects a current flowing into a collector of the replica transistor; and a second comparator circuit that compares the current flowing into the collector of the replica transistor detected by the replica current detection element with a predetermined second threshold value and outputs a comparison result.

This can improve the operation speed of the overcurrent or overvoltage protection function with a simple configuration.

Further, the power amplifier circuit may further include: a second amplifier for amplifying the radio frequency signal and outputting the amplified radio frequency signal; a third bias current supply circuit that supplies a third bias current to the second amplifier; a second detection circuit that detects whether or not a current or a voltage of the second amplifier is equal to or higher than a predetermined second threshold; and a second extraction circuit that extracts at least a part of the third bias current supplied to the second amplifier when the second detection circuit detects that the current or voltage of the second amplifier is equal to or greater than a predetermined second threshold value.

This makes it possible to apply the power amplifier circuit to a system using a plurality of frequency bands (bands).

Description of the reference numerals

1A, 1B, 1C, 1D, 1E power amplifying circuits, 2 amplifying parts, 20, 21 bias current supply circuits, 3 control parts, 30B overcurrent detection circuits 1, 31 current cut-off circuits, 32 current circuits, 33 Ibias current circuits, 34 current extraction circuits, 35 logic circuits, 36 overcurrent detection circuits 2, 37 attenuator circuits, 311-313 inverters, 321-323, 331-333, 341-343, 361, 362, 371P channel MOSFETs, 324, 334, 344N channel MOSFETs, Amp, 2 power amplifiers, Q, QD transistors, R-12, R1 resistance elements, L-L inductors, C capacitors, IS-4 constant current sources, Vs reference voltage sources.