阅读说明：本技术 GaN HEMT和Si-CMOS单片集成方法 (GaN HEMT and Si-CMOS monolithic integration method ) 是由 樊永辉 许明伟 樊晓兵 于 2020-12-30 设计创作，主要内容包括：本发明提供了一种GaN HEMT和Si-CMOS单片集成方法,所述方法包括以下步骤：步骤S100,在硅衬底上外延生长GaN外延层结构；步骤S200,蚀刻所述GaN外延层结构形成GaN HEMT器件区域和Si-CMOS器件区域；步骤S300,在GaN HEMT器件区域制备GaN HEMT；步骤S400,在Si-CMOS器件区域制备Si-CMOS。本发明通过蚀刻GaN外延层结构形成GaN HEMT器件区域和Si-CMOS器件区域,以在同一衬底上制备GaN HEMT和Si-CMOS,实现GaN HEMT和Si-CMOS的集成在同一芯片上,GaN HEMT和Si-CMOS单片集成的总体芯片面积小,性能优越,成本低。(The invention provides a GaN HEMT and Si-CMOS monolithic integration method, which comprises the following steps: step S100, epitaxially growing a GaN epitaxial layer structure on a silicon substrate; step S200, etching the GaN epitaxial layer structure to form a GaN HEMT device region and a Si-CMOS device region; step S300, preparing a GaN HEMT in the GaN HEMT device region; and S400, preparing the Si-CMOS in the Si-CMOS device area. According to the invention, the GaN HEMT device region and the Si-CMOS device region are formed by etching the GaN epitaxial layer structure, so that the GaN HEMT and the Si-CMOS are prepared on the same substrate, the GaN HEMT and the Si-CMOS are integrated on the same chip, and the GaN HEMT and the Si-CMOS are monolithically integrated, so that the total chip area is small, the performance is excellent and the cost is low.)

1. A GaN HEMT and Si-CMOS monolithic integration method, characterized in that the method comprises the following steps:

step S100, epitaxially growing a GaN epitaxial layer structure on a silicon substrate;

step S200, etching the GaN epitaxial layer structure to form a GaN HEMT device region and a Si-CMOS device region;

step S300, preparing a GaN HEMT in the GaN HEMT device region;

and S400, preparing the Si-CMOS in the Si-CMOS device area.

2. The GaN HEMT and Si-CMOS monolithic integration method according to claim 1, wherein step S200 comprises,

step S201, sequentially gluing, aligning, exposing and developing partial areas of the GaN epitaxial layer structure to form a GaN epitaxial layer structure area covered with photoresist and a GaN epitaxial layer structure area not covered with photoresist;

step S202, etching the GaN epitaxial layer structure region of the uncovered photoresist to form a Si-CMOS device region;

and step S203, removing the photoresist, and cleaning the GaN epitaxial layer structure region covered with the photoresist to form a GaN HEMT device region.

3. The GaN HEMT and Si-CMOS monolithic integration method according to claim 1, wherein step S300 comprises,

step S301, forming a drain electrode and a source electrode on the surface of the GaN epitaxial layer structure;

step S302, forming a grid on the surface of the GaN epitaxial layer structure;

step S303, forming an inductor, a capacitor or a resistor on the surface of the GaN epitaxial layer structure;

step S304, the drain electrode and the inductor, the capacitor or the resistor are interconnected through metal.

4. The GaN HEMT and Si-CMOS monolithic integration method according to claim 3, wherein step S300 further comprises, after metal interconnection, depositing a passivation layer over said GaN HEMT.

5. The GaN HEMT and Si-CMOS monolithic integration method according to claim 1, wherein step S400 comprises,

step S401, forming N grooves and P grooves in different areas on a silicon substrate through ion implantation or diffusion technology;

step S402, performing shallow trench isolation to form an active region on the silicon substrate;

step S403, forming a gate on the silicon substrate;

in step S404, a source and a drain are formed by ion implantation.

6. The GaN HEMT and Si-CMOS monolithic integration method according to claim 5, further comprising, after step S404, step S405, forming a contact hole on said silicon substrate.

7. The GaN HEMT and Si-CMOS monolithic integration method according to claim 6, further comprising, after step S405,

step S406, forming a plurality of metal interconnection layers on the upper surface of the silicon substrate;

in step S407, bond pads and passivation layers are sequentially formed on the metal interconnection layers.

8. The GaN HEMT and Si-CMOS monolithic integration method according to claim 1, further comprising, before step S100, initializing said silicon substrate.

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of semiconductor processes, in particular to a GaN HEMT and Si-CMOS monolithic integration method.

[ background of the invention ]

Currently, a radio frequency power amplifier and a control chip thereof or a low noise amplifier and a control chip thereof are manufactured separately. Namely, the radio frequency power amplifier and its control chip or the low noise amplifier and its control chip are two independent chips. As described above, two independent chips need to be manufactured, packaged, tested and sold separately, so the product has a large volume, large loss and high cost.

[ summary of the invention ]

The invention aims to provide a GaN HEMT and Si-CMOS monolithic integration method.

In order to achieve the above object, the present invention provides a GaN HEMT and Si-CMOS monolithic integration method, comprising the steps of: step S100, epitaxially growing a GaN epitaxial layer structure on a silicon substrate; step S200, etching the GaN epitaxial layer structure to form a GaN HEMT device region and a Si-CMOS device region; step S300, preparing a GaN HEMT in the GaN HEMT device region; and S400, preparing the Si-CMOS in the Si-CMOS device area.

Preferably, the step S200 includes a step S201 of sequentially applying glue, aligning, exposing, and developing on a partial region of the GaN epitaxial layer structure to form a GaN epitaxial layer structure region covered with the photoresist and a GaN epitaxial layer structure region not covered with the photoresist; step S202, etching the GaN epitaxial layer structure region of the uncovered photoresist to form a Si-CMOS device region; and step S203, removing the photoresist, and cleaning the GaN epitaxial layer structure region covered with the photoresist to form a GaN HEMT device region.

Preferably, the step S300 includes a step S301 of forming a drain and a source on the surface of the GaN epitaxial layer structure; step S302, forming a grid on the surface of the GaN epitaxial layer structure; step S303, forming an inductor, a capacitor or a resistor on the surface of the GaN epitaxial layer structure; step S304, the drain electrode and the inductor, the capacitor or the resistor are interconnected through metal.

Preferably, step S300 further includes, after the metal interconnect, depositing a passivation layer over the GaN HEMT.

Preferably, step S400 includes step S401 of forming N and P trenches in different regions on a silicon substrate by ion implantation or diffusion techniques; step S402, performing shallow trench isolation to form an active region on the silicon substrate; step S403, forming a gate on the silicon substrate; in step S404, a source and a drain are formed by ion implantation.

Preferably, step S405 is further included after step S404, and a contact hole is formed on the silicon substrate.

Preferably, step S406 is further included after step S405, forming a plurality of metal interconnection layers on the upper surface of the silicon substrate; in step S407, bond pads and passivation layers are sequentially formed on the metal interconnection layers.

Preferably, step S100 is preceded by initializing the silicon substrate.

The invention has the beneficial effects that: the GaN HEMT and Si-CMOS monolithic integration method is characterized in that a GaN HEMT device region and a Si-CMOS device region are formed by etching a GaN epitaxial layer structure, so that the GaN HEMT and the Si-CMOS are prepared on the same substrate, the GaN HEMT and the Si-CMOS are integrated on the same chip, and the GaN HEMT and the Si-CMOS monolithic integration method is small in total chip area, excellent in performance and low in cost.

[ description of the drawings ]

FIG. 1 is a flow chart of a monolithic integration method according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of monolithic integration of a GaN HEMT and a Si-CMOS in accordance with an embodiment of the present invention;

FIG. 3 is a schematic diagram of a GaN HEMT and a Si-CMOS monolithically integrated chip according to an embodiment of the invention.

[ detailed description ] embodiments

The invention is further described with reference to the following figures and embodiments.

It should be noted that all directional indicators (such as upper, lower, left, right, front, back, inner, outer, top, bottom … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components in a specific posture (as shown in the figure), and if the specific posture is changed, the directional indicator is changed accordingly.

As shown in fig. 1, an embodiment of the present invention provides a GaN HEMT and Si-CMOS monolithic integration method, including the following steps:

step S100, epitaxially growing a GaN epitaxial layer structure on a silicon substrate;

step S200, etching the GaN epitaxial layer structure to form a GaN HEMT device region and a Si-CMOS device region;

step S300, preparing a GaN HEMT in the GaN HEMT device region;

and S400, preparing the Si-CMOS in the Si-CMOS device area.

The size of the silicon substrate wafer in this embodiment is 3-12 inches.

The step S300 and the step S400 may be interchanged, that is, a Si-CMOS device region is first prepared, and then a GaN HEMT is prepared in the GaN HEMT device region. Or alternatively, the step of preparing the GaN HEMT in the GaN HEMT device region and the step of preparing the Si-CMOS in the Si-CMOS device region are alternately implemented so as to improve the manufacturing efficiency of the monolithic integration.

According to the invention, the GaN HEMT device region and the Si-CMOS device region are formed by etching the GaN epitaxial layer structure, so that the GaN HEMT and the Si-CMOS are prepared on the same substrate, the GaN HEMT and the Si-CMOS are integrated on the same chip, and the GaN HEMT and the Si-CMOS are monolithically integrated, so that the total chip area is small, the performance is excellent and the cost is low.

In the embodiment of the invention, the step S200 of etching the GaN epitaxial layer structure to form the GaN HEMT device region and the Si-CMOS device region comprises,

step S201, sequentially gluing, aligning, exposing and developing partial areas of the GaN epitaxial layer structure to form a GaN epitaxial layer structure area covered with photoresist and a GaN epitaxial layer structure area not covered with photoresist;

step S202, etching the GaN epitaxial layer structure region of the uncovered photoresist to form a Si-CMOS device region;

and step S203, removing the photoresist, and cleaning the GaN epitaxial layer structure region covered with the photoresist to form a GaN HEMT device region.

As shown in fig. 2a, in the device structure formed after step S201, the GaN epitaxial layer structure 20 is formed on the silicon substrate 10, and a partial region of the GaN epitaxial layer structure 20 is covered with the photoresist 30. As shown in fig. 2b, in the device structure formed after step S202, the GaN epitaxial layer structure 20 is formed on a partial region of the silicon substrate 10, and the GaN epitaxial layer structure 20 is covered with the photoresist 30. As shown in fig. 2c, in the device structure formed after step S203, a partial region on the silicon substrate 10 is covered with the GaN epitaxial layer structure 20 to form a GaN HEMT device region, and a partial region on the silicon substrate 10 is not covered with the GaN epitaxial layer structure 20 to form a Si-CMOS device region.

In a preferred embodiment, the GaN epitaxial layer structure has a thickness of 1-5um, which varies from application to application. The GaN epitaxial layer structure sequentially comprises a nucleating layer, a transition layer, a channel layer, an isolating layer and a cap layer from the upper surface of a silicon substrate.

The nucleation layer (seed layer) is a nitride film, such as AlN, GaN or other materials, with a thickness of 1-10 nm. The nucleation layer is made by metal organic chemical deposition (MOCVD), and the temperature is controlled at 500-700 ℃ to provide a high-quality seed layer for the subsequent film growth.

The transition layer (buffer layer) is AlGaN or other materials such as InAlN and InAlGaN, and the thickness is 0.5-4 um. By gradually changing the components of the transition layer material, the lattice constant of the transition layer material is finally close to or equal to that of the aluminum nitride material, thereby achieving lattice adaptation and reducing or eliminating dislocation defects. The transition layer may also include a superlattice layer composed of compound semiconductors having different compositions, which are substituted with each other, to further reduce stress generated during the fabrication of the GaN epitaxial layer.

The channel layer is a non-doped GaN crystal thin film and the thickness of the channel layer is 0.2-2 um. The channel layer is formed by an MOCVD method.

The isolating layer is a thin layer of AlN with the thickness of 5-20A. The isolation layer is made by an MOCVD method so as to limit the upward movement of electrons and improve the density of the two-dimensional electronic device.

The barrier layer is made of AlGaN, AlN, InN, InGaN and other binary, ternary or quaternary nitrides with the thickness of 10-50 nm. The barrier layer is used to supply electrons to the channel layer.

The cap layer is n-type doped GaN and has a thickness of 2-10 nm. The cap layer is used for preventing the barrier layer from being oxidized and simultaneously reducing the resistance of the source and drain electrode ohmic contact.

In a preferred embodiment, a GaN HEMT is fabricated in a GaN HEMT device region, specifically including the steps of:

and S301, forming a drain electrode and a source electrode on the surface of the GaN epitaxial layer structure.

Specifically, the drain and the source can be directly fabricated on the surface of the GaN epitaxial layer structure, or a groove can be etched first. The drain and source electrodes are made of a combination of several metals alloyed by high temperature annealing to reduce resistance. The metal combination comprises Ti, Al, Ni and Au, and the metal combination is deposited on the GaN epitaxial layer structure layer by a metal evaporation or sputtering method; after annealing, a first passivation layer is prepared, which is a silicon nitride (Si3N4) passivation layer or a silicon oxide (SiO2) passivation layer.

Step S302, forming a grid on the surface of the GaN epitaxial layer structure.

Specifically, the first passivation layer of the gate sub-structure is etched, and then metal is formed on the GaN epitaxial layer structure. An insulating layer, such as aluminum oxide or silicon nitride, may also be formed between the gate and the GaN epitaxial layer structure to form a MIS (metal-junction insulator-semiconductor) structure. The shape of the gate may be rectangular, T-shaped or Y-shaped. The grid electrode is made of Ni, Au, Pt, Ti, Al and other metals, and is deposited on the GaN epitaxial layer structure layer by layer through a metal evaporation or sputtering method.

Step S303, forming an inductor, a capacitor or a resistor on the surface of the GaN epitaxial layer structure.

And forming an inductor, a capacitor or a resistor on the surface of the GaN epitaxial layer structure, namely forming a matching circuit of the GaN HEMT, thereby forming a radio frequency power amplifier or a low noise amplifier. The inductor is formed by winding a metal coil, the capacitor is an MIM (metal-insulating medium-metal) capacitor, and the Resistor is a Thin Film Resistor (Thin Film Resistor).

And step S304, metal interconnection is carried out between the source and the drain and the inductor, the capacitor or the resistor.

And the metal interconnections can be directly connected or connected through an air bridge so as to realize the metal interconnection of the radio frequency power amplifier or the low noise amplifier with the resistor, the capacitor and the inductor.

After the metal interconnection, step S304 is further included, depositing a second passivation layer over the GaN HEMT to protect the device. The second passivation layer may be silicon nitride, silicon oxide, or Polyimide resin (Polyimide) or benzocyclobutene (BCB).

The steps S301 to S305 are front surface processes for fabricating a GaN HEMT. Optionally, the manufacturing of the GaN HEMT further includes a back surface process, specifically including wafer bonding (bonding), grinding and thinning (grinding), polishing (polishing), Backside Via lithography and etching (Backside Via Photo and Etch), Backside Via metallization (Via metallization), Debonding (Debonding), and wafer cleaning.

In a preferred embodiment, the preparation of the Si-CMOS in the Si-CMOS device region specifically comprises the following steps:

step S401, forming N grooves and P grooves in different areas on a silicon substrate through ion implantation or diffusion technology;

step S402, performing shallow trench isolation to form an active region on the silicon substrate;

step S403, forming a gate on the silicon substrate;

in step S404, a source and a drain are formed by ion implantation.

Step S405, forming contact holes on the silicon substrate through photoetching and etching processes, wherein the contact holes are used for leading out the grid electrode, the source electrode and the drain electrode of the Si-CMOS.

Step S406, forming a plurality of metal interconnection layers on the upper surface of the silicon substrate;

in step S407, bond pads and passivation layers are sequentially formed on the metal interconnection layers.

As shown in fig. 3, a GaN HEMT and Si-CMOS monolithic integrated chip is fabricated according to a GaN HEMT and Si-CMOS monolithic integration method provided in an embodiment of the present invention.

In a preferred embodiment, step S100 is preceded by initializing the silicon substrate.

The embodiment of the invention provides a GaN HEMT and Si-CMOS monolithic integration method, wherein the GaN HEMT (a radio frequency power amplifier or a low noise amplifier) and the Si-CMOS are manufactured on the same chip, so that the integration level is reduced, the manufacturing cost is reduced, and the overall performance of a device is improved.

While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.