阅读说明：本技术 电平转换模块、驱动电路及控制芯片 (Level conversion module, drive circuit and control chip ) 是由 郭晋亮 沈玉菡 于 2021-04-06 设计创作，主要内容包括：本申请提供了一种电平转换模块、驱动电路、控制芯片和电子烟,其中该电平转换模块应用于控制芯片中的驱动电路,该电平转换模块包括：电平转换单元和信号发生单元；信号发生单元用于向电平转换单元输出控制信号；电平转换单元用于在第一时相时,通过第一电平转换子单元和第二电平转换子单元交替输出第三电平；也即是说,仅通过控制芯片内的电平转换单元,即可输出大于预设电平值的第三电平,降低了控制芯片外器件的数量,减小了控制芯片外部器件占用的面积,同时降低了成本。(The application provides a level shift module, drive circuit, control chip and electron cigarette, wherein the drive circuit in the control chip is applied to this level shift module, and this level shift module includes: a level conversion unit and a signal generation unit; the signal generating unit is used for outputting a control signal to the level conversion unit; the level conversion unit is used for outputting a third level alternately through the first level conversion subunit and the second level conversion subunit in a first time phase; that is to say, only through the level conversion unit in the control chip, the third level larger than the preset level value can be output, the number of devices outside the control chip is reduced, the area occupied by the devices outside the control chip is reduced, and meanwhile, the cost is reduced.)

1. A level conversion module, wherein the level conversion module is applied to a driving circuit in a control chip, and the level conversion module comprises: a level conversion unit and a signal generation unit; the level conversion unit comprises a first level conversion subunit and a second level conversion subunit; the first level conversion subunit is connected with the signal generation unit; the second level shift subunit is respectively connected with the signal generation unit and the first level shift subunit;

the signal generating unit is used for outputting a control signal to the level conversion unit, wherein the control signal comprises a first time phase; in the first time phase, the level of the control signal is a first level and a second level which alternate according to a first preset frequency; a level value of the first level is greater than a level value of the second level;

the level conversion unit is used for outputting a third level alternately through the first level conversion subunit and the second level conversion subunit in the first phase; the level value of the third level is greater than a preset level value.

2. The level shift module of claim 1, wherein the first level shift subunit comprises a capacitor C1; the second level shifting subunit comprises a capacitor C2;

the first level shifting subunit is configured to output the third level based on a first difference voltage across the C1 at the second level of the first phase; and storing electrical energy via said C1 at said first level of said first phase;

the second level shifting subunit is configured to output the third level based on a second difference voltage across the C2 at the first level of the first phase; and storing electrical energy via the C2 at the second level of the first phase.

3. The level shift module as claimed in claim 1, wherein the first level shift sub-unit further comprises PMOS transistor M1, NMOS transistor M2, PMOS transistor M3, and NMOS transistor M4;

the signal generating unit is respectively connected with the grid of the M1 and the grid of the M2;

the drain of the M3 is connected with the drain of the M4; the drain of the M1 is connected with the drain of the M2;

the source of the M3 is connected with the gate of an NMOS tube of the driving circuit, and the gate of the M3 and the gate of the M4 are connected with the second level shifting subunit; the source of the M4 is connected with an external power supply;

the source of the M1 is connected to the external power supply and the source of the M2 is grounded.

4. The level shift module of claim 1, wherein the second level shift sub-unit further comprises a PMOS transistor M5, a third NMOS transistor M6, a fourth PMOS transistor M7, a fourth NMOS transistor M8, and a first inverter;

the signal generating unit is respectively connected with the gate of the M7 and the gate of the M8 through the first inverter;

the drain of the M7 is connected with the drain of the M8; the drain of the M5 is connected with the drain of the M6;

the source of the M5 is connected with the gate of an NMOS tube of the driving circuit, and the gate of the M5 and the gate of the M6 are connected with the first level shifting subunit; the source of the M6 is connected with an external power supply;

the source of the M7 is connected to the external power supply and the source of the M8 is grounded.

5. The level shift module according to any of claims 1-4, wherein the control signal further comprises a second phase in which the level of the control signal is the second level;

the signal generating unit comprises a first input port, a second input port, an output port and an AND gate;

the first input port is configured to receive a clock signal, and input the clock signal to the and gate, where the level of the clock signal is the first level and the second level that alternate according to the first preset frequency;

the second input port is used for receiving a square wave signal and inputting the square wave signal into the and gate, and the level of the square wave signal is the first level and the second level which are alternated according to a second preset frequency;

and the and gate is used for performing and calculation on the clock signal and the square wave signal to obtain the control signal with the first time phase and the second time phase alternating according to the second preset frequency, and outputting the control signal to the level conversion unit through the output port.

6. The level shift module according to any one of claims 1 to 4, further comprising an inverting unit; the inverting unit comprises a second inverter, a PMOS tube M9 and an NMOS tube M10;

a second input port of the signal generating unit is connected with the gate of the M9 and the gate of the M10 through the second inverter, respectively;

the source of the M9 is connected with an external power supply, and the drain of the M9 is respectively connected with the source of the M4 and the source of the M6;

the source of the M10 is grounded, and the drain of the M10 is respectively connected with the source of the M4 and the source of the M6.

7. The level shift module according to any of claims 1-4, wherein the control signal is the first phase, the level shift module further comprising a capacitor C3;

the first end of the C3 is connected to the first level shift subunit and the second level shift subunit, respectively, and is connected to at least two modules to be input through a logic driving unit;

the logic driving unit is used for outputting the third level to a target module to be input connected with the at least two modules to be input according to a preset time sequence, and the target module to be input is determined by the preset time sequence;

the second end of the C3 is connected to an external power source.

8. The level shift module according to claim 7, wherein the logic driving unit comprises at least two logic driving modules, and each logic driving module is connected with the at least two modules to be input in a one-to-one correspondence manner;

the first end of the C3 is connected with a module to be input corresponding to the logic driving module through the logic driving module;

and each logic driving module is conducted according to the preset time sequence, and a target logic driving module in a conducting state in at least two logic driving modules is used for outputting the third level to the target module to be input, wherein the target module to be input corresponds to the target logic driving module.

9. A driving circuit, wherein the driving circuit comprises the level shift module as claimed in any one of claims 1 to 8 and an NMOS transistor.

10. A control chip, characterized in that the control chip comprises the driving circuit according to claim 9 and at least one load resistor.

Technical Field

The present disclosure relates to semiconductor technologies, and in particular, to a level shift module, a driving circuit, and a control chip.

Background

In some electronic products using a battery for power supply, a Metal-Oxide-Semiconductor (MOS) transistor is usually used as a part of a driving circuit of a load resistor in the electronic product, and is connected to other circuits as a control chip of the electronic product. The constant current of the load resistor can be ensured by utilizing the characteristic that the saturation conducting current of the MOS tube is constant. In a conventional driving circuit of a load resistor, a P-type Metal-Oxide-Semiconductor (PMOS) transistor is usually used as a part of the driving circuit that ensures a constant current on the load resistor.

However, the PMOS transistor has the problems of large on-resistance, slow speed and high price. An N-type Metal-Oxide-Semiconductor (NMOS) transistor may be used as a part of the driving circuit that ensures a constant current across the load resistor. However, the NMOS transistor can be turned on when the gate voltage is higher than the source voltage, and the conventional control chip cannot achieve the boosting function, and under the condition that the power supply is single, a plurality of power transistors, inductors and capacitors need to be arranged outside the control chip to form a boosting circuit, so that the gate voltage of the NMOS transistor is increased, and thus, more external devices of the control chip are required, and the occupied area is large.

Disclosure of Invention

The application provides a level conversion module, can reduce control chip external device quantity, reduces control chip external device area occupied.

In a first aspect, an embodiment of the present application provides a level shift module, where the level shift module is applied to a driving circuit in a control chip, and the level shift module includes:

a level conversion unit and a signal generation unit; the level conversion unit comprises a first level conversion subunit and a second level conversion subunit; the first level conversion subunit is connected with the signal generation unit; the second level conversion subunit is respectively connected with the signal generation unit and the first level conversion subunit;

the signal generating unit is used for outputting a control signal to the level conversion unit, and the control signal comprises a first time phase; in a first time phase, the level of the control signal is a first level and a second level which alternate according to a first preset frequency; the level value of the first level is greater than the level value of the second level;

the level conversion unit is used for alternately outputting a third level through the first level conversion subunit and the second level conversion subunit in a first time phase; the level value of the third level is greater than the preset level value.

In one embodiment, the first level shifting subunit includes a capacitor C1; the second level shifting subunit includes a capacitor C2; the first level conversion subunit is used for outputting a third level based on the first difference voltage at two ends of the C1 when the second level of the first time phase is in the second level; and storing electrical energy at a first level during a first phase via C1; the second level conversion subunit is used for outputting a third level based on a second difference voltage at two ends of the C2 when the first level of the first phase is higher than the first level; and stores electrical energy via C2 at a second level during the first phase.

In one embodiment, the first level shifter unit further includes a PMOS transistor M1, an NMOS transistor M2, a PMOS transistor M3, an NMOS transistor M4; the signal generating unit is respectively connected with the grid of M1 and the grid of M2; the drain of M3 is connected with the drain of M4, and the drain of M1 is connected with the drain of M2; the source of the M3 is connected with the gate of the NMOS tube of the driving circuit, and the gate of the M3 and the gate of the M4 are connected with the second level shifting subunit; the source of M4 is connected with an external power supply; the source of M1 is connected to an external power supply and the source of M2 is grounded.

In one embodiment, the second level shifter unit further includes a PMOS transistor M5, a third NMOS transistor M6, a fourth PMOS transistor M7, a fourth NMOS transistor M8, and a first inverter; the signal generating unit is respectively connected with the grid of M7 and the grid of M8 through a first inverter; the drain of M7 is connected with the drain of M8, and the drain of M6 of M5 is connected with the drain of M6; the source of the M5 is connected with the gate of the NMOS tube of the driving circuit, and the gate of the M5 and the gate of the M6 are connected with the first level shifting subunit; the source of M6 is connected with an external power supply; the source of M7 is connected to an external power supply and the source of M8 is grounded.

In one embodiment, the control signal further includes a second phase in which the level of the control signal is a second level; the signal generating unit comprises a first input port, a second input port, an output port and an AND gate; the first input port is used for receiving a clock signal and inputting the clock signal into the AND gate, and the level of the clock signal is a first level and a second level which alternate according to a first preset frequency; the second input port is used for receiving a square wave signal and inputting the square wave signal into the AND gate, and the level of the square wave signal is a first level and a second level which are alternated according to a second preset frequency; and the AND gate is used for performing AND calculation on the clock signal and the square wave signal to obtain a control signal with a first time phase and a second time phase alternating according to a second preset frequency, and outputting the control signal to the level conversion unit through the output port.

In one embodiment, the level shift module further includes an inverting unit; the inverting unit comprises a second inverter, a PMOS tube M9 and an NMOS tube M10; the second input port of the signal generating unit is respectively connected with the gate of M9 and the gate of M10 through a second inverter; the source of M9 is connected with an external power supply, and the drain of M9 is respectively connected with the source of M4 and the source of M6; the source of M10 is grounded, and the drain of M10 is connected to the source of M4 and the source of M6, respectively.

In one embodiment, the control signal is a first phase, and the level shift module further includes a capacitor C3; a first end of the C3 is connected with the first level shift subunit and the second level shift subunit respectively, and is connected with at least two modules to be input through the logic driving unit; the logic driving unit is used for outputting a third level to a target module to be input connected with at least two modules to be input according to a preset time sequence, and the target module to be input is determined by the preset time sequence; the second terminal of C3 is connected to an external power source.

In one embodiment, the logic driving unit comprises at least two logic driving modules, and each logic driving module corresponds to at least two modules to be input one by one; the first end of the C3 is connected with a module to be input corresponding to the logic driving module through the logic driving module; and each logic driving module is conducted according to a preset time sequence, and a target logic driving module in a conducting state in at least two logic driving modules is used for outputting a third level to a target module to be input, and the target module to be input corresponds to the target logic driving module.

In a second aspect, a driving circuit includes the level shift module and the NMOS transistor of the driving circuit described in the first aspect.

In a third aspect, a control chip comprises the driving circuit of the second aspect and at least one load resistor.

The level conversion module, the driving circuit and the control chip, wherein the level conversion module is applied to the driving circuit in the control chip, and the level conversion module comprises: a level conversion unit and a signal generation unit; the level conversion unit comprises a first level conversion subunit and a second level conversion subunit, wherein the first level conversion subunit is connected with the signal generation unit, and the second level conversion subunit is respectively connected with the signal generation unit and the first level conversion subunit; the signal generating unit is used for outputting a control signal to the level conversion unit, and the control signal comprises a first time phase; in a first time phase, the level of the control signal is a first level and a second level which alternate according to a first preset frequency; the level value of the first level is greater than the level value of the second level; the level conversion unit is used for outputting a third level alternately through the first level conversion subunit and the second level conversion subunit in a first time phase; the level value of the third level is greater than the preset level value, that is, the third level greater than the preset level value can be output only through the level conversion unit in the control chip, so that the situation that a plurality of power tubes, inductors and capacitors are arranged outside the control chip to form a boost circuit and output voltage is improved is avoided, particularly, under the situation that a drive circuit comprises an NMOS tube, a plurality of devices do not need to be arranged outside the control chip to improve the grid voltage of the NMOS tube, the number of devices outside the control chip is reduced, and the occupied area of the devices outside the control chip is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic application environment diagram of a level shift module provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a level shift module provided in another embodiment of the present application;

fig. 3 is a schematic structural diagram of a level shift module provided in another embodiment of the present application;

fig. 4 is a schematic structural diagram of a level shift module provided in another embodiment of the present application;

fig. 5 is a schematic structural diagram of a level shift module provided in another embodiment of the present application;

fig. 6 is a schematic structural diagram of a level shift module according to an embodiment of the present application.

Description of the reference numerals

10. A control chip; 100. A drive circuit;

110. a level conversion module; 120. An NMOS tube;

111. a level conversion unit; 1111. A first level shift subunit;

1112. a second level shift subunit; 11121, a first inverter;

112. a signal generating unit; 1121. A first input port;

1122. a second input port; 1123. An AND gate;

1124. an output port; 113. An inverting unit;

1131. a second inverter; 20. A power source;

200. a load resistance; 300. A logic driving unit;

310. a logic driving module; 400. And (5) inputting the module.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It is to be understood that the terms "first," "second," "third," "fourth," and the like (if any) in the embodiments of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

The level shift module provided in this embodiment may be applied to the application environment shown in fig. 1. The level shift module 110 is applied to the driving circuit 100 in the control chip 10, wherein the control chip 10 further includes a load resistor 200, the driving circuit 100 further includes an NMOS transistor 120, a gate of the NMOS transistor 120 is connected to the level shift template 110, a source of the NMOS transistor 120 is connected to the load resistor 200, and a drain of the NMOS transistor 120 is usually connected to the external power source 20, that is, the external power source 20 outputs a drain voltage to the drain of the NMOS transistor 120. When the gate voltage of the NMOS transistor 120 is greater than the drain voltage, the NMOS transistor 120 is turned on, and at this time, the saturation turn-on current of the NMOS transistor 120 is constant, so that the current flowing through the load resistor 200 is also constant, thereby ensuring that the power of the load resistor 200 is constant. It should be noted that the level conversion module provided in the embodiment of the present application may also be applied to other application environments where a high level needs to be provided, and is not limited to the application environment shown in fig. 1.

Fig. 2 is a schematic structural diagram of a level shift module in an embodiment of the present application, and as shown in fig. 2, the level shift module 110 is applied to the driving circuit 100 in the control chip 10, and the level shift module 110 includes: a level conversion unit 111 and a signal generation unit 112; the level shift unit 111 includes a first level shift subunit 1111 and a second level shift subunit 1112; the first level shift subunit 1111 signal generation unit 112 is connected; the second level shift sub-unit 1112 is connected to the signal generation unit 112 and the first level shift sub-unit 1111, respectively; the signal generating unit 112 is configured to output a control signal to the level converting unit 111, where the control signal includes a first time phase; in a first time phase, the level of the control signal is a first level and a second level which alternate according to a first preset frequency; the level value of the first level is greater than the level value of the second level; the level shift unit 111 is configured to alternately output a third level through the first level shift subunit 1111 and the second level shift subunit 1112 in the first time phase; the level value of the third level is greater than the preset level value.

The level conversion module 110 is applied to the driving circuit 100 in the control chip 10, and is configured to output a third level greater than the preset level value. In one possible scenario, the level shift module 110 may be used to provide a voltage to the gate of an NMOS transistor in the driving circuit. If the voltage output from the external power supply 20 to the drain of the NMOS transistor is VDD, the NMOS transistor is turned on when the level conversion module 110 outputs the third level to the gate of the NMOS transistor, where the level value is greater than the preset level value, that is, the voltage VDD output from the external power supply 20 to the drain of the NMOS transistor. At this time, since the saturation on-current of the NMOS transistor 120 is constant, the current flowing through the load resistor 200 connected to the source of the NMOS transistor 120 is also constant, and the power of the load resistor 200 is constant.

The level shift unit 111 includes a first level shift subunit 1111 and a second level shift subunit 1112, the first level shift subunit 1111 is connected to the gate of the NMOS transistor 120 of the driving circuit and the signal generation unit 112, respectively, and the second level shift subunit 1112 is connected to the gate of the NMOS transistor 120 of the driving circuit and the signal generation unit 112, respectively. The first level shifting sub-unit 1111 and the second level shifting sub-unit 1112 may alternately output a third level to the gate of the NMOS transistor 120 of the driving circuit when receiving the first signal output by the signal generating unit 112; and stopping outputting the third level when the second signal is in the first time phase. It should be noted that the first level shifting sub-unit 1111 and the second level shifting sub-unit 1112 may have the same structure or different structures, and the embodiment of the present application does not limit this.

The signal generating unit 112 is configured to output a control signal to the level converting unit 111, where the control signal includes a first time phase; wherein the phase is used to indicate a change of the control signal within a preset period, for example, a level value of the control signal within the preset period alternates between a first level and a second level, or a level value of the control signal within the preset period continues to be the first level. In a first time phase, the level of the control signal is a first level and a second level which alternate according to a first preset frequency; the level value of the first level is greater than the level value of the second level. The level value of the first level is greater than the level value of the second level, i.e. the control signal in the first phase may be regarded as a square wave signal, comprising a first level with a high level value and a second level with a lower level than the first level, i.e. a low level, e.g. the second level may be a 0 level.

The level conversion module is applied to a driving circuit in a control chip, and comprises: a level conversion unit and a signal generation unit; the level conversion unit comprises a first level conversion subunit and a second level conversion subunit, wherein the first level conversion subunit is connected with the signal generation unit, and the second level conversion subunit is respectively connected with the signal generation unit and the first level conversion subunit; the signal generating unit is used for outputting a control signal to the level conversion unit, and the control signal comprises a first time phase; in a first time phase, the level of the control signal is a first level and a second level which alternate according to a first preset frequency; the level value of the first level is greater than the level value of the second level; the level conversion unit is used for outputting a third level alternately through the first level conversion subunit and the second level conversion subunit in a first time phase; the level value of the third level is greater than the preset level value, that is, the third level greater than the preset level value can be output only through the level conversion unit in the control chip, so that the situation that a plurality of power tubes, inductors and capacitors are arranged outside the control chip to form a boost circuit and output voltage is improved is avoided, particularly, under the situation that a drive circuit comprises an NMOS tube, a plurality of devices do not need to be arranged outside the control chip to improve the grid voltage of the NMOS tube, the number of devices outside the control chip is reduced, and the occupied area of the devices outside the control chip is reduced.

Fig. 3 is a schematic structural diagram of a level shift module according to another embodiment of the present application, and as shown in fig. 3, the first level shift subunit 1111 includes a capacitor C1, the second level shift subunit 1112 includes a capacitor C2, and the first level shift subunit 1111 is configured to output a third level based on a first difference voltage across C1 when the first level is the second level of the first phase; and storing electrical energy at a first level during a first phase via C1; the second level shift subunit 1112 is configured to output a third level based on the second difference voltage across C2 at the first level of the first phase; and stores electrical energy via C2 at a second level during the first phase.

The first level shifting subunit 1111 is configured to output a third level when the second level is at the first phase; the second level shifting sub-unit 1112 is configured to output a third level at the first level of the first phase.

At a first level of the first phase, C1 in the first level shifting subunit 1111 stores electrical energy, such that a voltage difference exists across C1. Since the voltage across the capacitor cannot change suddenly, the first level conversion subunit 1111 may superimpose the first difference voltage on the voltage of the initial signal based on the first difference voltage across C1, so that the level value of the final output third level is greater than a preset level value, where the preset level is greater than or equal to the threshold voltage of the NMOS transistor to be driven. Likewise, when at the second level of the first phase, C2 in second level shifting subunit 1112 stores electrical energy such that a voltage difference exists across C2. Since the voltage across the capacitor cannot change suddenly, the second level shift subunit 1112 may superimpose the second difference voltage on the voltage of the output initial signal based on the second difference voltage across C2, so that the level value of the finally output third level is greater than the preset level value, and the NMOS transistor to be driven is turned on.

Optionally, the first level shifter unit 1111 further includes a PMOS transistor M1, an NMOS transistor M2, a PMOS transistor M3, and an NMOS transistor M4; the signal generating unit 112 is respectively connected with the grid of M1 and the grid of M2; the drain of M3 is connected with the drain of M4, and the drain of M1 is connected with the drain of M2; in one possible case, the first end of C1 in the first level shifting subunit 1111 is connected to the drain of M3 and the drain of M4, respectively; the second end of the C1 in the first level shifting subunit 1111 is connected to the drain of the M1 and the drain of the M2, respectively; the source of M3 is connected to the gate of NMOS transistor 120 of the driving circuit, the gate of M3 and the gate of M4 are connected to the second level shifter unit 1112, and the gate of M3 and the gate of M4 are connected to the second end of C2; the source of M4 is connected to external power supply 20, the source of M1 is connected to external power supply 20, and the source of M2 is grounded.

At the first level of the first phase, M2 and M4 are turned on, and the first level shifting subunit 1111 may be grounded through M2 via the second terminal of C1, and charge C1 via the high level of the source of M4, so that there is a voltage difference across C1. The source of M4 is connected to the external power source 20, and the source level of M4 is VDD, so the first difference voltage across C1 can be stabilized at VDD. When the second level of the first phase is on, M1 is on, M2 and M4 are off, the source of M1 is connected to the external power supply 20, the level value of the drain of M1 is the same as the level value VDD output by the external power supply 20, and the level value of the second terminal of C1 is VDD. The voltage across the capacitor cannot change abruptly, and when the second terminal of C1 is VDD, the first terminal of C1 has a level of 2 × VDD. At this time, M3 is turned on, and the level value of the third level output through the source of M3 is 2 × VDD.

Optionally, the second level shifter unit 1112 further includes a PMOS transistor M5, an NMOS transistor M6, a PMOS transistor M7, an NMOS transistor M8, and a first inverter 11121; the signal generating unit is respectively connected with the grid of M7 and the grid of M8 through a first inverter 11121; the drain of M7 is connected with the drain of M8, and the drain of M5 is connected with the drain of M6; in one possible case, the first end of C2 in the second level shift subunit 1112 is connected to the drain of M7 and the drain of M8, respectively; the second end of C2 in the second level shift subunit 1112 is connected to the drain of M5 and the drain of M6, respectively; the source of M5 is connected to the gate of the NMOS transistor of the driving circuit, the gate of M5 and the gate of M6 are connected to the first level shifter unit 1111, and in one possible case, the gate of M5 and the gate of M6 are connected to the first end of C1; the source of M6 is connected to the external power supply, the source of M7 is connected to the external power supply, and the source of M8 is grounded.

At the second level of the first time phase, the gates of M7 and M8 are at the high level through the first inverter 11121, M8 is turned on, the first end of C2 is grounded through M8, and the high level of the source of M6 charges C2, so that a voltage difference exists between the two ends of C2. The source of M6 is connected to an external power source, and if the source level of M6 is VDD, the second difference voltage across C2 can be stabilized at VDD. At the first level of the first phase, the gates of M7 and M8 are low, M7 is on, M6 and M8 are off, the source of M7 is connected to the external power supply 20, the drain of M7 has the same level value as the level value VDD outputted from the external power supply 20, and the level value of the first terminal of C2 is VDD by the first inverter 11121. The voltage across the capacitor cannot change abruptly, and when the first terminal of C2 is VDD, the level of the second terminal of C2 is 2 × VDD. At this time, M5 is turned on, and the level value of the third level output through the source of M5 is 2 × VDD.

In the level shift module, the first level shift subunit includes a capacitor C1; the second level shifting subunit includes a capacitor C2; the first level conversion subunit is used for outputting a third level based on the first difference voltage at two ends of the C1 when the second level of the first time phase is in the second level; and storing electrical energy at a first level during a first phase via C1; the second level conversion subunit is used for outputting a third level based on a second difference voltage at two ends of the C2 when the first level of the first phase is higher than the first level; and when the second level of the first time phase, the electric energy is stored through the C2, so that the first level conversion sub-unit and the second level conversion sub-unit in the control chip can alternately output a third level which is larger than a preset level value, a plurality of power tubes, inductors and capacitors are prevented from being arranged outside the control chip, a boost circuit is formed, the number of devices outside the control chip is reduced, and the occupied area of the devices outside the control chip is reduced.

Fig. 4 is a schematic structural diagram of a level shift module according to another embodiment of the present application, and as shown in fig. 4, the control signal further includes a second time phase, and in the second time phase, the level of the control signal is a second level, and the signal generating unit 112 includes a first input port 1121, a second input port 1122, an output port 1123, and an and gate 1124; the first input port 1121 is configured to receive a clock signal, and input the clock signal to the and gate 1124, where the level of the clock signal is a first level and a second level that alternate according to a first preset frequency; the second input port 1122 is configured to receive a square wave signal, and input the square wave signal to the and gate 1124, where the level of the square wave signal is a first level and a second level that alternate according to a second preset frequency; and gate 1124 is configured to and calculate the clock signal and the square wave signal to obtain a control signal with a first phase and a second phase alternating according to a second preset frequency, and output the control signal to level shifting unit 111 through output port 1123.

The signal generating unit 112 may receive the clock signal (CLK shown in fig. 4) through the first input port 1121, receive the square wave signal (DRV shown in fig. 4) through the second input port 1122, and perform and calculation on the clock signal and the square wave signal through the and gate 1123 to obtain a control signal (shown in fig. 4) in which the first time phase and the second time phase alternate according to the second preset frequency, and further output the control signal obtained by the calculation to the level converting unit 111 through the output port 1123. It should be noted that the first preset frequency and the second preset frequency may be the same or different, and the embodiment of the present application does not limit this.

Fig. 5 is a schematic structural diagram of a level shift module according to another embodiment of the present application, and as shown in fig. 5, the level shift template 110 further includes an inverting unit 113; the inverting unit 113 comprises a second inverter 1131, a PMOS transistor M9 and an NMOS transistor M10; the second input port 1122 of the signal generating unit 112 is connected to the gate of M9 and the gate of M10 through a second inverter 1131; the source of M9 is connected with the external power supply 20, and the drain of M9 is respectively connected with the source of M4 and the source of M6; the source of M10 is grounded, and the drain of M10 is connected to the source of M4 and the source of M6, respectively.

The second inverter 1131 may be used to convert a high level to a low level and convert a low level to a high level. The second input port 1122 of the signal generating unit 112 receives the square wave signal, and may input the received square wave signal to the gate of M9 and the gate of M10 through the second inverter 1131. When the voltage level is at the first level in the first phase, the signals input to the gate of M9 and the gate of M10 through the second inverter 1131 are at a low level, M9 is turned on, M10 is turned off, the source of M9 is connected to the external power supply 20, and the signals input to the source of M4 and the source of M6 are at a high level output by the external power supply 20, and thus can be used to charge C1 and C2.

In one embodiment, as shown in fig. 6, when the control signal is the first phase, the level shift module 110 further includes a capacitor C3; a first end of C3 is connected to first level shifting sub-unit 1111 and second level shifting sub-unit 1112, respectively; and is connected with at least two modules 400 to be input (taking NMOS transistor of driving circuit as an example) through the logic driving unit 300; the logic driving unit is used for outputting a third level to a target module to be input connected with at least two modules to be input according to a preset time sequence, and the target module to be input is determined by the preset time sequence; the second terminal of C3 is connected to an external power source.

When the control signal is the first phase, the level shift module 110 may be regarded as a power source for providing power, and therefore, C3 is added between the first level shift subunit 1111, the second level shift subunit 1112 and the at least two modules to be input 400, so that the first level shift subunit 1111, the second level shift subunit 1112 can provide a voltage-stabilized signal to the at least two modules to be input through C3. When the target time in the preset sequence is reached, the logic driving unit 300 may turn on the channels between the first level shifting sub-unit 1111, the second level shifting sub-unit 1112, and the corresponding to-be-input module 400, so as to output the third level to the corresponding to-be-input module 400. The logic driving unit 300 may include a plurality of logic driving modules, one logic driving module may correspond to a plurality of modules to be input, and one logic driving module may also correspond to one module to be input, which is not limited in this embodiment of the present application.

In a possible case, optionally, the logic driving unit 300 includes at least two logic driving modules 310, and each logic driving module 310 corresponds to at least two modules 400 to be input one to one; a first end of the C3 is connected to the module to be input 400 corresponding to the logic driving module 310 through the logic driving module 310; each logic driving module 310 is turned on according to a preset time sequence, and a target logic driving module in a conducting state in at least two logic driving modules 310 is configured to output a third level to a target module to be input, where the target module to be input corresponds to the target logic driving module.

The logic driving unit 300 includes at least two logic driving modules 310, and each logic driving module 310 corresponds to each to-be-input module of the at least two to-be-input modules 400 one by one, that is, each logic driving module 310 has one to-be-input module corresponding to it. A first end of the C3 is connected with the module to be input 400 corresponding to the logic driving module through the logic driving module 310; each logic driving module 310 is turned on according to a preset time sequence, and a target logic driving module in a conducting state in at least two logic driving modules 310 is configured to output a third level to a target module to be input corresponding to the target logic driving module. That is, when the target time in the preset timing arrives, the target logic driving module in the on state may enable the third level to be output to the target module to be input by turning on the channels between the first level shifting subunit 1111, the second level shifting subunit 1112, and the target module to be input.

In an embodiment, a driving circuit is further provided, where the driving circuit includes the level shift module and the NMOS transistor of the driving circuit described in the above embodiments. The level conversion module provides a third level which is greater than or equal to a preset level value of the threshold voltage of the NMOS tube in the driving circuit.

The implementation principle and the beneficial effect of the driving circuit are similar to those of the level conversion module, and are not described again here.

In one embodiment, a control chip is further provided, and the control chip comprises the driving circuit and at least one load resistor.

The implementation principle and the beneficial effect of the control chip are similar to those of the level conversion module, and are not described herein again.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.