阅读说明：本技术 一种辅助绕组检测方法及电路 (Auxiliary winding detection method and circuit ) 是由 於昌虎 曾正球 赵志伟 于 2021-02-26 设计创作，主要内容包括：本发明提供一种辅助绕组检测方法及电路,基于现有电路元件,不需额外代价,使辅助绕组钳位拓扑更实用,具体为：通过在励磁阶段将检测引脚钳位至供电电压,从而流入检测引脚的电流与输入电压成比例,实现输入电压准确检测；通过在消磁阶段使得供电电压和检测引脚电压的电压差落在一个内部电阻上,再将该电阻流过的电流转移到另一内部电阻上,利用采样保持电路将另一内部电阻上的电压采样保存下来,实现输出电压的准确检测；通过比较检测引脚电压与供电引脚电压的大小,实现主开关管漏极电压谐振周期的检测。基于输入电压可实现输入欠压保护、输入前馈、ZVS检测等；基于输出电压可实现输出过压保护、原边反馈；基于谐振周期检测可实现准谐振控制等。(The invention provides an auxiliary winding detection method and circuit, based on the existing circuit elements, no extra cost is needed, so that the clamping topology of the auxiliary winding is more practical, and the method specifically comprises the following steps: the detection pin is clamped to the power supply voltage in the excitation stage, so that the current flowing into the detection pin is proportional to the input voltage, and the input voltage is accurately detected; in the degaussing stage, the voltage difference between the power supply voltage and the voltage of the detection pin is caused to fall on one internal resistor, then the current flowing through the resistor is transferred to the other internal resistor, and the voltage on the other internal resistor is sampled and stored by using the sample-and-hold circuit, so that the accurate detection of the output voltage is realized; the detection of the drain voltage resonance period of the main switching tube is realized by comparing the voltage of the detection pin with the voltage of the power supply pin. Input under-voltage protection, input feedforward, ZVS detection and the like can be realized based on input voltage; output overvoltage protection and primary side feedback can be realized based on the output voltage; quasi-resonance control can be realized based on resonance period detection, and the like.)

1. An auxiliary winding detection method is used for an auxiliary winding clamping flyback converter, an auxiliary winding in the auxiliary winding clamping flyback converter is controlled through a main control chip, and the auxiliary winding detection method is characterized in that:

the main control chip is controlled to detect the voltage of a pin FA and a pin VDD thereof, so that the value proportion of the detected parameter is positioned at the detection end of the corresponding detection circuit;

the method specifically comprises an input voltage detection step, wherein in the excitation stage of the transformer, the clamp main control chip detects the voltage of a pin FA to the voltage value of a pin VDD, so that the input voltage falls on the detection end of an input voltage detection circuit in proportion.

2. An auxiliary winding detection method is used for an auxiliary winding clamping flyback converter, an auxiliary winding in the auxiliary winding clamping flyback converter is controlled through a main control chip, and the auxiliary winding detection method is characterized in that:

the main control chip is controlled to detect the voltage of a pin FA and a pin VDD thereof, so that the value proportion of the detected parameter is positioned at the detection end of the corresponding detection circuit;

the method specifically comprises an output voltage detection step, wherein in a degaussing stage of the transformer, a voltage difference between a voltage of a detection pin FA of a main control chip and a voltage of a pin VDD of the main control chip is controlled to fall on a resistor, the voltage difference is a proportional value of the output voltage, and then the voltage difference is transmitted to a detection end of an output voltage detection circuit.

3. The detection method according to claim 1 or 2, characterized in that: the method also comprises a resonance period detection step, wherein the resonance period of the voltage of the drain electrode of the main switching tube of the auxiliary winding clamping flyback converter is obtained by detecting the voltage of the detection pin FA of the main control chip and the voltage of the detection pin VDD of the main control chip and comparing the voltage of the detection pin FA and the voltage of the detection pin VDD of the main control chip.

4. The utility model provides an auxiliary winding detection circuit for auxiliary winding clamper flyback converter, auxiliary winding clamper flyback converter realizes work through main control chip, its characterized in that: comprises an upper divider resistor, a lower divider resistor and an input voltage detection circuit, wherein one end of the upper divider resistor is connected with the synonym end of the auxiliary winding, the other end of the upper divider resistor is connected with one end of the lower divider resistor, the other end of the lower divider resistor is connected with the homonymy end of the auxiliary winding, one end of the upper divider resistor and one end of the input voltage detection circuit are connected with a pin VDD of a main control chip, the other end of the upper divider resistor and the other end of the input voltage detection circuit are connected with a pin FA of,

the input voltage detection circuit is used for controlling the main control chip to detect the voltage of a pin FA and a pin VDD thereof, so that the value proportion of the input voltage of the detected parameter is positioned at the detection end of the input voltage detection circuit;

specifically, the voltage clamping circuit is used for clamping the voltage of a detection pin FA of a main control chip to the voltage of a pin VDD of the main control chip in the excitation stage of the transformer, so that the ratio of an input voltage value falls on a lower voltage-dividing resistor.

5. The detection circuit of claim 4, wherein: the input voltage detection circuit comprises a power input amplifier 407, a PMOS tube 408, a PMOS tube 410, an NMOS tube 409, an NMOS tube 411 and an NMOS tube 412, wherein the negative input end of the power input amplifier 407 and the source of the PMOS tube 410 are connected with a main control chip detection pin FA, the positive input end of the power input amplifier 407 and the source of the PMOS tube 408 are connected with a main control chip pin VDD, the output end of the power input amplifier 407 is connected with the grid of the PMOS tube 410 and the grid of the PMOS tube 408, the drain of the PMOS tube 408 is connected with the grid of the NMOS tube 409 and the drain of the NMOS tube 409, the grid of the NMOS tube 409 is connected with the drain of the NMOS tube 411 and the drain of the PMOS tube 410, the grid of the NMOS tube 411 is in short circuit with the drain of the NMOS tube and is connected with the grid of the NMOS tube 412, the sources of the NMOS tube 409, the NMOS tube 411 and the NMOS tube.

6. The utility model provides an auxiliary winding detection circuit for auxiliary winding clamper flyback converter, auxiliary winding clamper flyback converter realizes work through main control chip, its characterized in that: the device comprises an upper voltage-dividing resistor, a lower voltage-dividing resistor and an output voltage detection circuit, wherein one end of the upper voltage-dividing resistor is connected with a different name end of an auxiliary winding, the other end of the upper voltage-dividing resistor is connected with one end of the lower voltage-dividing resistor, the other end of the lower voltage-dividing resistor is connected with a same name end of the auxiliary winding, one end of the upper voltage-dividing resistor and one end of the output voltage detection circuit are connected with a pin VDD of a main control chip, and the other end of the upper voltage-dividing resistor;

the output voltage detection circuit is used for controlling the voltage of a detection pin FA and a pin VDD of the main control chip to enable the value proportion of the output voltage of the detected parameter to fall on the detection end of the output voltage detection circuit;

specifically, the voltage difference control circuit is used for controlling the voltage difference between the voltage of a detection pin FA of the main control chip and the voltage of a detection pin VDD of the main control chip to fall on a resistor in the demagnetization stage of the transformer, the voltage difference is a proportional value of the output voltage, and then the voltage difference is transmitted to the detection end of the output voltage detection circuit.

7. The detection circuit of claim 6, wherein: the output voltage detection circuit comprises a power input amplifier 413, a resistor 414, a PMOS tube 415, a resistor 416, a sampling switch 417 and a holding capacitor 418, wherein the positive input end of the power input amplifier 413 is connected with a main control chip detection pin FA, the negative input end of the power input amplifier 413 is connected with one end of the resistor 414 and the source electrode of the PMOS tube 415, the output end of the power input amplifier is connected with the gate electrode of the PMOS tube 415, the other end of the resistor 414 is connected with a main control chip pin VDD, the drain electrode of the PMOS tube 415 is connected with one end of the resistor 416 and one end of the sampling switch 417, the other end of the sampling switch 417 is connected with the upper electrode plate of the holding capacitor 418, the other end of the resistor 416 and the lower electrode plate of the holding capacitor 418.

8. The detection circuit according to any one of claims 4 to 7, wherein: the resonant period detection circuit is connected with a main control chip detection pin FA at one end, and is connected with a main control chip pin VDD at the other end for detecting the voltage of the main control chip detection pin FA and the pin VDD, comparing the voltage of the main control chip detection pin FA and the pin VDD, and outputting an auxiliary winding clamping flyback converter main switching tube drain voltage resonant period signal.

9. The detection circuit of claim 8, wherein: the resonant period detection circuit comprises an NPN triode 419, an NPN triode 420, a current limiting resistor 421, a current limiting resistor 422, an NMOS tube 423, an NMOS tube 424, an NMOS tube 425, an NMOS tube 426 and a current comparator 427, wherein the collector of the NPN triode 419 is connected with the base of the NPN triode 419, the collector of the NPN triode 420 and a main control chip pin VDD, the emitter of the NPN triode 419 is connected with one end of the current limiting resistor 421, the other end of the current limiting resistor 421 is connected with the grid of the NMOS tube 423, the drain of the NMOS tube 423 and the grid of the NMOS tube 424, the drain of the NMOS tube 424 is connected with the positive input end of the current comparator 427, the base of the NPN triode 420 is connected with a main control chip detection pin FA, the emitter of the NPN triode 420 is connected with one end of the current limiting resistor 422, the other end of the current limiting resistor 422 is connected with the grid of the NMOS tube 425, the drain of the NMOS, The sources of the NMOS 424, 425 and 426 are all grounded, and the output of the current comparator 427 outputs a resonant periodic signal ZCD.

Technical Field

The invention belongs to the field of soft switching flyback converters, and particularly relates to auxiliary winding voltage detection.

Background

An active clamp flyback converter is a power converter topology capable of realizing soft switching of a power tube. The inductance of the transformer excitation inductor is reasonably designed, so that the clamp tube is turned off after the conduction process is continued until enough negative excitation current appears, and the negative excitation current discharges charges at a Switch node because the inductance current cannot suddenly change, thereby realizing Zero-Voltage switching-on (ZVS) of the main Switch tube. Therefore, the switching loss of the main switching tube is eliminated, the overall efficiency of the converter is improved, and the development of high frequency and high power density of the converter is facilitated.

As shown in fig. 1, a circuit diagram of a typical active clamp flyback converter is shown. In the figure, 101 is a clamp capacitor, 102(LK) is a leakage inductor, 103 is a power transformer, 104(LM) is an excitation inductor, 105(MA) is a clamp tube, 106 is a main control chip, 107 is a half-bridge driving chip, 108(MP) is a main switching tube, 109 is an excitation inductor current sampling resistor, 110 is a power supply auxiliary winding of the main control chip, 111 is a rectifier diode for supplying power to the main control chip, 112 is a power supply capacitor of the main control chip, 113 is a rectifier diode for supplying power to the half-bridge driving chip, 114 is a power supply capacitor of the half-bridge driving chip, 115(R1) is an upper voltage dividing resistor of an auxiliary winding detection circuit, 116(R2) is a lower voltage dividing resistor of the detection circuit, VDD is a power supply pin of the main control chip, FA is a detection pin of the main control chip, 117 is a secondary side rectifier diode, and 118 is an output filter. Fig. 2 shows a waveform diagram of a key signal of a typical non-complementary mode active-clamped flyback converter. Wherein, GL is the grid drive voltage waveform of the main switch tube, GH is the grid drive voltage waveform of the clamp tube, VDS is the drain voltage waveform of the main switch tube, ILM is the excitation inductance current waveform, and ILK is the leakage inductance current waveform.

With reference to fig. 1 and 2, the working principle of the non-complementary active clamp flyback converter is understood, the clamp tube MA is turned on briefly in the resonance stage at the end of demagnetization, the driving signal GH changes to a high level (at time T1 in fig. 2), based on the circuit topology of fig. 1, the excitation inductor LM realizes negative excitation, that is, the inductive current ILM is a negative current, and the slope of the current is the difference value obtained by subtracting the input voltage from the voltage stored on the clamp capacitor 101 divided by the inductance of the excitation inductor LM; the clamp tube MA is turned on for a period of time until T2 in fig. 2, and is turned off, since the current of the excitation inductor LM cannot change suddenly, the negative current discharges the charge of the drain of the main switch tube MP, that is, the voltage VDS becomes close to 0V, the current of the excitation inductor LM increases gradually, and the slope is the input voltage divided by the inductance of the excitation inductor LM; before the current of the excitation inductor LM is corrected, namely after the clamping tube MA is turned off, the main switching tube of the next period is turned on (at the time of T3 in figure 2) at an interval of a dead time, at the moment, the main switching tube MP realizes zero-voltage turning on, and the turning-on loss is eliminated; after a period of time, when the forward exciting current of the exciting inductor LM reaches the current-limiting point of the entire converter control loop (at time T4 in fig. 2), the main switching tube MP is turned off, and PWM control is implemented. According to the above functions, in addition to the main control chip, a high-voltage side half-bridge driving chip is required to raise the driving level of the clamp tube MA to the voltage of the VDS to achieve effective driving of the clamp tube MA, and the maximum operating voltage of the drain and source of the clamp tube MA is the input voltage plus the reflected voltage of the secondary side of the converter, so that the clamp tube MA needs to use a high-voltage-withstanding transistor, which is expensive.

In view of the cost of active clamping, an auxiliary winding clamping technique is proposed, as shown in fig. 3, for the topology of an auxiliary winding clamping flyback converter. The active clamp branch in fig. 1 is replaced by a conventional RCD clamp, that is, a clamp capacitor 301, a bleeder resistor 302, and a clamp diode 303 in fig. 3, and the clamp tube MA is connected in series to an auxiliary winding for supplying power to the main control chip. Specifically, the clamping tube MA is connected to the low-voltage side of the auxiliary winding in series, so that the source electrode of the clamping tube MA is used as a reference ground, and the design of a driving circuit is greatly simplified; further, the maximum operating voltage of the clamp MA becomes the input voltage divided by the turns ratio (NP/NA) of the primary winding and the auxiliary winding of the transformer, so that a low-cost low-withstand voltage transistor can be used. Still referring to fig. 2, the working timing sequence of the clamp tube MA and the main switch tube MP may be switched on shortly after the demagnetization of the excitation inductor is finished, so that the power supply capacitor 308 of the auxiliary winding discharges briefly, and the excitation inductor LM realizes negative excitation according to the end of the same name. Similar to active clamping, as long as the negative current of the exciting inductor LM is sufficient, the zero-voltage turn-on of the main switching tube MP in the next period can be realized.

The auxiliary winding clamping mode of fig. 3 does not affect the normal power supply of the main control chip, but brings difficulty to the detection of important parameters: in FIG. 1, the rectifier diode 111 of the auxiliary winding power supply loop is auxiliaryOn the high-voltage side of the auxiliary winding, the voltage dividing resistors 115 and 116 of the detection circuit use the ground as a reference potential, and when the input voltage VIN is detected in the excitation stage, the anode voltage of the rectifier diode isThe input voltage can be converted into a current proportional to VIN by clamping the voltage division point of 115/116, namely the FA pin, to 0VWhen the output voltage is detected in the demagnetization stage, the voltage of the FA pin isWhen the VDS resonance stage detects the resonance period, only the time of the voltage zero crossing of the FA pin needs to be detected; however, in fig. 3, the clamp tube MA is connected in series to the low-voltage side of the auxiliary winding to block the dc path to the ground, so that the detection of the three important parameters cannot use the ground as the reference potential, and how to accurately detect the three important parameters becomes an important problem in the use process of the auxiliary winding clamp topology.

Disclosure of Invention

In view of the fact that there is no simple and practical input voltage, output voltage and resonant period detection circuit in the auxiliary winding clamping topology, the present invention aims to provide an accurate and novel input voltage, output voltage and resonant period detection method and circuit, which are based on the existing circuit elements and can realize the detection of the above parameters without extra cost, so that the auxiliary winding clamping topology is more practical. The functions of input under-voltage protection, input feedforward, ZVS detection and the like can be realized based on the detection of the input voltage; based on output voltage detection, functions of output overvoltage protection, primary side feedback and the like can be realized; functions such as quasi-resonance control can be realized based on resonance period detection.

The detection method provided by the invention is realized by the following scheme:

an auxiliary winding detection method is used for an auxiliary winding clamping flyback converter, an auxiliary winding in the auxiliary winding clamping flyback converter is controlled by a main control chip, and the voltage of a pin FA and the voltage of the pin VDD of the pin FA are detected by controlling the main control chip, so that the value proportion of a detected parameter is dropped at the detection end of a corresponding detection circuit; the method specifically comprises an input voltage detection step, wherein in the excitation stage of the transformer, the clamp main control chip detects the voltage of a pin FA to the voltage value of a pin VDD, so that the input voltage falls on the detection end of an input voltage detection circuit in proportion.

As another specific implementation of the detection method, the detection method specifically includes an output voltage detection step, in a degaussing stage of the transformer, the main control chip is controlled to detect that a voltage difference between a voltage at the pin FA and a voltage at the pin VDD thereof falls on a resistor, and the voltage difference is a proportional value of the output voltage and then is transmitted to the detection end of the output voltage detection circuit.

Preferably, the detection method further comprises a resonance period detection step, wherein the resonance period of the drain voltage of the main switching tube of the auxiliary winding clamping flyback converter is obtained by detecting the voltage of the detection pin FA of the main control chip and the voltage of the detection pin VDD of the main control chip and comparing the voltage of the detection pin FA and the voltage of the detection pin VDD of the main control chip.

The invention also provides an auxiliary winding detection circuit, which is used for an auxiliary winding clamping flyback converter, the auxiliary winding clamping flyback converter works through a main control chip and comprises an upper divider resistor, a lower divider resistor and an input voltage detection circuit, one end of the upper divider resistor is connected with the synonym end of the auxiliary winding, the other end of the upper divider resistor is connected with one end of the lower divider resistor, the other end of the lower divider resistor is connected with the synonym end of the auxiliary winding, one end of the upper divider resistor and one end of the input voltage detection circuit are connected with a pin VDD of the main control chip, the other end of the upper divider resistor and the other end of the input voltage detection circuit are connected with a pin FA of the main control chip, the input voltage detection circuit is used for controlling the voltage of the pin FA and the pin VDD of the main control chip, the value proportion of the input voltage of the measured parameter falls, and clamping the voltage of a detection pin FA of the main control chip to the voltage of a pin VDD of the main control chip, so that the input voltage value is proportionally dropped on the lower voltage-dividing resistor.

The specific implementation mode of the input voltage detection circuit comprises a power input amplifier 407, a PMOS tube 408, a PMOS tube 410, an NMOS tube 409, an NMOS tube 411 and an NMOS tube 412, wherein a negative input end of the power input amplifier 407 and a source electrode of the PMOS tube 410 are connected with a detection pin FA of a main control chip, a positive input end of the power input amplifier 407 and a source electrode of the PMOS tube 408 are connected with a pin VDD of the main control chip, an output end of the power input amplifier 407 is connected with a grid electrode of the PMOS tube 410 and a grid electrode of the PMOS tube 408, a drain electrode of the PMOS tube 408 is connected with a grid electrode of the PMOS tube 409 and a drain electrode of the NMOS tube 409, a grid electrode of the NMOS tube 409 is connected with a drain electrode of the NMOS tube 411 and a drain electrode of the PMOS tube 410, the grid electrode of the NMOS tube 411 is in short circuit with the drain electrode thereof and is connected with the grid electrode of the NMOS tube 412, the source electrodes of.

According to the detection method, the invention also provides an auxiliary winding detection circuit for an auxiliary winding clamping flyback converter, the auxiliary winding clamping flyback converter works through a main control chip, the auxiliary winding clamping flyback converter comprises an upper voltage-dividing resistor, a lower voltage-dividing resistor and an output voltage detection circuit, one end of the upper voltage-dividing resistor is connected with the synonym end of the auxiliary winding, the other end of the upper voltage-dividing resistor is connected with one end of the lower voltage-dividing resistor, the other end of the lower voltage-dividing resistor is connected with the synonym end of the auxiliary winding, one end of the upper voltage-dividing resistor and one end of the output voltage detection circuit are connected with a pin VDD of the main control chip, the other end of the upper voltage-dividing resistor and the other end of the output voltage detection circuit are connected with a pin FA of the main control chip, the output voltage detection circuit is used for controlling the pin FA, and the voltage difference between the FA voltage of the detection pin of the main control chip and the VDD voltage of the pin of the main control chip is controlled to fall on a resistor, is a proportional value of the output voltage, and is transmitted to the detection end of the output voltage detection circuit.

The output voltage detection circuit comprises a power input amplifier 413, a resistor 414, a PMOS tube 415, a resistor 416, a sampling switch 417 and a holding capacitor 418, wherein the positive input end of the power input amplifier 413 is connected with a main control chip detection pin FA, the negative input end of the power input amplifier 413 is connected with one end of the resistor 414 and the source electrode of the PMOS tube 415, the output end of the power input amplifier is connected with the grid electrode of the PMOS tube 415, the other end of the resistor 414 is connected with a main control chip pin VDD, the drain electrode of the PMOS tube 415 is connected with one end of the resistor 416 and one end of the sampling switch 417, the other end of the sampling switch 417 is connected with the upper plate of the holding capacitor 418, the other end of the resistor 416 and the lower plate of the holding capacitor 418 are grounded, and the upper plate.

Preferably, the detection circuit further comprises a resonance period detection circuit, one end of the resonance period detection circuit is connected with a main control chip detection pin FA, and the other end of the resonance period detection circuit is connected with a main control chip pin VDD and used for detecting the voltage of the main control chip detection pin FA and the pin VDD thereof, comparing the voltage of the main control chip detection pin FA and the pin VDD thereof, and outputting a resonance period signal of the drain voltage of the main switching tube of the auxiliary winding clamping flyback converter.

As an embodiment of the resonant period detection circuit, the resonant period detection circuit includes an NPN transistor 419, an NPN transistor 420, a current limiting resistor 421, a current limiting resistor 422, an NMOS transistor 423, an NMOS transistor 424, an NMOS transistor 425, an NMOS transistor 426, and a current comparator 427, wherein a collector of the NPN transistor 419 is connected to a base thereof, a collector of the NPN transistor 420, and a main control chip pin VDD, an emitter of the NPN transistor 419 is connected to one end of the current limiting resistor 421, another end of the current limiting resistor 421 is connected to a gate of the NMOS transistor 423, a drain of the NMOS transistor 423, and a gate of the NMOS transistor 424, a drain of the NMOS transistor 424 is connected to a positive input terminal of the current comparator 427, a base of the NPN transistor 420 is connected to a main control chip detection pin FA, an emitter of the NPN transistor 420 is connected to one end of the current limiting resistor 422, another end of the current limiting resistor 422 is connected to a gate of the NMOS transistor 425, a drain of the NMOS transistor 425, the sources of the NMOS 423, 424, 425 and 426 are all grounded, and the output of the current comparator 427 outputs a resonant periodic signal ZCD.

The invention has the beneficial effects that:

1. the method and the circuit are accurate and novel detection methods and circuits for input voltage, output voltage and resonance period based on the characteristics of auxiliary winding clamping topology;

2. accurate detection based on important parameters enables the clamping topology of the auxiliary winding to be simpler and more practical, realizes zero voltage switching-on of a main switching tube and facilitates high frequency and miniaturization of a converter;

3. the accurate detection based on important parameters realizes important functions of input under-voltage protection, feedforward, output over-voltage protection, primary side feedback, quasi-resonance control and the like of the converter.

Drawings

Fig. 1 is a circuit diagram of a typical active clamp flyback converter;

fig. 2 is a waveform diagram of key signals of a typical non-complementary active clamp flyback converter;

fig. 3 is a circuit diagram of an auxiliary winding clamp flyback converter;

FIG. 4 is a circuit diagram of an auxiliary winding voltage detection circuit according to an embodiment of the present invention;

FIG. 5 is a waveform diagram of a key signal of the detection circuit of the present invention;

fig. 6 is a waveform diagram of key signals of an auxiliary winding clamp converter to which the detection circuit of the present invention is applied.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to fig. 4 to 6. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in fig. 4, an embodiment of the auxiliary winding detection circuit of the present invention includes an upper voltage-dividing resistor 403, a lower voltage-dividing resistor 404, a power input amplifier 407, a PMOS transistor 408, a PMOS transistor 410, an NMOS transistor 409, an NMOS transistor 411, an NMOS transistor 412, a power input amplifier 413, a resistor 414, a PMOS transistor 415, a resistor 416, a sampling switch 417, a holding capacitor 418, a transistor 419, a transistor 420, a resistor 421, a resistor 422, an NMOS transistor 423, an NMOS transistor 424, an NMOS transistor 425, an NMOS transistor 426, and a current comparator 427.

The upper voltage-dividing resistor 403 and the lower voltage-dividing resistor 404 are connected in series across the two ends of the auxiliary winding, and are used for detecting the voltage difference across the auxiliary winding. The middle points of the upper and lower voltage dividing resistors are connected with a detection pin FA of the main control chip, and the high-voltage side of the auxiliary winding supplies power to a pin VDD of the main control chip through a decoupling capacitor 406.

The power input amplifier 407, the PMOS transistor 408, the PMOS transistor 410, the NMOS transistor 409, the NMOS transistor 411, and the NMOS transistor 412 form an input voltage detection circuit. The negative input end of the power input amplifier 407 is connected with a detection pin FA of the main control chip and the source electrode of the PMOS tube 410, the positive input end is connected with a pin VDD of the main control chip, and the output end of the power input amplifier 407 is connected with the grid electrode of the PMOS tube 410 and the grid electrode of the PMOS tube 408; the drain electrode of the PMOS tube 408 is connected with the grid electrode of the PMOS tube and the drain electrode of the NMOS tube 409, and the source electrode of the PMOS tube 408 is connected with a pin VDD of the main control chip; the grid electrode of the NMOS tube 409 is connected with the drain electrode of the NMOS tube 411, and the grid electrode of the NMOS tube 411 is in short circuit with the drain electrode thereof and is connected with the grid electrode of the NMOS tube 412; the drain of the NMOS transistor 411 is also connected to the drain of the PMOS transistor 410; the sources of the NMOS transistor 409, the NMOS transistor 411 and the NMOS transistor 412 are all grounded; the drain current of the NMOS transistor 412 is the detected current IVIN proportional to the input voltage.

The specific working process is as follows: during the transformer excitation phase, i.e., the TC phase in fig. 5, the voltage across the primary winding NP of the transformer 401 is VIN and the voltage coupled across the auxiliary winding is VINThe dotted terminal VA of the auxiliary winding, i.e. the drain voltage of the clamp 402, is:

if the detection pin FA of the main control chip is not processed, the voltage of the detection pin FA of the main control chip is as follows:

since the power input amplifier 407 and the PMOS transistor 410 form a negative feedback, when the voltage of the main control chip detection pin FA is higher than the voltage of the main control chip pin VDD, the gate of the PMOS transistor 410 is pulled low, thereby increasing the saturation current of the PMOS transistor 410 and decreasing the voltage of the main control chip detection pin FA. Then, the voltage of the main control chip detection pin FA is clamped to the voltage of the main control chip pin VDD, no current flows through the resistor R1, and the current flowing into the main control chip detection pin FA is:

the input terminals of the power input amplifier 407 are all high impedance, and it can be seen that no current flows, and the current flowing into the detection pin FA of the main control chip flows into the drain of the NMOS 411 through the PMOS 410. NMOS transistor 411 and NMOS transistor 412 form a current mirror, assuming that the current mirror ratio is 1: m, then the detected current proportional to the input voltage VIN is:

in fact, according to the voltage waveform of the dotted terminal VA of the auxiliary winding in fig. 5, the voltage of the dotted terminal VA of the auxiliary winding suddenly becomes high at the beginning of the excitation, and the feedback loop formed by the power input amplifier 407 and the PMOS transistor 410 takes time to respond, which causes the actually detected current IVIN to lag behind the change of the dotted terminal VA of the auxiliary winding. Here, the PMOS transistor 408 and the NMOS transistor 409 form another feedback loop to increase the response speed of the PMOS transistor 410. The current of the PMOS tube 410 is increased, so that the current of the NMOS tube 411 is increased, and the NMOS tube 409 and the PMOS tube 411 form a current mirror, so that the current of the NMOS tube 409 is increased; because the PMOS transistor 408 is connected as a diode, the gate-source voltage difference is increased, which causes the gate voltage of the PMOS transistor 410 to be pulled down rapidly, and increases the response speed of the PMOS transistor 410. In the TC phase of transformer excitation, shown in fig. 5, the master control chip detect pin FA voltage waveform (dashed line) is actually clamped to VDD.

The output voltage sampling circuit includes a power input amplifier 413, a resistor 414, a PMOS transistor 415, a resistor 416, a sampling switch 417, and a holding capacitor 418. The positive input end of the power input amplifier 413 is connected with a main control chip detection pin FA, the negative input end of the power input amplifier is connected with one end of a resistor 414 and the source electrode of a PMOS tube 415, the output end of the power input amplifier is connected with the grid electrode of the PMOS tube 415, the other end of the resistor 414 is connected with a main control chip pin VDD, the drain electrode of the PMOS tube 415 is connected with one end of a resistor 416 and one end of a sampling switch 417, the other end of the resistor 416 is grounded, the other end of the sampling switch 417 is connected with the upper plate of a holding capacitor 418, the lower plate of the holding capacitor 418 is grounded, and the voltage of the upper.

The specific working process is as follows: during the degaussing phase of the transformer, i.e. the TD phase in fig. 5, the voltage across the secondary winding of the transformer 401 is VOUT and the voltage coupled across the secondary winding is VOUTThe voltage of the main control chip detection pin FA is as follows:

because the power input amplifier 413 and the PMOS transistor 415 form negative feedback, the voltage of the main control chip detection pin FA is lower than the voltage of the main control chip pin VDD, the gate voltage of the PMOS transistor 415 is pulled low, the current of the PMOS transistor 415 is increased, the voltage drop on the resistor 414 is increased, and finally the voltages of the positive and negative input ends of the power input amplifier 413 are equal. The voltage difference thus dropped across resistor 414 is:

the current flowing through resistor 414 also flows through resistor 416, so the voltage drop across resistor 416 is:

the resistance value R of the resistor 414 may be set₄₁₄And resistance value R of resistor 416₄₁₆Equal, the voltage drop across the resistor 416 can be set entirely by the upper and lower divider resistors R1 and R2 at the periphery of the chip.

The sampling switch 417 is turned on during the degaussing phase of the transformer, and the voltage on the resistor 416 is sampled and stored in the holding capacitor 418, so as to obtain the output voltage proportional value VO _ SAMP of the direct current.

The resonant period detection circuit comprises an NPN triode 419, an NPN triode 420, a current limiting resistor 421, a current limiting resistor 422, an NMOS tube 423, an NMOS tube 424, an NMOS tube 425, an NMOS tube 426 and a current comparator 427. A collector of the NPN triode 419 is connected to a base of the NPN triode 419, a collector of the NPN triode 420 and a pin VDD of the main control chip, and an emitter of the NPN triode 419 is connected to one end of the current limiting resistor 421; the other end of the current limiting resistor 421 is connected with the gate of the NMOS transistor 423, the drain of the NMOS transistor 423 and the gate of the NMOS transistor 424, and the sources of the NMOS transistor 423 and the NMOS transistor 424 are grounded; the drain of the NMOS transistor 424 is connected to the positive input terminal of the current comparator 427; the base electrode of the NPN triode 420 is connected with a detection pin FA of the main control chip, and the emitter electrode of the NPN triode 420 is connected with one end of the current limiting resistor 422; the other end of the current limiting resistor 422 is connected with the grid electrode of the NMOS tube 425, the drain electrode of the NMOS tube 425 and the grid electrode of the NMOS tube 426, and the source electrodes of the NMOS tube 425 and the NMOS tube 426 are grounded; the drain of the NMOS transistor 426 is connected to the negative input terminal of the current comparator 427, and the current comparator 427 outputs the resonant period signal ZCD.

The specific working process is as follows: the base of the NPN triode 420 is connected to the voltage of the detection pin FA of the main control chip, and fig. 5 shows the TR resonance stage, where the voltage waveform of the detection pin FA of the main control chip is a sine wave with VDD as the center value, and the resonance period is the same as VA, that is, the resonance period of VDS. Therefore, the resonance period can be detected by comparing the voltage of the main control chip detection pin FA with the voltage of the main control chip pin VDD. The voltage drop of the pin VDD of the main control chip across the NPN transistor 419 across the resistor 421 is:

VDD-V_BE419-V_GS423

wherein, V_BE419Is the emitter junction voltage drop, V, of the NPN triode 419_GS423Is the gate-source voltage drop of the NMOS transistor 423. Assuming that the ratio of the current mirror formed by the NMOS transistor 423 and the NMOS transistor 424 is 1:1, the current flowing from the positive input terminal of the sampling switch 417 is:

assuming that the size of the NPN transistor 420 is the same as that of the NPN transistor 419, the resistance of the current limiting resistor 422 is the same as that of the current limiting resistor 421 (R421), the size of the NMOS transistor 425 is the same as that of the NMOS transistor 423, and the ratio of the current mirror formed by the NMOS transistor 425 and the NMOS transistor 426 is 1:1, when the voltage of the main control chip detection pin FA is greater than the voltage of the main control chip pin VDD, the current flowing out from the negative input terminal of the sampling switch 417 is greater than the current flowing out from the positive input terminal thereof, and the sampling switch 417 outputs a low level. Similarly, when the voltage of the main control chip detection pin FA is less than the voltage of the main control chip pin VDD, the sampling switch 417 outputs a high level.

A key signal waveform schematic of the entire auxiliary winding clamp converter is given in fig. 6. In the excitation stage of each switching period, namely in the stage that a main switching tube driving signal GL is at a high level, the voltage of a detection pin FA of the main control chip is clamped to the voltage of a pin VDD of the main control chip, and a current value IVIN proportional to an input voltage VIN is detected in the chip; the difference value of the voltage of a main control chip pin VDD and the voltage of a main control chip detection pin FA is reduced to the voltage with ground as reference potential, as shown by a dotted line on a coordinate axis of VO _ SAMP, in a degaussing stage, the reduced voltage is sampled and held, and a detection value proportional to the output voltage VOUT can be obtained; and in the resonance stage, the voltage of a main control chip detection pin FA is compared with the voltage of a main control chip pin VDD, and a resonance period signal ZCD is output.

It should be clear that the embodiments of the invention are not limited thereto, and that, in light of the above, there are other embodiments of the auxiliary winding voltage detection circuit of the invention according to the general technical knowledge and conventional means in the field without departing from the basic technical idea of the invention; therefore, the present invention may be modified, replaced or changed in various other ways, which fall within the scope of the appended claims.