阅读说明：本技术 一种可编程门阵列的数字光子相关器及光子测量系统 (Digital photon correlator of programmable gate array and photon measurement system ) 是由 韩鹏 徐炳权 邱健 彭力 骆开庆 刘冬梅 于 2020-12-31 设计创作，主要内容包括：本发明公开了一种可编程门阵列的数字光子相关器及光子测量系统,所述数字光子相关器包括：设置在FPGA芯片内部电路的系统同步运行模块、光子计算模块、相关运算模块和通讯控制模块；其中,所述系统同步运行模块分别与所述光子计算模块、所述相关运算模块以及所述通讯控制模块连接；所述光子计算模块、所述相关运算模块和所述通讯控制模块依次连接,所述光子计算模块与外部的光电倍增管连接,所述通讯控制模块与外部的终端连接。本发明可以充分利用了FPGA芯片的逻辑资源和了FPGA芯片内的存储器资源,充分发挥FPGA中逻辑资源和存储器资源各自的性能和优势,来提高FPGA硬件光子相关器的运算速度和运算的最大通道数。(The invention discloses a digital photon correlator of a programmable gate array and a photon measuring system, wherein the digital photon correlator comprises: the system synchronous operation module, the photon calculation module, the related operation module and the communication control module are arranged in an internal circuit of the FPGA chip; the system synchronous operation module is respectively connected with the photon calculation module, the correlation operation module and the communication control module; the photon calculation module, the correlation operation module and the communication control module are sequentially connected, the photon calculation module is connected with an external photomultiplier, and the communication control module is connected with an external terminal. The invention can fully utilize the logic resource of the FPGA chip and the memory resource in the FPGA chip, fully exert the respective performance and advantages of the logic resource and the memory resource in the FPGA, and improve the operation speed of the FPGA hardware photon correlator and the maximum number of operation channels.)

1. A digital photonic correlator for a programmable gate array, comprising: the system synchronous operation module, the photon calculation module, the related operation module and the communication control module are arranged in an internal circuit of the FPGA chip;

the system synchronous operation module is respectively connected with the photon calculation module, the correlation operation module and the communication control module;

the photon calculation module, the correlation operation module and the communication control module are sequentially connected, the photon calculation module is connected with an external photomultiplier, and the communication control module is connected with an external terminal;

the system synchronous operation module is used for controlling the photon calculation module, the correlation operation module and the communication control module to synchronously operate;

the photon calculation module is used for receiving pulse signals of an external photomultiplier, counting the pulse signals according to a preset time sequence and outputting the pulse signals to the correlation operation module, wherein the pulse signals comprise analog electric signals or TTL signals;

the correlation operation module is used for performing parallel and serial synchronous operation on the pulse signals by adopting a preset multiplier and an accumulator to generate and store operation data;

and the communication control module is used for receiving a control instruction of an external terminal and outputting the operation data of the related operation module to the external terminal.

2. The digital photon correlator for a programmable gate array of claim 1, wherein the correlation module comprises: the device comprises a correlation operation control unit, at least one parallel structure operation unit and at least one serial structure operation unit, wherein the correlation operation control unit is respectively connected with the at least one parallel structure operation unit and the at least one serial structure operation unit;

the related operation control unit is used for controlling the operation states of the at least one parallel structure operation unit and the at least one serial structure operation unit so as to enable the at least one parallel structure operation unit and the at least one serial structure operation unit to carry out synchronous operation;

the parallel structure operation unit is used for operating a preset high-speed channel and performing parallel operation by adopting a plurality of triggers, multipliers and accumulators preset by an FPGA (field programmable gate array), wherein the number of the high-speed channel is the number of the multipliers;

the serial structure operation unit is used for operating a preset low-speed channel and performing serial operation by adopting a memory and a digital multiplier preset by an FPGA (field programmable gate array), wherein the number of the low-speed channel is the capacity of the preset memory.

3. The digital photonic correlator of a programmable gate array of claim 2, wherein said serial configuration arithmetic unit comprises: the serial minimum delay time controller, the serial operation shift register and the serial operation multiply accumulator are connected in sequence;

the serial minimum delay time controller is used for setting a minimum delay time;

the serial operation shift register is used for carrying out shift register by controlling an internal memory of the FPGA;

the serial operation multiply-accumulate device is used for shift register based on an FPGA internal memory, and adopts a digital multiplier to carry out serial operation to obtain serial operation data.

4. The digital photonic correlator of a programmable gate array according to claim 3, wherein said parallel structure arithmetic unit comprises: the parallel minimum delay time controller, the parallel operation shift register, the parallel operation multiply accumulator and the parallel data-to-serial data buffer are connected in sequence;

the parallel minimum delay time controller is used for setting a minimum delay time;

the parallel operation shift register is used for taking the plurality of preset triggers as basic delay units and carrying out shift register by controlling the preset triggers;

the parallel operation multiply accumulator is used for carrying out parallel operation through the plurality of preset multipliers and the plurality of accumulators to obtain parallel operation data;

the parallel data-to-serial data buffer is used for acquiring the address of the preset memory, storing the parallel operation data into the preset memory according to the address of the preset memory so that the parallel operation data are converted into a serial format by the preset memory, and performing data integration on the parallel operation data converted into the serial format and the serial operation data.

5. The digital photon correlator of the programmable gate array of claim 4, wherein the correlation module further comprises: an address management unit connected to the at least one parallel structure operation unit and the at least one serial structure operation unit, respectively;

the address management unit is used for acquiring serial operation data of the at least one serial structure operation unit and inputting the serial operation data into the preset memory so that the preset memory performs data integration on the parallel operation data converted into the serial format and the serial operation data to form operation function information.

6. The digital photon correlator for a programmable gate array of claim 2, wherein the photon calculation module comprises: two counters;

and the two counters are connected with the correlation operation control unit.

7. A photonic measurement system, comprising: the device comprises a photomultiplier, an FPGA circuit and an external terminal;

the photomultiplier, the FPGA circuit and the external terminal are sequentially connected;

the FPGA circuit is provided with a digital photonic correlator of a programmable gate array as claimed in any one of claims 1 to 6.

Technical Field

The invention relates to the technical field of particle size measurement by photon correlation spectroscopy, in particular to a digital photon correlator of a programmable gate array and a photon measurement system.

Background

In the particle size measurement process, the information contained in the particles is obtained by measuring the similarity of the change of the scattered light intensity signal at different moments, in order to obtain the information in the particles, correlation operation needs to be carried out on the scattered light intensity signal, and the device mainly adopted at present is a photon correlator or a digital correlator.

In the measurement in the photon correlation spectroscopy field, a hardware photon correlator is a main measurement device, and most photon correlators are realized by means of an FPGA. At present, there are two implementation ways for the hardware photon correlator based on the FPGA: one is realized by a logic unit only based on the FPGA, and the other is realized by two resources, namely a memory and a logic unit based on the FPGA. The correlator based on the logic unit of the FPGA is called a traditional correlator, and the correlator realized by two resources, namely the memory based on the memory of the FPGA and the logic unit is called a memory type correlator.

The correlator with the memory structure is used, although the maximum synthesizable channel number is more, the delay time of channel calculation is long, and the measurement efficiency is low; although the conventional correlator has short calculation delay time, the number of channels is small, the measured photon capacity is small, and if the number of channels is increased to improve the measurement, the delay time is also increased, so that the measurement efficiency is reduced.

Disclosure of Invention

The invention provides a digital photon correlator of a programmable gate array, which can realize synchronous operation of a serial structure and a parallel structure, and reduce delay time while increasing an operation channel.

A first aspect of an embodiment of the present invention provides a digital photon correlator for a programmable gate array, including: the system synchronous operation module, the photon calculation module, the related operation module and the communication control module are arranged in an internal circuit of the FPGA chip;

the system synchronous operation module is respectively connected with the photon calculation module, the correlation operation module and the communication control module;

the photon calculation module, the correlation operation module and the communication control module are sequentially connected, the photon calculation module is connected with an external photomultiplier, and the communication control module is connected with an external terminal;

the system synchronous operation module is used for controlling the photon calculation module, the correlation operation module and the communication control module to synchronously operate;

the photon calculation module is used for receiving pulse signals of an external photomultiplier, counting the pulse signals according to a preset time sequence and outputting the pulse signals to the correlation operation module, wherein the pulse signals comprise analog electric signals or TTL signals;

the correlation operation module is used for performing parallel and serial synchronous operation on the pulse signals by adopting a preset multiplier and an accumulator to generate and store operation data;

and the communication control module is used for receiving a control instruction of an external terminal and outputting the operation data of the related operation module to the external terminal.

In a possible implementation manner of the first aspect, the correlation operation module includes: the device comprises a correlation operation control unit, at least one parallel structure operation unit and at least one serial structure operation unit, wherein the correlation operation control unit is respectively connected with the at least one parallel structure operation unit and the at least one serial structure operation unit;

the related operation control unit is used for controlling the operation states of the at least one parallel structure operation unit and the at least one serial structure operation unit so as to enable the at least one parallel structure operation unit and the at least one serial structure operation unit to carry out synchronous operation;

the parallel structure operation unit is used for operating a preset high-speed channel and performing parallel operation by adopting a plurality of triggers, multipliers and accumulators preset by an FPGA (field programmable gate array), wherein the number of the high-speed channel is the number of the multipliers;

the serial structure operation unit is used for operating a preset low-speed channel and performing serial operation by adopting a memory and a digital multiplier preset by an FPGA (field programmable gate array), wherein the number of the low-speed channel is the capacity of the preset memory.

In one possible implementation manner of the first aspect, the serial structure operation unit includes: the serial minimum delay time controller, the serial operation shift register and the serial operation multiply accumulator are connected in sequence;

the serial minimum delay time controller is used for setting a minimum delay time;

the serial operation shift register is used for carrying out shift register by controlling an internal memory of the FPGA;

the serial operation multiply-accumulate device is used for shift register based on an FPGA internal memory, and adopts a digital multiplier to carry out serial operation to obtain serial operation data.

In a possible implementation manner of the first aspect, the parallel structure operation unit includes: the parallel minimum delay time controller, the parallel operation shift register, the parallel operation multiply accumulator and the parallel data-to-serial data buffer are connected in sequence;

the parallel minimum delay time controller is used for setting a minimum delay time;

the parallel operation shift register is used for taking the plurality of preset triggers as basic delay units and carrying out shift register by controlling the preset triggers;

the parallel operation multiply accumulator is used for carrying out parallel operation through the plurality of preset multipliers and the plurality of accumulators to obtain parallel operation data;

the parallel data-to-serial data buffer is used for acquiring the address of the preset memory, storing the parallel operation data into the preset memory according to the address of the preset memory so that the parallel operation data are converted into a serial format by the preset memory, and performing data integration on the parallel operation data converted into the serial format and the serial operation data.

In a possible implementation manner of the first aspect, the correlation operation module further includes: an address management unit connected to the at least one parallel structure operation unit and the at least one serial structure operation unit, respectively;

the address management unit is used for acquiring serial operation data of the at least one serial structure operation unit and inputting the serial operation data into the preset memory so that the preset memory performs data integration on the parallel operation data converted into the serial format and the serial operation data to form operation function information.

In one possible implementation manner of the first aspect, the photon calculation module includes: two counters;

and the two counters are connected with the correlation operation control unit.

A second aspect of an embodiment of the present invention provides a photon measurement system, including: the device comprises a photomultiplier, an FPGA circuit and an external terminal;

the photomultiplier, the FPGA circuit and the external terminal are sequentially connected;

the FPGA circuit is provided with the digital photon correlator of the programmable gate array.

Compared with the prior art, the digital photon correlator and the photon measurement system of the programmable gate array provided by the embodiment of the invention have the beneficial effects that: the invention can fully utilize the logic resource of the FPGA chip and the memory resource in the FPGA chip, fully exert the respective performance and advantages of the logic resource and the memory resource in the FPGA, and improve the operation speed of the FPGA hardware photon correlator and the maximum number of operation channels.

Drawings

Fig. 1 is a schematic structural diagram of a digital photon correlator of a programmable gate array according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a system synchronization module according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a correlation operation module according to an embodiment of the present invention;

FIG. 4 is a hardware structure diagram of a serial structure arithmetic unit according to an embodiment of the present invention;

FIG. 5 is a hardware structure diagram of an arithmetic unit with parallel structure according to an embodiment of the present invention;

FIG. 6 is a circuit diagram for converting parallel data to serial data according to an embodiment of the present invention;

FIG. 7 is a state transition diagram for parallel to serial data according to an embodiment of the present invention;

FIG. 8 is a timing diagram of parallel to serial data conversion according to an embodiment of the present invention;

FIG. 9 is a hardware configuration diagram of a correlation calculation control unit according to an embodiment of the present invention;

FIG. 10 is a state transition diagram of a relational computation control unit according to an embodiment of the present invention;

FIG. 11 is a timing diagram of the correlation calculation control unit according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a photon measurement system according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The correlators commonly used at present are divided into two types, one type is the correlator based on the logic unit of the FPGA and is called a traditional correlator, and the other type is the correlator based on the memory of the FPGA and the correlator realized by two resources of the logic unit and is called a memory type correlator.

The correlator with the memory structure is used, although the maximum synthesizable channel number is more, the delay time of channel calculation is long, and the measurement efficiency is low; although the conventional correlator has short calculation delay time, the number of channels is small, the measured photon capacity is small, and if the number of channels is increased to improve the measurement, the delay time is also increased, so that the measurement efficiency is reduced.

In order to solve the above problem, the digital photonic correlator of the programmable gate array provided in the embodiments of the present application will be described and explained in detail by the following specific embodiments.

Referring to fig. 1, a schematic structural diagram of a digital photonic correlator of a programmable gate array according to an embodiment of the present invention is shown.

As an example, the digital photon correlator of the programmable gate array may include: the system comprises a system synchronous operation module 101, a photon calculation module 102, a correlation operation module 103 and a communication control module 104 which are arranged in an internal circuit of the FPGA chip.

The system synchronous operation module 101 may be respectively connected to the photon calculation module 102, the correlation operation module 103, and the communication control module 104, the photon calculation module 102, the correlation operation module 103, and the communication control module 104 are sequentially connected, the photon calculation module 102 may be connected to an external photomultiplier, and the communication control module 104 may be connected to an external terminal.

In a specific implementation, the system synchronous operation module 101, the photon calculation module 102, the correlation operation module 103 and the communication control module 104 may be fixed-line in an internal circuit of the FPGA chip, and each module and the FPGA chip are integrally arranged, so as to simplify the structure of the whole digital photon correlator.

The internal circuit of the FPGA chip may be provided with a trigger, an adder, a multiplier, an accumulator, a multiplier, a memory, and the like, and may be used by the system synchronous operation module 101, the photon calculation module 102, the correlation operation module 103, and the communication control module 104.

Referring to fig. 2, a circuit diagram of a system synchronous operation module according to an embodiment of the present invention is shown, where the system synchronous operation module may be configured to control the photon calculation module, the correlation operation module, and the communication control module to operate synchronously.

As shown in fig. 2, Syn _ ctrl is a system synchronization operation module solidified on an FPGA chip. Wherein ext _ clk is an external hardware input clock pulse, and ext _ rst is an external input reset signal. clk _100M is the multiplied 100M system clock, sys _ rst _ n is the system reset signal. The system synchronous operation module adopts asynchronous reset and synchronous release modes, and can realize the synchronous effect of resetting the digital photon correlator. The system synchronous operation module 101 can provide synchronous clocks for the photon calculation module 102, the correlation operation module 103 and the communication control module 104, so that the photon calculation module 102, the correlation operation module 103 and the communication control module 104 can be ensured to operate synchronously in front of and behind.

In this embodiment, the photon calculating module 102 is configured to receive a pulse signal of an external photomultiplier, count the pulse signal according to a preset timing, and output the pulse signal to the correlation operation module. Wherein the pulse signal may include: analog electrical signals or TTL signals.

Specifically, the photon calculation module comprises: the two counters are respectively a counter A and a counter B;

both counters may be connected to the correlation operation control unit. The two counters can respectively receive pulse signals sent by external photomultiplier tubes and then respectively send the pulse signals to the relevant operation control unit.

In this embodiment, the correlation operation module may be configured to perform parallel and serial synchronous operations on the pulse signal by using a multiplier and an accumulator inside an FPGA chip, and generate and store operation data.

Referring to fig. 3, a circuit diagram of a correlation operation module according to an embodiment of the present invention is shown. In one embodiment, the correlation operation module may include: the device comprises a correlation operation control unit, at least one parallel structure operation unit, at least one serial structure operation unit and an address manager. Wherein the correlation operation control unit is connected to the at least one parallel structure operation unit and the at least one serial structure operation unit, respectively, and the address manager may be connected to the at least one parallel structure operation unit and the at least one serial structure operation unit, respectively.

The related operation control unit is used for controlling the operation states of the at least one parallel structure operation unit and the at least one serial structure operation unit so as to enable the at least one parallel structure operation unit and the at least one serial structure operation unit to carry out synchronous operation.

The parallel structure operation unit is used for operating a preset high-speed channel, and performing parallel operation by adopting a plurality of triggers, multipliers and accumulators preset by the FPGA, wherein the number of the high-speed channels is the number of the multipliers.

The serial structure operation unit is used for operating a preset low-speed channel and performing serial operation by adopting a memory and a digital multiplier preset by an FPGA (field programmable gate array), wherein the number of the low-speed channel is the capacity of the preset memory.

The address management unit is used for acquiring serial operation data of the at least one serial structure operation unit and inputting the serial operation data into the preset memory so that the preset memory performs data integration on the parallel operation data converted into the serial format and the serial operation data to form operation function information.

Referring to fig. 3, in this embodiment, the correlation operation module may include a correlation operation control unit a, a parallel structure operation unit B, four serial structure operation units and an address manager G, where the four serial structure operation units are CDEF respectively.

When data are acquired, the address management unit can acquire the data according to the connection sequence of the parallel structure operation unit B and the four serial structure operation units CDEF, and then send the data to the memory for splicing the memory; or sending the data to a memory according to the time sequence of the acquired data, splicing the data by the memory, and finally sending the spliced data to an external device or terminal.

Referring to fig. 4, a hardware structure diagram of a serial structure arithmetic unit according to an embodiment of the present invention is shown. In one embodiment, the serial architecture arithmetic unit may be a correlator implemented based on both resources of the memory and logic units of the FPGA, wherein the serial architecture arithmetic unit may include a serial minimum delay time controller U5, a serial arithmetic shift register U6, and a serial arithmetic multiply accumulator U7. The serial minimum delay time controller U5, the serial operation shift register U6 and the serial operation multiply accumulator U7 are connected in sequence.

The serial minimum delay time controller can set the minimum delay time, so that the delay time of each device in operation can be set by changing the minimum delay time of the serial operation shift register.

The serial operation shift register can be used for carrying out shift register by controlling an internal memory of the FPGA, thereby realizing the shift register function by controlling the address register of the memory and reading and writing the address register.

The serial operation multiply-accumulator can be used for shift register based on an FPGA internal memory, and serial operation is carried out by adopting a digital multiplier to obtain serial operation data. The function of multiply-accumulator is realized by controlling the read-write of the address register of the memory and the memory thereof and matching with a digital multiplier. And the capacity of the internal memory of the FPGA is the number of the low-speed channels.

Referring to fig. 5 to 8, a hardware structure diagram of an arithmetic unit with a parallel structure according to an embodiment of the present invention, a circuit diagram of converting parallel data into serial data according to an embodiment of the present invention, a state transition diagram of converting parallel data into serial data according to an embodiment of the present invention, and a timing diagram of converting parallel data into serial data according to an embodiment of the present invention are respectively shown.

In this embodiment, the parallel structure operation unit may include: the parallel minimum delay time controller U1, the parallel operation shift register U2, the parallel operation multiply accumulator U3 and the parallel data-to-serial data buffer U4 are connected in sequence.

The parallel minimum delay time controller U1 can be used to set the minimum delay time, and specifically, the delay time of each device in operation can be set by changing the value of the parallel operation shift register. In order to improve the accuracy of the dynamic light scattering measurement particles, the delay time can be set as small as possible, and the measurement accuracy can be improved by increasing the operation speed of the front part during the test.

The parallel operation shift register U2 may be configured to use the preset flip-flops as basic delay units, and perform shift register by controlling the preset flip-flops, so that a shift register function may be implemented by controlling the flip-flops.

The parallel operation multiply accumulator U3 may be configured to perform parallel operation through the predetermined plurality of multipliers and the plurality of accumulators to obtain parallel operation data. The number of the multipliers is the number of the high-speed channels.

The parallel data to serial data buffer U4 may be configured to obtain an address of the preset memory, store the parallel operation data into the preset memory according to the preset memory address, so that the preset memory converts the parallel operation data into a serial format, and perform data integration on the parallel operation data converted into the serial format and the serial operation data.

The preset memory is the FPGA internal memory.

In practical operation, after the correlation control module completes the SACF _ run state, the parallel data to serial data buffer is started, and as shown in fig. 6, the correlation control module stores the parallel data generated by the parallel operation multiply accumulator into the parallel operation shift register for post-processing.

As shown in fig. 7, for the state transition diagram of parallel data to serial data, the respective state functions of the state transition diagram are as follows:

silde: an idle waiting state. And will jump to the corresponding state upon receipt of the signal.

Sclr: the data state is initialized. When the clear signal acf _ clr comes, all the buffers in the memory are cleared.

SLLC _ wr: parallel data pre-write state. When the llc _ wr signal arrives, the parallel data buffer is saved and is ready to be shift-split, and then the switch state is entered.

Swrite: the state is written. And sequentially writing the parallel data shift and split into the memory.

Sread: data read status. And when the ram _ read signal arrives, sending the data from the memory to the upper computer through the communication module.

As shown in fig. 8, the state machine is in the Sidle state by default (state is 0), when the llc _ wr signal arrives, the state machine first enters the SLLC _ wr state (state is 2), then enters the Swrite state (state is 3), the parallel structure arithmetic unit splits the data din _ llc from the low bit to the high bit and stores the data din _ llc in the corresponding address, and after the storage is finished, the state machine jumps back to the Sidle state (state is 0). When the ram _ read signal arrives, the state machine enters a Sread state (state is 4), and reads out data from the memory according to the addresses in sequence and outputs the data through an rd _ data interface. After the output is finished, the state machine sigle state (state ═ 0). The function of writing the parallel data of the parallel structure arithmetic unit into the memory for management is realized through state machine control.

After the memory receives the parallel data of the parallel structure operation unit, the parallel data of the parallel structure operation unit can be subjected to data conversion and converted into a serial format, and data splicing with subsequent serial data is facilitated.

Referring to fig. 9 to 11, a hardware structure diagram of the correlation operation control unit according to an embodiment of the present invention, a state transition diagram of the correlation operation control unit according to an embodiment of the present invention, and a timing chart of the correlation operation control unit according to an embodiment of the present invention are respectively shown.

As shown in fig. 9, the circuit diagram of the correlation operation control unit is a circuit diagram, and the correlation operation control unit can control the states of the parallel structure operation unit and the four serial structure operation units, so that each state of the parallel structure operation unit and each state of the four serial structure operation units can be performed synchronously, and the final operation output result can be ensured to be synchronous.

As shown in fig. 10, a state transition diagram of the correlation operation control unit is shown, and each state function of the state transition diagram is as follows:

silde: an idle waiting state. And will jump to the corresponding state upon receipt of the signal.

Sclr: the data state is initialized. When the clear signal acf _ clr comes, all the buffers in the memory are cleared.

SLLC _ wr: parallel data pre-write state. When the llc _ wr signal arrives, the parallel data buffer is saved and is ready to be shift-split, and then the switch state is entered.

Swrite: the state is written. And sequentially writing the parallel data shift and split into the memory.

Sread: data read status. And when the ram _ read signal arrives, sending the data from the memory to the upper computer through the communication module.

As shown in fig. 11, a timing chart of the correlation computation control unit is a state (state 0) of the state machine as a default. The upper level sends a control signal to the correlator, after decoding to obtain an acf _ start set signal, the state jumps to an SACF _ clr state (state is 1), and the state sends an acf _ clr pulse signal to all the multiply accumulator modules, so that the parallel structure operation unit and the serial structure operation unit clear the cache. After the buffer is cleared, the state machine jumps to the SACF _ run state (state 2), and keeps the acf _ run end in a high level state for a relevant time. In this state, the parallel structure arithmetic unit and the serial structure arithmetic unit perform multiply-accumulate operation, data of the parallel structure arithmetic unit is temporarily stored in the register, and data of the serial structure arithmetic unit is directly stored in the memory. After the correlation operation is completed, the state machine jumps to the SLLC _ wr state (state 3), transmits an llc _ wr pulse signal, and writes the parallel configuration operation unit into the memory. And after the data are stored, the state machine jumps to the SACF _ rd state, sends an acf _ read pulse signal, and outputs the data operated by the parallel structure operation unit and the serial structure operation unit from the memory through the communication control module.

The communication control module can be used for receiving a control instruction of an external terminal and outputting the operation data of the related operation module to the external terminal.

After the calculation result is the operation data (parallel data + serial data), the external device may send a control command to the communication control module, for example, an acquisition command, a reception command, and the like. The communication control module can respond to the control instruction, acquire the operation data from the memory and send the operation data to external equipment. The external device may be a terminal.

During measurement, the photon calculation module can be connected to the output end of a photon detector (such as a photomultiplier tube) and the communication control module can be connected to a computer.

The computer sends an instruction to the FPGA chip, the system synchronous operation module receives the instruction and controls the photon computation module, the related operation module and the communication control module to synchronously operate, the related operation control unit in the related operation module sets the minimum delay time in the parallel structure operation unit and the serial structure operation unit, clears an internal register and a memory cache, and starts to work.

The photon counting module counts photon pulse signals at equal intervals through a preset time sequence interval, and the result is sent to the relevant operation module.

In the correlation operation module, the serial minimum delay time control module and the parallel minimum delay time control module send a data to the subsequent shift register after completing the sampling of a light intensity signal. In the parallel structure arithmetic unit, the number of the delay units is N, so the shift register can simultaneously output N data to the next multiplication accumulator; the number of the multiply-accumulate devices is consistent with that of the shift registers, and only one period is needed for one multiply-accumulate operation to obtain the multiply-accumulate result. In the serial structure arithmetic unit, a shift register controls an internal memory, and data in the internal memory are sent to a lower-level multiply accumulator one by one; the multiplier-accumulator control multiplier carries out multiplication and accumulation operations on the memory inside the multiplier-accumulator and the sent data in sequence, and refreshes the memory inside the multiplier-accumulator. The above functions are repeatedly executed, and the multiply-accumulator register data or the memory data in the parallel structure arithmetic unit and the serial structure arithmetic unit are the related functions of the required signals.

And finally, the computer takes out the operated data from the register through the communication control module, and obtains a function corresponding to the operated data, a correlation curve of the function and a measuring function.

In this embodiment, an embodiment of the present invention provides a digital photon correlator for a programmable gate array, which has the following beneficial effects: the invention can fully utilize the logic resource of the FPGA chip and the memory resource in the FPGA chip, fully exert the respective performance and advantages of the logic resource and the memory resource in the FPGA, and improve the operation speed of the FPGA hardware photon correlator and the maximum number of operation channels.

An embodiment of the present invention further provides a photon measurement system, and referring to fig. 12, a schematic structural diagram of the photon measurement system provided in the embodiment of the present invention is shown.

Wherein, as an example, the photon measuring system may include:

the device comprises a photomultiplier, an FPGA circuit and an external terminal;

the photomultiplier, the FPGA circuit and the external terminal are sequentially connected;

the FPGA circuit is provided with a digital photonic correlator of a programmable gate array as described in the above embodiments.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.