Voltage sensor, chip and electronic equipment

文档序号：632232 发布日期：2021-05-11 浏览：8次中文

阅读说明：本技术 一种电压传感器、芯片和电子设备 (Voltage sensor, chip and electronic equipment ) 是由吴启明马鑫林晓志白蕊霞王仙芳于 2020-12-29 设计创作，主要内容包括：本文公开一种电压传感器、芯片和电子设备,本发明实施例电压传感器包括：第一电压产生电路、第二电压产生电路和模数转换电路(ADC)；其中,第一电压产生电路产生稳定的第一电压差,根据产生的第一电压差输出第一差分参考电压；第二电压产生电路产生第二差分参考电压；ADC接收待检测的输入电压,根据第一差分参考电压和第二差分参考电压计算输入电压的电压信息。本发明实施例通过电压产生电路,获得由稳定的第一电压差输出的第一差分参考电压和第二差分参考电压,可以得到用于确定输入电压大小的参考电压；因为不需要传统的带隙基准产生电路,避免了传统带隙基准电压的随机失调误差,因此,在降低芯片体积和功耗的情况下,保证了电压传感器的精度。(The invention discloses a voltage sensor, a chip and an electronic device, wherein the voltage sensor comprises: a first voltage generating circuit, a second voltage generating circuit and an analog-to-digital conversion circuit (ADC); the first voltage generating circuit generates a stable first voltage difference and outputs a first differential reference voltage according to the generated first voltage difference; the second voltage generating circuit generates a second differential reference voltage; the ADC receives an input voltage to be detected, and calculates voltage information of the input voltage according to the first differential reference voltage and the second differential reference voltage. According to the embodiment of the invention, the first differential reference voltage and the second differential reference voltage output by the stable first voltage difference are obtained through the voltage generating circuit, and the reference voltage for determining the size of the input voltage can be obtained; because a traditional band gap reference generating circuit is not needed, random offset errors of traditional band gap reference voltage are avoided, and therefore the precision of the voltage sensor is guaranteed under the condition of reducing the chip volume and the power consumption.)

1. A voltage sensor, comprising: the device comprises a first voltage generating circuit, a second voltage generating circuit and an analog-to-digital conversion circuit ADC; wherein the content of the first and second substances,

the first voltage generating circuit is configured to: generating a stable first voltage difference, and outputting a first differential reference voltage according to the generated first voltage difference;

the second voltage generating circuit is configured to: generating two paths of second voltage differences to form second differential reference voltages;

the ADC is connected with the first voltage generating circuit and the second voltage generating circuit and is set as follows:

and receiving the input voltage to be detected, and calculating the voltage information of the input voltage according to the first differential reference voltage and the second differential reference voltage.

2. The voltage sensor according to claim 1, further comprising a voltage buffer unit, wherein the voltage buffer unit is connected to an input voltage to be detected, and an output terminal of the voltage buffer unit is connected to an input terminal of the analog-to-digital conversion module, and is configured to:

and processing the input voltage gain into a voltage signal in the working range of the ADC.

3. The voltage sensor of claim 1, wherein the first voltage generation circuit comprises: a first current source and a first transistor generating a first current; wherein the content of the first and second substances,

the first current source is connected with an emitter of the first transistor, a base of the first current source is connected with a collector of the first transistor and is grounded, and the emitter and the collector are respectively connected with a first output node and a second output node; the first current flows through the first transistor, the first voltage difference is generated between the base electrode and the emitter electrode of the first transistor, and the first differential reference voltage is output by the first output node and the second output node; or the like, or, alternatively,

4. The voltage sensor of claim 1, wherein the second voltage generation circuit comprises: the clock driving unit, the first control switch, the second current source for providing M current, the second transistor and the third transistor are all second current; wherein the content of the first and second substances,

the clock driving unit is configured to: generating a clock driving control signal according to a preset clock reference signal;

the input end of the first control switch is connected with the second current source, the first output end is connected with the emitter of the second transistor and the first input end of the second control switch, the second output end is connected with the emitter of the third transistor and the second input end of the second control switch, and the arrangement is that: controlling P second currents of the M currents to flow into the second transistor and the rest (M-P) second currents to enter the third transistor according to the clock driving control signal; the base electrode of the second transistor is connected with the collector electrode and is grounded, and the base electrode of the third transistor is connected with the collector electrode and is grounded; the output end of the second control switch outputs the second differential reference voltage; or the like, or, alternatively,

the input end of the first control switch is connected with the second current source, the first output end is connected with the base electrode and the collector electrode of the second transistor and the first input end of the second control switch, the second output end is connected with the base electrode and the collector electrode of the third transistor and the second input end of the second control switch, and the setting is that: controlling P second currents of the M currents to flow into the second transistor and the rest (M-P) second currents to enter the third transistor according to the clock driving control signal; the emitter of the second transistor is grounded, and the emitter of the third transistor is grounded; the output end of the second control switch outputs the second differential reference voltage;

wherein M is more than or equal to 2, P is more than or equal to 1, and M is more than P.

5. The voltage sensor according to any one of claims 1 to 4, wherein the ADC includes an arithmetic operation unit, an integration unit, and a quantization unit; wherein the content of the first and second substances,

the arithmetic operation unit is configured to: switching in the input voltage; performing gain amplification on the second differential reference voltage; controlling and outputting the first differential reference voltage used for voltage calculation and the second differential reference voltage after gain amplification according to a control signal provided by a quantization unit; performing accumulation operation on the input voltage, the first differential reference voltage for voltage calculation which is controlled to be output and the second differential reference voltage after gain amplification to obtain an accumulation operation result;

the integration unit is arranged to: calculating the accumulated operation result obtained within a preset time length according to a preset integral operation rule to obtain an integral operation result;

the quantization unit is configured to: comparing the integral operation result with a preset integral comparison value, and generating the control signal according to the comparison result; and generating the voltage information according to the integral operation result.

6. The voltage sensor according to claim 5, wherein the arithmetic operation unit includes: a first multiplexer U1, a second multiplexer U2, a first accumulator U23, and a first gain amplifier U4; wherein the content of the first and second substances,

a first input end of the first multiplexer U1 is connected to the negative first differential reference voltage, a second input end is connected to the 0 v voltage, and a control end is connected to the quantization unit; the output end of the first multiplexer U1 is connected with the first input end of the first accumulator U23; the first multiplexer U1 is configured to: selectively outputting the first differential reference voltage and 0V voltage according to the control signal output by the quantization unit;

a first input end of the second multiplexer U2 is connected to the second differential reference voltage, an output end of the second multiplexer U2 is connected to an input end of the first gain amplifier U4, a second input end of the second multiplexer U4 is connected to 0 volt, and a control end of the second multiplexer U2 is connected to the quantization unit; the output end of the first gain amplifier U4 is connected with the second input end of the first accumulator U23; the second multiplexer U2 is configured to: the output of the first gain amplifier U4 and the voltage of 0 volt are selectively output according to the control signal output by the quantization unit;

the first accumulator U23 is set to: accumulating the output of the first multiplexer U1, the output of the second multiplexer U2 and the input voltage to obtain the accumulation operation result;

when the first differential reference voltage expression is V (vbep, vben), vbep is a positive terminal voltage of the first differential reference voltage, and vben is a negative terminal voltage of the first differential reference voltage; when the second differential reference voltage expression is V (dvbep, dvben), dvbep is a positive terminal voltage of the second differential reference voltage, and dvben is a negative terminal voltage of the second differential reference voltage.

7. The voltage sensor of claim 6, wherein the first accumulator U23 is configured to obtain the accumulation result by accumulating according to the following equation:

the accumulation operation result is V (vsp, vsn) -KAdc V (vbep, vben) -KAdc Kvbg V (dvbp, dvben);

wherein, K is_AdcRepresenting an operational coefficient corresponding to the control signal; the Kvbg is a gain amplification multiple of the second differential reference voltage.

8. The voltage sensor of claim 6, wherein the integration unit comprises a second accumulator U25 and an integrator Z^-1(ii) a The quantization unit includes: a first comparator U26, a first inverter U27, and a second inverter U28; wherein the content of the first and second substances,

the integrator Z^-1Performing integral operation on an output result of the first accumulator U23 in a preset time length, and feeding back an integral operation result obtained by the integral operation to the second accumulator U25;

the first input end of the second accumulator U25 is connected with the output end of the first accumulator U23, and the second input end is connected with the output end of the first accumulator U23Is connected with the integrator Z^-1Output terminal of the integrator Z^-1And the positive input of the first comparator U26;

the output of the second accumulator U25 to the first accumulator U23 and the integrator Z^-1The output of (2) is accumulated and calculated;

the positive input end of the first comparator U26 is connected with the output end of the integrating unit, and the negative input end is connected with a comparison reference signal A1;

an output end of the first comparator U26 is connected with an input end of the first inverter U27 and control ends of the first multiplexer U1 and the second multiplexer U2, and the first comparator U26 compares the magnitude between the integration operation result and a comparison reference signal A1 under the control of a multi-phase non-overlapping clock signal to output the control signal;

the output end of the first inverter U27 is connected with the input end of the second inverter U28, the first inverter U27 is used for outputting a control signal in an inverted mode to be an inverted control signal, and the second inverter U28 is used for outputting the inverted control signal in the inverted mode to be the voltage information.

9. The voltage sensor according to claim 5, wherein the arithmetic operation unit includes: two parallel operation branches with the same structure, each operation branch comprises: a third multiplexer U9, a fourth multiplexer U10, a third accumulator U211, and a second gain amplifier U12; wherein the content of the first and second substances,

a first of said operational branches: a first input end of the third multiplexer U9 is connected to a negative end of the first differential reference voltage, a second input end of the third multiplexer U9 is connected to a 0 v voltage, and a control end of the third multiplexer U9 is connected to the quantization unit; the output end of the third multiplexer U9 is connected to the first input end of the third accumulator U211; the third multiplexer U9 is configured to: selectively outputting the negative terminal voltage and 0V voltage of the first differential reference voltage according to the control signal output by the quantization unit;

a first input end of the fourth multiplexer U10 is connected to the positive terminal of the second differential reference voltage, an output end of the fourth multiplexer is connected to the input end of the second gain amplifier U12, a second input end of the fourth multiplexer is connected to 0 v voltage, and a control end of the fourth multiplexer is connected to the quantization unit; the output end of the second gain amplifier U12 is connected with the first input end of the third accumulator U211; the fourth multiplexer U10 is configured to: the output of the second gain amplifier U12 and the voltage of 0 volt are selectively output according to the control signal output by the quantization unit;

the third accumulator U211 is set to: accumulating the output of the third multiplexer U9, the output of the fourth multiplexer U10, and the positive terminal voltage of the input voltage to obtain an accumulated operation result of the operation branch;

in a second of said operational branches: a first input end of the third multiplexer U9 is connected to the positive terminal of the first differential reference voltage, a second input end of the third multiplexer U9 is connected to 0 v, and a control end of the third multiplexer U9 is connected to the quantization unit; the output end of the third multiplexer U9 is connected to the first input end of the third accumulator U211; the third multiplexer U9 is configured to: selectively outputting the positive end voltage and 0V voltage of the first differential reference voltage according to the control signal output by the quantization unit;

a first input end of the fourth multiplexer U10 is connected to a negative end of the second differential reference voltage, an output end of the fourth multiplexer U10 is connected to an input end of a second gain amplifier U12, a second input end of the fourth multiplexer U3578 is connected to 0 v voltage, and a control end of the fourth multiplexer U10 is connected to the quantization unit; the output end of the second gain amplifier U12 is connected with the first input end of the third accumulator U211; the fourth multiplexer U10 is configured to: the output of the second gain amplifier U12 and the voltage of 0 volt are selectively output according to the control signal output by the quantization unit;

the third accumulator U211 is set to: and accumulating the output of the third multiplexer U9, the output of the fourth multiplexer U10 and the negative terminal voltage of the input voltage to obtain an accumulation operation result of the operation branch.

10. The voltage sensor of claim 9, wherein the integration unit comprises: the device comprises a first offset control switch, an operational amplifier U213, a second offset control switch, a first integrating capacitor and a second integrating capacitor; wherein the content of the first and second substances,

the first input end of the first offset control switch is connected with the output end of the first operation branch of the arithmetic operation unit, the second input end of the first offset control switch is connected with the output end of the second operation branch of the arithmetic operation unit, the first output end of the first offset control switch is connected with the positive input end of the operational amplifier U213, the second output end of the first offset control switch is connected with the negative input end of the operational amplifier U213, the two output ends of the second offset control switch are respectively connected with the positive output end and the negative output end of the operational amplifier U213 and the two input ends of the quantization unit, the first integrating capacitor is connected between the first input end of the first offset control switch and the first output end of the second offset control switch, and the second integrating capacitor is connected between the second input end of the first offset control switch and the second output end of the second offset control switch, the control ends of the first offset control switch and the second offset control switch are both connected with preset offset control signals.

11. The voltage sensor of claim 10, wherein the quantization unit comprises: a second comparator U214, a third inverter U215, and a fourth inverter U216; wherein the content of the first and second substances,

a positive input end and a negative input end of the second comparator U214 are respectively connected with a first output end and a second output end of a second offset switch of the integrating unit;

the output end of the second comparator U214 is connected to the input end of the third inverter U215 and the control end of the third multiplexer U9, and the second comparator U214 compares the magnitude between the accumulated operation result of the two operation branches and the comparison reference signal a1 under the control of a multi-phase non-overlapping clock signal to output the control signal;

12. The voltage sensor of claim 5, wherein the quantization unit is further configured to: and outputting the associated clock signal of the voltage information according to the multiphase non-overlapping clock signal.

13. The voltage sensor according to claim 5, further comprising a filtering unit; wherein the filtering unit includes: the device comprises a low-pass filtering module, a gain amplifying module and an offset setting module; wherein the content of the first and second substances,

the low-pass filtering module is arranged to: carrying out mean value operation on the voltage information output by the quantization unit;

the gain amplification module is configured to: determining a gain relation between the voltage information of the mean value operation and the voltage magnitude;

the offset setting module is configured to: and setting an offset value for correcting the gain relation between the voltage information of the determined mean value operation and the voltage magnitude.

14. The voltage sensor of claim 5, further comprising a first clock unit configured to:

receiving a first clock input signal, providing the plurality of non-overlapping clock signals to an arithmetic operation unit according to the received first clock input signal, and providing the clock reference signal to a second voltage generation circuit.

15. The voltage sensor of claim 11, further comprising a second clock unit configured to:

receiving a second clock input signal, providing the plurality of non-overlapping clock signals and the offset control signal for the arithmetic operation unit according to the received second clock input signal, and providing the clock reference signal for the second voltage generation circuit.

16. A chip having integrated therein a voltage sensor according to any one of claims 1 to 15.

17. An electronic device, wherein the chip according to claim 17 is loaded and operated in the electronic device.

Technical Field

This document relates to, but is not limited to, sensor technology, and more particularly to a voltage sensor, a chip, and an electronic device.

Background

As chip manufacturing processes advance, chips are developed toward smaller sizes and lower power supply voltages. The thermal effect effects of the chip are gradually being brought up to the research routine. In order to avoid the adverse effect of the abnormal input voltage of the chip on the performance of the chip, a voltage sensor needs to be integrated inside the chip so as to monitor the input voltage of the chip in real time.

At present, a voltage sensor integrated inside a chip mainly generates a voltage reference through a bandgap reference circuit, and quantizes an input voltage through an analog-to-digital converter (ADC, or referred to as an a/D converter) to obtain voltage information representing a voltage magnitude, such as a junction Voltage (VBE) between a base (B) and an emitter (E) of a Bipolar Junction Transistor (BJT). The design based on the band-gap reference circuit increases the cost for chip design, occupies more chip area and increases the electric quantity consumption; random deviation exists in the manufacturing of the band gap reference circuit, so that a voltage sensor generates large errors and the measurement precision is influenced; for high precision applications, an extra reference voltage source outside the chip is required to replace the bandgap reference circuit, which will increase the cost.

With the popularization of the internet of things technology, the requirements of people on the sensor are further improved, and the voltage sensor with high precision, small size and low cost becomes an important requirement for monitoring the voltage of the chip.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

Embodiments of the present invention provide a voltage sensor, a chip, and an electronic device, which can reduce the volume of the voltage sensor and ensure the detection accuracy of the voltage sensor.

An embodiment of the present invention provides a voltage sensor, including: the device comprises a first voltage generating circuit, a second voltage generating circuit and an analog-to-digital conversion circuit ADC; wherein the content of the first and second substances,

the second voltage generating circuit is configured to: generating two paths of second voltage differences to form second differential reference voltages;

the ADC is connected with the first voltage generating circuit and the second voltage generating circuit and is set as follows:

In an exemplary embodiment, the voltage sensor further includes a voltage buffer unit, the voltage buffer unit is connected to the input voltage to be detected, and the output terminal of the voltage buffer unit is connected to the input terminal of the analog-to-digital conversion module, and is configured to:

and processing the input voltage gain into a voltage signal in the working range of the ADC.

In one illustrative example, the first voltage generating circuit includes: a first current source and a first transistor generating a first current; wherein the content of the first and second substances,

the first current source is connected with the base electrode and the collector electrode of the first transistor, the emitter electrode of the first current source is grounded, and the collector electrode and the emitter electrode of the first current source are respectively connected with a first output node and a second output node; the first current flows through the first transistor, the first voltage difference is generated between an emitter and a base of the first transistor, and the first differential reference voltage is output by the first output node and the second output node. 5. The voltage sensor of claim 1, wherein the second voltage generation circuit comprises: the clock driving unit, the first control switch, the second current source for providing M current, the second transistor and the third transistor are all second current; wherein the content of the first and second substances,

the clock driving unit is configured to: generating a clock driving control signal according to a preset clock reference signal;

wherein M is more than or equal to 2, P is more than or equal to 1, and M is more than P.

In one illustrative example, the ADC includes an arithmetic operation unit, an integration unit, and a quantization unit; wherein the content of the first and second substances,

In an illustrative example, the arithmetic operation unit includes: a first multiplexer U1, a second multiplexer U2, a first accumulator U23, and a first gain amplifier U4; wherein the content of the first and second substances,

the first accumulator U23 is set to: accumulating the output of the first multiplexer U1, the output of the second multiplexer U2 and the input voltage to obtain the accumulation operation result;

In one illustrative example, the first accumulator U23 is configured to obtain the accumulation operation result by accumulating the operation by the formula:

the accumulation operation result is V (vsp, vsn) -KAdc V (vbep, vben) -KAdc Kvbg V (dvbp, dvben);

wherein, K is_AdcRepresenting an operational coefficient corresponding to the control signal; the Kvbg is a gain amplification multiple of the second differential reference voltage.

In one illustrative example, the integration unit includes a second accumulator U25 and an integrator Z^-1(ii) a The quantization unit includes: a first comparator U26, a first inverter U27, and a second inverter U28; wherein the content of the first and second substances,

a first input of the second accumulator U25 is connected to the output of the first accumulator U23, and a second input is connected to the integrator Z^-1Output terminal of the integrator Z^-1And the positive input of the first comparator U26;

the output of the second accumulator U25 to the first accumulator U23 and the integrator Z^-1The output of (2) is accumulated and calculated;

the positive input end of the first comparator U26 is connected with the output end of the integrating unit, and the negative input end is connected with a comparison reference signal A1;

In an illustrative example, the arithmetic operation unit includes: two parallel operation branches with the same structure, each operation branch comprises: a third multiplexer U9, a fourth multiplexer U10, a third accumulator U211, and a second gain amplifier U12; wherein the content of the first and second substances,

In one illustrative example, the integration unit includes: the device comprises a first offset control switch, an operational amplifier U213, a second offset control switch, a first integrating capacitor and a second integrating capacitor; wherein the content of the first and second substances,

In one illustrative example, the quantization unit includes: a second comparator U214, a third inverter U215, and a fourth inverter U216; wherein the content of the first and second substances,

In an illustrative example, the quantization unit is further configured to: and outputting the associated clock signal of the voltage information according to the multiphase non-overlapping clock signal.

In an exemplary instance, the voltage sensor further includes a filtering unit; wherein the filtering unit includes: the device comprises a low-pass filtering module, a gain amplifying module and an offset setting module; wherein the content of the first and second substances,

the low-pass filtering module is arranged to: carrying out mean value operation on the voltage information output by the quantization unit;

the gain amplification module is configured to: determining a gain relation between the voltage information of the mean value operation and the voltage magnitude;

In one illustrative example, the voltage sensor further comprises a first clock unit configured to:

In an exemplary embodiment, the voltage sensor further comprises a second clock unit configured to:

On the other hand, an embodiment of the present invention further provides an electronic device, where the chip is loaded and operated in the electronic device.

The voltage sensor of the embodiment of the invention comprises: a first voltage generating circuit, a second voltage generating circuit and an analog-to-digital conversion circuit (ADC); the first voltage generating circuit generates a stable first voltage difference and outputs a first differential reference voltage according to the generated first voltage difference; the second voltage generating circuit generates a second differential reference voltage; the ADC receives an input voltage to be detected, and calculates voltage information of the input voltage according to the first differential reference voltage and the second differential reference voltage. According to the embodiment of the invention, the first differential reference voltage and the second differential reference voltage output by the stable first voltage difference are obtained through the voltage generating circuit, and the reference voltage for determining the size of the input voltage can be obtained; because a traditional band gap reference generating circuit is not needed, random offset errors of traditional band gap reference voltage are avoided, and therefore the precision of the voltage sensor is guaranteed under the condition of reducing the chip volume and the power consumption.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is a block diagram of a voltage sensor according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a voltage buffer unit according to an embodiment of the present invention;

FIG. 3 is a diagram of a first voltage generation circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a first voltage generating circuit according to another embodiment of the present invention;

FIG. 5 is a diagram illustrating a second voltage generation circuit according to an embodiment of the present invention;

FIG. 6 is a diagram of another second voltage generation circuit according to another embodiment of the present invention;

FIG. 7 is a diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a relationship between voltage information and voltage according to an embodiment of the present invention;

FIG. 9 is a diagram of an alternative analog-to-digital conversion circuit according to another embodiment of the present invention;

FIG. 10 is a diagram illustrating a filtering unit according to an embodiment of the present invention;

FIG. 11 is a diagram illustrating a multi-phase non-overlapping clock signal according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Fig. 1 is a block diagram of a voltage sensor according to an embodiment of the present invention, as shown in fig. 1, including: a first voltage generating circuit, a second voltage generating circuit and an analog-to-digital conversion circuit (ADC); wherein the content of the first and second substances,

the second voltage generating circuit is configured to: generating two paths of second voltage differences to form second differential reference voltages;

the ADC is connected with the first voltage generating circuit and the second voltage generating circuit and is set as follows:

In an exemplary embodiment, the first voltage generation circuit and/or the second voltage generation circuit may be integrated in the same chip.

In an exemplary embodiment, the mismatch ratio is in accordance with a gaussian distribution according to the second differential reference voltage outputted by the two or more second voltage differences.

In an exemplary embodiment, the voltage sensor in the embodiment of the present invention further includes a voltage buffer unit, the voltage buffer unit is connected to the voltage buffer unit and connected to the input voltage to be detected, and the output terminal is connected to the input terminal of the analog-to-digital conversion module, and is configured to:

the input voltage gain is processed into a voltage signal within the operating range of the ADC.

In an exemplary embodiment, the voltage buffer unit according to the embodiment of the present invention may be integrated within a chip.

The embodiment of the invention assumes that Voltage _ senp and Voltage _ senn are a positive input end and a negative input end of the input Voltage to be detected. The two differential input voltages pass through a voltage buffer unit to obtain vsp and vsn. vsp and vsn are voltage signals suitable for the operating range of the ADC. In an exemplary embodiment, the input voltage may be gain-processed by a voltage buffer unit including a gain amplifier. Fig. 2 is a schematic diagram of a Voltage buffer unit according to an embodiment of the invention, and as shown in fig. 2, Voltage _ sensp and Voltage _ senn are input voltages to be detected, and are subjected to gain amplification by a gain amplifier in the Voltage buffer unit to obtain vsp and vsn, which are Voltage signals suitable for an ADC operating range.

In an illustrative example, a first voltage generation circuit according to an embodiment of the present invention includes: a first current source and a first transistor generating a first current; wherein the content of the first and second substances,

an emitter electrode of the first transistor is connected with a first current source, a base electrode of the first transistor is connected with a collector electrode and grounded, and the emitter electrode and the collector electrode are respectively connected with a first output node and a second output node; a first current flows through the first transistor, a reference voltage is generated at the base electrode and the emitter electrode of the first transistor, and a first differential reference voltage is output through the first output node and the second output node; alternatively, the first and second electrodes may be,

the base electrode of the first current source and the first transistor is connected with the collector electrode, the emitter electrode of the first current source is grounded, and the collector electrode and the emitter electrode of the first current source are respectively connected with the first output node and the second output node; the first current flows through the first transistor, a first voltage difference is generated between an emitter and a base of the first transistor, and the first differential reference voltage is output by the first output node and the second output node.

In an exemplary embodiment, the first voltage generating circuit of the embodiment of the invention further includes a first capacitor connected across the first output node and the second output node.

Fig. 3 is a schematic diagram of a first voltage generating circuit according to an embodiment of the invention, and as shown in fig. 3, the first voltage generating circuit includes: the first current source Ibias0, the first transistor Q0 and the first capacitor C0, the first current source Ibias0 is connected with the emitter of the first transistor Q0 and one end of the first capacitor C0 to form a first output node NA, and the base of the first transistor Q0 is connected with the collector of the first transistor Q0 and the other end of the first capacitor C0 to ground to form a second output node NB. The first current source Ibias0 provides a first current to the first transistor Q0, the first current passes through a base-emitter junction (i.e. BE junction) of the first transistor Q0 to generate a first differential reference voltage, the first differential reference voltage comprises two paths of reference voltages of a reference voltage vbep output by a positive terminal and a reference voltage vben output by a negative terminal, and the voltage difference between the two paths of reference voltages vbep and vben is a base-emitter junction voltage VBE of the transistor Q0; since the capacitor C0 is connected across the first output node NA and the second output node NB, the voltage difference VBE between the first differential reference voltages vbep and vben can be stabilized; embodiments of the present invention represent the first differential reference voltage as V (vbep, vben).

Fig. 4 is a schematic diagram of another first voltage generating circuit according to an embodiment of the invention, as shown in fig. 4, the first voltage generating circuit includes: a first current source Ibias0, a first transistor Q0 and a first capacitor C0, wherein the first current source Ibias0 is connected with the base and the collector of the first transistor Q0, the emitter is grounded, and the collector and the emitter are respectively connected with the first output node NA and the second output node NB.

In an illustrative example, a second voltage generation circuit according to an embodiment of the present invention includes: the clock driving unit, the first control switch, the second current source for providing M current, the second transistor and the third transistor are all second current; wherein the content of the first and second substances,

the clock driving unit is configured to: generating a clock driving control signal according to a preset clock reference signal;

the input end of the first control switch is connected with the second current source, the first output end of the first control switch is connected with the emitter of the second transistor and the first input end of the second control switch, the second output end of the first control switch is connected with the emitter of the third transistor and the second input end of the second control switch, and the first control switch is arranged to control P second currents in the M second currents to flow into the second transistor and control the other (M-P) second currents to flow into the third transistor according to a clock driving control signal; the base electrode of the second transistor is connected with the collector electrode and is grounded, and the base electrode of the third transistor is connected with the collector electrode and is grounded; the output end of the second control switch outputs a second differential reference voltage; or the like, or, alternatively,

the input end of the first control switch is connected with the second current source, the first output end is connected with the base electrode and the collector electrode of the second transistor and the first input end of the second control switch, the second output end is connected with the base electrode and the collector electrode of the third transistor and the second input end of the second control switch, and the setting is that: controlling P second currents of the M currents to flow into the second transistor according to the clock driving control signal, and enabling the rest (M-P) second currents to enter the third transistor; the emitter of the second transistor is grounded, and the emitter of the third transistor is grounded; the output end of the second control switch outputs a second differential reference voltage;

wherein M is more than or equal to 2, P is more than or equal to 1, and M is more than P.

Fig. 5 is a schematic diagram of a second voltage generation circuit according to an embodiment of the invention, as shown in fig. 5, including: the second transistor Q1, the third transistor Q2 and the second current source for providing the second current to the second transistor Q1 and the third transistor Q2, the second transistor Q1 and the third transistor Q2 generate two different base-emitter junction voltages VBE0 and VBE1 according to the second current provided by the second current source, and output a second differential reference voltage according to VBE0 and VBE1, the second differential reference voltage includes a reference voltage dvbep output by a positive terminal and a reference voltage dvben output by a negative terminal, and the second differential reference voltages dvbep and dvben of the embodiment of the present invention can be represented by the following formula (1) and formula (2):

in the embodiment of the present invention, the second differential reference voltages dvbep and dvben are denoted as V (dvbep, dvben), and can be expressed as formula (3):

where K is the Boltzmann constant, T is the absolute temperature, and q is the unit electron charge. I is_s1、I_s0Which are reverse saturation currents of the second transistor Q1 and the third transistor Q2, respectively. I is_E1And I_E0Emitter currents of the second transistor Q1 and the third transistor Q2, respectively. In general I_s1、I_s0In a certain proportional relationship, I_E1And I_E0In a certain proportion relation; for manufacturing reasons, there may be deviations and mismatches between the second transistor Q1 and the third transistor Q2, and between the second current sources to which the Q1, Q2 are connected. In the embodiment of the invention, the first control switch is used for selecting the second current flowing through the second transistor Q1 and the third transistor Q2, the second control switch is used for selecting VBE used for calculating voltage information, namely VBE0 and VBE1 are selected in turn, and deviation and mismatch between the transistors and between the second current sources are eliminated through mean value operation.

Fig. 6 is a schematic diagram of another second voltage generating circuit according to an embodiment of the invention, as shown in fig. 6, including: a second transistor Q1, a third transistor Q2, and a second current source for providing a second current to the second transistor Q1, the third transistor Q2; the input end of the first control switch is connected with the second current source, the first output end of the first control switch is connected with the base electrode and the collector electrode of the second transistor and the first input end of the second control switch, and the second output end of the first control switch is connected with the base electrode and the collector electrode of the third transistor and the second input end of the second control switch.

In an exemplary example, the second voltage generation circuit shown in fig. 5 and 6 further includes a clock driving unit, a first control switch, and a second control switch. The first output end of the first control switch is connected with the emitter of the second transistor and the first input end of the second control switch, the second output end of the first control switch is connected with the emitter of the second transistor Q1 and the second input end of the second control switch, the base of the second transistor Q1 is connected with the collector of the second transistor Q1 and grounded, the base of the third transistor Q2 is connected with the collector of the third transistor Q2 and grounded, and the output end of the second control switch is used for outputting second differential reference voltages dvben and dvbep. The clock driving unit is used for accessing a clock reference signal and generating a first clock driving control signal Ctl < m-1:0> and a second clock driving control signal polar according to the clock reference signal. The second current source I0< M-1:0> is connected with the first control switch and is used for providing M second currents, and M is M; the first control switch controls P of M second currents to enter a second transistor Q1 under the drive of a first clock drive control signal Ctl < M-1:0>, and the other (M-P) second currents enter a third transistor Q2, wherein M is more than or equal to 2, P is more than or equal to 1, and M is more than P; the second control switch outputs VBE0 and VBE1 as second differential reference voltages dvben and dvbep, respectively, driven by a second clock drive control signal (polar). The workflow of the second voltage generation circuit is explained below by way of example:

assuming that the 1 st time P is 1, the 1 st of the M branch second currents enters the second transistor Q1, and the 2 nd to M branch second currents enter the third transistor Q2; at the 2 nd moment, the 2 nd branch current enters the second transistor Q1, and the 1 st, 3 rd to M th branch second currents enter the third transistor Q2; by analogy, at the Mth moment, the Mth branch of the second current enters the second transistor Q1, and the 1 st to M-1 st branches of the second current enter the third transistor Q2. At the 1 st to mth timings, the VBE0 of the second transistor Q1 is output as the second differential reference voltage dvben, and the VBE1 of the third transistor Q2 is output as the second differential reference voltage dvbep. At the moment M +1, the 1 st branch of the second current enters the third transistor Q2, and the 2 nd to M branches of the second current enter the second transistor Q1; at the moment M +2, the second current of the 2 nd branch enters a third transistor Q2, and the second currents of the 1 st branch and the 3 rd branch to the M branch enter a second transistor Q1; by analogy, at the 2 × M time, the mth second current enters the third transistor Q2, and the 1 st to M-1 st second currents enter the second transistor Q1. At the above-mentioned M +1 to 2 × M time, the VBE1 of the third transistor Q2 is output as the second differential reference voltage dvben, and the VBE0 of the second transistor Q1 is output as the second differential reference voltage dvbep. When the manufacturing variations are not considered, the second transistor Q1 and the third transistor Q2 have the same size, and the M-branch second current has the same magnitude, so V (dvbep, dvben) can be expressed as formula (4):

taking into account the manufacturing variations, the average value of the second differential reference voltage obtained by calculation at 2 × M times can be expressed as formula (5):

by the formula (4) and the formula (5), the formula (6) can be obtained by operation:

in equation (6), Δ _ k represents the mismatch ratio at the k-th configuration, and since the mismatch ratio follows a gaussian distributionEquation (6) can be simplified to equation (7):

the embodiment of the invention reduces the influence of mismatch on the second differential reference voltage based on the operation of the second voltage generation circuit shown in fig. 5 and 6.

In an illustrative example, the first transistor Q0, the second transistor Q1, and the third transistor Q2 of embodiments of the present invention may each be a Bipolar Junction Transistor (BJT), a triode, and a field effect transistor (MOS); when the first transistor Q0, the second transistor Q1, and the third transistor Q2 are MOS transistors, the base of the transistors is the gate of the MOS transistor, the emitter is the source of the MOS transistor, and the collector is the drain of the MOS transistor.

In an illustrative example, an ADC according to an embodiment of the present invention includes an arithmetic operation unit, an integration unit, and a quantization unit; wherein the content of the first and second substances,

the arithmetic operation unit is configured to: inputting an input voltage; performing gain amplification on the second differential reference voltage; controlling and outputting a first differential reference voltage used for voltage calculation and a second differential reference voltage after gain amplification according to a control signal provided by a quantization unit; performing accumulation operation on the input voltage, the first differential reference voltage for voltage calculation and the second differential reference voltage after gain amplification, wherein the first differential reference voltage is used for controlling output, and the second differential reference voltage is used for obtaining an accumulation operation result;

the integration unit is arranged to: calculating the accumulated operation result obtained within the preset time according to a preset integral operation rule to obtain an integral operation result;

the quantization unit is configured to: comparing the integral operation result with a preset integral comparison value, and generating a control signal according to the comparison result; and generating voltage information according to the integral operation result.

In an illustrative example, the sum of the second differential reference voltage after gain amplification and the first differential reference voltage is equal to the reference voltage;

fig. 7 is a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention, as shown in fig. 7, the analog-to-digital conversion circuit includes an arithmetic operation unit, an integration unit, and a quantization unit; wherein the content of the first and second substances,

the arithmetic operation unit includes: a first multiplexer U1, a second multiplexer U2, a first accumulator U23, and a first gain amplifier U4; wherein the content of the first and second substances,

a first input end of the first multiplexer U1 is connected with a negative first differential reference voltage, a second input end of the first multiplexer U1 is connected with a 0V voltage, and a control end of the first multiplexer U1 is connected with the quantization unit; the output end of the first multiplexer U1 is connected with the first input end of the first accumulator U23; the first multiplexer U1 is configured to: selectively outputting the first differential reference voltage and the 0V voltage according to the control signal output by the quantization unit;

a first input end of the second multiplexer U2 is connected with a second differential reference voltage, an output end of the second multiplexer U2 is connected with an input end of the first gain amplifier U4, a second input end of the second multiplexer U2 is connected with 0V voltage, and a control end of the second multiplexer U2 is connected with the quantization unit; the output end of the first gain amplifier U4 is connected with the second input end of the first accumulator U23; the second multiplexer U2 is configured to: the output of the first gain amplifier U4 and the 0V voltage are selectively output according to the control signal output by the quantization unit; the first accumulator U23 is set to: and accumulating the output of the first multiplexer U1, the output of the second multiplexer U2 and the input voltage to obtain an accumulation operation result.

When the first differential reference voltage expression is V (vbep, vben), vbep is a positive terminal voltage of the first differential reference voltage, and vben is a negative terminal voltage of the first differential reference voltage; when the second differential reference voltage expression is V (dvbep, dvben), dvbep is a positive terminal voltage of the second differential reference voltage, and dvben is a negative terminal voltage of the second differential reference voltage. In an illustrative example, the first accumulator U23 of the present embodiment is configured to obtain the result of the accumulation operation by performing the accumulation operation according to the following equation (8):

accumulating the operation result to obtain V (vsp, vsn) -KAdc V (vbep, vben) -KAdc kvbg V (dvbp, dvben);

wherein, K_AdcRepresenting an operational coefficient corresponding to the control signal; kvbg is a multiple of the gain amplification of the second differential reference voltage.

In an exemplary embodiment, an integration unit of an embodiment of the present invention includes a second integration unitAccumulator U25 and integrator Z^-1(ii) a The quantization unit includes: a first comparator U26, a first inverter U27, and a second inverter U28; wherein the content of the first and second substances,

integrator Z^-1Performing integral operation on an output result of the first accumulator U23 in a preset time length, and feeding back an integral operation result obtained by the integral operation to the second accumulator U25;

the second accumulator U25 has a first input connected to the output of the first accumulator U23 and a second input connected to the integrator Z^-1Output terminal of the integrator Z^-1And the positive input of the first comparator U26;

the output of the second accumulator U25 to the first accumulator U23 and the integrator Z^-1The output of (a) is accumulated.

The integration unit of the embodiment of the invention passes through a second accumulator U15 and an integrator Z^-1The above operation is to perform averaging calculation on the accumulation operation result of the first accumulator within the preset time length, so as to obtain stable information for determining the voltage information.

The quantization unit includes: a first comparator U26, a first inverter U27, and a second inverter U28; wherein the content of the first and second substances,

the positive input end of the first comparator U26 is connected with the output end of the integrating unit, and the negative input end is connected with a comparison reference signal A1;

an output end of the first comparator U26 is connected with an input end of the first inverter U27 and control ends of the first multiplexer U1 and the second multiplexer U2, and the first comparator U26 compares the magnitude between the integration operation result and the comparison reference signal A1 under the control of the multiphase non-overlapping clock signals to output a control signal;

the output end of the first inverter U27 is connected to the input end of the second inverter U28, the first inverter U27 is used for inverting the control signal to output the inverted control signal as the inverted control signal, and the second inverter U28 is used for inverting the inverted control signal to output the inverted control signal as the voltage information.

It should be noted that the control signal output by the first comparator and K for calculating the accumulation operation result_AdcIn full correspondence, the control signal is used to advanceLine output control, K_AdcIs the operation information completely corresponding to the control signal. Furthermore, K_AdcAfter the process of inverting the output through the first inverter U17 and the second inverter U18, voltage information is obtained.

In the voltage sensor of the embodiment of the present invention, the analog-to-digital conversion unit may implement the calculation of the voltage information by equation (9):

where KAdc _ va represents an average value of the obtained voltage information, and Kvbg is a gain coefficient of the first gain amplifier U4;

in the embodiment of the present invention, V (vbep, vben) and V (dvbep, dvben) and the reference voltage Vbg of the calculated voltage satisfy formula (10):

vbg ═ V (vbep, vben) + kvbg ═ V (dvbp, dvben) formula (10)

Based on equation (9) and equation (10), equation (11) representing the voltage can be obtained:

in the above calculation formula, V (vsp, vsn) is the input voltage to be measured, and the corresponding voltage value can be obtained according to KAdc _ va. FIG. 8 is a schematic diagram of the relationship between voltage information and voltage according to the embodiment of the present invention, as shown in FIG. 8, K_Adc__vaLinearly with voltage.

Fig. 9 is a schematic diagram of another analog-to-digital conversion circuit according to another embodiment of the present invention, and as shown in fig. 9, an arithmetic operation unit in the analog-to-digital conversion circuit includes: two parallel operation branches with the same structure, each operation branch comprises: a third multiplexer U9, a fourth multiplexer U10, a third accumulator U211, and a second gain amplifier U12; wherein the content of the first and second substances,

in the first branch of operation: a first input end of the third multiplexer U9 is connected to a negative end of the first differential reference voltage, a second input end of the third multiplexer U9 is connected to 0V voltage, and a control end of the third multiplexer U9 is connected with the quantization unit; the output end of the third multiplexer U9 is connected to the first input end of the third accumulator U211; the third multiplexer U9 is configured to: selectively outputting the negative terminal voltage and 0V voltage of the accessed first differential reference voltage according to the control signal output by the quantization unit;

a first input end of the fourth multiplexer U10 is connected to one of the second differential reference voltages, an output end of the fourth multiplexer is connected to an input end of the second gain amplifier U12, a second input end of the fourth multiplexer is connected to 0 volt, and a control end of the fourth multiplexer is connected to the quantization unit; the output end of the second gain amplifier U12 is connected with the first input end of the third accumulator U211; the fourth multiplexer U10 is configured to: the output of the second gain amplifier U12 and the 0V voltage are selectively output according to the control signal output by the quantization unit;

the third accumulator U211 is set to: accumulating the output of the third multiplexer U9, the output of the fourth multiplexer U10 and the positive terminal voltage of the input voltage to obtain an accumulated operation result of the operation branch;

in the second branch of operation: a first input end of the third multiplexer U9 is connected to the positive end of the first differential reference voltage, a second input end of the third multiplexer U9 is connected to the 0V voltage, and a control end of the third multiplexer U9 is connected with the quantization unit; the output end of the third multiplexer U9 is connected to the first input end of the third accumulator U211; the third multiplexer U9 is configured to: selectively outputting the positive end voltage and 0V voltage of the connected first differential reference voltage according to the control signal output by the quantization unit;

a first input end of the fourth multiplexer U10 is connected to a negative end of the second differential reference voltage, an output end of the fourth multiplexer U10 is connected to an input end of the second gain amplifier U12, a second input end of the fourth multiplexer U10 is connected to 0V voltage, and a control end of the fourth multiplexer U10 is connected to the quantization unit; the output end of the second gain amplifier U12 is connected with the first input end of the third accumulator U211; the fourth multiplexer U10 is configured to: the output of the second gain amplifier U12 and the 0V voltage are selectively output according to the control signal output by the quantization unit;

It should be noted that the first differential reference voltage includes: vbep and vben; when the ADC shown in fig. 9 is used, the first input ends of the third multiplexers U9 in the two operation branches are respectively connected to one of the first differential reference voltages; likewise, the second differential reference voltage includes: dvbep and dvben; when the ADC shown in fig. 9 is used, the first input terminals of the fourth multiplexers U10 in the two operation branches are respectively connected to one of the second differential reference voltages.

The arithmetic operation unit shown in fig. 9 corresponds to an integration unit including: the first offset control switch, the operational amplifier U213, the second offset control switch, the first integrating capacitor C1 and the second integrating capacitor C2; wherein the content of the first and second substances,

the first input end of the first maladjustment control switch is connected with the output end of the first operation branch of the arithmetic operation unit, the second input end is connected with the output end of the second operation branch of the arithmetic operation unit, the first output end of the first maladjustment control switch is connected with the positive input end of the operational amplifier U213, the second output end of the first maladjustment control switch is connected with the negative input end of the operational amplifier U213, the two output ends of the second maladjustment control switch are respectively connected with the positive input end of the operational amplifier U213, the first integration capacitor is connected between the first input end of the first imbalance control switch and the first output end of the second imbalance control switch, the second integration capacitor is connected between the second input end of the first imbalance control switch and the second output end of the second imbalance control switch, and the control ends of the first imbalance control switch and the second imbalance control switch are both connected with preset imbalance control signals.

Assume that the operational amplifier U213 has an offset voltage voffset _ op, which contributes to the charge contribution of the integration unit at the forward access time: w1 ═ Citg × voffset _ op, the contribution at the reverse access instant is: w0 ═ Citg × voffset _ op, Citg is a constant coefficient. The long-time charge integration is not accumulated after the switches of the first offset control switch and the second offset control switch are controlled by the offset control signal, so that the precision can be improved.

Note that the first offset control switch and the second offset control switch may be provided to increase the processing accuracy of the integration unit, but if accuracy loss is allowed, the first offset control switch and the second offset control switch may not be provided.

The quantization unit corresponding to the arithmetic operation unit shown in fig. 9 includes: a second comparator U214, a third inverter U215, and a fourth inverter U216; wherein the content of the first and second substances,

a positive input end and a negative input end of the second comparator U214 are respectively connected with a first output end and a second output end of the second detuning switch of the integrating unit;

the output end of the second comparator U214 is connected to the input end of the third inverter U215 and the control end of the third multiplexer U9, and the second comparator U214 compares the magnitude between the accumulated operation result of the two operation branches and the comparison reference signal a1 under the control of the multiphase non-overlapping clock signal to output a control signal;

In an exemplary embodiment, the quantization unit of the embodiment of the present invention is further configured to: and outputting the channel associated clock signal of the voltage information according to the multiphase non-overlapping clock signal.

In an exemplary example, the voltage sensor according to the embodiment of the present invention further includes a filter unit; fig. 10 is a schematic diagram of a filtering unit according to an embodiment of the present invention, as shown in fig. 10, including: the device comprises a low-pass filtering module, a gain amplifying module and an offset setting module; wherein the content of the first and second substances,

the low-pass filtering module is arranged as follows: carrying out mean value operation on the voltage information output by the quantization unit;

the gain amplification module is set as follows: determining a gain relation between the voltage information of the mean value operation and the voltage magnitude;

Corresponding to the analog-to-digital conversion circuit shown in fig. 7, the voltage sensor according to the embodiment of the present invention further includes a first clock unit configured to:

the method comprises the steps of receiving a first clock input signal, providing a plurality of non-overlapping clock signals for the arithmetic operation unit according to the received first clock input signal, and providing a clock reference signal for the second voltage generation circuit.

Assuming that the first clock input signal is ADC _ clk _ i, the multiphase non-overlapping clock signal is ADC _ clk, and the clock reference signal required by the second voltage generating circuit is Ck _ vref; fig. 11 is a schematic diagram of multi-phase non-overlapping clock signals according to an embodiment of the present invention, as shown in fig. 11, in each of the non-overlapping clock signals Adc _ clk <1>, Adc _ clk <2>, … … and Adc _ clk < n >, an interval time between rising edges or falling edges of non-overlapping clock signals of adjacent phases is td (td >0), and an interval time between rising edges or falling edges of non-overlapping clock signals of adjacent phases is td (td >0) in each of the non-overlapping clock signals Adc _ clk < n +1>, Adc _ clk < n +2> … … Adc _ clk <2 n >. The time interval between the falling edge of the non-overlapping clock signal Adc _ clk < n > and the rising edge of the non-overlapping clock signal Adc _ clk < n +1> is also td; the time interval between the falling edge of the non-overlapping clock signal Adc _ clk <2 x n > and the rising edge of the non-overlapping clock signal Adc _ clk <1> is also td; according to the requirement of ADC pairs for clock multiphase, the clock unit can generate four-phase, six-phase … … and 2 x n-phase non-overlapped clock signals, wherein n is larger than or equal to 1.

Corresponding to the analog-to-digital conversion circuit shown in fig. 9, the voltage sensor according to the embodiment of the present invention further includes a second clock unit configured to:

and receiving a second clock input signal, providing a plurality of non-overlapping clock signals and offset control signals for the arithmetic operation unit according to the received second clock input signal, and providing a clock reference signal for the second voltage generation circuit.

The embodiment of the invention also provides a chip, and the voltage sensor is integrated in the chip.

The embodiment of the invention also provides electronic equipment, and the chip is loaded and operated in the electronic equipment.

"one of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art. "

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