阅读说明：本技术 数字辅助校准rms功率检测方法及系统 (Digital auxiliary calibration RMS power detection method and system ) 是由 周雯菁 唐涛 于 2020-12-28 设计创作，主要内容包括：本发明提供了一种数字辅助校准RMS功率检测方法及系统,包括：步骤S1：在RMS功率检测器基础上,断开输入对管连接的两个PMOS管之间的漏极连接；步骤S2：在输出级加入校准负载和充电电容,获取电压输出信息、抵抗电源噪声对检测结果的影响输出信息；步骤S3：根据电压输出信息、抵抗电源噪声对检测结果的影响输出信息,加入PMOS电流镜,偏置校准输出级,获取数字辅助校准RMS功率检测结果信息。本发明通过功率检测器的检测结果与参考电压对比,运用数字逻辑控制电流比特来稳定输出电压,消除PVT变化带来的检测误差。(The invention provides a method and a system for detecting digital auxiliary calibration RMS power, comprising the following steps: step S1: on the basis of the RMS power detector, disconnecting the drain electrode between two PMOS tubes connected with the input pair tube; step S2: adding a calibration load and a charging capacitor in an output stage to acquire voltage output information and output information resisting the influence of power supply noise on a detection result; step S3: and adding a PMOS current mirror and a bias calibration output stage according to the voltage output information and the output information resisting the influence of power supply noise on the detection result, and acquiring digital auxiliary calibration RMS power detection result information. According to the invention, the detection result of the power detector is compared with the reference voltage, the output voltage is stabilized by using the digital logic control current bit, and the detection error caused by PVT change is eliminated.)

1. A method for digitally assisted calibration RMS power detection, comprising:

step S1: on the basis of the RMS power detector, disconnecting the drain electrode between two PMOS tubes connected with the input pair tube;

step S2: adding a calibration load and a charging capacitor in an output stage to acquire voltage output information and output information resisting the influence of power supply noise on a detection result;

step S3: and adding a PMOS current mirror and a bias calibration output stage according to the voltage output information and the output information resisting the influence of power supply noise on the detection result, and acquiring digital auxiliary calibration RMS power detection result information.

2. The digitally-assisted calibration RMS power detection method of claim 1, further comprising:

step S4: connecting a digitally assisted calibration current circuit to the RMS power detector;

the digitally-assisted calibration current circuit includes: a PMOS current source and an NMOS current source.

3. The digitally-assisted calibration RMS power detection method as claimed in claim 1, wherein said step S3 further comprises:

step S3.1: and acquiring the detection result information of the power detector according to the detection control information of the power detector.

4. The digitally-assisted calibration RMS power detection method as claimed in claim 3, further comprising:

step S5: acquiring control information according to the reference voltage, and acquiring reference voltage information which is not influenced by PVT (voltage-to-voltage) variation;

step S6: and comparing the result detected by the power detector with the reference voltage which is not influenced by the PVT change according to the detection result information of the power detector and the reference voltage information which is not influenced by the PVT change to obtain comparison result information.

5. The digitally-assisted calibration RMS power detection method as claimed in claim 4, further comprising:

step S7: according to the comparison result information, the type and the current value of the output current source are controlled by using digital logic, and then the current is injected into the calibration output stage to ensure that the output voltage is stabilized at the corresponding output voltage corresponding to the input power.

6. A digitally-assisted calibration RMS power detection system, comprising:

module M1: on the basis of the RMS power detector, disconnecting the drain electrode between two PMOS tubes connected with the input pair tube;

module M2: adding a calibration load and a charging capacitor in an output stage to acquire voltage output information and output information resisting the influence of power supply noise on a detection result;

module M3: and adding a PMOS current mirror and a bias calibration output stage according to the voltage output information and the output information resisting the influence of power supply noise on the detection result, and acquiring digital auxiliary calibration RMS power detection result information.

7. The digitally-assisted calibration RMS power detection system as claimed in claim 6, further comprising:

module M4: connecting a digitally assisted calibration current circuit to the RMS power detector;

the digitally-assisted calibration current circuit includes: a PMOS current source and an NMOS current source.

8. The digitally-assisted calibration RMS power detection system as claimed in claim 7, wherein said module M3 further comprises:

module M3.1: and acquiring the detection result information of the power detector according to the detection control information of the power detector.

9. The digitally-assisted calibration RMS power detection system according to claim 8, further comprising:

module M5: acquiring control information according to the reference voltage, and acquiring reference voltage information which is not influenced by PVT (voltage-to-voltage) variation;

module M6: and comparing the result detected by the power detector with the reference voltage which is not influenced by the PVT change according to the detection result information of the power detector and the reference voltage information which is not influenced by the PVT change to obtain comparison result information.

10. The digitally-assisted calibration RMS power detection system as claimed in claim 9, further comprising:

module M7: according to the comparison result information, the type and the current value of the output current source are controlled by using digital logic, and then the current is injected into the calibration output stage to ensure that the output voltage is stabilized at the corresponding output voltage corresponding to the input power.

Technical Field

The invention relates to the technical field of power detection, in particular to a method and a system for detecting RMS (root mean square) power by means of digital auxiliary calibration.

Background

In a receiving link of a wireless transceiver, in order to meet the requirement of large dynamic range, a plurality of AGC are needed to be used for adjusting the whole gain no matter in a radio frequency front end or a baseband part; in the AGC module, a power detector is responsible for detecting the power of a signal and controls the gain of the signal in cooperation with a VGA. The accuracy of the power detector has a direct effect on the gain distribution of the rf front-end. When the gain is too large due to insufficient precision, the linearity of the radio frequency front end is reduced; when the gain is small, the noise contribution of the latter module is increased. A high accuracy power detector is therefore required to control the gain variation of the AGC, thereby improving the performance of the rf front end.

Currently, rf power detectors are implemented in three types, diode power detectors, SDLA power detectors and RMS power detectors.

The first type is a diode power detector as shown in fig. 2, which consists of a pair of triode source followers, a pair of current sources, two resistors and two capacitors. The radio frequency signal is input from the base electrode of the triode in one path, and the difference value output by the detectors in the two paths is used as output voltage and is 0 when no radio frequency is input in the other path. The capacitance connected with the triode of the radio frequency signal input is used for controlling the voltage change rate, and the capacitance of the other path is used for inhibiting the influence of the power supply voltage noise on the output voltage. This structure has the advantage of eliminating detection errors caused by process variations, but it still has the following disadvantages: (1) the error is large under different temperatures, which is related to the temperature; (2) the detection error increases when the input radio frequency power decreases; (3) not suitable for CMOS process integration.

The second type is the SDLA power detector, the structure of which is shown in FIG. 3. This type of detector includes a multi-stage limiting amplifier, full-wave rectifiers and an RC low-pass filter. The radio frequency input signal is input and is gradually amplified through the series of limiting amplifiers one by one. In the process, the output of the limiting amplifier reaches the upper limit of the output swing amplitude, then the limiting amplifier enters a limiting state, the output voltage of the limiting amplifier is limited to a fixed level, and the radio-frequency signal becomes a square wave. The full-wave rectifier converts the input and output voltage of each stage of limiting amplifier into current, and the current flows to the following LPF to generate the final output voltage of the power detector. However, the input/output curve of the power detector is subject to drift due to process, voltage, temperature and frequency variations, and its absolute detection accuracy is very limited.

The third type is a conventional RMS power detector, as shown in fig. 4, where a pseudo-differential pair in saturation converts the voltage of a radio frequency signal into a current; the PMOS transistor pair detector above the pseudo-differential pair provides bias current for eliminating DC bias related components and amplifying RF signal related useful components. The LPF filters out the ac component of the current associated with the rf signal, leaving only a current component proportional to the RMS value of the rf signal power. This results in an output current proportional to the square of the rf signal amplitude, thereby detecting the RMS value of the rf power. Like other power detectors, the input-output curve of an RMS power detector may also be biased by PVT variations and device mismatch.

Comparing the three types of power detectors, it can be known that the diode power detector needs to use a diode or a transistor, and when the rf power is reduced, the error of the detection result becomes larger and still affected by the temperature. Moreover, the CMOS process is not compatible with a vertical NPN transistor, nor does it provide a triode with superior performance. The detection result of the SDLA power detector can change the detection accuracy and the detection dynamic range by controlling the gain of the single limiting amplifier. However, the output of the power detector is subject to drift due to PVT variations, and the absolute detection accuracy is therefore limited only to a very narrow limit. The RMS power detector, while insensitive to the PAPR of the radio frequency signal, is limited in input range by the noise of the detector itself and the input to the tube operating region, and the detection result is still affected by PVT variations. The detection results of these detectors introduce offsets due to the presence of significant external disturbances. There is a need for an improved power detector that eliminates errors due to PVT variations.

Patent document CN104755944A discloses an innovative device and method capable of detecting the true Root Mean Square (RMS) power level of an analog input signal. For example, the electronic circuit may include: a squaring circuit that receives an analog input signal and processes the analog input signal using an analog transfer function of the squaring circuit to produce a squared output of the analog input signal; and a square root circuit that receives the squared output and processes the squared output using an analog transfer function of the square root circuit to produce an analog RMS output signal that represents the true RMS power level of the analog input signal. The patent still leaves room for improvement in process configuration and technical performance.

Disclosure of Invention

In view of the deficiencies in the prior art, it is an object of the present invention to provide a method and system for digitally assisted calibration of RMS power detection.

The invention provides a method for detecting the RMS power by digital auxiliary calibration, which comprises the following steps:

step S1: on the basis of the RMS power detector, disconnecting the drain electrode between two PMOS tubes connected with the input pair tube; step S2: adding a calibration load and a charging capacitor in an output stage to acquire voltage output information and output information resisting the influence of power supply noise on a detection result; step S3: and adding a PMOS current mirror and a bias calibration output stage according to the voltage output information and the output information resisting the influence of power supply noise on the detection result, and acquiring digital auxiliary calibration RMS power detection result information.

Preferably, the method further comprises the following steps:

step S4: connecting a digitally assisted calibration current circuit to the RMS power detector;

the digitally-assisted calibration current circuit includes: a PMOS current source and an NMOS current source.

Preferably, the step S3 further includes:

step S3.1: and acquiring the detection result information of the power detector according to the detection control information of the power detector.

Preferably, the method further comprises the following steps:

step S5: and acquiring control information according to the reference voltage, and acquiring reference voltage information which is not influenced by PVT change.

Step S6: and comparing the result detected by the power detector with the reference voltage which is not influenced by the PVT change according to the detection result information of the power detector and the reference voltage information which is not influenced by the PVT change to obtain comparison result information.

Preferably, the method further comprises the following steps:

step S7: according to the comparison result information, the type and the current value of the output current source are controlled by using digital logic, and then the current is injected into the calibration output stage to ensure that the output voltage is stabilized at the corresponding output voltage corresponding to the input power.

A digitally assisted calibration RMS power detection system provided in accordance with the present invention includes:

module M1: on the basis of the RMS power detector, disconnecting the drain electrode between two PMOS tubes connected with the input pair tube;

module M2: adding a calibration load and a charging capacitor in an output stage to acquire voltage output information and output information resisting the influence of power supply noise on a detection result;

module M3: and adding a PMOS current mirror and a bias calibration output stage according to the voltage output information and the output information resisting the influence of power supply noise on the detection result, and acquiring digital auxiliary calibration RMS power detection result information.

Preferably, the method further comprises the following steps:

module M4: connecting a digitally assisted calibration current circuit to the RMS power detector;

the digitally-assisted calibration current circuit includes: a PMOS current source and an NMOS current source.

Preferably, the module M3 further includes:

module M3.1: and acquiring the detection result information of the power detector according to the detection control information of the power detector.

Preferably, the method further comprises the following steps:

module M5: and acquiring control information according to the reference voltage, and acquiring reference voltage information which is not influenced by PVT change.

Module M6: and comparing the result detected by the power detector with the reference voltage which is not influenced by the PVT change according to the detection result information of the power detector and the reference voltage information which is not influenced by the PVT change to obtain comparison result information.

Preferably, the method further comprises the following steps:

module M7: according to the comparison result information, the type and the current value of the output current source are controlled by using digital logic, and then the current is injected into the calibration output stage to ensure that the output voltage is stabilized at the corresponding output voltage corresponding to the input power.

Compared with the prior art, the invention has the following beneficial effects:

1. according to the invention, the detection result of the power detector is compared with the reference voltage, the output voltage is stabilized by using the digital logic control current bit, and the detection error caused by PVT change is eliminated.

2. The invention provides a novel digital auxiliary calibration RMS power detector which can eliminate the influence of PVT change on power detection and improve the detection precision. A digital auxiliary calibration scheme is added on the basis of the traditional RMS power detector, and aims to eliminate detection errors generated by PVT variation and device mismatch. The novel digitally-assisted calibration RMS power detector includes a power detector core circuit, a calibration current array and a power detector bias circuit;

3. the invention can eliminate the error of the detection result caused by PVT change and device mismatch, thereby improving the detection precision of the detector.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a schematic overall flow chart of the present invention.

Fig. 2 is a schematic diagram of a diode power detector in the prior art.

Fig. 3 is a diagram of a prior art SDLA power detector.

FIG. 4 is a schematic diagram of a conventional RMS power detector of the background art.

FIG. 5 is a schematic diagram of a first power detector core circuit and a digital calibration current array in an embodiment of the invention.

Fig. 6 is a schematic diagram of a second power detector core circuit and a digital calibration current array in an embodiment of the invention.

FIG. 7 is a flow chart illustrating digital calibration of a power detector according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of continuously comparing the output detection voltage and the output reference voltage according to the embodiment of the invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The invention provides a novel digital auxiliary calibration RMS power detector which can eliminate the influence of PVT change on power detection and improve the detection precision. A digital auxiliary calibration scheme is added on the basis of the traditional RMS power detector, and aims to eliminate detection errors generated by PVT variation and device mismatch. A novel digitally assisted calibration RMS power detector includes a power detector core circuit, a calibration current array and a power detector bias circuit.

The core circuit of the power detector is used for extracting direct current which is in direct proportion to the RMS value of radio frequency input power and generates an output voltage signal by flowing through a resistor. The power detector core circuit includes a bias portion, an input stage, an LPF, and a calibration output stage. The input stage is an NMOS differential input pair transistor, a pair of DC blocking resistors and a pair of DC biasing resistors. Equal direct current bias voltage is connected to the NMOS differential input pair transistors through the direct current bias resistors, differential radio frequency input signals are input into the NMOS differential input pair transistors through the blocking capacitors and are superposed together to be converted into current. The NMOS differential input pair tube and the NMOS tube in the bias part are in proportional relation and work in a saturation region, so that an upper limit exists in the detectable radio frequency signal power. The PMOS current mirror connected with the NMOS tube has the same proportional relation and is used for biasing the detector. The bias section both removes the dc current generated by the bias voltage and amplifies the ac current component associated with the rf input signal. This alternating current flows through the LPF leaving only a direct current component proportional to the RMS power of the rf input signal. The resulting current after mirroring flows through the resistance of the calibration output stage, generating the output voltage.

The calibration current array includes two parts of current, an NMOS current and a PMOS current, which supply current to the calibration load. Six binary weight bits control the number of ways the current mirror is turned on, and the switch at the output is determined by the highest control bit. According to the comparison between the output voltage of the power detector and the reference voltage, the digital logic circuit changes the control bit of the current and determines the value of the calibration current injected or extracted from the calibration load. The control bits are initially default to all 0 s and the novel digitally-assisted calibrated RMS power detector switches to the detection mode. The highest control bit, based on the comparison result, requires that the current injected into the calibration output stage of the power detector core circuit becomes 1 and then becomes 0. Then the calibration current is changed again by the dichotomy. After seven cycles, the output voltage is stably controlled to be close to the reference voltage. And (5) finishing calibration.

The power detector biasing circuit provides band-gap reference voltage for an NMOS tube in a core circuit of the power detector, generates required different direct current biasing voltages through a voltage dividing resistor, and inputs a calibration RMS voltage and outputs a reference voltage. The resulting voltage remains constant over PVT variations.

An improved RMS power detector core circuit. Compared with the traditional RMS power detector, the drain electrode connection between two PMOS tubes connected by the input pair tube is disconnected, and the calibration load and the charging capacitor are added in the output stage to output voltage so as to resist the influence of power supply noise on the detection result. And a PMOS current mirror is also added to bias and calibrate an output stage.

A digitally assisted calibration current circuit. Including PMOS current sources and NMOS current sources. The results detected by the power detector are compared to a reference voltage that is not affected by PVT variations. The type of the output current source and the magnitude of the current are controlled by using digital logic, and then the current is injected into the calibration output stage to ensure that the output voltage is stabilized at the corresponding output voltage corresponding to the input power.

Such as: a method of digitally assisted calibration is added to improve upon conventional RMS power detectors. The improved RMS power detector has an operating mode and a calibration mode. Normally detecting the power of the radio frequency signal in the working mode; in the calibration mode, a dc voltage with a known power is input, and the output voltage of the power detector varies greatly due to PVT influence. The output voltage is stabilized at a certain reference voltage value by the injection or extraction of current through the digitally calibrated current array. The reference voltage value is the output voltage of the power detector under the typical condition when the reference power is input. Therefore, the invention can eliminate the error of the detection result caused by PVT change and device mismatch, thereby improving the detection precision of the detector.

Fig. 5 and 6 are a power detector core circuit and a digital calibration current array of the present invention. R3 and R4 are large DC bias resistors, connected to the DC bias voltage, and C3 and C4 are DC blocking capacitors. When the power detector enters a working mode, M2-M4 are in a saturation region and are connected with the same bias voltage; the rf signals from C3 and C4 coupled to the gates of M3 and M4 are converted to dc current proportional to the RMS value of the rf signal power and to doubled ac current. There may also be alternating current at the frequency of the radio frequency signal due to device mismatch. Then, the signal passes through M7 of the current mirror and is filtered by LPF, and only the DC component of the RF signal voltage is left to drive M8. When the power detector enters a detection mode, no radio frequency signal is input, RMS voltage corresponding to known signal power is input to the gates of M3 and M4, and under the influence of PVT change, the output detection voltage deviates from the output reference voltage under the typical condition.

The digital calibration current array output is connected between R2 and R3. Comparing the output detection voltage with the output reference voltage, if the output detection voltage is larger than the output reference voltage, starting an NMOS current source by the digital calibration current array, and extracting current from the calibration output stage; if the current is smaller, the digital calibration current array starts the PMOS current source to inject current into the calibration output stage. In seven control bits of the digital calibration current array, the first bit is the highest bit to determine the current source type, the rest are binary current weights, and the calibration period is seven clock periods. The second bit weight is 25, and the convergence rate is increased by adopting a dichotomy. Referring to fig. 8, which is a flow chart of digital calibration of the power detector of the present invention, in the nth cycle, the nth control bit is changed to change the calibration current, and then the comparison between the output detection voltage and the output reference voltage is continued as shown in fig. 7, so that the output voltage of the power detector will be stabilized around the output reference voltage after seven clock cycles. Changing the clock frequency can adjust the calibration time.

On the basis of a traditional RMS power detector, a digital auxiliary calibration method is provided, which eliminates detection errors caused by PVT changes, improves detection precision, and can also consume smaller area and lower power consumption. When the power detector is just started or the circuit temperature is greatly changed, digital calibration can be started, and detection errors caused by PVT changes are eliminated. The detector has extremely small detection error, and the area and power consumption are controlled at a better level due to the digital calibration.

In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.